Transputer
Motherboard User
Manual
Ref: TMB M 711
Document reference number TMB M 711.
Copyright 1997 Transtech Parallel Systems.
This publication is protected by Copyright Law, with all rights
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Parallel Systems.
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Table of Contents
Chapter 1 Introduction 1
Chapter 2 Using Transputer Modules 3
2.1 Introducing TRAMs ................................................................. 3
2.1.1 Hardware Description .................................................... 3
2.2 Building a Computer from TRAMs .......................................... 7
2.2.1 Physically building the System ...................................... 7
2.2.2 Configuring the System ................................................. 8
2.3 A More Complex Example .................................................... 10
2.3.1 Control Aspects ........................................................... 10
2.3.2 Topology Aspects ........................................................ 11
2.3.3 Network Configuration Aspects ................................... 13
2.4 Summary ............................................................................... 14
Chapter 3 The TRAM Standard 17
3.1 Introduction ........................................................................... 17
3.2 The Transputer Module ......................................................... 18
3.2.1 Overview ..................................................................... 18
3.2.2 Functional Description ................................................. 18
3.2.3 Electrical Description ................................................... 21
3.3 The Transputer Module Motherboard ................................... 21
3.3.1 Overview ..................................................................... 21
3.3.2 Link Configuration ....................................................... 22
3.3.3 System Control ............................................................ 25
3.4 Host Computer Interface ....................................................... 30
3.4.1 Host IO Space ............................................................. 30
3.4.2 Link Interface ............................................................... 32
3.4.3 System Control Interface ............................................. 33
3.4.4 Interrupts and DMA ..................................................... 33
3.4.5 DMA & Interrupt Channels .......................................... 34
TMB M 711 Transputer Motherboard User Manual i
Chapter 4 The TMB03 Motherboard 35
4.1 Board Configuration Jumpers ................................................36
4.1.1 Control Configuration ...................................................37
4.1.2 Board IO Address ........................................................37
4.1.3 Link Speed Configuration .............................................38
4.1.4 Master and Slave Configuration ...................................38
4.1.5 IRQ & DMA Selection ..................................................40
4.2 The Edge Connector ..............................................................41
4.2.1 Use of the master link ..................................................43
4.3 Example .................................................................................43
Chapter 5 The TMB04 Motherboard 45
5.1 Fitting TRAMs ........................................................................46
5.2 Fitting memory .......................................................................46
5.3 Board Configuration Jumpers ................................................47
5.3.1 On-board transputer clock and memory ......................48
5.3.2 Control Configuration ...................................................49
5.3.3 Board IO Address ........................................................50
5.3.4 Link Speed Configuration .............................................51
5.3.5 Master and Slave Configuration ...................................52
5.3.6 IRQ & DMA Selection ..................................................52
5.4 The Edge Connector ..............................................................53
Chapter 6 The TMB08 Motherboard 57
6.1 Overview ................................................................................57
6.2 Network Configuration ...........................................................58
6.2.1 Electronic Link Configuration .......................................58
6.2.2 The Link Patch Area ....................................................60
6.2.3 Summary of Network Configuration .............................62
6.3 Description .............................................................................62
6.3.1 Board Configuration .....................................................62
6.3.2 IRQ & DMA Selection ..................................................64
6.3.3 The Edge Connector ....................................................65
6.3.4 The Link Patch Area ....................................................67
6.4 Examples ...............................................................................68
6.4.1 Stand-alone TMB08 .....................................................68
6.4.2 Multiple TMB08s ..........................................................69
ii Transputer Motherboard User Manual TMB M 711
Chapter 7 The TMB12 Motherboard 73
7.1 Overview ............................................................................... 73
7.2 Description ............................................................................ 76
7.2.1 Board Configuration .................................................... 76
7.2.2 The P1 Edge Connector .............................................. 76
7.2.3 The P2 Edge Connector .............................................. 77
7.2.4 Other Hardware ........................................................... 81
7.3 Network Configuration ........................................................... 82
7.3.1 Electronic Link Switching ............................................. 82
7.3.2 The K1 Header Block .................................................. 86
7.3.3 The P1 Edge Connector .............................................. 87
7.3.4 Summary ..................................................................... 89
Chapter 8 The TMB14 Motherboard 91
8.1 Overview ............................................................................... 91
8.2 VMEbus Interface .................................................................. 93
8.2.1 Link Adaptor Registers ................................................ 94
8.2.2 Subsystem Control Registers ...................................... 95
8.2.3 Interrupt Control Registers .......................................... 95
8.3 Link and Control Configuration .............................................. 96
8.3.1 Links ............................................................................ 97
8.3.2 Subsystem ................................................................... 99
8.4 Board Setup ........................................................................ 101
8.4.1 VMEbus Interface ...................................................... 102
8.4.2 Link Speed Configuration .......................................... 102
8.4.3 Control Configuration ................................................ 103
8.4.4 Link configuration ...................................................... 104
8.4.5 Sysreset Lengthening ................................................ 105
8.5 Connector Pinouts ............................................................... 105
8.6 Programming ....................................................................... 112
Chapter 9 The TMB16 Motherboard 115
9.1 Overview ............................................................................. 115
9.2 Network Configuration ......................................................... 116
9.2.1 Electronic Link Configuration ..................................... 117
9.2.2 The Link Patch Area .................................................. 118
9.2.3 Summary of Network Configuration .......................... 120
TMB M 711 Transputer Motherboard User Manual iii
9.3 Board Setup .........................................................................121
9.3.1 Control Configuration .................................................121
9.3.2 Board Address ...........................................................122
9.3.3 Link speed ..................................................................122
9.3.4 IRQ & DMA Selection ...............................................122
9.3.5 Reserved switches .....................................................123
9.4 The Edge Connector ............................................................123
9.5 Examples .............................................................................125
9.5.1 Stand-alone ................................................................126
9.5.2 Multiple TMB16s ........................................................126
9.5.3 Link Adaptor ...............................................................128
9.6 The Host Interface ...............................................................128
9.6.1 Operation of the Hardware .........................................129
9.6.2 Memory Maps ............................................................131
9.6.3 Operation of the Software ..........................................133
Chapter 10 The TMB17 Motherboard 135
10.1 Overview ............................................................................135
10.2 Windows 95 .......................................................................136
10.3 PCI Interface ......................................................................137
10.3.1 Hardware Description ..............................................137
10.3.2 Register Map ............................................................137
10.3.3 PCI Configuration .....................................................139
10.4 Network Configuration .......................................................139
10.4.1 Electronic Link Configuration ...................................139
10.4.2 The Link Patch Area ................................................141
10.4.3 Summary of Network Configuration .........................144
10.5 Description .........................................................................144
10.5.1 Board Configuration .................................................144
10.5.2 The Edge Connector ................................................146
10.5.3 The Link Patch Area ................................................148
10.6 Examples ...........................................................................149
10.6.1 Stand-alone TMB17 .................................................149
10.6.2 Multiple TMB17s ......................................................150
Chapter 11 Utilities Software 153
11.1 PC Installation ....................................................................153
iv Transputer Motherboard User Manual TMB M 711
11.2 Solaris 2 Installation .......................................................... 154
11.2.1 FORCE CPU-3CE ................................................... 154
11.2.2 FORCE CPU-5V ...................................................... 155
11.2.3 Software .................................................................. 155
11.2.4 Configuration File .................................................... 156
11.3 Environment Variables ...................................................... 157
11.4 Connection Database ........................................................ 158
11.5 Network test utilities .......................................................... 159
11.5.1 Link Switch Configuration ........................................ 160
11.6 The Inmos server program ................................................ 162
11.7 Transputer host I/O utilities ............................................... 162
11.8 Inmos Aserver Support ..................................................... 163
11.9 Solaris 2 Device Driver ...................................................... 164
11.10 Reference Manual Pages ................................................ 166
11.10.1 Commands ............................................................ 166
check(1)......................................................................... 166
ckmon(1) ........................................................................ 168
ftest(1) ............................................................................169
iserver(1) ........................................................................170
load(1) ............................................................................172
mtest(1) ..........................................................................173
11.10.2 Linked Process Units ............................................. 175
hostmux(2)..................................................................... 175
iocache(2) ...................................................................... 179
11.10.3 Program Function Calls ......................................... 181
genio(3).......................................................................... 181
Chapter 12 Trouble-shooting 185
12.1 TRAM checklist ................................................................. 185
12.1.1 Reset ....................................................................... 186
12.1.2 Links ........................................................................ 186
12.1.3 Link speed ............................................................... 186
12.1.4 Analyse .................................................................... 186
12.1.5 Power ...................................................................... 186
12.1.6 Clock ....................................................................... 186
12.2 PC Host Interface .............................................................. 187
Index 189
TMB M 711 Transputer Motherboard User Manual v
vi Transputer Motherboard User Manual TMB M 711
Chapter 1
Introduction
This manual describes the Transtech transputer module (TRAM)
motherboards.
Introduction
Chapter 2 gives an introduction to the concepts and
nomenclature of transputer modules. All
users should read this before attempting to
configure a TRAM motherboard.
Chapter 3 gives a detailed description of the TRAM
standard for modules and motherboards.
This chapter contains more advanced
information required for fault-finding,
designing compatible hardware or for
systems programming.
Chapter 4 describes the TMB03 low-cost
motherboard for PC.
Chapter 5 describes the TMB04 motherboard for PC
with transputer.
Chapter 6 describes the TMB08 motherboard for PC.
Chapter 7 describes the TMB12 double extended
eurocard motherboard.
Chapter 8 describes the TMB14 6U VME slave
motherboard.
Chapter 9 describes the TMB16 high performance
Chapter 10 describes the TMB17 high performance
Chapter 11 describes the test software and utilities
TMB M 711 Transputer Motherboard User Manual 1
motherboard for PC.
PCI motherboard for PC.
provided with the boards.
Introduction
Chapter 12 provides a detailed trouble-shooting guide.
2 Transputer Motherboard User Manual TMB M 711
Using Transputer Modules
Chapter 2
Using Transputer Modules
This chapter contains a beginners guide to setting up and using
transputer equipment based on TRAMs. It discusses simple
configurations of transputers for the most popular programming
environments and how to link two motherboards together to
construct larger networks. If you have purchased a standard
configuration PARAstation it will already be configured for you and
the following should only be read to understand the concepts behind
your parallel processing system. F or more detailed inf ormation refer
to Chapter 3
‘The TRAM Standard’
.
2.1 Introducing TRAMs
TRAMs are small assemblies based on transputers with a standard
electrical and mechanical interface. They plug onto standard
motherboards which in turn plug into or can be connected to a range
of host computers. This allows TRAMs and motherboards from
different vendors to be plugged into a wide variety of computing
platforms, giving the user the ability to construct a computing
machine which meets their requirements exactly in terms of
performance and IO function.
2.1.1 Hardware Description
This section contains a description of the transputer hardware which
allows users unfamiliar with TRAMs to understand the installation
procedure described in the next section.
The smallest size of TRAM measures about 3.5" long by 1" wide
(10cm by 2.5cm). This is called a Size 1 TRAM. The size of larger
TRAMs is always a multiple of the Size 1 TRAM. The size 1 TRAM
TMB M 711 Transputer Motherboard User Manual 3
Introducing TRAMs
has 16 pins which plug into sockets on the motherboard. TRAMs are
marked in one corner (pin 1) for orientation purposes. See figure 1.
TRAM pins
Size 1 TRAM
Size 2 TRAM
Subsystem
Pin 1
Pin 1
Figure 1. Transputer Modules
Some TRAMs have a subsystem - this consists of three zero profile
sockets mounted on the underside of the TRAM in one corner
(always next to pin 1). Only slot 0 on the motherboard has the
capacity to accept the subsystem from such a TRAM. Figure 2 shows
4 Transputer Motherboard User Manual TMB M 711
Using Transputer Modules
how to used the supplied double ended connector to plug these
sockets into similar sockets on the motherboard.
3-way double ended
header strip
Module
Motherboard
zero profile sockets
Figure 2. Subsystem Port Connections
Because of the way the subsystem connects to the motherboard it is
not compulsory to perform this connection if it is not needed and
hence TRAMs with subsystem can plug into any socket on the
motherboard.
The location where the TRAM plugs onto a motherboard is called a
slot or site. Slots are numbered from zero. Figure 3 shows a slice of
a typical motherboard. Note that the slots are not all oriented the
same way and that the ordering of slots is not contiguous. This allo ws
better utilization of the motherboard when plugging in TRAMs of
different sizes.
s4 s5 s2 s0 s3 s6
The motherboard is specially wired so that if it is populated with size
1 TRAMs then the transputers are all connected in a pipeline. This is
TMB M 711 Transputer Motherboard User Manual 5
Figure 3. TRAM slots on a motherboard
Introducing TRAMs
achieved by connecting link2 of one transputer to link1 of the next
transputer. See figure 4.
Slot0 Slot1 Slotn
L1 L2 L1 L2 L1 L2
PipeHead
TRAMs which are larger than size 1 do not use all of the sites
underneath them. The only active site is the one below pin 1 of the
TRAM. This means that the pipeline is broken at the unused slots
underneath the TRAM. T o bridge these breaks a special pipe jumper
can be used. Figure 5 shows a pipe jumper.
PipeTail
Figure 4. The Default Transputer Pipeline
Pin1
Marker
Figure 5. Pipe Jumper
6 Transputer Motherboard User Manual TMB M 711
Using Transputer Modules
Pipe jumpers are plugged in with the same orientation as TRAMs, i.e.
with their pin1 adjoining the orientation mark on the motherboard.
Figure 6 shows a situation in which a pipe jumper may be needed.
Pipe jumper in slot 3
s4 s5 s2 s0 s3 s6
Size 2 TRAM
covers slot 3
Figure 6. Using pipe jumpers
The diagram shows slot 3 being covered by a large TRAM. If it is
required to continue the pipeline on beyond slot 3, in this case there
is a TRAM in slot 4, then slot 3 will need to be jumpered.
2.2 Building a Computer from TRAMs
This section describes the setting up of a simple system consisting
of a number of transputers on a single module motherboard. Building
the system consists of three main stages:
1. Plug the TRAMs onto the motherboard,
2. Configure the motherboard reset structure for the software de velopment system or application being used,
2.2.1 Physically building the System
Transputer modules and motherboards contain components which
can be damaged by static electricity. It is theref ore advisab le to tak e
some simple precautions before handling TRAMs and module
motherboards:
• keep the TRAM plugged into its anti-static mat when it is not
plugged onto a motherboard,
• keep module motherboards in their anti-static bags when they
are not in use,
• before handling TRAMs or motherboards ground yourself by
touching an earth (the metal enclosure of electrical equipment is
always earthed),
TMB M 711 Transputer Motherboard User Manual 7
Building a Computer from TRAMs
• try to avoid touching the TRAM pins when plugging them in.
Plug the TRAMs into the motherboard slots as required by your
application. When doing this note that:
• TRAMs should be oriented the correct way round to avoid
permanent damage,
• if you are using the occam TDS, or the interactive debugger
supplied with the Inmos C or occam toolsets, you will need to
connect the subsystem on the TRAM that plugs into slot 0,
• TRAMs are shipped with spacers attached to their pins to raise
them above any components on the motherboard. When there
are no components on the motherboard these spacers can be
removed if you wish to lower the height profile of the
motherboard/TRAM combination. However please bear in mind
that adequate airflow under the TRAM is required for cooling.
See figure 7.
Motherboard
Figure 7. TRAM spacer
2.2.2 Configuring the System
The next stage is to set all the configuration options of the board.
Normally, the only options which have to be considered are the
control structure and the transputer network.
The following sections discuss the rele vant options without ref erence
to a particular motherboard. For details of the actual
jumpers/switches to set ref er to the hardw are chapter in the product
specific section of this document.
Components
Module
Spacer
2.2.2.1 The Control Structure
In order to be able to program and use the TRAMs on the
motherboard there is a mechanism for their control. The most
important control signal sent to a TRAM is the reset signal. When a
TRAM receives this signal, the transputer is reset to an initial state.
8 Transputer Motherboard User Manual TMB M 711
Using Transputer Modules
The transputer has to be in this state before a user program can be
loaded onto it.
There are two basic control architectures that are commonly used:
• the host computer controls all of the processors in the system.
This configuration is suitable for the Inmos toolsets and 3L
scientific languages where the various tools in the programming
environment (compilers, linkers etc.) are invoked from the host
computer. Figure 8 shows what this looks like.
control
host
TRAM 0
TRAM 1 TRAM n
Figure 8. Control architecture for 3L/toolset
• the host computer controls only one transputer - the root or
master transputer. This configuration is suitable for occam TDS
users and also for Inmos toolset users who wish to use the
interactive debugger, where a program (i.e. the TDS) runs on the
master processor while other processors in the network are
controlled from the master processor’s subsystem port and are
called a subnetwork. This enables TDS or the interactive
debugger to boot/debug the other processors. Figure 9 shows
the situation.
control
subsystem control
host
In order for the host computer to be able to control any transputers
the motherboard or transputer host interface board must be set up
correctly. See the relevant manual for your host
adaptor/motherboard.
TMB M 711 Transputer Motherboard User Manual 9
TRAM 0
TRAM 1 TRAM n
Figure 9. Control architecture for TDS
A More Complex Example
2.2.2.2 The Transputer Network
The only thing to be done here is to put in pipe jumpers where they
are needed. Some simple rules for determining when pipe jumpers
are needed follow:
1. If a large TRAM (greater than size 1) is in the middle of your
intended pipeline then the large TRAM will need its unused slots
jumpering.
2. If your motherboard is not fully populated and you wish to
continue the pipeline onto another motherboard, then the unused
slots on the motherboard will need jumpering.
2.3 A More Complex Example
This section shows how you could build up a TRAM network based
on a number of motherboards. A common example of this is driving
a number of slave TMB12 boards from a motherboard inside a PC.
The TMB12 doesn’t have a host computer interface and therefore
has to be slaved to a master.
There are three aspects to connecting up several motherboards:
1. Sorting out the control system
2. connecting up the transputers
3. connecting up the configuration pipeline
2.3.1 Control Aspects
The control architecture of the single motherboard now has to be
connected to other motherboards. Each motherboard has three
control ports for this purpose. They are called
down
.
The motherboards will normally be connected into a chain. Control is
fed into the up port of a board. Normally control is propagated out of
the down port. Hence, to connect up a chain the up port of one board
is connected to the down port of the next board.
The only exception to this rule arises when the first motherboard in
the system is considered. In this case it is desired to control a
subsystem from the master processor and the TRAMs on the slave
boards should be part of that subsystem. The subsystem port has
been provided for just this situation.
subsystem,up
and
10 Transputer Motherboard User Manual TMB M 711
Using Transputer Modules
Figure 10 shows a reset cable which is used to connect the control
ports of different boards together.
Down/Subsystem Up
reset
error
analyse
Figure 10. Reset Cable
Figure 11 shows the control connections for the simpler case of the
3L languages and figure 12 shows the connections for users of the
occam TDS or Inmos toolsets.
down
HOST
Figure 11. Control in multi-motherboard systems
SubSystem
HOST
Figure 12. Control in multi-motherboard systems (TDS)
2.3.2 Topology Aspects
up down
TMB12
up down
TMB12
up down
TMB12
up down
TMB12
In order for the transputers to communicate their links must be
connected together. In keeping with the pipeline connections made
within a single motherboard, when several motherboards are wired
up, all the transputers are connected into a single pipeline.
TMB M 711 Transputer Motherboard User Manual 11
A More Complex Example
This is achieved by connecting the end of the pipeline of one
motherboard to the beginning of the pipeline on the next
motherboard.
The start of the pipeline (slot 0 link 1) is called
the pipeline (slot n link 2) is called
PipeTail
PipeHead
. The end of
. Hence you must connect
the PipeTail of one board to the PipeHead of the next board.
Because the PipeT ail to PipeHead connection is actually a transputer
link, the cable used to make this connection is a standard INMOS link
cable. See figure 13.
ground
out
in
ground
ground
out
in
ground
Figure 13. Standard link cable
Figures 14 & 15 illustrate the required connections.
up down
TMB12
HOST
down
up down
TMB12
PipeTailPipeTail
PipeHeadPipeHead
Figure 14. The default pipeline in multi motherboard systems
12 Transputer Motherboard User Manual TMB M 711
Using Transputer Modules
SubSystem
HOST
up down
TMB12
PipeTailPipeTail
Figure 15. The default pipeline (TDS)
2.3.3 Network Configuration Aspects
A subject which has not been discussed fully in this chapter is that of
network configuration. This is the process of connecting up
transputer links to meet the network topology demanded by the
application.
The previous section has dealt with the default pipeline, but what
hasn’t been mentioned yet is how the user can connect up TRAM link
0s & 3s.
up down
TMB12
PipeHeadPipeHead
all
the
In fact, the connection of these links is extremely flexible. On most
motherboards there are electronic link switches which perf orm link0
- link3 connections. The link switches are controlled b y transputer(s)
on the motherboards called configuration transputers.
The configuration transputers from different motherboards are
connected together into a pipeline called the configuration pipeline
which is programmable. Transtech TRAM motherboards are shipped
with a software system the NCS (Network Configuration Software) to
program the link crossbars, Inmos boards are shipped with their own
system the MMS (Module Motherboard Software).
Hence, the remaining job to be done is to connect up the
configuration pipeline
setup the crossbar switches. Each motherboard has two pipeline
connections for this purpose called
Figures 16 & 17 show the details.
, a pipeline of T2 transputers that are used to
ConfigUp
and
ConfigDown
.
TMB M 711 Transputer Motherboard User Manual 13
Summary
down
HOST
PipeTail
ConfigDown
up down
TMB12
PipeHead
ConfigUp ConfigDown
PipeTail
up down
TMB12
PipeHead
ConfigUp
Figure 16. Configuration pipeline in multi motherboard systems
SubSystem
HOST
PipeTail
PipeHead
up down
TMB12
PipeTail
up down
TMB12
PipeHead
ConfigDown
Figure 17. Configuration pipeline in multi motherboard systems
The head of the configuration pipeline is connected to link 1 of TRAM
slot 0 of the first motherboard.
Chapter 3 contains a full description of network configuration.
2.4 Summary
This chapter has given a beginners ov erview of Transputer Modules
and module motherboards. Users should understand how to
construct single motherboard and multi motherboard computing
systems from TRAMs.
This chapter has given a statement of the actions to be perf ormed in
constructing TRAM based systems, often without explaining e xactly
ConfigUp ConfigDown
(TDS)
ConfigUp
14 Transputer Motherboard User Manual TMB M 711
Using Transputer Modules
why those actions are necessary . This is in k eeping with a beginners
introduction. For an explanation of the underlying system, read
Chapter 3 which gives details of the TRAM standard and can be
regarded as containing a conceptual model of TRAM equipment.
TMB M 711 Transputer Motherboard User Manual 15
Summary
16 Transputer Motherboard User Manual TMB M 711
Chapter 3
The TRAM Standard
This chapter forms a reference guide for TRAM equipment. It
describes the philosophy behind the TRAM standard before
describing Transputer Modules and Module motherboards. The
chapter discusses transputer networks and hierarchical control as
implemented on multiple motherboards.
The TRAM Standard
The nature of reference dictates that the information be detailed.
Inspite of this, all users should aim to understand most of the material
in this chapter in order to gain the most out of using their TRAM
equipment.
3.1 Introduction
The transputer is a general purpose computational element
packaged as a single chip. It contains special dedicated
communications circuitry which enables a complete computing
engine to be constructed from more than one device. In this sense,
the transputer is very much a building block of large parallel
computers. In keeping with the building block philosophy of
transputers the Transputer Module (TRAM) standard was evolv ed so
that transputer based computing could be purchased in a way that
allowed users to customize their computers to their particular
application.
The standard allows parallel machines to be constructed with a mix
of computational performance and memory tailored for a given
application. The flexibility of the standard allows other functionality to
be inserted into the parallel machine at the optimum place, for
instance disk, graphics and other input/output capability.
T o achie ve this the standard first defines the Transputer Module. This
is a small circuit board which will generally contain a transputer,
TMB M 711 Transputer Motherboard User Manual 17
The Transputer Module
some memory and some application specific circuitry. The TRAM is
in its own right a Dual-in-Line module which plugs into a purpose
designed TRAM motherboard. The motherboard (the second part of
the standard) provides power and link connectivity services to the
TRAMs mounted on it. Transtech’s range of motherboards support
up to 16 TRAMs on a single motherboard. The motherboard itself is
mounted inside a host computer. Transtech supply motherboards for
host computers with a PC AT Bus (IBM AT and all clones) or a VME
bus. as well as mother boards with no specific host interf ace but with
links to other motherboards.
3.2 The Transputer Module
3.2.1 Overview
A TRAM is a self contained computing subsystem. Physically it is
small and will contain either a transputer or some other device which
connects via INMOS links. TRAMs:
• interface to each other via INMOS links
• have a standard pinout
The basic size of a TRAM is 1.05" by 3.66" overall (2.67cm by
9.3cm). This basic size is referred to as Siz e 1. A size 1 TRAM is big
enough to contain a 30MHz T805 transputer with 4MBytes of
Dynamic RAM. Often TRAMs are larger than Size 1, e.g. a size 3
TRAM measures 3.15" by 3.66" (8.01cm by 9.3cm), which is big
enough for a 30Mhz T805 transputer and 16MBytes of Dynamic
RAM.
The properties of the TRAM ensure that the standard is independent
of:
• transputer type (e.g., T225, T425, T805)
• transputer speed (15 - 30MHz)
• peripheral function (i860 second processor, graphics output,
frame grabber, SCSI interface, etc.)
• memory size (32KBytes to 24MBytes)
3.2.2 Functional Description
3.2.2.1 Pinout of Size 1 Module
18 Transputer Motherboard User Manual TMB M 711
Figure 18 shows the pinout of a size 1 TRAM.
The TRAM Standard
Link2Out
Link2In
Vcc
Link1Out
Link1In
LinkSpeed A
LinkSpeed B
ClockIn (5MHz)
The TRAM brings out all four of the transputer’s links for connection
to other TRAMs.
speed of the transputer’s links. Asserting both of these pins high
causes the links to operate at 20Mbits/sec, deasserting both these
pins low causes the links to operate at 10Mbits/sec. Other
combinations of states of these two signals are illegal.
1
Link2 Link3
Link0Link1
16
Link3In
Link3Out
Gnd
Link0In
Link0Out
notError
Reset
Analyse
Figure 18. Pinout of Size 1 TRAM (not to scale)
LinkSpeedA
and
LinkSpeedB
control the operating
The transputer’s
from the TRAM. The reset and analyse signals are taken directly to
the transputer and allow the transputer to be programmed and
debugged. The error output from the transputer is buffered by a
transistor on the TRAM. This has the effect of in verting the signal (it
becomes
output. This allows wire-ORing of the error signals allowing any
TRAM to signal error back to the host computer.
The other pins of the TRAM provide power to the circuitry and a clock
for the transputer. Note that the input clock signal for the transputer
is multiplied by an on chip Phase Locked Loop to give the final
processor clock (typically 20 to 35 MHz).
notError
error,analyse
3.2.2.2 Subsystem Signals
In order to be able to manage a network of transputers the error,
analyse and reset signals are taken to the host computer. However ,
it is often convenient to be ab le to driv e these signals from a
transputer. These signals are collectively known as the
signals. Most TRAMs have a subsystem port which allows them to
and
reset
signals are brought out
) and also makes the signal an open collector
master
subsystem
TMB M 711 Transputer Motherboard User Manual 19
The Transputer Module
control a (sub)network of transputers. The subsystem port is shown
in figure 19.
1
SubsystemnotError
SubsystemReset
SubsystemAnalyse
16
Figure 19. Subsystem Pins
The subsystem port consists of three zero profile sockets on the
underside of the TRAM. In order to connect the subsystem to the
motherboard a special double ended subsystem port connector is
used. This is shown in figure 2.
This arrangement reflects the optionality of subsystem pins on the
TRAM and ensures that TRAMs fitted with subsystem pins are still
plug compatible with TRAMs not fitted with subsystem pins.
Details of how to program the subsystem port of a TRAM are
contained in the next section.
20 Transputer Motherboard User Manual TMB M 711
3.2.3 Electrical Description
The basic circuitry of a Transputer Module is shown in figure 20.
transputer
The TRAM Standard
linksIn
linksOut
NotError
Figure 20. Basic TRAM circuit
An explanation of the features of this circuit follows:
• Link inputs are protected from positive Electrostatic Discharge by
the inclusion of a signal diode taken to the positive supply rail. To
prevent unconnected link inputs floating a pull down resistor is
also included.
• Link outputs have a line resistance to match the output
impedance to that of the transmission line to which it is
connected.
• The
version of the transputer’s error flag.
Other connections require no special circuitry
3.3 The Transputer Module Motherboard
3.3.1 Overview
The module motherboard allows access to Transputer Modules from
a variety of host machines. The motherboard can usually be divided
into two distinct parts: the host specific interface part and the generic
TRAM part (although some motherboards do not have a host specific
interface).
The design goals of the motherboard standard were that the user
should be able to:
TMB M 711 Transputer Motherboard User Manual 21
NotError
output is an inverted, buffered open collector
The Transputer Module Motherboard
• build computing systems consisting of any mix of TRAMs
• configure the transputers into any topology
• chain a number of motherboards together
• run and test applications on transputers without first having to
configure the links
The architecture that was evolved to meet these requirements
consists of the following important features:
• the modules in a network are connected in a pipeline using two
links from each module
• the remaining links from each module are available for user
configuration either by direct wiring (via edge connectors) or via
a programmable link switch (IMS C004). When using C004
switches:
• a number of links are taken from the C004 to edge connectors
• each C004 is controlled by a T2 transputer
• the T2 transputers are connected together in a separate
pipeline
• the first module in the pipeline on a given motherboard can
control a subsystem of other modules that may reside on the
same motherboard, another motherboard or be distributed
across a number of boards (the first module requires a
subsystem port)
• an interface may be provided to allow non-transputer based host
computers to control and communicate with the TRAMs on the
motherboard.
The remainder of this section discusses the above f eatures in greater
detail.
3.3.2 Link Configuration
3.3.2.1 Pipeline
Transputer Modules are plugged into module slots on the
motherboard. The number of slots on a motherboard depends only
on the size of the motherboard. The slots are numbered from zero.
The modules on the motherboard are connected together into a
pipeline, as shown in figure 4.
Assuming for the moment that all TRAMs are size 1, then link2 of the
module in slot0 is connected to link1 of the module in slot1 (slots are
not necessarily connected in number order, see the product specific
22 Transputer Motherboard User Manual TMB M 711
The TRAM Standard
section of the manual for the order in which the y are connected), and
so on for the other slots on the motherboard. Link1 of module 0
(called
general brought out to the edge connector to allow pipelines to be
constructed across several motherboards (figure 21).
PipeHead
) and link2 of module n (called
PipeTail
) are in
PipeHeadPipeHead
Board0 Board1 Boardn
PipeTailPipeTail
Figure 21. Module pipeline split across several motherboards.
Not all applications will use all of the slots on the motherboard. Some
applications will require to use TRAMs which are larger than size1
(but only use one set of 16 pins for interfacing to the motherboard).
In both of these cases the pipeline will become broken. To avoid this
a special pipeline jumper is supplied which bridges the break (figure
5).
The pipe jumper plugs into unused slots (either on the motherboard
or on a TRAM) and connects link1 of that slot to link2 of that slot.
3.3.2.2 Programmable Link Configuration
Some motherboards have a n umber of C004 link crossbar switches
mounted on them. These are devices that allow the topology of the
interconnections between transputers to be set electronically under
software control.
PipeHead
PipeTail
The links 0 and 3 of each slot on the motherboard are taken to the
switches for programmable link connection. The degree of
interconnectivity achievab le depends on the number of slots and the
number of switches on the board. F or example, on the TMB12 16 slot
motherboard, two switches provide for 64 link connections.
3.3.2.3 The Configuration Pipeline
Each link switch is controlled by a 16 bit T2 transputer. Each T2 can
control up to two link switches via its links 0 and 3 (figure 22).
TMB M 711 Transputer Motherboard User Manual 23
The Transputer Module Motherboard
L1 L2
C004
Config
L0
T2ConfigUp ConfigDown
L3
Config
C004
ConfigUp
Figure 22. Control of the Link Configuration System
The other links are used to construct a pipeline of configuration
transputers. This pipeline ma y extend across a number of boards to
allow configuration to extend throughout a transputer system.
Connection to other boards is achieved by edge connections
ConfigUp
and
ConfigDown
(figure 23)
ConfigDown
ConfigDown
ConfigUp
Board0 Board1 Boardn
Figure 23. Multi-board configuration pipeline for TMB12’s
Usually the link switch configuration data will originate from the a
module on the first motherboard in the system. Hence one of the
links of that module must be connected to the first T2 of the
24 Transputer Motherboard User Manual TMB M 711
The TRAM Standard
configuration pipeline. Figure 24 shows the standard way of
achieving this: Link 1 of the module in site0 is taken via a link patch
to the T2. Note that this effectively terminates both
ConfigUp
.
Slot0
PipeHead
and
ConfigUp
Jumper
PipeHead
Link patch area
Figure 24. Controlling the configuration pipeline
3.3.2.4 Software for Link Configuration
To configure their network to a desired topology the user can
program the T2 pipeline directly or make use of the software system
or wiring files supplied with the board.
Note: Transtech module motherboards are currently supplied with
the NCS (network Configuration Software) for electronic link
configuration.
12
12
T2
3.3.3 System Control
The design requirements of the motherboard, part of the TRAM
standard, stated that a hierarchical control structure be provided to
control networks of transputers. In practice this allows networks to be
constructed out of subnetworks. An example might be where each
TRAM in a
transputers.
In order to control a transputer, only three signals are needed: a
signal to reset the transputer, a signal to analyse (statically debug)
the transputer and a signal from the transputer to indicate that an
error has occurred. These signals are collectively called the
subsystem signals.
TMB M 711 Transputer Motherboard User Manual 25
master
network controls its own subnetwork of
The Transputer Module Motherboard
The subsystem signals are driven by a master. The master controls
all downstream processors connected to these subsystem signals
(i.e. a subnetwork). Normally there are two types of master in a
transputer network: the host computer and modules fitted with
subsystem ports.
3.3.3.1 Source of Control
For control purposes the modules on a motherboard are divided into
two groups:
processor on a motherboard (T2 - if there is one) is included into the
latter of the above two g roups . Note that the error signal of the T2 is
left unconnected.
Within a motherboard there are options as to what source controls
the TRAMs on that motherboard:
• Module0 can be controlled from either the host computer or from
an external source,
module0
and
modules1 to n
. The configuration
• Modules1 to n can be controlled from either a host computer, a
module0 TRAM fitted with subsystem or an external source.
In general the external source will in fact be another motherboard.
The external source arrives on the motherboard at the
Hence module0 can be controlled either from the
host interface (if there is one). Modules1 to n are controlled either
from the up port, from the host computer interface or from module0’s
subsystem (figure 25).
Up Host subsystem
Board Control Select
Slot0 Slot0
control subsystem
up
connector.
up
port or from the
Down
Subsystem
Slot1 to n Control select
Slot0
26 Transputer Motherboard User Manual TMB M 711
Slot1 to n
Figure 25. Source of control
The two selection options (board control select & slot1 to n control
select) are altered by means of jumpers on the motherboard.
From figure 25 it can be seen that a subsystem of transputers
controlled by a master TRAM consists of modules1 to n on this
motherboard plus any modules on slaved motherboards. A
subsystem of transputers controlled by a host computer consist of all
the TRAMs on this motherboard plus any modules on slaved
motherboards.
3.3.3.2 Up, Down & Subsystem
Large networks are built up by connecting motherboards together.
For this purpose, each motherboard has three control ports:
up
•
•
(control in), source of external control,
down
(control out), echo of the up port,
The TRAM Standard
subsystem
•
port.
Figure 26 shows the control ports.
notUpReset
notUpAnalyse
Up port
Down port Subsystem port
notDownAnalyse
notDownReset
(control out), connected to module0’s subsystem
notUpError
Module motherboard
notDownError
notSubSystemReset
notSubSystemError
notSubSystemAnalyse
3.3.3.3 Multi-board Control
This section shows how the control ports are connected to map the
subnetwork model of transputer networks onto a number of module
motherboards.
TMB M 711 Transputer Motherboard User Manual 27
Figure 26. Module motherboard Up, Down and Reset
The Transputer Module Motherboard
The simplest relation between two motherboards is direct
connection.Motherboards can be chained together by connecting the
down port of one board to the up port of the next. In this case all the
boards in the chain are controlled from the same source, i.e.
whatever it is that controls the first motherboard in the chain.
The other type of relation between two motherboards is that of
master-slave. This allows the module0 of the first motherboard to
control a subnetwork of TRAMs, some of which may be on the
second motherboard. This is achieved if the subsystem port of the
first motherboard is connected to the up port of the second
motherboard.
Figure 27 shows a master network consisting of all the of processors
on
boarda
boarde
own subnetworks. The first subnetwork consists of the processor on
modules1 to n of
second subnetwork consists of the processors on modules1 to n of
boarde
, as well as the first processor on each of
. Two of the processors in this master network control their
boardb
and all the processors on
and all of the modules on
boardf/g
boardb
boardc/d
and
. The
.
a
Up
Sub
Down
system
bc
Up
Down
Sub
system
Up
Down
Sub
system
Up
Down
Sub
system
ef
Up
Down
Sub
system
Up
Down
Sub
system
Up
Down
Sub
system
Figure 27. Controlling a subsystem of boards
The notReset and notAnalyse signals flow from the subsystem of a
master board to the up port of a slave board. From there they are
connected directly to the down port of the slave board. Hence reset
and analyse are connected to all boards in a chain allowing the
master to control all processors without hindrance. E.g. boardc can
be reset/analysed by boarda without interference b y boardb in figure
27, above.
d
g
28 Transputer Motherboard User Manual TMB M 711
The TRAM Standard
The notReset and notAnalyse arriving at the slave’ s up port are also
sent to the slave’s subsystem port, but in this case the signals are
logically OR-ed with the analyse and reset signals of the boards’s
subsystem. This means that a board may be reset/analysed by its
own master OR by the master of that master. E.g.
controlled by either
The notError signal is treated similarly, but flows in the opposite
direction. The error from a module on a motherboard is passed to the
up port of that motherboard. It is logically OR-ed with any notError
signal arriving at that boards down port. This allows error signals to
propagate back to the master - it also means that ANY processor in
a subsystem can send an error to the master. E.g. processors on
boardc/d
above.
The notError signal arriving at a subsystem port is not propagated to
the up port, but is handled by that board. It is assumed that a
subsystem master can handle errors in its own subsystem.
can send error back to their master (
boardb
or
boarda
in figure 27, above.
Boardd
boardb
can be
) in figure 27,
3.3.3.4 Subsystem Registers
When the source of control is a transputer module in site 0 of some
motherboard then the transputer on that module has control of the
subsystem via its subsystem pins. These pins are driven by
subsystem registers on the TRAM which are in turn mapped into the
transputer’s memory map.
For 32 bit transputers the memory mapping is as follows:
Register Mode Hardware byte address
SubsystemResetLatch Write Only #00000000
SubsystemAnalyseLatch Write Only #00000004
SubsystemError Read Only #00000000
Table 1: memory-mapped registers
The operation of the registers is as follows:
• Writing a 1 into bit 0 of SubsystemResetLatch asserts
subsystemReset
• Writing a 0 into bit 0 of SubsystemResetLatch deasserts
subsystemReset
TMB M 711 Transputer Motherboard User Manual 29
;
;
Host Computer Interface
• Writing a 1 into bit 0 of SubsystemAnalyseLatch asserts
subsystemAnalyse
• Writing a 0 into bit 0 of SubsystemAnalyseLatch deasserts
subsystemAnalyse
• Reading a 1 from bit 0 of SubsystemErrorLatch indicates that
subsystemError
• Reading a 0 from bit 0 of SubsystemErrorLatch indicates that
subsystemError
The subsystem is reset/analysed under control of the transputer on
the TRAM. However, the subsystem must be reset when the TRAM
is reset. As already described the following combinational logic is
used to propagate the subsystem signals:
• SubsystemReset = UpReset OR SubsystemResetLatch
;
;
is TRUE;
is FALSE;
• SubsystemAnalyse = UpAnalyse OR SubsystemAnalyseLatch
• SubsystemError does NOT propagate
Because of filtering on the motherboard it is recommended that when
resetting/analysing subsystems the corresponding signal is held
asserted for at least 5 ms. In the case of reset, the subsystem should
be left for a further 5 ms before attempting to boot it.
3.4 Host Computer Interface
Most motherboards have an interface to a host computer. The host
supplies file services and terminal IO to application programs
running on the transputer network. Clearly the structure of the host
interface is not generic - the remainder of this section discusses the
standard PC interface f or PC AT machines and clones. This interface
is commonly referred to as a “B004” interface.
3.4.1 Host IO Space
In PC machines interface hardware is mapped into a special address
space called the IO space. The driver program running on the PC
uses this address space to talk to the add-in card.
The module motherboard employs a bloc k of addresses within the IO
space.It is possible to locate the base of this b lock at one of a number
of places in this address space so as to prevent conflicts with other
add-in cards. By default the base address is150 hex.
30 Transputer Motherboard User Manual TMB M 711
The TRAM Standard
A summary of the register addresses used within the block used is
given in table 2. These are all explained in greater detail in the
following sections.
IO Address Register
boardbase + #00 InputDataRegister
boardbase + #01 OutputDataRegister
boardbase + #02 InputStatusRegister
boardbase + #03 OutputStatusRegister
boardbase + #10 Reset register (write only)
boardbase + #11 Analyse register (write only)
boardbase + #10 Error register (read only)
boardbase + #12 DMA request register
boardbase + #13 Interrupt control register
Table 2: IO Registers
TMB M 711 Transputer Motherboard User Manual 31
Host Computer Interface
3.4.2 Link Interface
The link interface employs an IMS C012 link adapter chip. This
device converts between an 8 bit bidirectional port on one side and
a transputer serial link on the other, see figure 28.
PC IO
Bus
8
Link engine
Input data
register
Input status
register
Output data
register
Output status
register
8
Figure 28. Logical structure of the C012 link adapter
The four registers of the C012 are mapped into the first four
addresses in the board’s IO space.
Data arriving at the C012 from the serial link is latched into the
InputDataRegister. A flag in the InputStatusRegister is set to indicate
that the contents of the data register are valid. Current servers poll
this flag in software to see if any data has arrived. When the data
register is read the flag in the status register is cleared.
Output to the link from the PC follows a similar pattern. An
in the OutputStatusRegister indicates whether the
OutputDataRegister can be written to. Current servers poll the in use
flag in software, sending a byte to the data register as soon as the
link becomes free (i.e. the last byte has been sent).
The C012 link connects to link 0 slot0, and on some motherboards it
can be connected to the edge connector, allowing the board to be
used as a link adaptor to communicate with external transputer
systems.
32 Transputer Motherboard User Manual TMB M 711
in use
flag
3.4.3 System Control Interface
The next three registers in the IO space are the system control
registers. In terms of function they are identical to the subsystem
latches on some TRAMs. Only bit 0 of these registers is used:
Reset register: setting bit 0 to ‘1’ asserts Reset to the
motherboard, clearing bit 0 to ‘0’ deasserts
Reset.
Analyse register: Setting bit 0 to ‘1’ asserts analyse to the
motherboard, clearing bit 0 to ‘0’ deasserts
analyse.
Error register: Reading a ‘1’ from bit 0 indicates an Error
on the motherboard, Reading a ‘0’ from bit
0 indicates no Error.
The TRAM Standard
3.4.4 Interrupts and DMA
Two other registers are provided on Transtech’s range of
motherboards are not part of the basic “B004” interface. The two
other registers provide support for allowing DMA access to the link
hardware. This overcomes the inherent inefficiency of software
polling for every single byte read or written to the link adapter,
however these features are not often used. No standard software
from Transtech uses these features.
The PC contains a DMA controller chip (the 8237) which is employed
for these high speed transfers. A DMA transfer to the to the
motherboard is initiated by writing a ‘0’ to the DMA request register.
A DMA transfer from the motherboard is initiated by writing a ‘1’ to
the DMA request register.
To discover when the DMA has completed it is possible to poll the
status of the DMA controller chip. However, a better method is to
generate an interrupt to the PC. For this purpose the last register in
the motherboard IO space is the interrupt control register. This
register is a mask register allowing the PC to be interrupted on any
combination of four events. Figure 29 shows the structure of this
register.
TMB M 711 Transputer Motherboard User Manual 33
Host Computer Interface
To allow an interrupt on any of these sources write a ‘1’ to the
relevant bit position. To inhibit an interrupt on any of these sources
write a ‘0’ to the relevant bit position.
bit 0bit 1bit 2bit 3
End of DMATransputerLink dataLink data
transfererror input readyoutput ready
Figure 29. Interrupt control mask register
Once the PC has been interrupted the interrupt handler must
determine the source of the interrupt. This can be done by reading
the Input/OutputStatusRegisters, the Error register and the status
registers on the DMA controller chip.
3.4.5 DMA & Interrupt Channels
There is a small degree of flexibility in terms of the interrupt channel
and DMA channel that can be used within the PC: the DMA channel
can be set to 1 or 2 and the interrupt channel can be set to 3 or 6.
DMA channel 1 is often used by ethernet or other networking cards.
DMA channel 2 is used by the PC to communicate with the floppy
disk controller. It is possible to share DMA channel 2 with the floppy
disk controller by careful programming of the floppy disk controller
enable flag located at IO address space #3F2. Whenever a floppy
disk access is about to take place the BIOS alwa ys enables location
#3F2. Hence to use DMA channel 2, the software must disable the
controller (by writing a zero to the enable flag) and enable its own
drivers. At the end of the DMA transf er the softw are m ust disab le its
own drivers.
The floppy disk subsystem also uses interrupt channel 6. The floppy
disk uses this interrupt channel to notify the PC that it is inactive and
as such the PC can switch off the “in use” lamp on the front panel.
The interrupt is generated about two seconds after the last disk
access. Any software using this interrupt channel, should be able to
handle such interrupts (or be able to guarantee that such interrupts
cannot arrive).
34 Transputer Motherboard User Manual TMB M 711
Chapter 4
The TMB03 Motherboard
This chapter gives a detailed hardware description of the TMB03.
The various features of the board are described and some examples
of configuration are given.
The TMB03 Motherboard
The TMB03 is a small PC hosted TRAM motherboard, with space to
plug in up to five Transputer Modules. It has a dummy site allowing a
size six TRAM to be fitted
It is possible to use the TMB03 without TRAMs as a driver board (PCto-link adapter) for e xternal transputer systems via the master link on
the edge connector.
Figure 30 shows the layout of this board for reference.
Board configuration jumpers
slot 1
slot 2slot 0 slot 4slot 3
TMB M 711 Transputer Motherboard User Manual 35
C012
Figure 30. Layout of the TMB03
37 way D-type
edge connector
Board Configuration Jumpers
4.1 Board Configuration Jumpers
This section describes the various board configuration settings and
TMB03 specific functionality.
Most of the configuration options are adjusted by the means of a
jumper block at the top right corner of the board which is shown in
figure 31 for reference.
IBM/UP
Mod0SS
AS0
AS1
10MB/s
MS
Figure 31. Board configuration jumpers
The jumpers are briefly described below, and in detail in the f ollowing
sections.
IBM/UP The source of control f or the TRAM in slot0
can be from either the host PC or from the
edge connector (UP).
Mod0SS The TRAMs in slots 1, 2, 3 & 4 can be
controlled either from the subsystem of the
TRAM in slot 0 or from the source which
controls slot 0.
AS0/AS1 The board’ s IO address can be set to #150,
#200 or #300.
10MB/s The transputer link speeds can be set to
M & S Allow the board to be used as a
36 Transputer Motherboard User Manual TMB M 711
10MHz or 20MHz.
Slave
board.
Master
or
4.1.1 Control Configuration
The board’s control configuration jumpers, IBM/UP and Mod0SS,
allow the source of control for the module in slot 0 and the modules
in slots 1, 2, 3 & 4 to be determined. The control consist of the TRAM
signals reset, error and analyse.
Jumper in/out Description
IBM/UP out Slot 0 is controlled by the PC (default)
in Slot 0 is controlled by the edge
Table 3: Slot 0 control selection
The TMB03 Motherboard
connector up port
Jumper in/out Description
Mod0SS out Slots 1 to 4 are controlled from the Slot
in Slots 1 to 4 are controlled from the same
Table 4: Slots 1 to 9 control selection
4.1.2 Board IO Address
Configuration of the board IO base address is achieved via jumpers
AS0, AS1, as follows:
AS0 AS1 Description
in in Base address 150 hex (default)
in out Base address 200 hex
0’s subsystem port
source as Slot 0 (default)
out in Base address 300 hex
TMB M 711 Transputer Motherboard User Manual 37
Table 5: Base address select jumper
Board Configuration Jumpers
4.1.3 Link Speed Configuration
The link speed select jumper controls the speed of all transputer links
on the board.
Jumper in/out Description
10MB/s out 20 MBits/s (default)
in 10 MBits/s
Table 6: Link speed selection jumper
4.1.4 Master and Slave Configuration
The TMB03 can be used either as a master board or a slave board.
In master configuration the TMB03 behaves as an ordinary TRAM
motherboard with module0 link0 connected to the PC via C012
interface circuitry. It also acts as a PC link interf ace board to connect
to external transputers, with no TRAMs on the TMB03.
In slave configuration, module0 link0 is connected to the edge
connector providing a further mechanism to chain motherboards
together. (The normal PipeTail - PipeHead connection can be made
regardless of the master/slave configuration.)
By altering the M/S jumpers it is possible to connect module0 link0 to
the edge connector as an external link,
removed
removal.
Connect TRAM slot 0 link
0 to the host link (default)
Connect host link to
external transputer
Connect external
transputer to slot 0 link 0
from the board. The C012 is socketed to allow easy
Desired Configuration Required setup
M/S jumpers set to M, nothing
connected to master edge link,
TRAM in slot 0, C012 fitted
M/S jumpers set to M, link cable
connected to master edge link,
nothing in slot 0, C012 fitted
M/S jumpers set to S, link cable
connected to master edge link,
TRAM in slot 0, C012 removed
as long as the C012 is
Table 7: Host link, Slot 0 link 0, and Master edge link options
38 Transputer Motherboard User Manual TMB M 711
The TMB03 Motherboard
Figure 32 shows the effect of these jumpers and figure 33 shows
their use.
MASTER configuration
link out
C012
link in
link0 in
module0
L0 out
master outmaster in
SLAVE configuration
link0 in
module0
master in
link0 out
master out
Figure 32. Board Master & Slave Configuration
MASTER
(default)
M
S
SLAVE
M
S
Figure 33. Master & Slave Configuration options
IMPORTANT: note that to use the board configured as a slave
according to figure 32, the C012 chip must be removed. See
figure 30 on page 35 for the location of the C012.
Permanent damage may result if you do not remove the C012
when configuring the TMB03 as a slave, or if you use the master
TMB M 711 Transputer Motherboard User Manual 39
Board Configuration Jumpers
edge link when a TRAM is fitted in slot 0 and the board is
configured as a master.
4.1.5 IRQ & DMA Selection
The default connections are to use DMA channel 1 and interrupt line
3. These defaults are made by actual copper tr acks on the surface of
the printed circuit board. To alter the defaults, cut the existing tracks
and hook up the solder pads as required. It is possible to configure
the board to use DMA channels 1, 2 or 3 and to use interrupts 3, 4,
5, 6, 7 or 9. To disable the Interrupts and DMA, just cut the tracks.
Your warrantee will not be affected by cutting the tr ac ks or soldering
between the solder pads.
Figure 34 shows the area and details the default connections.
IRQ9
DMA2 (in)
DMA3 (out)
DMA3 (in)
DMA1 (out)
DMA1 (in)
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DMA2 (out)
DMA (out)
DMA (in)
IRQ
Figure 34. Selection pins for Interrupt/DMA channel.
40 Transputer Motherboard User Manual TMB M 711
4.2 The Edge Connector
On the right hand edge of the TMB03 is a 37-way D-type edge
connector. On the TMB03 the edge connector is used for two
purposes:
• connecting to other motherboards control signals (via up, down
and subsystem)
• connecting transputer links to construct the desired network
topology.
Figure 35 shows the pinout of the edge connector.
downError
downReset
master linkout
module4 link2out
subsystemAnalyse
module4 link3in
module4 link0in
GND
module3 link3out
module3 link0out
module2 link3 out
module2 link0in
module1 link3in
module1 link0in
GND
module0 link3out
module0 link1out
upAnalyse
GND
19
18
17
16
15
14
13
12
11
10
The TMB03 Motherboard
37
downAnalyse
36
master linkin
35
module4 link2in
34
subsystemError
33
subsystemReset
32
module4 link3out
31
module4 link0out
30
module3 link3in
29
module3 link0in
28
9
8
7
6
5
4
3
2
1
module2 link3in
27
GND
26
module2 link0out
25
module1 link3out
24
module1 link0out
23
module0 link3in
22
module0 link1in
21
upError
20
upReset
TMB M 711 Transputer Motherboard User Manual 41
Figure 35. D-type pinout
The Edge Connector
Included in the accompanying cable pack is a mini-bac kplane board
(“hedgehog”) which plugs into the edge connector and brings out the
various links and ports onto standard connectors which accept link
cables and reset cables. The pinout of this connector is shown in
figure 36.
DN
SU
L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
UP
circuit board
stencilling
down
subsystem
master link
module4 link2 (PipeTail)
module4 link3
module4 link0
module3 link3
module3 link0
module2 link3
module2 link0
module1 link3
module1 link0
module0 link3
module0 link1 (PipeHead)
up
Function
Figure 36. Connections on break out board
Essentially, the connector brings out the three control ports, the
link0s and link3s of all the transputers (for network configuration) and
the ends of the default pipeline. This is summarized for reference
purposes in figure 37.
42 Transputer Motherboard User Manual TMB M 711
The TMB03 Motherboard
L0
L1
S0
3
12
0
L3
S1
3
12
0
L2
Host
L11
PC
Figure 37. Summary of Network interconnect
4.2.1 Use of the master link
L5
S2
3
12
0
L4
L7
S3
3
12
0
L6
L9
S4
3
12
0
L8
L10
The TMB03’s master link pro vides extra functionality o ver the normal
PC motherboards. Howe v er, care must be e xercised in its use so as
not to damage the hardware. Below is a list of all of the valid
configurations:
• board set to master mode, master link not connected to anything
& one or more TRAMs plugged onto the board - normal
operation.
• board set to master mode, master link connected to an external
rack of transputer equipment & no TRAM in slot0 of the board use as a link adapter card.
• board set to slave mode, master link optionally connected to
external transputer equipment, one or more TRAMs plugged onto
the board & the C012 removed - slave use.
4.3 Example
The default configuration of the TMB03 is suitable for stand-alone
operation with software such as the Inmos Toolsets and 3L. The
TMB M 711 Transputer Motherboard User Manual 43
Example
example given here shows to configure a system consisting of two
TMB03s in the same PC. In this case:
• the two boards must have different addresses
• one board must be slaved to the other
• the default pipeline needs to be connected
Set the jumpers as follows:
Jumper First board Second board
IBM/UP out in
Mod0SS in in
AS0 in out
AS1 in in
10MB/s out out
M/S M M
Table 8: Jumper settings for two TMB03s
Fit TRAMs in all sites (using pipe-jumpers on unused slots and on the
inactive slots of TRAMs larger than size 1). No subsystem pins are
needed.
Fit the boards in your PC, and using the “hedgehog” breakout
boards, make the following connections:
Cable First board Second board
Reset Cable Down Up
Link Cable Pipetail (L10) Pipehead (L0)
Table 9: Connections between TMB03s
Power on the PC and run check.
When connecting the TMB03 to motherboards which include
electronic link switching, then the TMB03’ s PipeHead could be used
as ConfigDown (i.e. it may be connected to ConfigUp of the
configurable motherboard).
44 Transputer Motherboard User Manual TMB M 711
Chapter 5
The TMB04 Motherboard
The TMB04 is a transputer board for PCs with a single T4 or T8
transputer , up to 16 MBytes of memory in SIMMs, a B004-compatible
PC link interface, and four TRAM sites.
The TMB04 Motherboard
The board has been designed to support transputer clock speeds
from 17.5 to 35 MHz, and the memory access time can be set to 3,
4, 5 or 6 cycles. This allows the matching of many different speeds
of memory device to different speeds of transputer.
Figure 38 shows the location of the various jumpers and s witches on
the board.
SW1
SW3
3
memory
LK5
LK6
T805
slot0slot1slot2slot
LK11
TMB M 711 Transputer Motherboard User Manual 45
LK12
Figure 38. Layout of the TMB04
SW2
Fitting TRAMs
5.1 Fitting TRAMs
Up to 4 size one TRAMs may be fitted to the TMB04, and the general
considerations discussed in section 2.2 apply. However note that:
• the TRAM sites are arranged sequentially (so pipe jumpers are
needed if you have TRAMs larger than size one),
• there are large components under the TRAM sites, so SIL spacer
strips are needed. When a TRAM is placed over the on-board
transputer (in slots 0 and 1), and the TRAM has components on
its underside, use of an additional set of spacers is
recommended to avoid overheating the transputer,
• there are no holes in the board, so the TRAMs cannot be secured
with nylon bolts.
5.2 Fitting memory
The TMB04 can be fitted with 4, 8, 12 or 16 SIMMs, which can be
either 256 KByte or 1 MByte. The board is normally supplied with 60
or 70 ns SIMMs. Memory should be expanded in the sequence
shown below - populating the SIMM slots in numerical order (the
numbers are printed on the PCB):
13 9 5 1 16 12 8 415 11 7 314 10 6 2
See section 5.3.1 below for setting the memory speed selection
switches.
46 Transputer Motherboard User Manual TMB M 711
Figure 39. SIMM slot numbering.
The TMB04 Motherboard
5.3 Board Configuration Jumpers
This section describes the various board configuration settings and
TMB04 specific functionality.
The jumpers and switches are briefly described below, and in detail
in the following sections.
SW1 DMA and IRQ selection, IO base address
selection, C012 and TRAM slot link speed
selection, reset subsytem selection.
SW2 On-board transputer clock speed and link
speed selection.
SW3 Memory speed selection.
LK5 Connect transputer link 0 to host or edge
connector.
LK6 The source of control for the on-board
transputer can be from either the host PC
or from the edge connector (UP).
LK11 Selects the size of the memory SIMMs.
LK12 The TRAMs in slots 0 to 3 can be controlled
either from the subsystem of the on-board
transputer or from the source which
controls the transputer.
In the following sections , it is assumed that you are holding the board
component side up, with the PC bus edge connector pointing
towards you and the D-type connector to the right.
The jumper groups LK5 and LK11 each consist of two jumpers, and
LK6 and LK12 each consist of three jumpers. Each jumper can be in
left
and
right
one of two positions, referred to as
the jumper connects the central pin to the pin on the left, while in the
right position it connects the central pin to the one on the right. All
jumpers in a jumper group must be in the same position (left or right).
Each of the switch blocks consists of several switches, numbered
from one at the top, downwards. The switches are
switch is moved to the right and
switch numbers and the on position are marked on the s witch bloc ks.
off
when it is moved to the left. The
. In the left position
on
when the
TMB M 711 Transputer Motherboard User Manual 47
Board Configuration Jumpers
5.3.1 On-board transputer clock and memory
The processor clock speed of the on-board transputer is selected by
SW2, switches 4, 5 and 6, as follows. You may set a clock speed
slower than that marked on the transputer, but not faster.
SW2.4 SW2.5 SW2.6 Processor clock
on off off 17.5 MHz
on on on 20 MHz (default)
on off on 25 MHz
off off on 30 MHz
Table 10: Processor clock speed select
The number of cycles taken to access local memory of the on-board
transputer can be selected by SW3. The correct setting depends on
the SIMM’s ro w access time (T
), the clock speed of the transputer
RAC
(as set by SW2), and on the number of SIMMs fitted.
Processor
clock
SIMM
speed
Cycles
SW
3.1
SW
3.2
SW
3.3
SW
3.4
20 MHz 70 ns 3 on off off off
25 MHz 60 ns
30 MHz 40 ns
20 MHz 90 ns 4 off on off off
25 MHZ 70 ns
30 MHz 60 ns
20 MHz 120 ns 5 off off on off
25 MHz 90 ns (default)
30 MHz 70 ns
Table 11: Memory access time selection (up to 8 MBytes)
48 Transputer Motherboard User Manual TMB M 711
6 off off off on
The TMB04 Motherboard
If more than 8 MBytes of memory is fitted, add one memory cycle to
the above.
Note that only one switch of SW3 should be on, or improper
operation will result.
Jumper bloc k LK11 selects the memory size of each SIMM fitted, as
follows:
Jumper Position Description
LK11 Left Memory is in 1 MByte SIMMs (default)
Right Memory is in 256KByte SIMMs
Table 12: SIMM size selection jumper
5.3.2 Control Configuration
The board’s control configur ation jumpers, LK6 and LK12, allow the
source of control for the on-board transputer and the modules in slots
0 to 3 to be determined. The control consist of the TRAM signals
reset, error and analyse.
Note that subsystem pins are not needed with the TMB04 - the onboard transputer acts as the master , and it’ s subsystem port is wired
directly to the jumpers.
Jumper Position Description
LK6 Left Transputer is controlled by the PC
Right Transputer is controlled by the edge
Table 13: On-board transputer control jumper
(default)
connector up port
TMB M 711 Transputer Motherboard User Manual 49
Board Configuration Jumpers
Jumper Position Description
LK12 Left Slots 0 to 3 are controlled from the
Right Slots 0 to 34 are controlled from the
Table 14: On-board transputer subsystem jumper
By default, the reset line of the on-board transputer’s subsystem is
asserted whenever the on-board transputer is reset. However, the
TMB04 allows you to disable this beha vior, so the TRAM slots are not
reset when the on-board transputer is reset.
transputer’s subsystem port (default)
same source as the transputer
Switch Position Description
SW1.8 on transputer’s reset is copied to
off transputer’s reset is not copied to
Table 15: On-board transputer subsystem reset handling
5.3.3 Board IO Address
Configuration of the board IO base address is achieved via switch
SW1, as follows:
SW1.4 SW1.5 Description
off on Base address 150 hex (default)
on off Base address 200 hex
subsystem (default)
subsystem
off off Base address 300 hex
on on Host link interface disabled
50 Transputer Motherboard User Manual TMB M 711
Table 16: Base address select switch
5.3.4 Link Speed Configuration
The speeds of various links on the board are set by switches as
follows. Wherever two links are connected, they must be set at the
same speed.
Switch Position Description
SW1.6 on C012 link at 10 MBits/s
off C012 link at 20 MBits/s (default)
Table 17: C012 link speed selection switch
Switch Position Description
The TMB04 Motherboard
SW1.7 on Links at 10 MBits/s
off Links at 20 MBits/s (default)
Table 18: TRAM slots 0 to 3 link speed selection switch
SW
2.1
on on on 10 MBits/s 10 MBits/s
on on off 10 MBits/s 5 MBits/s
on off on 5 MBits/s 10 MBits/s
on off off 5 MBits/s 5 MBits/s
off on on 10 MBits/s 10 MBits/s
off on off 10 MBits/s 20 MBits/s
off off on 20 MBits/s 10 MBits/s
SW
2.2
SW
2.3
on-board transputer
link 0
on-board transputer
links 1 to 3
off off off 20 MBits/s (default) 20 MBits/s (default)
Table 19: Master transputer link speed selection switch
TMB M 711 Transputer Motherboard User Manual 51
Board Configuration Jumpers
5.3.5 Master and Slave Configuration
Link 0 of the on-board transputer may be connected either to the PC
interface or to the D-type connector.
Jumper Position Description
LK5 Left transputer link 0 connected to PC
interface (default)
Right transputer link 0 connected to D-type
connector (L0 on the hedgehog)
Table 20: On-board transputer link 0 jumper
5.3.6 IRQ & DMA Selection
The DMA channel and IRQ number can be set using SW1 as follo ws:
SW1.1 SW1.2 Description
on on No DMA channel
off on DMA channel 1 (default)
on off DMA channel 2
off off No DMA channel
Table 21: DMA channel selection switch
Switch Position Description
SW1.3 on IRQ number 3 (default)
52 Transputer Motherboard User Manual TMB M 711
off IRQ number 6
Table 22: IRQ number selection switch
5.4 The Edge Connector
On the right hand edge of the TMB04 is a 37-way D-type edge
connector. On the TMB04 the edge connector is used for two
purposes:
• connecting to other motherboards control signals (via up, down
and subsystem)
• connecting transputer links to construct the desired network
topology.
Figure 40 shows the pinout of the edge connector.
downError
downReset
slot 0 link 3 out
slot 3 link 2 out
subsystemAnalyse
slot 0 link 1 in
slot 3 link 3 in
GND
slot 3 link 0 out
slot 2 link 0 out
slot 1 link 0 out
slot 0 link 0 in
transputer link 3 in
transputer link 2 in
GND
transputer link 1 out
transputer link 0 out
upAnalyse
GND
19
18
17
16
15
14
13
12
11
10
The TMB04 Motherboard
37
downAnalyse
36
slot 0 link 3 in
35
slot 3 link 2 in
34
subsystemError
33
subsystemReset
32
slot 0 link 1 out
31
slot 3 link 3 out
30
slot 3 link 0 in
29
slot 2 link 0 in
28
9
8
7
6
5
4
3
2
1
slot 1 link 0 in
27
GND
26
slot 0 link 0 out
25
transputer link 3 out
24
transputer link 2 out
23
transputer link 1 in
22
transputer link 0 in
21
upError
20
upReset
TMB M 711 Transputer Motherboard User Manual 53
Figure 40. D-type pinout
The Edge Connector
Included in the accompanying cable pack is a mini-bac kplane board
(“hedgehog”) which plugs into the edge connector and brings out the
various links and ports onto standard connectors which accept link
cables and reset cables. The pinout of this connector is shown in
figure 41.
DN
SU
L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
UP
circuit board
stencilling
down
subsystem
slot 0 link 3
slot 3 link 2 (PipeTail)
slot 0 link 1
slot 3 link 3
slot 3 link 0
slot 2 link 0
slot 1 link 0
slot 0 link 0
transputer link 3
transputer link 2
transputer link 1
transputer link 0
up
Function
Figure 41. Connections on break out board
Essentially, the connector brings out the three control ports, the
link0s and link3s of all the transputers (for network configuration) and
the ends of the default pipeline. This is summarized for reference
purposes in figure 42.
Note that to connect a link of the on-board transputer to one of the
TRAM slots, the link must be looped back at the D-type, or made
using a link cable and the hedgehog - there are no links connecting
the transputer to the TRAM sites on the board.
54 Transputer Motherboard User Manual TMB M 711
The TMB04 Motherboard
L1
L3
on-board
transputer
3
12
0
Host
PC
L2
L11
L9
S0
3
12
0
L4
S1
3
12
0
S2
3
12
0
L5 L6 L7
L0
Figure 42. Summary of Network interconnect
L8
S3
3
12
0
L10
TMB M 711 Transputer Motherboard User Manual 55
The Edge Connector
56 Transputer Motherboard User Manual TMB M 711
Chapter 6
The TMB08 Motherboard
This chapter gives a detailed hardware description of the TMB08.
The various features of the board are described and some examples
of configuration are given.
The TMB08 Motherboard
6.1 Overview
The TMB08 is a full length PC hosted TRAM motherboard, with
space to plug in up to ten Transputer Modules.
The TMB08 is shipped with an IMSC004 link switch, which provides
for setting up user defined topologies. The switch is flexible enough
to allow any TRAM’ s link 0 or 3 to be connected to any other TRAM’ s
link 0 or 3 or any one of eight edge connections.
The TMB08 has a link patch area which, amongst other things,
allows
Figure 43 shows the TRAM layout of this board for reference.
slot
1
PipeHead
and
ConfigUp
slot
2345 6 78
to be connected together.
slot
slotslot slot slot slotslot
0
slot
9
TMB M 711 Transputer Motherboard User Manual 57
Figure 43. TMB08 TRAM layout
Network Configuration
Figure 44 shows the board layout for reference.
Board configuration switches
Link Patch area
Programming header for manufacturer
use only
37-way D-type edge connector
Figure 44. TMB08 board layout
6.2 Network Configuration
This section provides an overview of network configuration on the
TMB08. It describes the wiring of the electronic link switch, the patch
area and shows the relationship between these and the edge
connector.
6.2.1 Electronic Link Configuration
This section describes the organization of the electronic link switch,
the IMSC004.
In this application the C004 is used simply as a crossbar switch. The
device is connected to 30 links, and can s witch any link connected to
any other link connected.
The links connected to the C004 are:
• link0 of all TRAM slots except module0 (module0 link0 is always
connected to the host PC),
• link3 of all TRAM slots,
• link 0 of the T2 configuration processor,
58 Transputer Motherboard User Manual TMB M 711
The TMB08 Motherboard
• eight edge connectors,
• two spare links, which are taken to the patch area.
The C004 is programmed via the T2 configuration processor on the
board. This in turn is programmed via
ConfigUp
The connections are shown in figure 45 for reference.
IMS C004
.
module1 L0
module2 L0
module3 L0
module4 L0
module5 L0
module6 L0
module7 L0
module8 L0
module9 L0
module0 L3
module1 L3
module2 L3
module3 L3
module4 L3
module5 L3
link1
link2
link3
link4
link5
link6
link7
link8
link9
link10
link11
link12
link13
link14
link15
link16
link17
link18
link19
link20
link21
link22
link23
link24
link25
link26
link27
link28
link29
ConfigLink
L3
ConfigUp ConfigDown
L1 L2
Configuration
Processor
module6 L3
module7 L3
module8 L3
module9 L3
edge0
edge1
edge2
edge3
edge4
edge5
edge6
edge7
C004 L28
C004 L29
TMB M 711 Transputer Motherboard User Manual 59
L0
IMSC004 Link 0
Figure 45. C004 Wiring
Network Configuration
6.2.2 The Link Patch Area
The link patch area is a 6x2 jumper header on 0.1" spacing. The
required connections can be made by moving push-on shorting links
to the correct positions
The primary purpose of the patch area is to allow
ConfigUp
either connect these two together (for the first motherboard in a
system) or to take them off the board (for a slave motherboard).
The links taken to the patch area are:
ConfigUp
•
PipeHead
•
• two of the links from the crossbar switch (
• two links which are taken directly to the edge connector
(
Figure 46 shows the links attached to the patch area and the default
connections made when the board is shipped.
to be terminated correctly . Using the patch it is possib le to
, i.e., link1 of the configuration processor
. i.e., Module0 link1
patch0/1
)
C004 L29
patch1
slot0 link1
T2 Config
patch0
PipeHead
C004L28/29
C004 L28
and
)
60 Transputer Motherboard User Manual TMB M 711
L0
root
module0
PC
Root module can setup C004
L1
L1
T2
L3
C004
Figure 46. The Link Patch Area for Master Board
C004 L29
patch1
slot0 link1
T2 Config
The TMB08 Motherboard
patch0
C004 L28
edge
module0
L1
root
T2
L1
edge
L3
C004
Figure 47. TMB08 Patch Area, connections for slave board
TMB M 711 Transputer Motherboard User Manual 61
Description
6.2.3 Summary of Network Configuration
Figure 48 shows the interconnection between the module slots, the
electronic link switch, the link patch area and the edge connector. It
is included for reference.
Edge connector
patch
PC link
ConfigUp
C004 L28/29
3
1
slot
0
0
edge0 to 7
2
1
3
T2 C004
0
30
slot
2
2
1
1
0
3
slot
21
1
2
PipeTailConfigDownpatch0/1
0
3
slot
2
9
6.3 Description
6.3.1 Board Configuration
The basic board configuration is achieved by the use of the
configuration switches. In the top right hand corner of the board there
is a 6 way switch bank. Switch 1 is on the right, switch 6 left is not
used.
The switches control the following functions:
62 Transputer Motherboard User Manual TMB M 711
Figure 48. Network configuration summary
• S1, S2 Board base address
• S3 Module link speed
• S4 Modules 1-9 control source
• S5 Module 0 control source
6.3.1.1 Link Speed
Switch 3 controls the transputer link speed. With the switch off/open
(default) the links run at 20MHz. With the switch on/closed the links
run at 10MHz.
6.3.1.2 Board Address
Switches S1 and S2 select the board base address. The four
possible options are shown in Figure 49.
The TMB08 Motherboard
S2 S1 Board address (Hex)
on on 150
off on 200
on off 250
off off 300
Figure 49. Board address options
6.3.1.3 Control Configuration
There are two configuration options relating to board control:
S4 MD0
•
S5 IBM
•
If switch S4 is on, then the source of control f or modules1 to 9 is from
the same source as module0. If S4 is off then modules1 to 9 are
controlled from module0’s subsystem.
If switch S5 is on, then the source of control for module0 is from
on the edge connector. If S5 is off then the source of control is the
host PC.
, source of control for modules1 to 9.
, source of control for module0
up
TMB M 711 Transputer Motherboard User Manual 63
Description
Figure 50 summarizes for the case of the link area.
S4 S5
on on
S4 S5
off off
source of control -
source of control -
Figure 50. Control configuration (link)
6.3.2 IRQ & DMA Selection
The interrupt request level and DMA channel used are progr ammed
by writing to 4bits in the IRQ and DMA channel select register. At
base address +#14. This is a read/write register so that the
programmed selection can be read back. The register coding is as
shown in figure 51 and figure 52
module 0: edge connector
modules 1 to 9: same as module0
module 0: host PC
modules 1 to 9: module0’s subsystem
Bit 1
0
0
1
1
Bit 0 IRQ
0
1
0
1
3
- reset value
5
11
15
Figure 51. IRQ Channel select.
64 Transputer Motherboard User Manual TMB M 711
The TMB08 Motherboard
.
Bit 3
0
0
1
1
Bit 2 DMA Channel
0
1
0
1
Figure 52. DMA Channel select.
Note: although the TMB08 has a 8 bit (XT) interface the board is that
of a 16bit (AT) board. The extra connector (short connector) allows
more flexible IRQ and DMA selection. If the board is plugged into a
8 bit only slot then only IQR 3 or 5 and DMA 1 or 3 can be used.
6.3.3 The Edge Connector
On the right hand edge of the TMB08 is a 37-way D-type edge
connector.
On the TMB08 the edge connector is used for connection to other
motherboards. For this purpose the following are brought out:
0
- reset value
1
DMA Disabled
3
• the three control ports and the configuration link,
• twelve transputer links.
TMB M 711 Transputer Motherboard User Manual 65
Description
Figure 53 shows the pin-out of the edge connector.
19
18
17
16
15
14
13
12
10
11
37
downAnalyse
36
ConfigDown in
35
PipeTail in
34
subsystemError
33
subsystemReset
32
patch link1out
31
patch link0out
30
edge link7in
29
edge link6in
28
9
27
8
26
7
25
6
24
5
23
4
22
3
21
2
20
1
edge link5in
GND
edge link4out
edge link3out
edge link2out
edge link1in
edge link0in
NotUpError
NoyUpReset
downError
downReset
ConfigDown out
PipeTail out
subsystemAnalyse
patch link1in
patch link0in
GND
edge link7out
edge link6out
edge link5out
edge link4in
edge link3in
edge link2in
GND
edge link1out
edge link0out
NotUpAnalyse
GND
Included in the accompanying cable pack is a mini-bac kplane board
which plugs into the edge connector and brings out the various links
and ports onto standard connectors which accept link cables and
reset cables. The pinout of this connector is shown in figure 54.
66 Transputer Motherboard User Manual TMB M 711
Figure 53. D-type pinout
The TMB08 Motherboard
.
DN
SU
L11
L10
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
UP
down
subsystem
ConfigDown
PipeTail
patch link1
patch link0
edge link7
edge link6
edge link5
edge link4
edge link3
edge link2
edge link1
edge link0
up
circuit board
stencilling
Figure 54. Connections on break out board
6.3.4 The Link Patch Area
The default wiring for the link patch area is to connect:
ConfigUp
•
patch0
•
patch1
•
patch0/1
The
C004 to the edge connector.
to
PipeHead
to
C004 L28
to
C004 L29
connections allow 10 links to be brought out from the
Function
,
,
.
TMB M 711 Transputer Motherboard User Manual 67
Examples
The pinout of the link patch area is shown in figure 55 along with the
default connections.
Figure 55. TMB08 Patch Area, connections for master board
6.4 Examples
This section shows how to set the board configuration options f or two
examples:
C004 L29
PC
Root module can setup C004
patch1
L0
module0
slot0 link1
T2 Config
root
L1
L1
patch0
C004
C004 L28
T2
L3
• a single TMB08 configured for use with an Inmos Toolset,
• two TMB08s connected as a single system, configured for use
with an Inmos Toolset.
6.4.1 Stand-alone TMB08
The most common stand-alone configuration for the TMB08 is for
use with the Inmos Toolsets, with every TRAM reset from the PC.To
achieve this configuration, set the link the link patch area as shown
in figure 55, and make the following setting:
68 Transputer Motherboard User Manual TMB M 711
The TMB08 Motherboard
:
Switches Setting Description
S1
S2
S3 off Use 20 Mbit/s links
S4 on Slot1-9 reset as slot 0
S5 off Slot 0 controlled from PC
on
on
Table 23: Default settings for stand-alone operation
6.4.2 Multiple TMB08s
As an example of connecting multiple motherboards together
consider a system consisting of two TMB08s in the same PC. In this
case:
• the two boards must have different addresses
• one board must be slaved to the other
• the default pipeline needs to be connected
• the configuration pipeline needs to be connected
Base Address #150
First set up one board with the same configuration as for stand-alone
operation (see above). Ensure that pipe-jumpers are used in empty
TRAM slots, and in the inactive slots of any TRAMs larger than size
1, so that link 2 of the last TRAM on the motherboard is taken out to
pipe tail.
TMB M 711 Transputer Motherboard User Manual 69
Examples
Then set up the second board as follows . The link patch area should
be configured as shown in figure 56.
C004 L29
patch1
slot0 link1
T2 Config
patch0
C004 L28
edge
module0
L1
root
T2
L1
edge
L3
C004
Figure 56. TMB08 Patch Area, connections for slave board
The jumpers and links on the slave board should be set up as f ollows:
Switches Setting Description
S1
S2
on
off
Bus address #200
S3 off Use 20 Mbit/s links
S4 on Slots 1 to 9 controlled from
same source as slot 0
S5 on Slot 0 controlled from UP
Table 24: Settings for slave operation
70 Transputer Motherboard User Manual TMB M 711
The TMB08 Motherboard
Plug both boards into the PC and fit hedgehogs, and make the
following connections between the boards:
Cable First board Second board
Reset Cable Down (DN) Up (UP)
Link Cable Pipetail (L10) Patch 1 (L9)
Link Cable ConfigDown (L11) Patch 0 (L8)
Table 25: Connections between TMB08s
TMB M 711 Transputer Motherboard User Manual 71
Examples
72 Transputer Motherboard User Manual TMB M 711
Chapter 7
The TMB12 Motherboard
7.1 Overview
The TMB12 Motherboard
The TMB12 is a double extended eurocard TRAM motherboard, with
space for up to sixteen Transputer Modules.
The board is essentially a stand-alone motherboard in that it contains
no interface hardware to any host computer. Connection to other
transputer systems is achieved via an edge connector which brings
32 links out of the board. Board services (power, configuration and
system services) are also brought out to an edge connector.
The TMB12 is designed to be plugged into a purpose designed rack
(the Transrack) which provides mechanical stability, power and
cooling services.
The TMB12 has two C004 link switch chips and a controlling T222
transputer on board in order to provide for softw are control of network
configuration.
TMB M 711 Transputer Motherboard User Manual 73
Overview
Figure 57 shows the layout of TRAM sites on the motherboard for
reference.
Slot1
Slot5
Slot9
Slot13
Slot0
Slot4
Slot8
Slot12
Slot2
Slot6
Slot10
Slot14
Slot3
Slot7
Slot11
Slot15
Figure 57. TMB12 TRAM layout
Figure 58 shows the general board layout (including configuration
jumpers and switches) for reference.
74 Transputer Motherboard User Manual TMB M 711
K1
The TMB12 Motherboard
P1
SW1
P3
P2
L2
L3
L1
P4
Figure 58. TMB12 board layout
The major components outlined in the figure are described very
briefly here:
• P1 - carries 32 transputer links off the board,
• P2 - carries power, pipeline and configuration links, and system
control signals off the board,
• K1 - allows the default pipeline to be broken up,
• SW1 - provides for board configuration (mainly link speeds).
TMB M 711 Transputer Motherboard User Manual 75
Description
7.2 Description
7.2.1 Board Configuration
The TMB12 has a number of hardware options which are selectable
by switch bank SW1. Table 26 shows the options that can be
selected.
Switch Setting Description
SW1.1 off C004 links at 20Mbits/s (default)
on C004 links10Mbits/s
SW1.2 & off All TRAMs at 20Mbits/s (default)
SW1.3 on All TRAMs at 10Mbits/s
SW1.4 off T2 link 0 at 20Mbits/s (default)
on T2 link 0 at 10Mbits/s
SW1.5 off T2 links 1, 2 & 3 at 20Mbits/s
(default)
on T2 links 1, 2 & 3 10Mbits/s
SW1.6 off Slots 1 to 15 controlled from slot 0
subsystem
on Slots 1 to 15 controlled from UP
(default)
Table 26: TMB12 Link speed and control selection
In nearly all applications, SW1.1 to SW1.5 will be OFF, and SW1.6
will be ON.
Note that it is only sensible to have all the links on the board
operating at the same speed.
Slot 0 is always controlled from the UP port.
7.2.2 The P1 Edge Connector
The TMB12 has two edge connectors called P1 and P2. Both of
these connectors are standard DIN41612 96 way connectors.
Ensure that when wiring to one of these connectors you do not
76 Transputer Motherboard User Manual TMB M 711
The TMB12 Motherboard
accidentally wire to the wrong connector - this could cause
permanent damage to the board.
Connector P1 carries 32 links from the electronic switches, whilst
connector P2 carries a number of board and system services.
The P1 edge connector brings 32 transputer links out of the TMB12
for connection to other boards. Table 27 shows the pinout of this
connector.
When looking at the component side of the TMB12 with the DIN
connectors to the right, pin 0 of the connector is at the top. This is
also true when the TMB12 is mounted into a Transrack. The
numbering of the links is consistent with table 30 and the numbering
scheme used by NCS.
In order to assist in connecting standard link cables to the edge
connector, the TMB12 comes with a break out board in the cable
pack. This plugs into the P1 edge connector and brings the links out
onto standard link plugs.
7.2.3 The P2 Edge Connector
Edge connector P2 carries:
• the power supply (+5V required, rated @ at least 3Amps),
• up, down & subsystem,
• ConfigUp & ConfigDown,
• PipeHead & PipeTail,
• a link from the C004 switches,
• a link to the K1 header block,
• and a number of uncommitted pins (connected to P4).
Note that under normal operation (the TMB12 mounted in a
Transrack), sufficient power and cooling are provided. A po wer cable
is provided with the TMB12 for stand-alone operation, but it is not
recommended that stand-alone operation be permanent.
Table 28 gives the detailed pinout of this connector.
In order to allow standard link and reset cables to be attached to the
TMB12, a special back-to-back connector is supplied in the cable
pack which has a number of ke ying pins (either pins remov ed or pins
sleev ed) which assist in locating the cables to the correct point. This
is shown in figure 59.
TMB M 711 Transputer Motherboard User Manual 77
Description
Pin c b a
edge L0 IC3linkout0 IC2linkin0 GND
edge L1 IC3linkout2 IC2linkin2 GND
edge L2 IC2linkout4 IC3linkin4 GND
edge L3 IC2linkout5 IC3linkin5 GND
edge L4 IC2linkout6 IC3linkin6 GND
edge L5 IC2linkout3 IC3linkin3 GND
edge L6 IC3linkout1 IC2linkin1 GND
edge L7 IC3linkout7 IC2linkin7 GND
edge L8 IC3linkout29 IC2linkin29 GND
edge L9 IC3linkout30 IC2linkin30 GND
edge L10 IC2linkout31 IC3linkin31 GND
edge L11 IC2linkout28 IC3linkin28 GND
edge L12 IC3linkout24 IC2linkin24 GND
edge L13 IC2linkout25 IC3linkin25 GND
edge L14 IC2linkout26 IC3linkin26 GND
edge L15 IC3linkout27 IC2linkin27 GND
edge L16 IC3linkout17 IC2linkin17 GND
edge L17 IC2linkout19 IC3linkin19 GND
edge L18 IC2linkout22 IC3linkin22 GND
edge L19 IC3linkout23 IC2linkin23 GND
edge L20 IC2linkout16 IC3linkin16 GND
edge L21 IC2linkout18 IC3linkin18 GND
edge L22 IC3linkout21 IC2linkin21 GND
edge L23 IC3linkout20 IC2linkin20 GND
edge L24 IC3linkout10 IC2linkin10 GND
edge L25 IC3linkout13 IC2linkin13 GND
edge L26 IC3linkout14 IC2linkin14 GND
edge L27 IC3linkout11 IC2linkin11 GND
edge L28 IC2linkout8 IC3linkin8 GND
edge L29 IC2linkout9 IC3linkin9 GND
edge L30 IC2linkout12 IC3linkin12 GND
edge L31 IC2linkout15 IC3linkin15 GND
78 Transputer Motherboard User Manual TMB M 711
Table 27: P1 connector pinout
The TMB12 Motherboard
Pin c b a
0 GND GND GND
1 VCC VCC VCC
2PAUXnc PAUX
3 VCC VCC VCC
4 GND GND GND
5 VCC VCC VCC
6 GND GND GND
7nc nc nc
8 slot0linkout1 slot0linkout0 slot15linkout2
9 slot0linkin1 slot0linkin0 slot15linkin2
10 GND GND GND
11 nc nc nc
12 GND GND GND
13 nc nc nc
14 IC1linkout1 IC3linkout22 IC1linkout2
15 IC1linkin1 IC2linkin22 IC1linkin2
16 GND GND GND
17 nc nc nc
18 P4/3 nc P4/2
19 P4/4 nc nc
20 P4/5 GND nc
21 P4/6 nc notSubReset
22 P4/7 K1/11 notSubAnalyse
23 P4/8 K1/10 notSubError
24 P4/9 GND GND
25 P4/10 nc nc
26 nc GND nc
27 notUpReset nc notDownReset
28 notUpAnalyse K1/3 notDownAnalyse
29 notUpError K1/18 notDownError
30 GND GND GND
31 GND GND GND
TMB M 711 Transputer Motherboard User Manual 79
Table 28: P2 connector pinout
Description
GND
VCC
VCC
GND
VCC
GND
slot0linkout1
slot0linkin1
PipeHead
GND
nc
GND
IC1linkout1
IC1linkin1
ConfigUp
GND
nc
GND
VCC
VCC
GND
VCC VCC
GND GND
slot0linkout0 slot15linkout2
slot0linkin0 slot15linkin2
PipeTailSubsystem
GND GND
nc nc
GND GND
IC3linkout22 IC1linkout2
IC2linkin22
GND GND
ConfigDown
IC1linkin2
nc nc
P4/3
P4/4
P4/5
P4/6
P4/7
P4/8
P4/9
P4/10
nc
notUpReset
notUpAnalyse
Up
notUpError
GND
nc
nc
P4/2
nc
GND nc
notSubReset
K1/11 notSubAnalyse
K1/10
notSubError
GND
nc
GND nc
notDownReset
K1/3 notDownAnalyse
K1/18 notDownError
Down
GND
GND
Figure 59. Mini-backplane P2 Connections
80 Transputer Motherboard User Manual TMB M 711
7.2.4 Other Hardware
This section describes the remaining hardware outside of the
electronic link switches.
7.2.4.1 Error Lights
There are three LEDs mounted on the edge of the TMB12 protuding
through the front plate. They monitor the error signals coming from
the various slots. Figure 60 summarizes.
The TMB12 Motherboard
(LD2) displays error lines from the front row of
slots (excluding slot0) i.e., slots1,5,9,13,4,8 &12
(LD3) displays error lines from the back row of
slots, i.e., slots 2,6,10,14,3,7,11 &15
(LD1) displays error line from slot0
Figure 60. Error lights on the TMB12
7.2.4.2 User Power Connector
There is an optional four-way power connector, P3, mounted at the
front of the board. The connector plug is compatible with the power
supply socket on most disk units, and can be used to drive such
peripherals. From top to bottom the pins are:
Top connected to P2 3a & 3c (PAUX)
0V
0V
Bottom 5V
Table 29: User Power connector, P3
The pins are rated for currents up to 3Amps.
7.2.4.3 Uncommitted Pins
Nine of the pins on edge connector P2 are wired to nine of the pins
(2 through 10) of an uncommitted connector, P4, on the board. The
two other pins of P4 (1 & 11) are wired to ground. P4 allows
TMB M 711 Transputer Motherboard User Manual 81
Network Configuration
application specific signals to be brought onto the motherboard, e.g.,
RS232 lines. The individual pins of P4 are rated at 50mA @ 25V with
respect to ground. Note that pin1 of P4 is at the top.
7.3 Network Configuration
This section provides an overview of network configuration on the
TMB12. It describes the electronic link switching, the pipeline and the
relation with the edge connectors.
7.3.1 Electronic Link Switching
This section describes the organization of the electronic link
switches.
The two C004s on the TMB12 allow complex transputer topologies
to be constructed. They are used in a slightly unusual way to allow
the maximum amount of re-connectivity on the TMB12 given the
constraints of the hard-wired pipeline.
In general, the link output signals from all the link0s on all the slots
(16 signals) are connected to 16 inputs of one of the C004s (IC2).
The link input signals from all the link3s on all the slots (16 signals)
are connected to 16 of the outputs of the same C004. The C004 can
therefore switch any link0 output to any link3 input.
Similarly , the other C004 is connected to the TRAM slot’ s link0 inputs
and link3 outputs. This C004 can therefore s witch any link3 output to
any link0 input.
This means that each half of a switched link connection between two
transputers is routed through a different C004. The result of this
wiring scheme is that any link0 of any transputer can be connected
to any link3 of any transputer. However, a link0 may not connect
directly to another link0.
In a similar fashion to the transputer links, there are 32 edge
connector links. Edge links are divided equally into two types:
• type 0: wired as per transputer link0’s, i.e., link output to IC2 and
link input from IC3
• type3: wired as per transputer link3’s, i.e., link output to IC3 and
link input from IC2.
Hence, the link switching that can be achieved is:
• any link0 to any link3,
• any link0 to any edge link of type3,
82 Transputer Motherboard User Manual TMB M 711
The TMB12 Motherboard
• any link3 to any edge link of type0,
• any edge link of type0 to any edge link of type3.
Where there are 16 link0’s , 16 link3’s and 16 each of edge links types
0 & 3.
Note that a link0 can be wired to another link0 by connecting the two
link0s to two edge connector links and hard-wiring the edge
connector links together.
Figure 61 shows the general wiring scheme between the TRAM slots
and the switches, figure 62 the connections to the T2 configuration
processor, and table 30 shows the link wiring in full detail.
Unless otherwise stated the edge connector referred to is P1. These
figures are included for reference only. Programming of the link
switches is best achieved with the NCS provided.
Note that the naming of the links connected to the edge connector
P1 is from the perspective of the edge connector looking towards the
C004s. Hence,
edge L6 out
is a link wire going towards the C004s,
and is connected to the input of the appropriate C004.
TMB M 711 Transputer Motherboard User Manual 83
Network Configuration
Edge Connector Links
IMSC004 (IC2)
Slot
15
L3In
L2
L3Out
Slot
L1
0
L3In
L2
L3Out
L1
Pipehead
L0Out
L0In
L0Out
L0In
IMSC004 (IC3)
Edge Connector Links
Figure 61. Connection details of the link switches
Pipetail
Figure 62. Connections to the configuration processor
84 Transputer Motherboard User Manual TMB M 711
IC2
Config Up
1
30
T2
2
Config Down
IC3
configconfig
The TMB12 Motherboard
Link
No.
0 edge L0 out slot 2 L3 in slot 2 L3 out edge L0 in
1 edge L6 out slot 5 L3 in slot 5 L3 out edge L6 in
2 edge L1 out slot 1 L3 in slot 1 L3 out edge L1 in
3 slot 5 L0 out edge L5 in edge L5 out slot 5 L0 in
4 slot 2 L0 out edge L2 in edge L2 out slot 2 L0 in
5 slot 1 L0 out edge L3 in edge L3 out slot 1 L0 in
6 slot 6 L0 out edge L4 in edge L4 out slot 6 L0 in
7 edge L7 out slot 6 L3 in slot 6 L3 out edge L7 in
8 slot 15 L0 out edge L28 in edge L28 out slot 15 L0 in
9 slot 8 L0 out edge L29 in edge L29 out slot 8 L0 in
10 edge L24 out slot 15 L3 in slot 15 L3 out edge L24 in
11 edge L27 out slot 11 L3 in slot 11 L3 out edge L27 in
12 slot 12 L0 out edge L30 in edge L30 out slot 12 L0 in
13 edge L25 out slot 12 L3 in slot 12 L3 out edge L25 in
14 edge L26 out slot8 L3 in slot8 L3 out edge L26 in
IC2 link in IC2 link out IC3 link in IC3 link out
15 slot 11 L0 out edge L3 in edge L3 out slot 11 L0 in
16 slot 7 L0 out edge L20 in edge L20 out slot 7 L0 in
17 edge L16 out slot 3 L3 in slot 3 L3 out edge L16 in
18 slot 4 L0 out edge L21 in edge L21 out slot 4 L0 in
19 slot 3 L0 out edge L17 in edge L17 out slot 3 L0 in
20 edge L23 out slot 7 L3 in slot 7 L3 out edge L23 in
21 edge L22 out slot 4 L3 in slot 4 L3 out edge L22 in
22 P2 pin b15
(slot 0 L0 out)
23 edge L19 out K1 pin 20
24 edge L12 out slot 14 L3 in slot 14 L3 out edge L12 in
25 slot 13 L0 out edge L13 in edge L13 out slot 13 L0 in
26 slot 14 L0 out edge L14 in edge L14 out slot 14 L0 in
27 edge L15 out slot 13 L3 in slot 13 L3 out edge L15 in
28 slot 9 L0 out edge L11 in edge L11 out slot 9 L0 in
29 edge L8 out slot 9 L3 in slot 9 L3 out edge L8 in
30 edge L9 out slot 10 L3 in slot 10 L3 out edge L9 in
edge L18 in edge L18 out P2 pin b14
(slot 0 L0 in)
(slot 0 L3 in)
K1 pin 1
(slot 0 L3 out)
edge L19 in
31 slot 10 L0 out edge L10 in edge L10 out slot 10 L0 in
TMB M 711 Transputer Motherboard User Manual 85
Table 30: Connections to the C004s
Network Configuration
7.3.2 The K1 Header Block
The TMB12 has a slightly modified default pipeline (connecting the
TRAM slots in a chain using links 1 and 2). This is designed to allow
users to construct complex topologies, whilst maintaining
compatibility with the TRAM standard.
The default pipeline is split into four sub-pipelines by the K1 header
block. By default this header is jumpered such that the four subpipelines are connected together into one long pipeline.
The default pipeline is split at locations: 3-4, 7-8 and 11-12. Also
taken to K1 are two links from the P2 edge connector and one link
from the electronic switches. Figure 63 illustrates this along with the
default connections.
PipeHead (P2)
K1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
PipeTail (P2)
C004switches P2 Edge connector
K1 is a 20 pin header block organized 10 by 2 pins. Small jumpers
are used to set the configuration.
86 Transputer Motherboard User Manual TMB M 711
Figure 63. K1 connection diagram
The TMB12 Motherboard
Figure 64 gives the detailed pinout of the K1 connector and shows
the default positions of the jumpers.
Edge of board
P2/23b
Slot 3, Link2out
Slot 4, Link1in
Slot 7, Link2out
Slot 8, Link1in
Slot 11, Link2out
Slot 12, Link1in
P2/30b
Slot 0, Link3in
IC3 Link23out
11
12
13
14
15
16
17
18
19
20
P2/24b
10
Slot 3, Link2in
9
Slot 4, Link1out
8
Slot 7, Link2in
7
Slot 8, Link1out
6
Slot 11, Link2in
5
Slot 12, Link1out
4
P2/29b
3
Slot 0, Link3out
2
IC3 Link23in
1
Figure 64. Details of K1 header, showing default jumper settings
7.3.3 The P1 Edge Connector
This section describes the network configuration aspects of the use
of the P1 edge connector. For detailed pinouts see section 7.2.2 on
page 76.
The edge links of P1 are divided up into type0 links and type3 links.
Remember that the C004s can connect a type0 edge link to link 3 of
any TRAM slot, and a type3 edge link to link 0 of any TRAM slot.
Table 31 classifies all the edge links into one of these two types.
If the desired network topology includes connecting transputer link0’s
together, then this can be achieved by wiring the transputer links to
the edge connector and using a short link cable to jumper the break
out board. Clearly transputer link0s can be wired to any edge link of
type3. Table 32 shows the recommended wiring to make on the
break out board to achieve link0-link0 and link3-link3 connections.
Note that this table also describes the default wiring of the break out
board on shipping.
TMB M 711 Transputer Motherboard User Manual 87
Network Configuration
P1 edge Link Link type P1 edge Link Link type
edge L0 type 0 edge L16 type 3
edge L1 type 0 edge L17 type 3
edge L2 type 3 edge L18 type 3
edge L3 type 3 edge L19 type 0
edge L4 type 3 edge L20 type 3
edge L5 type 3 edge L21 type 3
edge L6 type 0 edge L22 type 0
edge L7 type 0 edge L23 type 0
edge L8 type 0 edge L24 type 0
edge L9 type 0 edge L25 type 0
edge L10 type 3 edge L26 type 0
edge L11 type 3 edge L27 type 0
edge L12 type 0 edge L28 type 3
edge L13 type 3 edge L29 type 3
edge L14 type 3 edge L30 type 3
edge L15 type 0 edge L31 type 3
Table 31: Edge link classification
Link 0 Link 3
From To From To
edge L2 edge L3 edge L0 edge L1
edge L4 edge L5 edge L6 edge L7
edge L10 edge L11 edge L8 edge L9
edge L13 edge L14 edge L12 edge L15
edge L17 edge L18 edge L16 edge L19
edge L20 edge L21 edge L22 edge L23
edge L28 edge L29 edge L24 edge L25
edge L30 edge L31 edge L26 edge L27
Table 32: Default P1 link cable connections
88 Transputer Motherboard User Manual TMB M 711
7.3.4 Summary
This section summarizes the network configuration of the TMB12 by
providing a brief description of all of the aspects described in the
preceding sections.
• the link0’s and link3s of modules in sites 1 to 15 are taken to an
electronic link switch array. Also taken to this array are 32 edge
connector links (P1). In general, any module link0 can connect to
any module link3 or to one of 16 edge connector links.
• the default pipeline is broken up into four equal length sub-
pipelines by header K1. Normally these sub-pipelines are
connected together into one long pipeline.
• slot0 link0 is taken directly to edge connector P2. Also taken to
P2 is the C004 link that it would have been expected to be wired
to. In normal use, these two links would be wired together using
a specially provided link jumper (the “yellow plug cable”, see
figure 65). slot0 link0 is brought directly to the edge connector as
it allows those applications that require it to have two directly
wired links to other transputer equipment, i.e., links which bypass
the C004s.
The TMB12 Motherboard
VCC
GND
slot0linkout0
slot0linkin0
GND
nc
GND
IC3linkout22
IC2linkin22
GND
nc
Figure 65. Jumpering slot0 link0 to the C004s
• slot0 link3 is taken to the header block K1. Also taken to K1 is the
C004 link that slot0 link3 is normally wired to. Because there is a
TMB M 711 Transputer Motherboard User Manual 89
Network Configuration
link between K1 and P2, this allows slot0 link3 to be taken off the
board, bypassing the electronic switches.
Figure 66 shows the main relations between P2, K1 and the link
switches.
C004 switches
16b/15b 1/20
10b/9b
10c/9c
0123
L 23L 22
19/2
9/12
13/8
4567
7/14
15/6
8 9 10 11
5/16
17/4
12 13 14 15
10a/9a
16c/15c
T2
16a/15a
K1P2
30b/29b
23b/24b
3/18
11/10
Figure 66. Network configuration
90 Transputer Motherboard User Manual TMB M 711
Chapter 8
The TMB14 Motherboard
8.1 Overview
The TMB14 Motherboard
The TMB14 is a 6U (160mm) VME TRAM motherboard, with space
for up to eight Transputer Modules.
The link connections between the TRAMs are controlled by a pair of
C004 link switches. 24 links are tak en from these to edge connectors
on the board. This arrangement allows almost any network topology
to be adopted.
The board also provides a single bidirectional link and subsystem
port which can be controlled through its VMEbus interface by a host
computer.
Figure 67 shows the lay out of the board with the major components,
switches and jumpers highlighted.
TMB M 711 Transputer Motherboard User Manual 91
Overview
SLOT 1
P4
ERROR
LEDs
P5
SLOT 3
SLOT 5
SLOT 7
SLOT 0
SLOT 2
SLOT 4
SLOT 6
C004
B
T2
C004
A
P1
P3
SWITCHES
& JUMPERS
P2
There are five edge connectors:
• P1 - VMEbus connector,
• P2,4,5 - C004, pipeline and configuration links, and system
control signals,
• P3 -user power connector.
The T2 and C004’s A and B control the link interconnections.
Because there are two C004’s for eight TRAM slots,
links are reconfigurable. It is therefore possible to emulate the hardwired pipeline connecting links 1 and 2 of each TRAM, as used on
other motherboards.
The error LEDs reflect the error status of each TRAM slot.
92 Transputer Motherboard User Manual TMB M 711
Figure 67. TMB14 board layout
all
the TRAM
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