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TS512MDOM44H-S
DATASHEET
35 pgs2.32 Mb0

Transcend TS512MDOM44H-S, TS2GDOM44H, TS128MDOM44H, TS256MDOM44H-S, TS256MDOM44H DATASHEET

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Description
Description
DescriptionDescription
With an IDE interface and strong data retention ability,
44-Pin IDE Flash Modules are ideal for use in the
harsh environments where Industrial PCs, Set-Top
Boxes, etc. are used.
Placement
Placement
PlacementPlacement
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Features
Features
FeaturesFeatures
•
RoHS compliant products
•
Storage Capacity: 128MB ~ 8GB
• Operating Voltage: 3.3V ±5% or 5V ±10%
• Operating Temperature: 0°C ~ 70°C
• Operating Humidity (Non condensation): 0% to 95%
•
Storage Humidity (Non condensation): 0% to 95%
•
Endurance: 2,000,000 Program/Erase cycles
•
MTBF: 1,000,000 hours
•
Durability of Connector: 10,000 times
• Fully compatible with devices and OS that support the IDE standard (pitch = 2.00mm)
•
Built-in ECC function assures high reliability of data transfer
•
Supports up to Ultra DMA Mode 4
•
Supports PIO Mode 6
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Dimensions
Dimensions
DimensionsDimensions
Side Millimeters Inches
A
B
C
46.00 ± 0.40 1.81 ± 0.016
28.00 ± 0.20 1.10 ± 0.008
6.00 ± 0.50 0.24 ± 0.020
Transcend Information Inc.
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Ver 1.0
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Pin
Pin
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Pin
Pin Assignments
Assignments
Pin Pin
AssignmentsAssignments
Pin
No.
Name
01 -RESET 12 HD12 23 IOWB 34 PDIAGB
02 GND 13 HD2 24 GND 35 HA0
03 HD7 14 HD13 25 IORB 36 HA2
04 HD8 15 HD1 26 GND 37 CE1B
05 HD6 16 HD14 27 IORDY 38 CE2B
06 HD9 17 HD0 28 NC 39 DASPB
07 HD5 18 HD15 29 -DMACK 40 GND
08 HD10 19 GND 30 GND 41 VCC
09 HD4 20 NC 31 IREQ 42 VCC
10 HD11 21 DMARQ 32 IOIS16B 43 GND
11 HD3 22 GND 33 HA1 44 GND
Pin
No.
Name
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Pin
Name
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Pin Definition
Pin Definition
Pin DefinitionPin Definition
Symbol Function
HD0 ~ HD15 Data Bus (Bi-directional)
HA0 ~ HA2 Address Bus (Input)
-RESET Device Reset (Input)
IORB Device I/O Read (Input)
IOWB Device I/O Write (Input)
IOIS16B Transfer Type 8/16 bit (Output)
CE1B, CE2B Chip Select (Input)
PDIAGB Pass Diagnostic (Bi-directional)
DASPB
DMARQ
DMACK-
IREQ Interrupt Request (Output)
NC No Connection
GND Ground
VCC Vcc Power Input
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Disk Active/Slave Present
(Bi-directional) DMA request
DMA acknowledge
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Pin
Pin Layout
Layout
Pin Pin
LayoutLayout
Pin1 Pin43
Pin2 Pin44
Bulge
Transcend Information Inc.
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Block Diagram
Block Diagram
Block DiagramBlock Diagram
With 1 pcs of Flash Memory:
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With 2 pcs of Flash Memory:
Transcend Information Inc.
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Absolute Maximum Rating
Absolute Maximum Ratingssss
Absolute Maximum RatingAbsolute Maximum Rating
Symbol Parameter Min Max Unit
VDD-VSS DC Power Supply -0.6 +6 V
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Ta Operating Temperature 0 +70
Tst Storage Temperature -40 +85
Recommended Operating Conditions
Recommended Operating Conditions
Recommended Operating ConditionsRecommended Operating Conditions
Symbol Parameter Min Max Units
VDD Power supply 3.0 5.5 V
VIN Input voltage 0 VDD+0.3 V
Ta Operating Temperature 0 +70
DC Cha
DC Characteristics
DC ChaDC Cha
(Ta=0 oC to +70 oC, Vcc = 5.0V ±±±± 10%)
Supply Voltage VCC 4.5 5.5 V High level output voltage VOH VCC-0.8 -- V Low level output voltage VOL -- 0.8 V
High level input voltage
Low level input voltage
(Ta=0 oC to +70 oC, Vcc = 3.3V ±±±± 5%)
racteristics
racteristics racteristics
Parameter Symbol Min Max Unit Remark
VIH
VIL
4.0 --
2.92 --
-- 0.8
-- 1.70
V
Non-schmitt trigger
V
Schmitt trigger1
V
Non-schmitt trigger
V
Schmitt trigger1
°
C
°
C
°
C
Parameter Symbol Min Max Unit Remark
Supply Voltage VCC 3.135 3.465 V High level output voltage VOH VCC-0.8 -- V Low level output voltage VOL -- 0.8 V
High level input voltage
Low level input voltage
Transcend Information Inc.
VIH
VIL
2.4 --
2.05 --
-- 0.6
-- 1.25
4
V
Non-schmitt trigger
V
Schmitt trigger1
V
Non-schmitt trigger
V
Schmitt trigger1
Ver 1.0
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Transcend Information Inc.
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True IDE PIO Mode Read/Write Timing
t0
Cycle time (min) 1 600 383 240 180 120 100 80
t1
Address Valid to -IORD/-IOWR setup (min) 70 50 30 30 25 15 10
t2
-IORD/-IOWR (min) 1
t2
-IORD/-IOWR (min) Register (8 bit)
t2i
-IORD/-IOWR recovery time (min)
t3
-IOWR data setup (min)
t4
-IOWR data hold (min)
t5
-IORD data setup (min)
t6
-IORD data hold (min)
t
-IORD data tristate (max)2
6Z
t7
Address valid to IOCS16 assertion (max)
t8
Address valid to IOCS16 released (max)
t9
-IORD/-IOWR to address valid hold Read Data Valid to IORDY active (min), if
t
RD
IORDY initially low after tA
tA
IORDY Setup time 3
tB
IORDY Pulse Width (max)
tC
IORDY assertion to release (max)
Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below
120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width shall still be met.
Item
4
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Mode
0
165 125 100 80 70 65 55 290 290 290 80 70 65 55
-- -- -- 70 25 25 20 60 45 30 30 20 20 15 30 20 15 10 10 5 5 50 35 20 20 20 15 10
5 5 5 5 5 5 5
30 30 30 30 30 20 20
4
90 50 40 N/A N/A N/A N/A
4
60 45 30 N/A N/A N/A N/A 20 15 10 10 10 10 10
0 0 0 0 0 0 0
35 35 35 35 35 N/A
1250 1250 1250 1250 1250 N/A
5 5 5 5 5 N/A
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Mode
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Mode
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N/A N/A N/A
5
5
5
(1) t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum
command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t
shall be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means
2i
a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device’s identify device data.
(2) This parameter specifies the time from the negation edge of -IORD to the time that the data bus is
released by the device.
(3) The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is
inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device is not driving IORDY negated at tA after the activation of -IORD or -IOWR, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of -IORD or -IOWR, then tRD shall be met and t5 is not applicable.
(4) t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
(5) IORDY is not supported in this mode.
Transcend Information Inc.
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Ver 1.0
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True IDE PIO Mode Timing Diagram
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Figure 1: True IDE PIO Mode Timing Diagram
Notes: (1) Device address consists of -CS0, -CS1, and A[02::00] (2) Data consists of D[15::00] (16-bit) or D[07::00] (8 bit) (3) -IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored. (4) The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle
is to be extended is made by the host after tA from the assertion of -IORD or -IOWR. The assertion and negation of IORDY is described in the following three cases:
(4-1) Device never negates IORDY: No wait is generated. (4-2) Device starts to drive IORDY low before tA, but causes IORDY to be asserted before tA: No wait
generated.
(4-3) Device drives IORDY low before tA: wait generated. The cycle completes after IORDY is reasserted. For
cycles where a wait is generated and -IORD is asserted, the device shall place read data on D15-D00 for tRD before causing IORDY to be asserted.
Transcend Information Inc.
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True IDE Multiword DMA Mode Read/Write Timing Specification
M
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t0
Cycle time (min) 1 480 150 120 100 80
tD
-IORD / -IOWR asserted width(min)
tE
-IORD data access (max) 150 60 50 50 45
tF
-IORD data hold (min) 5 5 5 5 5
tG
-IORD/-IOWR data setup (min) 100 30 20 15 10
tH
-IOWR data hold (min) 20 15 10 5 5 DMACK to –IORD/-IOWR setup
tI
(min)
-IORD / -IOWR to -DMACK hold
tJ
(min)
t
-IORD negated width (min) 1 50 50 25 25 20
KR
t
-IOWR negated width (min) 1 215 50 25 25 20
KW
t
-IORD to DMARQ delay (max) 120 40 35 35 35
LR
t
-IOWR to DMARQ delay (max) 40 40 35 35 35
LW
tM
CS(1:0) valid to –IORD / -IOWR 50 30 25 10 5
tN
CS(1:0) hold 15 10 10 10 10
tZ
-DMACK 20 25 25 25 25
Item
Mode 0
(ns)
1
215 80 70 65 55
0 0 0 0 0
20 5 5 5 5
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
Notes:
(1) t0 is the minimum total cycle time and tD is the minimum command active time, while tKR and tKW are the
minimum command recovery time or command inactive time for input and output cycles respectively. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, tD, tKR, and tKW shall be met. The minimum total cycle time requirement is greater than the sum of tD and tKR or tKW.for input and output cycles respectively. This means a host implementation can lengthen either or both of tD and either of tKR, and tKW as needed to ensure that t0 is equal to or greater than the value reported in the device’s identify device data.
Transcend Information Inc.
8
Ver 1.0
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True IDE Multiword DMA Mode Read/Write Timing Diagram
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Figure 2: True IDE Multiword DMA Mode Read/Write Timing Diagram
Notes: (1) If the Card cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ within the
time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert the signal at a later time to continue the DMA operation.
(2) This signal may be negated by the host to suspend the DMA transfer in progress.
Transcend Information Inc.
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Ultra DMA Mode Read/Write Timing Specification
Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA, commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol.
UDMA Signal Type
DMARQ Output DMARQ DMACK Input -DMACK
STOP Input STOP1 HDMARDY(R) HSTROBE(W)
DDMARDY(W)
DSTROBE(R)
DATA Bidir D[15:00]
ADDRESS Input A[02:00]5
CSEL input -CSEL
INTRQ Output INTRQ
Card Select Input
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TRUE IDE MODE
-HDMARDY
HSTROBE(W)
-DDMARDY(W) DSTROBE(R)
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UDMA
-CS0
-CS1
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Notes: 1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.
2) The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command.
3) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command.
4) The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.
5) Address lines 03 through 10 are not used in True IDE mode.
Several signal lines are redefined to provide different functions during an Ultra DMA data burst. These lines assume their UDMA definitions when:
1. An Ultra DMA mode is selected, and
2. A host issues a READ DMA, or a WRITE DMA command requiring data transfer, and
3. The device asserts (-)DMARQ, and
4. The host asserts (-)DMACK.
These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation
of -DMACK by the host at the termination of an Ultra DMA data burst.
With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the same agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra
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DMA data-out burst.
During an Ultra DMA data burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data.
Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA mode at which the system operates. The Ultra DMA mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only one Ultra DMA mode shall be selected at any given time. All timing requirements for a selected Ultra DMA mode shall be satisfied. Devices supporting any Ultra DMA mode shall also support all slower Ultra DMA modes.
An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET FEATURES disable reverting to defaults command has been issued. The device may revert to a Multiword DMA mode if a SET FEATURES enable reverting to default has been issued. An Ultra DMA capable device shall clear any previously selected Ultra DMA mode and revert to the default non-Ultra DMA modes after executing a power-on or hardware reset.
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Both the host and device perform a CRC function during an Ultra DMA data burst. At the end of an Ultra DMA data burst the host sends its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match, the device reports an error in the error register. If an error occurs during one or more Ultra DMA data bursts for any one command, the device shall report the first error that occurred. If the device detects that a CRC error has occurred before data transfer for the command is complete, the device may complete the transfer and report the error or abort the command and report the error.
NOTE through to the host software driver regardless of whether all data requested by the command has been transferred.
−
If a data transfer is terminated before completion, the assertion of INTRQ should be passed
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