TS2G~16GCF300 |
300X CompactFlash Card |
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Description |
Features |
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The Transcend CF 300X is a High Speed Compact Flash Card with high quality Flash Memory assembled on a printed circuit board.
Placement
Dimensions
•CompactFlash Specification Version 4.1 Complaint
•RoHS compliant products
•Single Power Supply: 3.3V±5% or 5V±10%
•Operating Temperature: -25oC to 85oC
•Storage Temperature: -40oC to 85oC
•Operating Humidity (Non condensation): 0% to 95%
•Storage Humidity (Non condensation): 0% to 95%
•Built-in 13/24-bit ECC (Error Correction Code) functionality and wear-leveling algorithm ensures highly reliable of data transfer
913bit BCH ECC (2k+64 / 4k+128 byte per page flash)
924bit BCH ECC (4k+208 byte per page flash)
•Operation Modes:
9PC Card Memory Mode
9PC Card IO Mode
9True IDE Mode
•True IDE Mode supports:
9Ultra DMA Mode 0 to Ultra DMA Mode 5 (Ultra DMA mode 5 must use Power supply: 3.3V)
9MultiWord DMA Mode 0 to MultiWord DMA Mode 4
9PIO Mode 0 to PIO Mode 6
•PC Card Mode supports up to Ultra DMA Mode 5
•True IDE mode: Fixed Disk (Standard)
•PC Card Mode: Removable Disk (Standard)
•Durability of Connector: 10,000 times
•Support S.M.A.R.T (Self-defined)
•Support Security Command
•Support Wear-Leveling to extend product life
•Compliant to CompactFlash, PC Card Mode, and ATA standards
Transcend Information Inc. |
1 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
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Transcend
Transcend Information Inc. |
2 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
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Block Diagram
Transcend Information Inc. |
3 |
V1.6
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TS2G~16GCF300 |
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300X CompactFlash Card |
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Pin Assignments and Pin Type |
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PC Card Memory Mode |
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PC Card I/O Mode |
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True IDE Mode4 |
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Pin |
Signal |
Pin |
In, Out Type |
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Pin Num |
Signal |
Pin |
In, Out |
Pin |
Signal |
Pin |
In, Out |
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Num |
Name |
Type |
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Name |
Type |
Type |
Num |
Name |
Type |
Type |
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1 |
GND |
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Ground |
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1 |
GND |
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Ground |
1 |
GND |
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Ground |
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2 |
D03 |
I/O |
I1Z, OZ3 |
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2 |
D03 |
I/O |
I1Z, OZ3 |
2 |
D03 |
I/O |
I1Z, OZ3 |
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3 |
D04 |
I/O |
I1Z, OZ3 |
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3 |
D04 |
I/O |
I1Z, OZ3 |
3 |
D04 |
I/O |
I1Z, OZ3 |
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4 |
D05 |
I/O |
I1Z, OZ3 |
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4 |
D05 |
I/O |
I1Z, OZ3 |
4 |
D05 |
I/O |
I1Z, OZ3 |
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5 |
D06 |
I/O |
I1Z, OZ3 |
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5 |
D06 |
I/O |
I1Z, OZ3 |
5 |
D06 |
I/O |
I1Z, OZ3 |
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6 |
D07 |
I/O |
I1Z, OZ3 |
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6 |
D07 |
I/O |
I1Z, OZ3 |
6 |
D07 |
I/O |
I1Z, OZ3 |
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7 |
-CE1 |
I |
I3U |
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7 |
-CE1 |
I |
I3U |
7 |
-CS0 |
I |
I3Z |
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8 |
A10 |
I |
I1Z |
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8 |
A10 |
I |
I1Z |
8 |
A102 |
I |
I1Z |
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9 |
-OE |
I |
I3U |
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9 |
-OE |
I |
I3U |
9 |
-ATA SEL |
I |
I3U |
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10 |
A09 |
I |
I1Z |
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10 |
A09 |
I |
I1Z |
10 |
A092 |
I |
I1Z |
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11 |
A08 |
I |
I1Z |
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11 |
A08 |
I |
I1Z |
11 |
A082 |
I |
I1Z |
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12 |
A07 |
I |
I1Z |
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12 |
A07 |
I |
I1Z |
12 |
A072 |
I |
I1Z |
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13 |
VCC |
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Power |
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13 |
VCC |
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Power |
13 |
VCC |
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Power |
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14 |
A06 |
I |
I1Z |
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14 |
A06 |
I |
I1Z |
14 |
A062 |
I |
I1Z |
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15 |
A05 |
I |
I1Z |
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15 |
A05 |
I |
I1Z |
15 |
A052 |
I |
I1Z |
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16 |
A04 |
I |
I1Z |
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16 |
A04 |
I |
I1Z |
16 |
A042 |
I |
I1Z |
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17 |
A03 |
I |
I1Z |
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17 |
A03 |
I |
I1Z |
17 |
A032 |
I |
I1Z |
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18 |
A02 |
I |
I1Z |
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18 |
A02 |
I |
I1Z |
18 |
A02 |
I |
I1Z |
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19 |
A01 |
I |
I1Z |
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19 |
A01 |
I |
I1Z |
19 |
A01 |
I |
I1Z |
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20 |
A00 |
I |
I1Z |
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20 |
A00 |
I |
I1Z |
20 |
A00 |
I |
I1Z |
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21 |
D00 |
I/O |
I1Z, OZ3 |
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21 |
D00 |
I/O |
I1Z, OZ3 |
21 |
D00 |
I/O |
I1Z, OZ3 |
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22 |
D01 |
I/O |
I1Z, OZ3 |
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22 |
D01 |
I/O |
I1Z, OZ3 |
22 |
D01 |
I/O |
I1Z, OZ3 |
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23 |
D02 |
I/O |
I1Z, OZ3 |
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23 |
D02 |
I/O |
I1Z, OZ3 |
23 |
D02 |
I/O |
I1Z, OZ3 |
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24 |
WP |
O |
OT3 |
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24 |
-IOIS16 |
O |
OT3 |
24 |
-IOCS16 |
O |
ON3 |
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25 |
-CD2 |
O |
Ground |
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25 |
-CD2 |
O |
Ground |
25 |
-CD2 |
O |
Ground |
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26 |
-CD1 |
O |
Ground |
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26 |
-CD1 |
O |
Ground |
26 |
-CD1 |
O |
Ground |
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27 |
D111 |
I/O |
I1Z, OZ3 |
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27 |
D111 |
I/O |
I1Z, OZ3 |
27 |
D111 |
I/O |
I1Z, OZ3 |
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28 |
D121 |
I/O |
I1Z, OZ3 |
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28 |
D121 |
I/O |
I1Z, OZ3 |
28 |
D121 |
I/O |
I1Z, OZ3 |
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29 |
D131 |
I/O |
I1Z, OZ3 |
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29 |
D131 |
I/O |
I1Z, OZ3 |
29 |
D131 |
I/O |
I1Z, OZ3 |
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30 |
D141 |
I/O |
I1Z, OZ3 |
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30 |
D141 |
I/O |
I1Z, OZ3 |
30 |
D141 |
I/O |
I1Z, OZ3 |
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31 |
D151 |
I/O |
I1Z, OZ3 |
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31 |
D151 |
I/O |
I1Z, OZ3 |
31 |
D151 |
I/O |
I1Z, OZ3 |
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32 |
-CE21 |
I |
I3U |
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32 |
-CE21 |
I |
I3U |
32 |
-CS11 |
I |
I3Z |
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33 |
-VS1 |
O |
Ground |
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33 |
-VS1 |
O |
Ground |
33 |
-VS1 |
O |
Ground |
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Transcend Information Inc. |
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V1.6 |
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TS2G~16GCF300 |
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300X CompactFlash Card |
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PC Card Memory Mode |
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PC Card I/O Mode |
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True IDE Mode4 |
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Pin |
Signal Name |
Pin |
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In, Out |
Pin |
Signal Name |
Pin |
In, Out |
Pin |
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Signal Name |
Pin |
In, Out |
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Num |
Type |
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Type |
Num |
Type |
Type |
Num |
Type |
Type |
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-IORD |
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-IORD |
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-IORD7 |
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34 |
HSTROBE10 |
I |
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I3U |
34 |
HSTROBE10 |
I |
I3U |
34 |
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HSTROBE8 |
I |
I3Z |
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HDMARDY11 |
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-HDMARDY11 |
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-HDMARDY9 |
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35 |
-IOWR |
I |
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I3U |
35 |
-IOWR |
I |
I3U |
35 |
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-IOWR7 |
I |
I3Z |
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STOP10,11 |
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STOP10,11 |
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STOP8,9 |
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36 |
-WE |
I |
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I3U |
36 |
-WE |
I |
I3U |
36 |
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-WE3 |
I |
I3U |
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37 |
READY |
O |
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OT1 |
37 |
-IREQ |
O |
OT1 |
37 |
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INTRQ |
O |
OZ1 |
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38 |
VCC |
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Power |
38 |
VCC |
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Power |
38 |
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VCC |
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Power |
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39 |
-CSEL5 |
I |
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I2Z |
39 |
-CSEL5 |
I |
I2Z |
39 |
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-CSEL |
I |
I2U |
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40 |
-VS2 |
O |
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OPEN |
40 |
-VS2 |
O |
OPEN |
40 |
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-VS2 |
O |
OPEN |
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41 |
RESET |
I |
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I2Z |
41 |
RESET |
I |
I2Z |
41 |
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-RESET |
I |
I2Z |
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-WAIT |
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-WAIT |
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IORDY7 |
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ON1 |
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42 |
-DDMARDY10 |
O |
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OT1 |
42 |
-DDMARDY10 |
O |
OT1 |
42 |
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-DDMARDY8 |
O |
OT113 |
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DSTROBE11 |
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DSTROBE11 |
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DSTROBE9 |
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43 |
-INPACK |
O |
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OT1 |
43 |
-INPACK |
O |
OT1 |
43 |
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DMARQ |
O |
OZ1 |
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-DMARQ12 |
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-DMARQ12 |
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44 |
-REG |
I |
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I3U |
44 |
-REG |
I |
I3U |
44 |
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-DMACK 6 |
I |
I3U |
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-DMACK 12 |
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DMACK 12 |
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45 |
BVD2 |
O |
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OT1 |
45 |
-SPKR |
O |
OT1 |
45 |
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-DASP |
I/O |
I1U, ON1 |
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46 |
BVD1 |
O |
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OT1 |
46 |
-STSCHG |
O |
OT1 |
46 |
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-PDIAG |
I/O |
I1U, ON1 |
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47 |
D081 |
I/O |
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I1Z, |
47 |
D081 |
I/O |
I1Z, |
47 |
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D081 |
I/O |
I1Z, OZ3 |
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OZ3 |
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OZ3 |
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48 |
D091 |
I/O |
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I1Z, |
48 |
D091 |
I/O |
I1Z, |
48 |
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D091 |
I/O |
I1Z, OZ3 |
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OZ3 |
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OZ3 |
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49 |
D101 |
I/O |
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I1Z, |
49 |
D101 |
I/O |
I1Z, |
49 |
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D101 |
I/O |
I1Z, OZ3 |
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OZ3 |
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OZ3 |
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50 |
GND |
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Ground |
50 |
GND |
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Ground |
50 |
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GND |
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Ground |
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Note: 1) These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow for 3-state
signals not to consume current.
2)The signal should be grounded by the host.
3)The signal should be tied to VCC by the host.
4)The mode is required for CompactFlash Storage Cards.
5)The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled upon the card in these modes, it should not be left floating by the host in PC Card modes. In these modes, the pin should be connected by the host to PC Card A25 or grounded by the host.
6)If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older hosts: while DMA operations are not active, the card shall ignore this signal,including a floating condition
7)Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.
8)Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.
9)Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active.
10)Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Write is active.
11)Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Read is active.
12)Signal usage in PC Card I/O and Memory Mode when Ultra DMA protocol is active.
Transcend Information Inc. |
5 |
V1.6
TS2G~16GCF300 |
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300X CompactFlash Card |
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Signal Description |
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Signal Name |
Dir. |
Pin |
Description |
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A10 – A00 |
I |
8,10,11,12, |
These address lines along with the -REG signal are used to select the following: |
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(PC Card Memory Mode) |
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14,15,16,17, |
The I/O port address registers within the CompactFlash Storage Card , the |
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18,19,20 |
memory mapped port address registers within the CompactFlash Storage Card, |
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a byte in the card's information structure and its configuration control and status |
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registers. |
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A10 – A00 |
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This signal is the same as the PC Card Memory Mode signal. |
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(PC Card I/O Mode) |
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A02 - A00 |
I |
18,19,20 |
In True IDE Mode, only A[02:00] are used to select the one of eight registers |
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(True IDE Mode) |
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in the Task File, the remaining address lines should be grounded by the host. |
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BVD1 |
I/O |
46 |
This signal is asserted high, as BVD1 is not supported. |
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(PC Card Memory Mode) |
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-STSCHG |
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This signal is asserted low to alert the host to changes in the READY and Write |
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(PC Card I/O Mode) |
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Protect states, while the I/O interface is configured. Its use is controlled by the |
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Status Changed |
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Card Config and Status Register. |
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-PDIAG |
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In the True IDE Mode, this input / output is the Pass Diagnostic signal in the |
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(True IDE Mode) |
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Master / Slave handshake protocol. |
||
|
|
|
|
||
BVD2 |
I/O |
45 |
This signal is asserted high, as BVD2 is not supported. |
||
(PC Card Memory Mode) |
|
|
|
|
|
-SPKR |
|
|
This line is the Binary Audio output from the card. If the Card does not support |
||
(PC Card I/O Mode) |
|
|
the Binary Audio function, this line should be held negated. |
||
-DASP |
|
|
In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in |
||
(True IDE Mode) |
|
|
the Master/Slave handshake protocol. |
||
|
|
|
|
||
-CD1, -CD2 |
O |
26,25 |
These Card Detect pins are connected to ground on the CompactFlash Storage |
||
(PC Card Memory Mode) |
|
|
Card. They are used by the host to determine that the CompactFlash Storage |
||
|
|
|
|
Card is fully inserted into its socket. |
|
-CD1, -CD2 |
|
|
This signal is the same for all modes. |
||
(PC Card I/O Mode) |
|
|
|
|
|
-CD1, -CD2 |
|
|
This signal is the same for all modes. |
||
(True IDE Mode) |
|
|
|
|
|
|
|
|
|
|
|
Transcend Information Inc. |
6 |
V1.6
TS2G~16GCF300 |
|
300X CompactFlash Card |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
Signal Name |
Dir. |
Pin |
Description |
|
-CE1, -CE2 |
I |
7,32 |
These input signals are used both to select the card and to indicate to the card |
||
whether a byte or a word operation is being performed. -CE2 always accesses |
|||||
(PC Card Memory Mode) |
|
|
the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the |
||
Card Enable |
|
|
word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1, |
||
|
|
|
|
-CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29, |
|
|
|
|
|
Table 31, Table 35, Table 36 and Table 37. |
|
-CE1, -CE2 |
|
|
This signal is the same as the PC Card Memory Mode signal. |
||
|
|
|
|
||
(PC Card I/O Mode) |
|
|
|
|
|
Card Enable |
|
|
|
|
|
-CS0, -CS1 |
|
|
In the True IDE Mode, -CS0 is the address range select for the task file |
||
|
|
registers while -CS1 is used to select the Alternate Status Register and the |
|||
(True IDE Mode) |
|
|
|||
|
|
Device Control Register. |
|||
|
|
|
|
||
|
|
|
|
While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the |
|
|
|
|
|
width of the transfers shall be 16 bits. |
|
|
|
|
|
||
-CSEL |
I |
39 |
This signal is not used for this mode, but should be connected by the host to PC |
||
(PC Card Memory Mode) |
|
|
Card A25 or grounded by the host. |
||
-CSEL |
|
|
This signal is not used for this mode, but should be connected by the host to PC |
||
(PC Card I/O Mode) |
|
|
Card A25 or grounded by the host. |
||
-CSEL |
|
|
This internally pulled up signal is used to configure this device as a Master or a |
||
(True IDE Mode) |
|
|
Slave when configured in the True IDE Mode. |
||
|
|
|
|
When this pin is grounded, this device is configured as a Master. |
|
|
|
|
|
When the pin is open, this device is configured as a Slave. |
|
|
|
|
|
||
D15 - D00 |
I/O |
31,30,29,28, |
These lines carry the Data, Commands and Status information between the host |
||
(PC Card Memory Mode) |
|
27,49,48,47, |
and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB |
||
|
|
|
6,5,4,3,2, |
of the Odd Byte of the Word. |
|
|
|
|
23, 22, 21 |
||
|
|
|
|
|
|
D15 - D00 |
|
|
This signal is the same as the PC Card Memory Mode signal. |
||
(PC Card I/O Mode) |
|
|
|
|
|
D15 - D00 |
|
|
In True IDE Mode, all Task File operations occur in byte mode on the low order |
||
(True IDE Mode) |
|
|
|||
|
|
bus D[7:0] while all data transfers are 16 bit using D[15:0]. |
|||
|
|
|
|
||
|
|
|
|
||
GND |
-- |
1,50 |
Ground. |
||
(PC Card Memory Mode) |
|
|
|
|
|
GND |
|
|
This signal is the same for all modes. |
||
(PC Card I/O Mode) |
|
|
|
|
|
GND |
|
|
This signal is the same for all modes. |
||
(True IDE Mode) |
|
|
|
|
|
|
|
|
|
|
|
Transcend Information Inc. |
|
7 |
|
||
|
|
|
|
V1.6 |
TS2G~16GCF300 |
|
300X CompactFlash Card |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
Signal Name |
Dir. |
Pin |
Description |
|
-INPACK |
O |
43 |
This signal is not used in this mode. |
||
(PC Card Memory Mode except |
|
|
|
|
|
Ultra DMA Protocol Active) |
|
|
|
|
|
-INPACK |
|
|
The Input Acknowledge signal is asserted by the CompactFlash Storage Card |
||
|
|
when the card is selected and responding to an I/O read cycle at the address that |
|||
(PC Card I/O Mode except Ultra |
|
|
is on the address bus. This signal is used by the host to control the enable of any |
||
DMA Protocol Active) |
|
|
input data buffers between the CompactFlash Storage Card and the CPU. |
||
Input Acknowledge |
|
|
|||
|
|
Hosts that support a single socket per interface logic, such as for Advanced |
|||
|
|
|
|
||
|
|
|
|
Timing Modes and Ultra DMA operation may ignore the –INPACK signal from the |
|
|
|
|
|
device and manage their input buffers based solely on Card Enable signals. |
|
-DMARQ |
|
|
This signal is a DMA Request that is used for DMA data transfers between host |
||
(PC Card Memory Mode -Ultra |
|
|
and device. It shall be asserted by the device when it is ready to transfer data to |
||
DMA Protocol Active) |
|
|
or from the host. For Multiword DMA transfers, the direction of data transfer is |
||
-DMARQ |
|
|
controlled by -IORD and -IOWR. This signal is used in a handshake manner with |
||
|
|
(-)DMACK, i.e., the device shall wait until the host asserts (-)DMACK before |
|||
(PC Card I/O Mode -Ultra DMA |
|
|
|||
Protocol Active) |
|
|
negating (-)DMARQ, and re-asserting (-)DMARQ if there is more data to |
||
DMARQ |
|
|
transfer. |
||
|
|
In PCMCIA I/O Mode, the -DMARQ shall be ignored by the host while the host is |
|||
(True IDE Mode) |
|
|
|||
|
|
|
|
performing an I/O Read cycle to the device. The host shall not initiate an I/O |
|
|
|
|
|
Read cycle while -DMARQ is asserted by the device. |
|
|
|
|
|
In True IDE Mode, DMARQ shall not be driven when the device is not selected in |
|
|
|
|
|
the Drive-Head register. |
|
|
|
|
|
While a DMA operation is in progress, -CS0 (-CE1)and -CS1 (-CE2) shall be held |
|
|
|
|
|
negated and the width of the transfers shall be 16 bits. |
|
|
|
|
|
If there is no hardware support for True IDE DMA mode in the host, this output |
|
|
|
|
|
signal is not used and should not be connected at the host. In this case, the BIOS |
|
|
|
|
|
must report that DMA mode is not supported by the host so that device drivers |
|
|
|
|
|
will not attempt DMA mode operation. |
|
|
|
|
|
A host that does not support DMA mode and implements both PC Card and True |
|
|
|
|
|
IDE modes of operation need not alter the PC Card mode connections while in |
|
|
|
|
|
True IDE mode as long as this does not prevent proper operation in any mode. |
|
-IORD |
I |
34 |
This signal is not used in this mode. |
||
(PC Card Memory Mode except |
|
|
|
|
|
Ultra DMA Protocol Active) |
|
|
This is an I/O Read strobe generated by the host. This signal gates I/O data onto |
||
|
|
|
|
||
-IORD |
|
|
the bus from the CompactFlash Storage Card when the card is configured to use |
||
(PC Card I/O Mode except Ultra |
|
|
the I/O interface. |
||
DMA Protocol Active) |
|
|
|
|
|
-IORD |
|
|
In True IDE Mode, while Ultra DMA mode is not active, this signal has the same |
||
|
|
function as in PC Card I/O Mode. |
|||
(True IDE Mode – Except Ultra |
|
|
|||
DMA Protocol Active) |
|
|
|
|
|
-HDMARDY |
|
|
In all modes when Ultra DMA mode DMA Read is active, this signal is asserted |
||
|
|
by the host to indicate that the host is ready to receive Ultra DMA data-in bursts. |
|||
(All Modes - Ultra DMA Protocol |
|
|
The host may negate – HDMARDY to pause an Ultra DMA transfer. |
||
DMA Read) |
|
|
|
|
|
HSTROBE |
|
|
In all modes when Ultra DMA mode DMA Write is active, this signal is the data |
||
(All Modes - Ultra DMA Protocol |
|
|
out strobe generated by the host. Both the rising and falling edge of HSTROBE |
||
DMA Write) |
|
|
cause data to be latched by the device. The host may stop generating |
||
|
|
|
|
HSTROBE edges to pause an Ultra DMA data-out burst. |
|
|
|
|
|
|
|
|
|
|
|
|
|
Transcend Information Inc. |
|
8 |
|
||
|
|
|
|
V1.6 |
TS2G~16GCF300 |
|
300X CompactFlash Card |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
Signal Name |
Dir. |
Pin |
Description |
|
-IOWR |
I |
35 |
This signal is not used in this mode. |
||
(PC Card Memory Mode– Except |
|
|
|||
Ultra DMA Protocol Active) |
|
|
|
|
|
-IOWR |
|
|
The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the |
||
|
|
CompactFlash Storage Card controller registers when the CompactFlash |
|||
(PC Card I/O Mode –Except Ultra |
|
|
|||
|
|
Storage Card is configured to use the I/O interface. |
|||
DMA Protocol Active) |
|
|
|||
|
|
|
|
The clocking shall occur on the negative to positive edge of the signal (trailing |
|
|
|
|
|
edge). |
|
-IOWR |
|
|
In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has |
||
(True IDE Mode – Except Ultra |
|
|
the same function as in PC Card I/O Mode. When Ultra DMA mode protocol is |
||
|
|
supported, this signal must be negated before entering Ultra DMA mode |
|||
DMA Protocol Active) |
|
|
|||
|
|
protocol. |
|||
|
|
|
|
||
STOP |
|
|
In All Modes, while Ultra DMA mode protocol is active, the assertion of this signal |
||
(All Modes – Ultra DMA Protocol |
|
|
causes the termination of the Ultra DMA data burst. |
||
Active) |
|
|
|
|
|
|
|
|
|
||
-OE |
I |
9 |
This is an Output Enable strobe generated by the host interface. It is used to read |
||
(PC Card Memory Mode) |
|
|
data from the CompactFlash Storage Card in Memory Mode and to read the CIS |
||
|
|
|
|
and configuration registers. |
|
-OE |
|
|
In PC Card I/O Mode, this signal is used to read the CIS and configuration |
||
(PC Card I/O Mode) |
|
|
registers. |
||
-ATA SEL |
|
|
To enable True IDE Mode this input should be grounded by the host. |
||
(True IDE Mode) |
|
|
|||
|
|
|
|
||
READY |
O |
37 |
In Memory Mode, this signal is set high when the CompactFlash Storage Card is |
||
(PC Card Memory Mode) |
|
|
ready to accept a new data transfer operation and is held low when the card is |
||
|
|
|
|
busy. |
|
|
|
|
|
At power up and at Reset, the READY signal is held low (busy) until the |
|
|
|
|
|
CompactFlash Storage Card has completed its power up or reset function. No |
|
|
|
|
|
access of any type should be made to the CompactFlash Storage Card during |
|
|
|
|
|
this time. |
|
|
|
|
|
Note, however, that when a card is powered up and used with RESET |
|
|
|
|
|
continuously disconnected or asserted, the Reset function of the RESET pin is |
|
|
|
|
|
disabled. Consequently, the continuous assertion of RESET from the application |
|
|
|
|
|
of power shall not cause the READY signal to remain continuously in the busy |
|
|
|
|
|
state. |
|
-IREQ |
|
|
I/O Operation – After the CompactFlash Storage Card Card has been configured |
||
(PC Card I/O Mode) |
|
|
for I/O operation, this signal is used as -Interrupt Request. This line is strobed |
||
|
|
|
|
low to generate a pulse mode interrupt or held low for a level mode interrupt. |
|
INTRQ |
|
|
In True IDE Mode signal is the active high Interrupt Request to the host. |
||
(True IDE Mode) |
|
|
|
|
Transcend Information Inc. |
9 |
V1.6
TS2G~16GCF300 |
|
300X CompactFlash Card |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
Signal Name |
Dir. |
Pin |
Description |
|
-REG |
I |
44 |
This signal is used during Memory Cycles to distinguish between Common |
||
Memory and Register (Attribute) Memory accesses. High for Common Memory, |
|||||
(PC Card Memory Mode– Except |
|
|
Low for Attribute Memory. |
||
Ultra DMA Protocol Active) |
|
|
|||
|
|
|
|
||
Attribute Memory Select |
|
|
In PC Card Memory Mode, when Ultra DMA Protocol is supported by the host |
||
|
|
|
|
and the host has enabled Ultra DMA protocol on the card the, host shall keep the |
|
|
|
|
|
-REG signal negated during the execution of any DMA Command by the device. |
|
-REG |
|
|
The signal shall also be active (low) during I/O Cycles when the I/O address is on |
||
(PC Card I/O Mode –Except Ultra |
|
|
the Bus. |
||
DMA Protocol Active) |
|
|
In PC Card I/O Mode, when Ultra DMA Protocol is supported by the host and the |
||
|
|
|
|
||
|
|
|
|
host has enabled Ultra DMA protocol on the card the, host shall keep the -REG |
|
|
|
|
|
signal asserted during the execution of any DMA Command by the device. |
|
-DMACK |
|
|
This is a DMA Acknowledge signal that is asserted by the host in response to |
||
(PC Card Memory Mode when |
|
|
(-)DMARQ to initiate DMA transfers. |
||
Ultra DMA Protocol Active) |
|
|
In True IDE Mode, while DMA operations are not active, the card shall ignore the |
||
DMACK |
|
|
|||
|
|
(-)DMACK signal, including a floating condition. |
|||
(PC Card I/O Mode when Ultra |
|
|
If DMA operation is not supported by a True IDE Mode only host, this signal |
||
DMA Protocol Active) |
|
|
|||
-DMACK |
|
|
should be driven high or connected to VCC by the host. |
||
|
|
|
|
||
(True IDE Mode) |
|
|
A host that does not support DMA mode and implements both PC Card and |
||
|
|
|
|
True-IDE modes of operation need not alter the PC Card mode connections |
|
|
|
|
|
while in True-IDE mode as long as this does not prevent proper operation all |
|
|
|
|
|
modes. |
|
RESET |
I |
41 |
The CompactFlash Storage Card is Reset when the RESET pin is high with the |
||
(PC Card Memory Mode) |
|
|
following important exception: |
||
|
|
|
|
The host may leave the RESET pin open or keep it continually high from the |
|
|
|
|
|
application of power without causing a continuous Reset of the card. Under |
|
|
|
|
|
either of these conditions, the card shall emerge from power-up having |
|
|
|
|
|
completed an initial Reset. |
|
|
|
|
|
The CompactFlash Storage Card is also Reset when the Soft Reset bit in the |
|
|
|
|
|
Card Configuration Option Register is set. |
|
RESET |
|
|
This signal is the same as the PC Card Memory Mode signal. |
||
(PC Card I/O Mode) |
|
|
|
|
|
-RESET |
|
|
In the True IDE Mode, this input pin is the active low hardware reset from the |
||
(True IDE Mode) |
|
|
host. |
||
|
|
|
|
||
VCC |
-- |
13,38 |
+5 V, +3.3 V power. |
||
(PC Card Memory Mode) |
|
|
|
|
|
VCC |
|
|
This signal is the same for all modes. |
||
(PC Card I/O Mode) |
|
|
|
|
|
VCC |
|
|
This signal is the same for all modes. |
||
(True IDE Mode) |
|
|
|
|
|
|
|
|
|
|
|
Transcend Information Inc. |
|
10 |
|
||
|
|
|
|
V1.6 |
TS2G~16GCF300 |
|
300X CompactFlash Card |
||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
Signal Name |
Dir. |
Pin |
Description |
||
-VS1 |
O |
33 |
Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host so |
|||
-VS2 |
that the CompactFlash Storage Card CIS can be read at 3.3 volts and -VS2 is |
|||||
|
40 |
|||||
(PC Card Memory Mode) |
|
reserved by PCMCIA for a secondary voltage and is not connected on the Card. |
||||
|
|
|||||
-VS1 |
|
|
This signal is the same for all modes. |
|||
-VS2 |
|
|
|
|
||
(PC Card I/O Mode) |
|
|
|
|
||
-VS1 |
|
|
This signal is the same for all modes. |
|||
-VS2 |
|
|
|
|
||
(True IDE Mode) |
|
|
|
|
||
-WAIT |
O |
42 |
The -WAIT signal is driven low by the CompactFlash Storage Card to signal the |
|||
(PC Card Memory Mode – Except |
host to delay completion of a memory or I/O cycle that is in progress. |
|||||
Ultra DMA Protocol Active) |
|
|
|
|
||
-WAIT |
|
|
This signal is the same as the PC Card Memory Mode signal. |
|||
(PC Card I/O Mode –Except Ultra |
|
|
|
|
||
DMA Protocol Active) |
|
|
|
|
||
IORDY |
|
|
In True IDE Mode, except in Ultra DMA modes, this output signal may be used as |
|||
(True IDE Mode – Except Ultra |
|
|
IORDY. |
|||
DMA Protocol Active) |
|
|
|
|
||
-DDMARDY |
|
|
In all modes, when Ultra DMA mode DMA Write is active, this signal is asserted |
|||
|
|
by the device during a data burst to indicate that the device is ready to receive |
||||
(All Modes – Ultra DMA Write |
|
|
||||
Protocol Active) |
|
|
Ultra DMA data out bursts. The device may negate -DDMARDY to pause an |
|||
|
|
|
|
Ultra DMA transfer. |
||
DSTROBE |
|
|
In all modes, when Ultra DMA mode DMA Read is active, this signal is the data in |
|||
(All Modes – Ultra DMA Read |
|
|
strobe generated by the device. Both the rising and falling edge of DSTROBE |
|||
Protocol Active) |
|
|
cause data to be latched by the host. The device may stop generating |
|||
|
|
|
|
DSTROBE edges to pause an Ultra DMA data in burst. |
||
-WE |
I |
36 |
This is a signal driven by the host and used for strobing memory write data to the |
|||
(PC Card Memory Mode) |
|
|
registers of the CompactFlash Storage Card when the card is configured in the |
|||
|
|
|
|
memory interface mode. It is also used for writing the configuration registers. |
||
-WE |
|
|
In PC Card I/O Mode, this signal is used for writing the configuration registers. |
|||
(PC Card I/O Mode) |
|
|
|
|
||
-WE |
|
|
In True IDE Mode, this input signal is not used and should be connected to VCC |
|||
(True IDE Mode) |
|
|
by the host. |
|||
WP |
O |
24 |
Memory Mode – The CompactFlash Storage Card does not have a write protect |
|||
(PC Card Memory Mode) |
switch. This signal is held low after the completion of the reset initialization |
|||||
Write Protect |
|
|
sequence. |
|||
-IOIS16 |
|
|
I/O Operation – When the CompactFlash Storage Card is configured for I/O |
|||
(PC Card I/O Mode) |
|
|
Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A |
|||
|
|
|
|
Low signal indicates that a 16 bit or odd byte only operation can be performed at |
||
|
|
|
|
the addressed port. |
||
-IOCS16 |
|
|
In True IDE Mode this output signal is asserted low when this device is expecting |
|||
(True IDE Mode) |
|
|
a word data transfer cycle. |
Transcend Information Inc. |
11 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
Electrical Specification
The following tables indicate all D.C. Characteristics for the CompactFlash Storage Card. Unless otherwise stated, conditions are:
Vcc = 5V ±10%
Vcc = 3.3V ± 5%
Absolute Maximum Conditions
DC Characteristics CompactFlash Interface I/O at 5.0V
Parameter |
Symbol |
Min. |
Max. |
Unit |
Remark |
Supply Voltage |
VCC |
4.5 |
5.5 |
V |
|
High level output voltage |
VOH |
VCC ─ 0.8 |
|
V |
|
Low level output voltage |
VOL |
|
0.8 |
V |
|
High level input voltage |
VIH |
4.0 |
|
V |
Non-schmitt trigger |
2.92 |
|
V |
Schmitt trigger1 |
||
Low level input voltage |
VIL |
|
0.8 |
V |
Non-schmitt trigger |
|
1.70 |
V |
Schmitt trigger1 |
||
Pull up resistance2 |
RPU |
50 |
73 |
KOhm |
|
Pull down resistance |
RPD |
50 |
97 |
KOhm |
|
CompactFlash Interface I/O at 3.3V
Parameter |
Symbol |
Min. |
Max. |
Unit |
Remark |
Supply Voltage |
VCC |
3.135 |
3.465 |
V |
|
High level output voltage |
VOH |
VCC ─ 0.8 |
|
V |
|
Low level output voltage |
VOL |
|
0.8 |
V |
|
High level input voltage |
VIH |
2.4 |
|
V |
Non-schmitt trigger |
2.05 |
|
V |
Schmitt trigger1 |
||
Low level input voltage |
VIL |
|
0.6 |
V |
Non-schmitt trigger |
|
1.25 |
V |
Schmitt trigger1 |
||
Pull up resistance2 |
RPU |
52.7 |
141 |
KOhm |
|
Pull down resistance |
RPD |
47.5 |
172 |
KOhm |
|
1.Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW pins
2.Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW, CSEL (P35), PDIAG, DASP pins
Transcend Information Inc. |
12 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
Input Power
Input Leakage Current
Input Characteristics for UDMA mode >4
In UDMA modes greater than 4, the following characteristics apply. Voltage output high and low values shall be met at the source connector to include the effect of series termination.
Table: Input Characteristics (UDMA Mode > 4)
Parameter |
Symbol |
MIN |
MAX |
Units |
|
DC supply voltage to drivers |
VDD3 |
3.3 –8% |
3.3% + 8% |
Volts |
|
Low to high input threshold |
V+ |
1.5 |
2.0 |
Volts |
|
High to low input threshold |
V- |
1.0 |
1.5 |
Volts |
|
Difference between input thresholds: |
VHYS |
320 |
|
Volts |
|
((V+ current value) - (V-current value)) |
|
||||
|
|
|
|
||
Average of thresholds: |
VTHRAVG |
1.3 |
1.7 |
Volts |
|
((V+ current value) + (V-current value))/2 |
|||||
|
|
|
|
||
Output Drive Type |
|
|
|
|
Transcend Information Inc. |
13 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
Output Drive Characteristics for UDMA mode > 4
In UDMA modes greater than 4, the characteristics specified in the following table apply. Voltage output high and low values shall be met at the source connector to include the effect of series termination.
Table: Output Drive Characteristics (UDMA Mode > 4)
Parameter |
Symbol |
MIN |
MAX |
Units |
|
DC supply voltage to drivers |
VDD3 |
3.3 –8% |
3.3% + 8% |
Volts |
|
Voltage output high at -6 mA to +3 mA (at VoH2 the output shall be |
VoH2 |
VDD3–0.51 |
VDD3+0.3 |
Volts |
|
able to supply and sink current toVDD3) |
|||||
|
|
|
|
||
Voltage output low at 6 mA |
VoL2 |
|
0.51 |
Volts |
Notes:
1)IoLDASP shall be 12 mA minimum to meet legacy timing and signal integrity.
2)IoH value at 400 μ A is insufficient in the case of DMARQ that is pulled low by a 5.6 kΩ resistor.
3)Voltage output high and low values shall be met at the source connector to include the effect of series termination.
4)A device shall have less than 64 μ A of leakage current into a 6.2 KΩ pull-down resistor while the INTRQ signal is in the released state.
Signal Interface
Electrical specifications shall be maintained to ensure data reliability. Additional requirements are necessary for Advanced Timing Modes and Ultra DMA modes operations. See next sections for additional information.
Transcend Information Inc. |
14 |
V1.6
TS2G~16GCF300 |
|
300X CompactFlash Card |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
Item |
Signal |
Card10 |
Host10 |
|
|
|
-CE1 |
Pull-up to VCC 500 KΩ R 50 KΩ and |
|
|
|
|
-CE2 |
|
|
|
|
|
shall be sufficient to keep inputs inactive |
|
|
|
|
Control Signal |
-REG |
|
|
|
|
|
-IORD |
when the pins are not connected at the |
|
|
|
|
-IOWR |
host.1 |
|
|
|
|
-OE |
Pull-up to VCC 500 KΩ R 50 KΩ .1,2 |
|
|
|
|
-WE |
|
|
|
|
|
RESET |
Pull-up to VCC 500 KΩ R 50 KΩ .1,2,9, |
|
|
|
|
READY |
|
Pull-up to VCC R 10 KΩ .3 |
|
|
Status Signal |
-WAIT |
|
||
|
|
WP |
|
|
|
|
|
|
|
In PCMCIA PC Card modes Pull-up to VCC |
|
|
|
|
|
R 10 KΩ .4 |
|
|
|
|
|
In True IDE mode, if DMA operation is |
|
|
|
|
|
supported by the host, Pull-down to Gnd R |
|
|
|
-INPACK |
|
5.6 KΩ .5 |
|
|
|
|
PC Card / True IDE hosts switch the pull-up |
||
|
|
|
|
||
|
|
|
|
to pull down in True IDE mode if DMA |
|
|
|
|
|
operation is supported. |
|
|
|
|
|
The PC Card mode Pull-up may be left |
|
|
|
|
|
active during True IDE mode if True IDE |
|
|
|
|
|
DMA operation is not supported. |
|
|
|
|
|
|
|
|
Address |
A[10:00] |
|
|
|
|
-CSEL |
|
|
|
|
|
|
|
|
|
|
|
Data Bus |
D[15:00] |
|
1. |
|
|
|
|
|
||
|
Card Detect |
-CD[2:1] |
Connected to GND in the card |
|
|
|
Voltage Sense |
-VS1 |
|
Pull-up to Vcc 10 KΩ R 100KΩ . |
|
|
-VS2 |
|
|||
|
|
|
|
|
|
|
Battery/Detect |
BVD[2:1] |
|
Pull-up R 50 KΩ .3.6 |
Transcend Information Inc. |
15 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF 10 at a DC current of 700 μ A low
state and 150 μ A high state, including pull-resistor. The socket shall be able to drive at least the following load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF with DC current 700 μ A low state and 150 μ A high state per socket).
2)Resistor is optional.
3)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μ A low
state and 100 μ A high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μ A low state and 100 μ A high state.
4)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μ A low state and 100 μ A high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μ A low state and 100 μ A high state.
5)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μ A low
state and 100 μ A high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μ A low state and 1100 μ A high state.
6)BVD2 was not defined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.”
7)Address Signals: each card shall present a load of no more than 100pF 10 at a DC current of 450μ A low state and
150μ A high state. The host shall be able to drive at least the following load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450μ A low state and 150μ A high state per socket).
8)Data Signals: the host and each card shall present a load no larger than 50pF 10 at a DC current of 450μ A and 150μ A high state. The host and each card shall be able to drive at least the following load 10 while meeting all AC
timing requirements: 100pF with DC current 1.6mA low state and 300μ A high state. This permits the host to wire two sockets in parallel without derating the card access speeds.
9)Reset Signal: This signal is pulled up to prevent the input from floating when a CFA to PCMCIA adapter is used in a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal operation the pull-up should be turned off once the Reset signal has been actively driven low by the host. Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input current leakage test.
10)Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for CF Advanced Timing Modes and Ultra DMA Electrical Requirements for additional required limitations on the implementation of CF Advanced Timing modes and Ultra DMA modes respectively.
Additional Requirements for CF Advanced Timing Modes
The CF Advanced Timing modes include PC Card I/O and Memory modes that are 100ns or faster, PC Card Ultra DMA modes 3 or above and True IDE PIO Modes 5,6, Multiword DMA Modes 3,4 and True IDE Ultra DMA modes 3 or above.
When operating in CF Advanced timing modes, the host shall conform to the following requirements:
1)Only one CF device shall be attached to the CF Bus.
2)The host shall not present a load of more than 40pF to the device for all signals, including any cabling.
3)The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host controller. 0.46 m (18 in) cables are not supported.
4)The -WAIT and IORDY signals shall be ignored by the host.
Transcend Information Inc. |
16 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with systems that do not support CF Advanced timing modes
Transcend Information Inc. |
17 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
Ultra DMA Electrical Requirements
¾Host and Card signal capacitance limits for Ultra DMA operation
The host interface signal capacitance at the host connector shall be a maximum of 25 pF for each signal as measured at
1MHz.
The card interface signal capacitance at the card connector shall be a maximum of 20 pF for each signal as measured at
1MHz.
¾Series termination required for Ultra DMA operation
Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA modes. Table describes typical values for series termination at the host and the device.
Table: Typical Series Termination for Ultra DMA
Signal |
Host Termination |
Device Termination |
-IORD (-HDMARDY,HSTROBE) |
22 ohm |
82 ohm |
-IOWR (STOP) |
22 ohm |
82 ohm |
-CS0, -CS1 |
33 ohm |
82 ohm |
A00, A01, A02 |
33 ohm |
82 ohm |
-DMACK |
22 ohm |
82 ohm |
D15 through D00 |
33 ohm |
33 ohm |
DMARQ |
82 ohm |
22 ohm |
INTRQ |
82 ohm |
22 ohm |
IORDY (-DDMARDY, DSTROBE) |
82 ohm |
22 ohm |
-RESET |
33 ohm |
82 ohm |
NOTE − Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA mode. Shows signals also requiring a pull-up or pull-down resistor at the host. The actual termination values should be selected to compensate for transceiver and trace impedance to match the characteristic cable impedance.
Transcend Information Inc. |
18 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
Table: Ultra DMA Termination with Pull-up or Pull down Example
¾ Printed Circuit Board (PCB) Trace Requirements for Ultra DMA
On any PCB for a host or device supporting Ultra DMA:
9The longest D[15:00] trace shall be no more than 0.5" longer than either STROBE trace as measured from the IC pin to the connector.
9The shortest D[15:00] trace shall be no more than 0.5" shorter than either STROBE trace as measured from the IC pin to the connector.
¾Ultra DMA Mode Cabling Requirement
9Operation in Ultra DMA mode requires a crosstalk suppressing cable. The cable shall have a grounded line between each signal line.
9For True IDE mode operation using a cable with IDE (ATA) type 40 pin connectors it is recommended that the host sense the cable type using the method described in the ANSI INCITS 361-2002 AT Attachment - 6 standard, to prevent use of Ultra DMA with a 40 conductor cable.
Transcend Information Inc. |
19 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
Attribute Memory Read Timing Specification
Attribute Memory access time is defined as 300 ns. Detailed timing specs are shown in Table below
Speed Version |
|
|
|
300 ns |
|
Item |
Symbol |
IEEE Symbol |
Min ns. |
|
Max ns. |
Read Cycle Time |
tc(R) |
tAVAV |
300 |
|
|
Address Access Time |
ta(A) |
tAVQV |
|
|
300 |
Card Enable Access Time |
ta(CE) |
tELQV |
|
|
300 |
Output Enable Access Time |
ta(OE) |
tGLQV |
|
|
150 |
Output Disable Time from CE |
tdis(CE) |
tEHQZ |
|
|
100 |
Output Disable Time from OE |
tdis(OE) |
tGHQZ |
|
|
100 |
Address Setup Time |
tsu (A) |
tAVGL |
30 |
|
|
Output Enable Time from CE |
ten(CE) |
tELQNZ |
5 |
|
|
Output Enable Time from OE |
ten(OE) |
tGLQNZ |
5 |
|
|
Data Valid from Address Change |
tv(A) |
tAXQX |
0 |
|
|
Note: All times are in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -CE signal or both the -OE signal and the -WE signal shall be de-asserted between consecutive cycle operations.
Transcend Information Inc. |
20 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
Configuration Register (Attribute Memory) Write Timing Specification
The Card Configuration write access time is defined as 250 ns. Detailed timing specifications are shown in Table below.
Table: Configuration Register (Attribute Memory) Write Timing
Speed Version |
|
|
|
250 ns |
|
|
|
|
|
|
|
Item |
Symbol |
IEEE Symbol |
Min ns |
|
Max ns |
|
|
|
|
|
|
Write Cycle Time |
tc(W) |
tAVAV |
250 |
|
|
|
|
|
|
|
|
Write Pulse Width |
tw(WE) |
tWLWH |
150 |
|
|
|
|
|
|
|
|
Address Setup Time |
tsu(A) |
tAVWL |
30 |
|
|
|
|
|
|
|
|
Write Recovery Time |
trec(WE) |
tWMAX |
30 |
|
|
|
|
|
|
|
|
Data Setup Time for WE |
tsu(D-WEH) |
tDVWH |
80 |
|
|
|
|
|
|
|
|
Data Hold Time |
th(D) |
tWMDX |
30 |
|
|
|
|
|
|
|
|
Note: All times are in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card .
Transcend Information Inc. |
21 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
Common Memory Read Timing Specification
|
Cycle Time Mode: |
250 ns |
120 ns |
100 ns |
80 ns |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
Item |
Symbol |
IEEE |
Min |
Max |
Min |
Max |
Min |
Max |
Min |
Max |
|
Symbol |
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
|||
|
|
||||||||||
Output Enable Access Time |
ta(OE) |
tGLQV |
|
125 |
|
60 |
|
50 |
|
45 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Output Disable Time from OE |
tdis(OE) |
tGHQZ |
|
100 |
|
60 |
|
50 |
|
45 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Address Setup Time |
tsu(A) |
tAVGL |
30 |
|
15 |
|
10 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address Hold Time |
th(A) |
tGHAX |
20 |
|
15 |
|
15 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CE Setup before OE |
tsu(CE) |
tELGL |
0 |
|
0 |
|
0 |
|
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CE Hold following OE |
th(CE) |
tGHEH |
20 |
|
15 |
|
15 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Wait Delay Falling from OE |
tv(WT-OE |
tGLWTV |
|
35 |
|
35 |
|
35 |
|
na1 |
|
|
) |
|
|
|
|
|
|
|
|
|
|
Data Setup for Wait Release |
tv(WT) |
tQVWTH |
|
0 |
|
0 |
|
0 |
|
na1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Wait Width Time2 |
tw(WT) |
tWTLWTH |
|
350 |
|
350 |
|
350 |
|
na1 |
|
|
|
|
|
|
|
|
|
|
|
|
Notes:1) –WAIT is not supported in this mode.
2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -WAIT signal may be ignored if the -OE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12µs but is intentionally less in this specification.
Transcend Information Inc. |
22 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
Common Memory Write Timing Specification
|
Cycle Time Mode: |
250 ns |
|
120 ns |
100 ns |
80 ns |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
Item |
Symbol |
IEEE |
Min |
|
Max |
Min |
Max |
Min |
Max |
Min |
Max |
Symbol |
ns. |
|
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
||
|
|
|
|||||||||
Data Setup before WE |
tsu (D-WEH) |
tDVWH |
80 |
|
|
50 |
|
40 |
|
30 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Data Hold following WE |
th(D) |
tWMDX |
30 |
|
|
15 |
|
10 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
WE Pulse Width |
tw(WE) |
tWLWH |
150 |
|
|
70 |
|
60 |
|
55 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Address Setup Time |
tsu(A) |
tAVWL |
30 |
|
|
15 |
|
10 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
CE Setup before WE |
tsu(CE) |
tELWL |
0 |
|
|
0 |
|
0 |
|
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Write Recovery Time |
trec(WE) |
tWMAX |
30 |
|
|
15 |
|
15 |
|
15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Address Hold Time |
th(A) |
tGHAX |
20 |
|
|
15 |
|
15 |
|
15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
CE Hold following WE |
th(CE) |
tGHEH |
20 |
|
|
15 |
|
15 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Wait Delay Falling from WE |
tv (WT-WE) |
tWLWTV |
|
|
35 |
|
35 |
|
35 |
|
na1 |
|
|
|
|
|
|
|
|
|
|
|
|
WE High from Wait Release |
tv(WT) |
tWTHWH |
0 |
|
|
0 |
|
0 |
|
na1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Wait Width Time2 |
tw (WT) |
tWTLWTH |
|
|
350 |
|
350 |
|
350 |
|
na1 |
|
|
|
|
|
|
|
|
|
|
|
|
Notes: 1) –WAIT is not supported in this mode.
2)The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card. The -WAIT signal may be ignored if the -WE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12μs but is intentionally less in this specification.
Transcend Information Inc. |
23 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
I/O Input (Read) Timing Specification
|
Cycle Time Mode: |
250 ns |
|
120 ns |
100 ns |
80 ns |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
Item |
Symbol |
IEEE |
Min |
|
Max |
Min |
Max |
Min |
Max |
Min |
Max |
Symbol |
ns. |
|
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
||
|
|
|
|||||||||
Data Delay after IORD |
td(IORD) |
tlGLQV |
|
|
100 |
|
50 |
|
50 |
|
45 |
|
|
|
|
|
|
|
|
|
|
|
|
Data Hold following IORD |
th(IORD) |
tlGHQX |
0 |
|
|
5 |
|
5 |
|
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
IORD Width Time |
tw(IORD) |
tlGLIGH |
165 |
|
|
70 |
|
65 |
|
55 |
|
|
|
|
|
|
|
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|
|
|
|
|
Address Setup before IORD |
tsuA(IORD) |
tAVIGL |
70 |
|
|
25 |
|
25 |
|
15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Address Hold following IORD |
thA(IORD) |
tlGHAX |
20 |
|
|
10 |
|
10 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
CE Setup before IORD |
tsuCE(IORD) |
tELIGL |
5 |
|
|
5 |
|
5 |
|
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
CE Hold following IORD |
thCE(IORD) |
tlGHEH |
20 |
|
|
10 |
|
10 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
REG Setup before IORD |
tsuREG (IORD) |
tRGLIGL |
5 |
|
|
5 |
|
5 |
|
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
REG Hold following IORD |
thREG (IORD) |
tlGHRGH |
0 |
|
|
0 |
|
0 |
|
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
INPACK Delay Falling from IORD3 |
tdfINPACK (IORD) |
tlGLIAL |
0 |
|
45 |
0 |
na1 |
0 |
na1 |
0 |
na1 |
|
|
|
|
|
|
|
|
|
|
|
|
INPACK Delay Rising from IORD3 |
tdrINPACK (IORD) |
tlGHIAH |
|
|
45 |
|
na1 |
|
na1 |
|
na1 |
IOIS16 Delay Falling from Address3 |
tdfIOIS16 (ADR) |
tAVISL |
|
|
35 |
|
na1 |
|
na1 |
|
na1 |
IOIS16 Delay Rising from Address3 |
tdrIOIS16 (ADR) |
tAVISH |
|
|
35 |
|
na1 |
|
na1 |
|
na1 |
Wait Delay Falling from IORD3 |
tdWT(IORD) |
tlGLWTL |
|
|
35 |
|
35 |
|
35 |
|
na2 |
Data Delay from Wait Rising3 |
td(WT) |
tWTHQV |
|
|
0 |
|
0 |
|
0 |
|
na2 |
Wait Width Time3 |
tw(WT) |
tWTLWTH |
|
|
350 |
|
350 |
|
350 |
|
na2 |
Transcend Information Inc. |
24 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
I/O Output (Write) Timing Specification
|
Cycle Time Mode: |
255 ns |
120 ns |
100 ns |
80 ns |
||||||
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|
Item |
Symbol |
IEEE |
Min |
Max |
Min |
Max |
Min |
Max |
Min |
Max |
|
Symbol |
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
ns. |
|||
|
|
||||||||||
Data Setup before IOWR |
tsu(IOWR) |
tDVIWH |
60 |
|
20 |
|
20 |
|
15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Data Hold following IOWR |
th(IOWR) |
tlWHDX |
30 |
|
10 |
|
5 |
|
5 |
|
|
|
|
|
|
|
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|
|
|
|
|
|
IOWR Width Time |
tw(IOWR) |
tlWLIWH |
165 |
|
70 |
|
65 |
|
55 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address Setup before IOWR |
tsuA(IOWR) |
tAVIWL |
70 |
|
25 |
|
25 |
|
15 |
|
|
|
|
|
|
|
|
|
|
|
|
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|
Address Hold following IOWR |
thA(IOWR) |
tlWHAX |
20 |
|
20 |
|
10 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CE Setup before IOWR |
tsuCE (IOWR) |
tELIWL |
5 |
|
5 |
|
5 |
|
5 |
|
|
|
|
|
|
|
|
|
|
|
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|
|
CE Hold following IOWR |
thCE (IOWR) |
tlWHEH |
20 |
|
20 |
|
10 |
|
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
REG Setup before IOWR |
tsuREG (IOWR) |
tRGLIWL |
5 |
|
5 |
|
5 |
|
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
REG Hold following IOWR |
thREG (IOWR) |
tlWHRGH |
0 |
|
0 |
|
0 |
|
0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IOIS16 Delay Falling from Address3 |
tdfIOIS16 (ADR) |
tAVISL |
|
35 |
|
na1 |
|
na1 |
|
na1 |
|
IOIS16 Delay Rising from Address3 |
tdrIOIS16 (ADR) |
tAVISH |
|
35 |
|
na1 |
|
na1 |
|
na1 |
|
Wait Delay Falling from IOWR3 |
tdWT(IOWR) |
tlWLWTL |
|
35 |
|
35 |
|
35 |
|
na2 |
|
IOWR high from Wait high3 |
tdrIOWR (WT) |
tWTJIWH |
0 |
|
0 |
|
0 |
|
na2 |
|
|
Wait Width Time3 |
tw(WT) |
tWTLWTH |
|
350 |
|
350 |
|
350 |
|
na2 |
Transcend Information Inc. |
25 |
V1.6
TS2G~16GCF300 |
300X CompactFlash Card |
|
|
|
|
True IDE PIO Mode Read/Write Timing Specification
|
Item |
|
|
|
Mode |
|
|
|
Note |
|
|
|
|
|
|
|
|
|
|||
|
0 |
1 |
2 |
3 |
4 |
5 |
6 |
|||
|
|
|
||||||||
|
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|
|
|
|
|
|
|
t0 |
Cycle time (min) |
600 |
383 |
240 |
180 |
120 |
100 |
80 |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
t1 |
Address Valid to -IORD/-IOWR |
70 |
50 |
30 |
30 |
25 |
15 |
10 |
|
|
setup (min) |
|
|||||||||
|
|
|
|
|
|
|
|
|
||
t2 |
-IORD/-IOWR (min) |
165 |
125 |
100 |
80 |
70 |
65 |
55 |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
t2 |
-IORD/-IOWR (min) Register (8 bit) |
290 |
290 |
290 |
80 |
70 |
65 |
55 |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
t2i |
-IORD/-IOWR recovery time (min) |
- |
- |
- |
70 |
25 |
25 |
20 |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
t3 |
-IOWR data setup (min) |
60 |
45 |
30 |
30 |
20 |
20 |
15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
t4 |
-IOWR data hold (min) |
30 |
20 |
15 |
10 |
10 |
5 |
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
t5 |
-IORD data setup (min) |
50 |
35 |
20 |
20 |
20 |
15 |
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
t6 |
-IORD data hold (min) |
5 |
5 |
5 |
5 |
5 |
5 |
5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
T6Z |
-IORD data tristate (max) |
30 |
30 |
30 |
30 |
30 |
20 |
20 |
2 |
|
|
|
|
|
|
|
|
|
|
|
|
t7 |
Address valid to -IOCS16 assertion |
90 |
50 |
40 |
n/a |
n/a |
n/a |
n/a |
4 |
|
(max) |
||||||||||
|
|
|
|
|
|
|
|
|
||
t8 |
Address valid to -IOCS16 released |
60 |
45 |
30 |
n/a |
n/a |
n/a |
n/a |
4 |
|
(max) |
||||||||||
|
|
|
|
|
|
|
|
|
||
t9 |
-IORD/-IOWR to address valid hold |
20 |
15 |
10 |
10 |
10 |
10 |
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
tRD |
Read Data Valid to IORDY active |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
|
(min), if IORDY initially low after tA |
|
|||||||||
|
|
|
|
|
|
|
|
|
||
tA |
IORDY Setup time |
35 |
35 |
35 |
35 |
35 |
na5 |
na5 |
3 |
|
tB |
IORDY Pulse Width (max) |
1250 |
1250 |
1250 |
1250 |
1250 |
na5 |
na5 |
|
|
tC |
IORDY assertion to release (max) |
5 |
5 |
5 |
5 |
5 |
na5 |
na5 |
|
Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width shall still be met.
1)t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t0, t2, and t2i shall be met. The minimum total cycle time requirement is greater than the sum of t2 and t2i. This means a host implementation can lengthen either or both t2 or t2i to ensure that t0 is equal to or greater than the value reported in the device’s identify device data. A CompactFlash Storage Card implementation shall support any legal host implementation.
2)This parameter specifies the time from the negation edge of -IORD to the time that the data bus is no longer driven by the CompactFlash Storage Card (tri-state).
3)The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the CompactFlash Storage Card is not driving IORDY negated at tA after the activation of -IORD or -IOWR, then t5 shall be met and tRD is not applicable. If the CompactFlash Storage Card is driving IORDY negated at the time tA after the activation of -IORD or -IOWR, then tRD shall be met and t5 is not applicable.
4)t7 and t8 apply only to modes 0, 1 and 2. For other modes, this signal is not valid.
5)IORDY is not supported in this mode.
Transcend Information Inc. |
26 |
V1.6