Transcend TS32GMSM360 User Manual

Side

Millimeters

Inches

A

29.85 +/-0.15

1.06 +/-0.006

B

26.8 +/-0.15

1.175 +/-0.006

C

3.85 (Max)

0.152 (Max)

MSM360 –
SATA III 6Gb/s mSATA mini SSD

Transcend MSM360 series are mSATA mini Solid State

Drives (SSDs) with high performance and quality Flash

Memory assembled on a printed circuit board. These

devices feature cutting-edge technology to enhance

product life and data retention. MSM360 is designed

specifically for various applications, such as Ultrabooks,

industrial PCs, vehicle PCs and road surveillance

recording.

Placement

Features

 RoHS compliant
 Power Supply: 3.3V±5%
 Operating Temperature: -0oC to 70oC
 Built-in 66 bits per 1KByte ECC (Error Correction Code)

functionality ensures highly reliable of data transfer.

 Global wear-leveling algorithm eliminates excessive write

operation and extends product life.

 Supports S.M.A.R.T (Self-defined)
 Supports Security Command
 Supports Device Sleep

 Fully compatible with devices and OS that support the

SATA 6Gb/s standard

 Compliant with JEDEC MO-300B
 Supports Transcend SSD Scope Pro (Optional)

Dimensions

Physical Specification

Form Factor

MO-300B

Storage Capacities

128GB

Dimensions

Length

26.8  0.15 mm

Width

29.85  0.15 mm

Height

3.85 mm (Max)

Input Voltage

3.3V  5%

Weight

3g

Connector

PCI Express Mini Card Connector

Environmental Specifications

Operating Temperature

0 ℃ to 70 ℃

Storage Temperature

- 45 ℃ to 85 ℃

Humidity
Operating

0% to 95% (Non-condensing)

Non-Operating

0% to 95% (Non-condensing)

Performance

Model P/N

Sequential

Read*

Sequential

Write*

Random

Read

(4KB QD32)*

Random

Write

(4KB QD32)*

IOPS

Random Read

(4KB QD32)**

IOPS

Random Write

(4KB QD32)**

TS128GMSM360

514.1

160.4

117.5

156.4

32743

38150

Reliability

Data Reliability

Supports BCH ECC 66 bits per 1K byte

MTBF

1,000,000 hours

Endurance (Terabytes Written)

128G

TBT

Regulations

Compliance

CE, FCC and BSMI

Specifications

Note: Maximum transfer speed recorded
* 25 °C , test on GA-Z87Z-UD3H, 4GB, Windows® 8.1 x64 with AHCI mode, benchmark utility CrystalDiskMark (version 3.0.1), copied file 1000MB
** Random read/write performance based on IOmeter2008 with 4K file size and queue depth of 32
*** The recorded performance is obtained while the SSD is not operating as an OS disk

Actual Capacity

Model P/N

User Max. LBA

Cylinder

Head

Sector

TS128GMSM360

250,069,680

16,383

16

63

Power Requirements

Input Voltage

3.3V  5%

Mode

Max. (mA)

TS128GMSM360

Write

(peak)

523

Read

(peak)

379

Idle

(peak)

115

Devslp

(peak)

1.5

Package Dimensions

The figure below illustrates the Transcend MSM360 mSATA mini Solid State Disk. All dimensions are in mm.

*Note: Tighten mounting screws with no more than 1.0kgf-cm (0.07LB-ft) of torque.

Pin No.

Pin Name

Pin No.

Pin Name

01

NC

02

3.3V

03

NC

04

GND

05

NC

06

NC

07

NC

08

NC

09

GND

10

NC

11

NC

12

NC

13

NC

14

NC

15

GND

16

NC

17

NC

18

GND

19

NC

20

NC

21

GND

22

NC

23

TX+

24

3.3V

25

TX-

26

GND

27

GND

28

NC

29

GND

30

NC

31

RX-

32

NC

33

RX+

34

GND

35

GND

36

NC

37

GND

38

NC

39

3.3V

40

GND

41

3.3V

42

NC

43

NC

44

NC/DEVSLP(optional)

45

Vendor

46

NC

47

Vendor

48

NC

49

DAS/DSS*

50

GND

51

Presence Detection**

52

3.3V

Pin Assignments

* Device Activity Signal / Disable Staggered Spin-up
** Connect to GND internally

Pin Layout

SATA Host

NAND

Flash

NAND

Flash

NAND

Flash

NAND

Flash

SSD Controller

Flash Interface

SATA Interface

Block Diagram

Features

Wear Leveling Algorithm

The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block
with the lowest erase count among the free blocks. This is known as dynamic wear leveling. If the free block erase count is
higher than a threshold value plus data blocks, it will activate the static wear leveling, replacing the not so frequently used
user blocks with the high erase count free blocks.

ECC Algorithm

Using a BCH 66 bit Error Correction Code algorithm with each channel, the controller can correct up to 66 random bit
errors per 1K byte data sector for MLC NAND flash. The hardware executes parity generation and error
detection/correction features.

Bad Block Management

When the flash encounters an ECC, program or erase failure, the controller will mark the block as a bad block to

prevent use of this block and cause data loss in the future.