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TS1GLH72V1H
User Manual
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Transcend TS1GLH72V1H User Manual

1
Symbol
Function
A0–A14
SDRAM address bus
BA0, BA1
SDRAM bank select
BG0, BG1
SDRAM bank group select
RAS_n
SDRAM row address strobe
CAS_n
SDRAM column address strobe
WE_n
SDRAM write enable
CS0_n, CS1_n
DIMM Rank Select Lines
CKE0, CKE1
SDRAM clock enable lines
ODT0, ODT1
SDRAM on-die termination control lines
ACT_n
SDRAM activate
DQ0–DQ63
DIMM memory data bus
CB0–CB7
DIMM ECC check bits
DM_n/DBI_n/
Input data mask and data bus inversion
DQS0_t–DQS8_t
SDRAM data strobes (positive line of differential pair)
DQS0_c–DQS8_c
SDRAM data strobes (negative line of differential pair)
CK0_t, CK1_t
SDRAM clocks (positive line of differential pair)
CK0_c, CK1_c
SDRAM clocks (negative line of differential pair)
PARITY
SDRAM parity input
VDD
SDRAM I/O and core power supply
VREFCA
SDRAM command/address reference supply
VSS
Power supply return (ground)
VDDSPD
Serial SPD EEPROM positive power supply
SCL
I2C serial bus clock for EEPROM
SDA
I2C serial bus data line for EEPROM
SA0–SA2
I2C slave address select for EEPROM
ALERT_n
SDRAM ALERT_n
VPP
SDRAM Supply
RESET_n
Set DRAMs to a Known State
EVENT_n
SPD signals a thermal event has occurred
VTT
SDRAM I/O termination supply
RFU
Reserved for future use
NC
No Connection
TS1GLH72V1H
Description
DDR4 ECC U-DIMMs are high-speed, low power memory modules that use 512Mx8bits DDR4 SDRAM in FBGA package and a 4K-bit serial EEPROM on a 260-pin printed circuit board. DDR4 ECC U-DIMMs are Dual In-Line memory modules and are intended for mounting into 260-pin edge connector sockets. The synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. The large range of operation frequencies and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
Pin Identification
Features
RoHS compliant JEDEC standard 1.2V ± 0.06V power supply VDDQ=1.2V ± 0.06V Clock Freq: 1067MHZ for 2133Mb/s/Pin. Programmable CAS Latency: 10,11,12,13,14,15,16 Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
Programmable /CAS Write Latency (CWL)
= 11, 14(DDR4-2133)
8 bit pre-fetch Burst Length: 4, 8 Bi-directional Differential Data-Strobe On Die Termination with ODT pin Serial presence detect with EEPROM On DIMM Thermal Sensor Asynchronous reset
2
Dimensions (Unit: millimeter)
Note:
1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.
3
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
Pin
No
Pin
Name
01
NC
37
VSS
73
VDD
109
VSS
145
NC
181
DQ29
217
VDD
253
DQ41
02
VSS
38
DQ24
74
CK0_t
110
DM5_n/ DBI5_n,
NC
146
VREFCA
182
VSS
218
CK1_t
254
VSS
03
DQ4
39
VSS
75
CK0_c
111
NC
147
VSS
183
DQ25
219
CK1_c
255
DQS5_c
04
VSS
40
DM3_n/
DBI3_n,
NC
76
VDD
112
VSS
148
DQ5
184
VSS
220
VDD
256
DQS5_t
05
DQ0
41
NC
77
VTT
113
DQ46
149
VSS
185
DQS3_c
221
VTT
257
VSS
06
VSS
42
VSS
78
EVENT_n
114
VSS
150
DQ1
186
DQS3_t
222
PARITY
258
DQ47
07
DM0_n/ DBI0_n,
NC
43
DQ30
79
A0
115
DQ42
151
VSS
187
VSS
223
VDD
259
VSS
08
NC
44
VSS
80
VDD
116
VSS
152
DQS0_c
188
DQ31
224
BA1
260
DQ43
09
VSS
45
DQ26
81
BA0
117
DQ52
153
DQS0_t
189
VSS
225
A10/AP
261
VSS
10
DQ6
46
VSS
82
RAS_n/A16
118
VSS
154
VSS
190
DQ27
226
VDD
262
DQ53
11
VSS
47
CB4/ NC
83
VDD
119
DQ48
155
DQ7
191
VSS
227
RFU
263
VSS
12
DQ2
48
VSS
84
CS0_n
120
VSS
156
VSS
192
CB5, NC
228
WE_n/A14
264
DQ49
13
VSS
49
CB0/ NC
85
VDD
121
DM6_n/ DBI6_n,
NC
157
DQ3
193
VSS
229
VDD
265
VSS
14
DQ12
50
VSS
86
CAS_n/A15
122
NC
158
VSS
194
CB1, NC
230
NC
266
DQS6_c
15
VSS
51
DM8_n/
DBI8_n,
NC
87
ODT0
123
VSS
159
DQ13
195
VSS
231
VDD
267
DQS6_t
16
DQ8
52
NC
88
VDD
124
DQ54
160
VSS
196
DQS8_c
232
A13
268
VSS
17
VSS
53
VSS
89
CS1_n
125
VSS
161
DQ9
197
DQS8_t
233
VDD
269
DQS5
18
DMI_n/
DBI1_n,
NC
54
CB6/
DBI8_n,
NC
90
VDD
126
DQ50
162
VSS
198
VSS
234
NC
270
VSS
19
NC
55
VSS
91
ODT1
127
VSS
163
DQS1_c
199
CB7, NC
235
NC
271
DQ51
20
VSS
56
CB2/ NC
92
VDD
128
DQ60
164
DQS1_t
200
VSS
236
VDD
272
VSS
21
DQ14
57
VSS
93
NC
129
VSS
165
VSS
201
CB3, NC
237
NC
273
DQ61
22
VSS
58
RESET_n
94
VSS
130
DQ56
166
DQ15
202
VSS
238
SA2
274
VSS
23
DQ10
59
VDD
95
DQ36
131
VSS
167
VSS
203
CKE1
239
VSS
275
DQ57
24
VSS
60
CKE0
96
VSS
132
DM7_n/ DBI7_n,
NC
168
DQ11
204
VDD
240
DQ37
276
VSS
25
DQ20
61
VDD
97
DQ32
133
NC
169
VSS
205
RFU
241
VSS
277
DQS7_c
26
VSS
62
ACT_n
98
VSS
134
VSS
170
DQ21
206
VDD
242
DQ33
278
DQS7_t
27
DQ16
63
BG0
99
DM4_n/ DBI4_n,
NC
135
DQ62
171
VSS
207
BG1
243
VSS
279
VSS
28
VSS
64
VDD
100
NC
136
VSS
172
DQ17
208
ALERT_n
244
DQS4_c
280
DQ63
29
DM2_n/ DBI2_n,
NC
65
A12/BC_n
101
VSS
137
DQ58
173
VSS
209
VDD
245
DQS4_t
281
VSS
30
NC
66
A9
102
DQ38
138
VSS
174
DQS2_c
210
A11
246
VSS
282
DQ59
31
VSS
67
VDD
103
VSS
139
SA0
175
DQS2_t
211
A7
247
DQ39
283
VSS
32
DQ22
68
A8
104
DQ34
140
SA1
176
VSS
212
VDD
248
VSS
284
VDDSPD
33
VSS
69
A6
105
VSS
141
SCL
177
DQ23
213
A5
249
DQ35
285
SDA
34
DQ18
70
VDD
106
DQ44
142
VPP
178
VSS
214
A4
250
VSS
286
VPP
35
VSS
71
A3
107
VSS
143
VPP
179
DQ19
215
VDD
251
DQ45
287
VPP
36
DQ28
72
A1
108
DQ40
144
RFU
180
VSS
216
A2
252
VSS
288
VPP
Note:
1. VPP is 2.5V DC.
2. Pin 230 is defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pin 230 is defined as SAVE_n for NVDIMMs.
3. Pins 1 and 145 are defined as NC for UDIMMs, RDIMMs and LRDIMMs. Pins 1 and 145 are defined as 12V for Hybrid /NVDIMM
4. The 5th VPP is required on all modules and DIMMs.
Pin Assignments
4
Block Diagram 8GB, 1Gx72 Module(2 Rank x8)
This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes
in specifications at any time without prior notice.
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