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SD80 Secure Digital Card
Transcend Information Inc.
1
Description
Secure Digital Card is a compact, slim and high
capacity storage media with copyright protection.
Designed in advanced SD specification Ver.1.1,
Transcend SD80 series now reaches a new
performance milestone. Based on 0.16 um process
controller and high quality SLC (Single-Level-Cell)
NAND Flash chip, Transcend SD80 series can
provide high performance ,low power consumption yet
excellent reliability.
-Manufactured with SLC NAND Flash chip
-Operating Temperature : -25 ~ 85°C
Placement
Front Back
Features
• Storage Capacity: 128M~1GB
• Operating Voltage: 2.7 ~ 3.6V
• Operating Temperature: -25 ~ 85°C
• Insertion/removal durability: 10,000 cycles
• Fully compatible with SD card spec. v1.1
• Support SD command class 0,2,4,5,7,8
• Mechanical Write Protection Switch
• Forward compatibility to MultiMediaCard Version 2.11
• Supports Copy Protection for Recorded Media(CPRM)
for music and other commercial media
• Form Factor: 24mm x 32mm x 2.1mm
Pin Definition
SD Mode SPI Mode
Pin No.
Name Type
Description Name Type
Description
1
CD/DAT3
I/O/PP
Card Detect/Data Line [Bit3]
CS I
Chip Select (neg true)
2
CMD PP Command/Response
DI I
Data In
3
V
SS1
S Supply voltage ground
VSS S
Supply voltage ground
4
V
DD
S Supply voltage
VDD S
Supply voltage
5
CLK I Clock
SCLK
I
Clock
6
V
SS2
S Supply voltage ground
VSS2
S
Supply voltage ground
7
DAT0 I/O/PP Data Line [Bit0]
DO O/PP
Data Out
8
DAT1 I/O/PP Data Line [Bit1]
RSV
9
DAT2
I/O/PP Data Line [Bit2] RSV
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Architecture
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Bus Operating Conditions
• General
Parameter Symbol
Min. Max. Unit Remark
Peak voltage on all lines -0.3 VDD+0.3
V
All Inputs
Input Leakage Current -10 10 µA
All Outputs
Output Leakage Current -10 10 µA
• Power Supply Voltage
Parameter Symbol
Min. Max. Unit Remark
Supply voltage V
DD
2.0 3.6 V CMD0, 15,55,ACMD41
commands
Supply voltage specified in OCR register 2.7 3.6 V Except CMD0, 15,55,
ACMD41 commands
Supply voltage differentials (V
SS1
, V
SS2
) -0.3 0.3 V
Power up time 250 ms From 0v to VDD Min.
•
Bus Signal Line Load
The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance C
HOST
, the bus
capacitance C
BUS
itself and the capacitance C
CARD
of each card connected to this line:
CL = C
HOST
+ C
BUS
+ Ν*C
CARD
Parameter Symbol
Min. Max. Unit Remark
Bus signal line capacitance CL 100 pF fPP ≤ 20 MHz, 7 cards
Single card capacitance C
CARD
10 pF
Maximum signal line inductance 16 nH fPP ≤ 20 MHz
Pull-up resistance inside card (pin1) R
DAT3
10 90 kΩ May be used for card
detection
Note that the total capacitance of CMD and DAT lines will be consist of C
HOST
, C
BUS
and one C
CARD
only since they are
connected separately to the SD Memory Card host.
Parameter Symbol
Min. Max. Unit Remark
Pull-up resistance R
CMD
, R
DAT
10 100 kΩ To prevent bus floating
Bus signal line capacitance CL 250 pF fPP ≤ 5 MHz, 21 cards
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•
Bus Signal Levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
To meet the requirements of the JEDEC specification JESD8-1A, the card input and output voltages shall be within the
following specified ranges for any VDD of the allowed voltage range:
Parameter Symbol Min. Max. Unit Remark
Output HIGH voltage V
OH
0.75* VDD V I
OH
= -100 µA @VDD min
Output LOW voltage V
OL
0.125* VDD V I
OL
= -100 µA @VDD min
Input HIGH voltage V
IH
0.625* VDD V
DD
+ 0.3 V
Input LOW voltage V
IL
VSS – 0.3 0.25* VDD V
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•
Bus Timing (Default)
Parameter Symbol Min Max. Unit Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency Data Transfer Mode f
PP
0 25 MHz CL ≤ 100 pF, (7 cards)
Clock frequency Identification Mode
(The low freq. is required for MultiMediaCard
compatibility.)
f
OD
0 400 KHz CL ≤ 250 pF, (21 cards)
t
WL
10 ns CL ≤ 100 pF, (7 cards) Clock low time
50 ns CL ≤ 250 pF, (21 cards)
t
WH
10 ns CL ≤ 100 pF, (7 cards) Clock high time
50 ns CL ≤ 250 pF, (21 cards)
Clock rise time t
TLH
10 ns CL ≤ 100 pF, (7 cards)
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50 ns CL ≤ 250 pF, (21 cards)
t
THL
10 ns CL ≤ 100 pF, (7 cards) Clock fall time
50 ns CL ≤ 250 pF, (21 cards)
Inputs CMD, DAT (referenced to CLK)
Input set-up time t
ISU
5 ns CL ≤ 25 pF, (1 cards)
Input hold time t
IH
5 ns CL ≤ 25 pF, (1 cards)
Outputs CMD, DAT (referenced to CLK)
Output Delay time during Data Transfer Mode t
ODLY
0 14 ns CL ≤ 25 pF, (1 cards)
Output Delay time during Identification Mode t
ODLY
0 50 ns CL ≤ 25 pF, (1 cards)
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•
Bus Timing (High Speed Mode)
Parameter Symbol Min Max. Unit Remark
Clock CLK (All values are referred to min (VIH) and max (VIL)
Clock frequency Data Transfer Mode f
PP
0 50 MHz
Clock low time t
WL
7 ns
Clock high time t
WH
7 ns
Clock rise time t
TLH
3 ns
Clock fall time t
THL
3 ns
Inputs CMD, DAT (referenced to CLK)
Input set-up time t
ISU
6 ns
Input hold time t
IH
2 ns
Outputs CMD, DAT (referenced to CLK)
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Output Delay time during Data Transfer Mode t
ODLY
14 ns
Output Hold time t
OH
2.5 ns
Total System capacitance for each line CL 40 pF
Reliability and Durability
Temperature Operation: -25°C / 85°C (Target spec)
Storage: -40°C (168h) / 85°C (500h)
Junction temperature: max. 95°C
Moisture and corrosion Operation: 25°C / 95% rel. humidity
Storage: 40°C / 93% rel. hum./500h
Salt Water Spray: 3% NaCl/35C; 24h acc. MIL STD Method 1009
Durability 10.000 mating cycles
Bending 10N
Torque 0.15N.m or +/-2.5 deg
Drop test 1.5m free fall
Visual inspection
Shape and form
No warpage; no mold skin; complete form; no cavities surface smoothness <= -0.1
mm/cm² within contour; no cracks; no pollution (fat, oil dust, etc.)
Minimum moving force of W P witch 40gf (Ensures that the WP switch will not slide while it is inserted to the connector.)
WP Switch cycles minimum 1000 Cycles(@Slide force 0.4N to 5N)
Above technical information is based on industry standard data and tested to be reliable. However, Transcend makes no
warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product.
Transcend reserves the right to make changes in specifications at any time without prior notice.
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Register Information
Within the card interface six registers are defined: OCR, CID, CSD, RCA, DSR and SCR. These can be accessed only
by corresponding commands. The OCR, CID, CSD and SCR registers carry the card/content specific information,
while the RCA and DSR registers are configuration registers storing actual configuration parameters.
1. OCR register
The 32-bit operation conditions register stores the VDD voltage profile of the card. Additionally, this register
includes status information bits. One status bit is set if the card power up procedure has been finished. This register
includes another status bit indicating the card capacity status after set power up status bit. The OCR register shall be
implemented by the cards. The 32-bit operation conditions register stores the VDD voltage profile of the card. Bit 7 of
OCR is newly defined for Dual Voltage Card and set to 0 in default. If a Dual Voltage Card does not receive CMD8,
OCR bit 7 in the response indicates 0, and the Dual Voltage Card which received CMD8, sets this bit to 1.
Additionally, this register includes 2 more status information bits. Bit 31 - Card power up status bit, this status bit
is set if the card power up procedure has been finished. Bit 30 - Card capacity status bit, this status bit is set to 1 if card
is High Capacity SD Memory Card. 0 indicates that the card is Standard Capacity SD Memory Card. The Card Capacity
status bit is valid after the card power up procedure is completed and the card power up status bit is set to 1. The Host
shall read this status bit to identify a Standard or High Capacity SD Memory Card.
The OCR register shall be implemented by the cards.
OCR Register Definition
1) This bit is valid only when the card power up status bit is set.
2) This bit is set to LOW if the card has not finished the power up routine.
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A voltage range is not supported if the corresponding bit value is set to LOW. As long as the card is busy, the
corresponding bit (31) is set to LOW.
2. CID Register
The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the
card identification phase. Every individual flash card shall have a unique identification number. The structure of the
CID register is defined in the following paragraphs:
•
MID:
An 8-bit binary number that identifies the card manufacturer. The MID number is controlled, defined,
and allocated to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to
ensure uniqueness of the CID register.
•
OID :
A 2-character ASCII string that identifies the card OEM and/or the card contents (when used as a
distribution media either on ROM or FLASH cards). The OID number is controlled, defined, and allocated
to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to ensure
uniqueness of the CID register.
Note: SD-3C, LLC licenses companies that wish to manufacture and/or sell SD Memory Cards, including but not limited to flash memory,
ROM, OTP, RAM, and SDIO Combo Cards.
SD-3C, LLC is a limited liability company established by Matsushita Electric Industrial Co. Ltd., SanDisk Corporation and Toshiba
Corporation.
•
PNM :
The product name is a string, 5 ASCII characters long.
•
PRV
The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing an “n.m”
revision number. The “n” is the most significant nibble and “m” is the least significant nibble.
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As an example, the PRV binary value field for product revision “6.2” will be: 0110 0010
•
PSN
The Serial Number is 32 bits of binary number.
•
MDT
The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y)
and the other is four bits representing the month(m).
The “m” field [11:8] is the month code. 1 = January.
The “y” field [19:12] is the year code. 0 = 2000.
As an example, the binary value of the Date field for production date “April 2001” will be:
00000001 0100.
•
CRC
CRC7 checksum (7 bits).
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3. CSD Register
The following sections describe the CSD fields and the relevant data types for the High Capacity SD Memory Card.
CSD Version 2.0 is applied to only the High Capacity SD Memory Card. The field name in parenthesis is set to fixed
value and indicates that the host is not necessary to refer these fields. The fixed values enables host, which refers to
these fields, to keep compatibility to CSD Version 1.0. The Cell Type field is coded as follows: R = readable, W(1) =
writable once, W = multiple writable.
The CSD Register Fields (CSD Version 2.0)
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The following sections describe the CSD fields and the relevant data types. If not explicitly defined otherwise, all bit
strings are interpreted as binary coded numbers starting with the left bit first.
•
CSD_STRUCTURE
Field structures of the CSD register are different depend on the Physical Specification Version and Card
Capacity.
The CSD_STRUCTURE field in the CSD register indicates its structure version.
The following table shows the version number of the related CSD structure.
CSD Register Structure
•
TAAC
This field is fixed to 0Eh, which indicates 1 ms. The host should not use TAAC, NSAC, and R2W_FACTOR to calculate
timeout and should uses fixed timeout values for read and write operations.
•
NSAC
This field is fixed to 00h. NSAC should not be used to calculate time-out values.
•
TRAN_SPEED
The following table defines the maximum data transfer rate per one data line - TRAN_SPEED:
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Note that for current SD Memory Cards that field must be always 0_0110_010b (032h) which is equal to 25MHz - the
mandatory maximum operating frequency of SD Memory Card.
In High-Speed mode, that field must be always 0_1011_010b (05Ah) which is equal to 50MHz. And when the timing
mode returns to the default by CMD6 or CMD0 command, its value will be 032h.
•
CCC
The SD Memory Card command set is divided into subsets (command classes). The card command class register
CCC defines which command classes are supported by this card. A value of ‘1’ in a CCC bit means that the
corresponding command class is supported.
•
READ_BL_LEN
This field is fixed to 9h, which indicates READ_BL_LEN=512 Byte.
•
READ_BL_PARTIAL
This field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is allowed.
•
WRITE_BLK_MISALIGN
This field is fixed to 0, which indicates write access crossing physical block boundaries is always disabled in High
Capacity SD Memory Card.
•
READ_BLK_MISALIGN
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This field is fixed to 0, which indicates read access crossing physical block boundaries is always
disabled in High Capacity SD Memory Card.
•
DSR_IMP
Defines if the configurable driver stage is integrated on the card. If set, a driver stage register (DSR)must be
implemented also.
•
C_SIZE
This field is expanded to 22 bits and can indicate up to 2 TBytes (It is the same as the maximum memory space
specified by a 32-bit block address.)
This parameter is used to calculate the user data area capacity in the SD memory card (not include the protected area).
The user data area capacity is calculated from C_SIZE as follows: memory capacity = (C_SIZE+1) * 512K byte
As the maximum capacity of the Physical Layer Specification Version 2.00 is 32 GB, the upper 6 bits of this field shall
be set to 0.
•
ERASE_BLK_EN
This field is fixed to 1, which means the host can erase one or multiple units of 512 bytes.
•
SECTOR_SIZE
This field is fixed to 7Fh, which indicates 64 KBytes. This value does not relate to erase operation. Version 2.00 cards
indicates memory boundary by AU size and this field should not be used.
•
WP_GRP_SIZE
This field is fixed to 00h. The High Capacity SD Memory Card does not support write protected groups.
•
WP_GRP_ENABLE
This field is fixed to 0. The High Capacity SD Memory Card does not support write protected groups.
•
R2W_FACTOR
This field is fixed to 2h, which indicates 4 multiples. Write timeout can be calculated by multiplying the read access time
and R2W_FACTOR. However, the host should not use this factor and should use 250 ms for write timeout
•
WRITE_BL_LEN
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This field is fixed to 9h, which indicates WRITE_BL_LEN=512 Byte.
•
WRITE_BL_PARTIAL
This field is fixed to 0, which indicates partial block read is inhibited and only unit of block access is allowed.
•
FILE_FORMAT_GRP
This field is set to 0. Host should not use this field.
•
COPY
Defines if the contents is original (= ‘0’) or has been copied (=’1’). The COPY bit for OTP and MTP devices, sold to end
consumers, is set to ‘1’ which identifies the card contents as a copy. The COPY bit is an one time programmable bit.
•
PERM_WRITE_PROTECT
Permanently protects the whole card content against overwriting or erasing (all write and erase commands for this card
are permanently disabled). The default value is ‘0’, i.e. not permanently write protected.
•
TMP_WRITE_PROTECT
Temporarily protects the whole card content from being overwritten or erased (all write and erase commands for this
card are temporarily disabled). This bit can be set and reset. The default value is ‘0’, i.e. not write protected.
•
FILE_FORMAT
This field is set to 0. Host should not use this field.
•
CRC
The CRC field carries the check sum for the CSD contents.
The checksum has to be recalculated by the host for any CSD modification. The default corresponds to the initial CSD
contents.
The following table lists the correspondence between the CSD entries and the command classes. A ‘+’ entry indicates
that the CSD field affects the commands of the related command class.
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4. RCA Register
The writable 16-bit relative card address register carries the card address that is published by the card during the card
identification. This address is used for the addressed host-card communication after the card identification procedure.
The default value of the RCA register is 0x0000. The value0x0000 is reserved to set all cards into the Stand-by State
with CMD7.
5. DSR Register (Optional)
It can be optionally used to improve the bus performance for extended operating conditions (depending on parameters
like bus length, transfer rate or number of cards). The CSD register carries the information about the DSR register
usage. The default value of the DSR register is 0x404.
6. SCR Register
In addition to the CSD register there is another configuration register that named - SD CARD Configuration Register
(SCR). SCR provides information on SD Memory Card's special features that were configured into the given card. The
size of SCR register is 64 bit. This register shall be set in the factory by the SD Memory Card manufacturer.
The following table describes the SCR register content.
•
SCR_STRUCTURE
Version number of the related SCR structure in the SD Memory Card Physical Layer Specification.
SCR Register Structure Version
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•
SD_SPEC
Describes the SD Memory Card Physical Layer Specification version supported by this card.
SD_SPEC Physical Layer Specification Version Number
0 Version 1.0-1.01
1 Version 1.10
2 Version 2.00
3-15 reserved
Physical Layer Specification Version
•
DATA_STAT_AFTER_ERASE
Defines the data status after erase, whether it is ‘0’ or ‘1’ (the status is card vendor dependent).
•
SD_SECURITY
Describes the security algorithm supported by the card.
SD Supported Security Algorithm
Note that it is mandatory for a regular writable SD Memory Card to support Security Protocol. For ROM (Read Only)
and OTP (One Time Programmable) types of the SD Memory Card, the security feature is optional. In the case of
Standard Capacity SD Memory Card, this field shall be set to 2 (Version 1.01). In the case of High Capacity SD
Memory Card, this field shall be set to 3 (Version 2.00).
•
SD_BUS_WIDTHS
Describes all the DAT bus widths that are supported by this card.
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Since SD Memory Card shall support at least the two bus modes 1bit or 4bit width then any SD Card shall set at least
bits 0 and 2 (SD_BUS_WIDTH="0101").
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Mechanical Dimension
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