TQ-Systems TQMa8Xx Preliminary User's Manual

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TQMa8Xx Preliminary User's Manual

TQMa8Xx UM 0002

23.09.2018

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TABLE OF CONTENTS

1. ABOUT THIS MANUAL................................................................................................................................................................................1

1.1 Copyright and license expenses.............................................................................................................................................................1

1.2 Registered trademarks ..............................................................................................................................................................................1

1.3 Disclaimer......................................................................................................................................................................................................1

1.4 Imprint............................................................................................................................................................................................................ 1

1.5 Tips on safety................................................................................................................................................................................................2

1.6 Symbols and typographic conventions ............................................................................................................................................... 2

1.7 Handling and ESD tips...............................................................................................................................................................................2

1.8 Naming of signals ....................................................................................................................................................................................... 3

1.9 Further applicable documents / presumed knowledge................................................................................................................. 3

2. BRIEF DESCRIPTION ....................................................................................................................................................................................4

2.1 Block diagram i.MX 8X...............................................................................................................................................................................4

2.2 Key functions and characteristics...........................................................................................................................................................5

3. ELECTRONICS ...............................................................................................................................................................................................6

3.1 Interfaces to other systems and devices..............................................................................................................................................6

3.1.1 Pin multiplexing ..........................................................................................................................................................................................6

3.1.2 Connector X1................................................................................................................................................................................................7

3.1.3 Connector X2................................................................................................................................................................................................8

3.1.4 Connector X3................................................................................................................................................................................................9

3.2 System components ............................................................................................................................................................................... 10

3.2.1 i.MX 8X CPU................................................................................................................................................................................................ 10

3.2.1.1 i.MX 8X derivatives................................................................................................................................................................................... 10

3.2.1.2 i.MX 8X errata ............................................................................................................................................................................................ 10

3.2.1.3 Boot modes................................................................................................................................................................................................ 10

3.2.2 Memory....................................................................................................................................................................................................... 11

3.2.2.1 DDR3L SDRAM .......................................................................................................................................................................................... 11

3.2.2.2 eMMC NAND flash ................................................................................................................................................................................... 11

3.2.2.3 QSPI NOR flash .......................................................................................................................................................................................... 12

3.2.2.4 EEPROM....................................................................................................................................................................................................... 12

3.2.2.5 EEPROM with temperature sensor...................................................................................................................................................... 13

3.2.3 RTC................................................................................................................................................................................................................ 13

3.2.4 Interfaces .................................................................................................................................................................................................... 14

3.2.5 Reset............................................................................................................................................................................................................. 14

3.2.6 Power........................................................................................................................................................................................................... 15

3.2.6.1 Power supply............................................................................................................................................................................................. 15

3.2.6.2 Power consumption................................................................................................................................................................................ 15

3.2.6.3 LICELL........................................................................................................................................................................................................... 15

3.2.6.4 ADC input voltage V_ADC_IN .............................................................................................................................................................. 16

3.2.6.5 USB_OTG[2:1]_VBUS ............................................................................................................................................................................... 16

3.2.6.6 Provided TQMa8Xx voltages ................................................................................................................................................................ 16

3.2.6.7 Voltage monitoring................................................................................................................................................................................. 16

3.2.6.8 Power-Up sequence TQMa8Xx / carrier board ............................................................................................................................... 17

3.2.6.9 Power modes............................................................................................................................................................................................. 17

3.2.6.10 PMIC ............................................................................................................................................................................................................. 17

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TABLE OF CONTENTS (continued)

4. MECHANICS ............................................................................................................................................................................................... 18

4.1 Connectors................................................................................................................................................................................................. 18

4.2 Dimensions ................................................................................................................................................................................................ 19

4.3 Component placement.......................................................................................................................................................................... 20

4.4 Adaptation to the environment .......................................................................................................................................................... 21

4.5 Protection against external effects..................................................................................................................................................... 21

4.6 Thermal management............................................................................................................................................................................ 21

4.7 Structural requirements......................................................................................................................................................................... 21

4.8 Notes of treatment .................................................................................................................................................................................. 21

5. SOFTWARE.................................................................................................................................................................................................. 21

6. SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS......................................................................................................... 22

6.1 EMC............................................................................................................................................................................................................... 22

6.2 ESD................................................................................................................................................................................................................ 22

6.3 Operational safety and personal security......................................................................................................................................... 22

6.4 Climate and operational conditions................................................................................................................................................... 23

6.5 Reliability and service life ...................................................................................................................................................................... 23

7. ENVIRONMENT PROTECTION................................................................................................................................................................ 24

7.1 RoHS............................................................................................................................................................................................................. 24

7.2 WEEE

7.3 REACH

.......................................................................................................................................................................................................... 24

7.4 EuP................................................................................................................................................................................................................ 24

7.5 Battery ......................................................................................................................................................................................................... 24

7.6 Packaging................................................................................................................................................................................................... 24

7.7 Other entries.............................................................................................................................................................................................. 24

8. APPENDIX ................................................................................................................................................................................................... 25

8.1 Acronyms and definitions ..................................................................................................................................................................... 25

8.2 References.................................................................................................................................................................................................. 27

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TABLE DIRECTORY

Table 1: Terms and conventions..............................................................................................................................................................2

Table 2: Pinout connector X1....................................................................................................................................................................7

Table 3: Pinout connector X2....................................................................................................................................................................8

Table 4: Pinout connector X3....................................................................................................................................................................9

Table 5: i.MX 8X derivatives.................................................................................................................................................................... 10

Table 6: Boot-Mode / BT_FUSE_SEL..................................................................................................................................................... 10

Table 7: EEPROM........................................................................................................................................................................................ 12

Table 8: Manufacturer EEPROM ............................................................................................................................................................ 13

Table 9: Temperature sensor SE97BTP................................................................................................................................................ 13

Table 10: Reset and config signals.......................................................................................................................................................... 14

Table 11: TQMa8Xx power consumption @ 3.3 V .............................................................................................................................. 15

Table 12: TQMa8Xx LICELL........................................................................................................................................................................ 15

Table 13: USB_OTG[2:1]_VBUS ................................................................................................................................................................ 16

Table 14: Provided TQMa8Xx voltages.................................................................................................................................................. 16

Table 15: Provided PMIC signals ............................................................................................................................................................. 17

Table 16: TQMa8Xx connectors............................................................................................................................................................... 18

Table 17: Carrier board mating connectors......................................................................................................................................... 18

Table 18: Labels on TQMa8Xx.................................................................................................................................................................. 20

Table 19: Climate and operational conditions extended temperature range –25 °C to +85 °C.......................................... 23

Table 20: Climate and operational conditions industrial temperature range –40 °C to +85 °C .......................................... 23

Table 21: Acronyms..................................................................................................................................................................................... 25

Table 22: Further applicable documents.............................................................................................................................................. 27

ILLUSTRATION DIRECTORY

Illustration 1: Block diagram i.MX 8X CPU.......................................................................................................................................................4

Illustration 2: Block diagram TQMa8Xx............................................................................................................................................................ 6

Illustration 3: Block diagram DDR3L interface............................................................................................................................................ 11

Illustration 4: Block diagram eMMC interface............................................................................................................................................. 11

Illustration 5: Block diagram QSPI interface ................................................................................................................................................ 12

Illustration 6: Block diagram EEPROM interface......................................................................................................................................... 12

Illustration 7: Block diagram temperature sensor interface................................................................................................................... 13

Illustration 8: Block diagram Reset................................................................................................................................................................. 14

Illustration 9: Block diagram power supply................................................................................................................................................. 15

Illustration 10: Block diagram power supply carrier board....................................................................................................................... 17

Illustration 11: TQMa8Xx dimensions, side view.......................................................................................................................................... 19

Illustration 12: TQMa8Xx CPU position, top view......................................................................................................................................... 19

Illustration 13: TQMa8Xx dimensions, top view through TQMa8Xx................................................................................................... 19

Illustration 14: TQMa8Xx, component placement top............................................................................................................................... 20

Illustration 15: TQMa8Xx, component placement bottom....................................................................................................................... 20

REVISION HISTORY

Rev. Date Name Pos. Modification

0001 19.06.2018 Petz Initial release

0002 23.09.2018 Petz

All Illustration 2 Table 10 Table 19, Table 20

Links updated, ® and ™ added/updated Names of i.MX 8X derivatives corrected Remarks clarified “Package temperature” replaced with “Case temperature” Case temperature DDR3L SDRAM changed to +95 °C

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1. ABOUT THIS MANUAL

1.1 Copyright and license expenses

in electronic, machine readable, or in any other form without the written consent of TQ-Systems GmbH. The drivers and utilities for the components used as well as the BIOS are subject to the copyrights of the respective

manufacturers. The licence conditions of the respective manufacturer are to be adhered to. Bootloader-licence expenses are paid by TQ-Systems GmbH and are included in the price. Licence expenses for the operating system and applications are not taken into consideration and must be calculated / declared

separately.

1.2 Registered trademarks

TQ-Systems GmbH aims to adhere to copyrights of all graphics and texts used in all publications, and strives to use original or license-free graphics and texts.

All brand names and trademarks mentioned in the Preliminary User's Manual, including those protected by a third party, unless specified otherwise in writing, are subjected to the specifications of the current copyright laws and the proprietary laws of the present registered proprietor without any limitation. One should conclude that brand and trademarks are rightly protected by a third party.

1.3 Disclaimer

TQ-Systems GmbH does not guarantee that the information in this Preliminary User's Manual is up-to-date, correct, complete or of good quality. Nor does TQ-Systems GmbH assume guarantee for further usage of the information. Liability claims against TQSystems GmbH, referring to material or non-material related damages caused, due to usage or non-usage of the information given in this Preliminary User's Manual, or due to usage of erroneous or incomplete information, are exempted, as long as there is no proven intentional or negligent fault of TQ-Systems GmbH.

TQ-Systems GmbH explicitly reserves the rights to change or add to the contents of this Preliminary User's Manual or parts of it without special notification.

Important Notice:

Before using the MBa8Xx or parts of the schematics of the MBa8Xx, you must evaluate it and determine if it is suitable for your intended application. You assume all risks and liability associated with such use. TQ-Systems GmbH makes no other warranties including, but not limited to, any implied warranty of merchantability or fitness for a particular purpose. Except where prohibited by law, TQ-Systems GmbH will not be liable for any indirect, special, incidental or consequential loss or damage arising from the usage of the MBa8Xx or schematics used, regardless of the legal theory asserted.

1.4 Imprint

TQ-Systems GmbH Gut Delling, Mühlstraße 2

D-82229 Seefeld

Tel: +49 8153 9308–0 Fax: +49 8153 9308–4223 E-Mail: Web:

Info@TQ-Group TQ-Group

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1.5 Tips on safety

Improper or incorrect handling of the product can substantially reduce its life span.

1.6 Symbols and typographic conventions

Table 1: Terms and conventions

Symbol Meaning

This symbol represents the handling of electrostatic-sensitive modules and / or components. These components are often damaged / destroyed by the transmission of a voltage higher than about 50 V. A human body usually only experiences electrostatic discharges above approximately 3,000 V.

This symbol indicates the possible use of voltages higher than 24 V. Please note the relevant statutory regulations in this regard. Non-compliance with these regulations can lead to serious damage to your health and may damage

or destroy the component.

This symbol indicates a possible source of danger. Ignoring the instructions described can cause health damage, or damage the hardware.

This symbol represents important details or aspects for working with TQ-products.

Command

A font with fixed-width is used to denote commands, contents, file names, or menu items.

1.7 Handling and ESD tips

General handling of your TQ-products

The TQ-product may only be used and serviced by certified personnel who have taken note of the information, the safety regulations in this document and all related rules and regulations.

A general rule is not to touch the TQ-product during operation. This is especially important when switching on, changing jumper settings or connecting other devices without ensuring beforehand that the power supply of the system has been switched off.

Violation of this guideline may result in damage / destruction of the TQMa8Xx and be dangerous to your health.

Improper handling of your TQ-product would render the guarantee invalid.

Proper ESD handling

The electronic components of your TQ-product are sensitive to electrostatic discharge (ESD). Always wear antistatic clothing, use ESD-safe tools, packing materials etc., and operate your TQ-

product in an ESD-safe environment. Especially when you switch modules on, change jumper settings, or connect other devices.

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1.8 Naming of signals

A hash mark (#) at the end of the signal name indicates a low-active signal. Example: RESET#

If a signal can switch between two functions and if this is noted in the name of the signal, the low-active function is marked with a hash mark and shown at the end.

Example: C / D#

If a signal has multiple functions, the individual functions are separated by slashes when they are important for the wiring. The identification of the individual functions follows the above conventions. Example: WE2# / OE#

1.9 Further applicable documents / presumed knowledge

• Specifications and manual of the modules used:

These documents describe the service, functionality and special characteristics of the module used (incl. BIOS).

• Specifications of the components used:

The manufacturer's specifications of the components used, for example CompactFlash cards, are to be taken note of. They contain, if applicable, additional information that must be taken note of for safe and reliable operation. These documents are stored at TQ-Systems GmbH.

• Chip errata:

It is the user's responsibility to make sure all errata published by the manufacturer of each component are taken note of. The manufacturer’s advice should be followed.

• Software behaviour:

No warranty can be given, nor responsibility taken for any unexpected software behaviour due to deficient components.

• General expertise:

Expertise in electrical engineering / computer engineering is required for the installation and the use of the device.

The following documents are required to fully comprehend the following contents:

• MBa8Xx circuit diagram

• MBa8Xx User’s Manual

• i.MX 8X Data Sheet

• i.MX 8X Reference Manual

• U-Boot documentation:

• PTXdist documentation:

• TQ-Support Wiki:

www.denx.de/wiki/U-Boot/Documentation www.ptxdist.de support.tq-group.com/doku.php?id=en:arm:tqma8xx

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2. BRIEF DESCRIPTION

This Preliminary User's Manual describes the hardware of TQMa8Xx revision 01xx in combination with the MBa8Xx revision 01xx and refers to some software settings. The MBa8Xx serves as an evaluation board for the TQMa8Xx. A certain TQMa8Xx version does not necessarily provide all features described in this Preliminary User's Manual. This Preliminary User's Manual does also not replace the NXP i.MX 8X Reference Manual (2). The CPU derivatives provide dual, and quad ARM® Cortex™ A35 cores, and up to two Dual ARM® Cortex™-M4 co-processors. In addition, the CPUs include an OpenGL ES 3.0 or 3.1 GPU as well as a VPU supporting up to 4K h.265 decoder.

The TQMa8Xx is a universal Minimodule based on these NXP ARM® Cortex™ A35 i.MX 8X CPUs, see also Table 5. An i.MX 8X Cortex™ A35 core typically operates at 1.2 GHz.

2.1 Block diagram i.MX 8X

Illustration 1: Block diagram i.MX 8X CPU (Source:

The TQMa8Xx extends the TQ-Systems GmbH product range and offers an outstanding computing performance. A suitable i.MX 8X derivative (i.MX 8DualX, i.MX 8DualXPlus, or i.MX 8QuadXPlus) can be selected for each requirement. All essential CPU signals are routed to the connectors. There are therefore no restrictions for customers using the TQMa8Xx with

respect to an integrated customised design. All essential components like CPU, DDR3L SDRAM, eMMC, and power management are already integrated on the TQMa8Xx. The main features of the TQMa8Xx are:

• 64-bit NXP i.MX 8X CPU with up to 4 × ARM

NXP)

Cortex™ A35 and 1 × ARM® Cortex™ M4F

• Derivatives: i.MX 8DualX / i.MX 8DualXPlus / i.MX 8QuadXPlus

• Up to 2 Gbyte DDR3L SDRAM, with 2 × 32 bit data bus interface, one channel optional with ECC

• Up to 64 Gbyte eMMC NAND flash

• Up to 256 Mbyte QSPI NOR flash (optional)

• 64 kbit EEPROM

• EEPROM + temperature sensor

• NXP Power Management Integrated Circuit PF8100, “ASIL” ready

• All essential CPU signals are routed to the TQMa8Xx connectors

• Extended temperature range

• Boot mode selection on TQMa8Xx

• 3.3 V single supply voltage

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2.2 Key functions and characteristics

The following components are implemented on the TQMa8Xx:

• NXP i.MX 8DualX / i.MX 8DualXPlus / i.MX 8QuadXPlus / CPU

• DDR3L SDRAM

• eMMC NAND flash

• QSPI NOR flash

• EEPROM

• EEPROM + Temperature sensor

• RTC (optional)

• Supervisor with Reset structure

• Power supply by PMIC with Power Sequencing (single 3.3 V supply)

• Boot configuration

• Three connectors (2 × 120 pins, 1 × 40 pins)

The following primary interfaces are provided at the TQMa8Xx connectors: 1

• 2 × GbE (Gigabit Ethernet)

• 2 × I

• 1 × JTAG

• 1 × LVDS interface

• 2 × CAN

• 3 × SPI

• 2 × USB 2.0 OTG

• 1 × USB 3.0

• 2 × UART

• 1 × SD 4-bit (SDIO / MMC / SD card)

• 1 × QSPI)

• 1 × I

S (MCASP)

• 1 × PCIe

1: Number of interfaces depend on i.MX 8X derivative.

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3. ELECTRONICS

The information provided in this Preliminary User's Manual is only valid in connection with the tailored boot loader, which is preinstalled on the TQMa8Xx, and the

BSP provided by TQ-Systems GmbH, see also chapter 5.

Illustration 2: Block diagram TQMa8Xx

3.1 Interfaces to other systems and devices

3.1.1 Pin multiplexing

When using the CPU signals, the multiple pin configurations by different CPU-internal function units must be taken note of. NXP provides a tool showing the multiplexing and simplifies the selection and configuration (NXP Pin Mux Tool):

The pin assignment listed in Table 2, Table 3, and Table 4 refers to the corresponding

BSP provided by TQ-Systems GmbH

in combination with the MBa8Xx.

The electrical and pin characteristics are to be taken from the i.MX 8X Data Sheet (1), the i.MX 8X Reference Manual (2), and the PMIC Data Sheet (4).

Attention: Destruction or malfunction

Depending on the configuration, many i.MX 8X balls can provide several different functions. Please take note of the information in the i.MX 8X Reference Manual (2), and the i.MX 8X Errata (3)

concerning the configuration of these pins before integration or start-up of your carrier board. Improper programming by operating software can cause malfunctions, deterioration or

destruction of the TQMa8Xx.

The meanings given in the following tables must be observed: RFU: Reserved pins without function.

To support future TQMa8Xx versions, these pins must not be connected. DNC: These pins must never be wired and must be left open.

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3.1.2 Connector X1

Table 2: Pinout connector X1

Ball I/O Level Group Signal Pin Signal Group Level I/O Ball

– P 0 V Ground GND 1 2 GND Ground 0 V P –

E35 O 1.8 V ENET ENET1_REFCLK_OUT 3 4 TEMP_EVENT# CONFIG – O –

– P 0 V Ground GND 5 6 GND Ground 0 V P –

D32 I 1.8 V ENET ENET1_RXC 7 8 ENET1_TXC ENET 1.8 V O F30

– P 0 V Ground GND 9 10 GND Ground 0 V P – D34 I 1.8 V ENET ENET1_RX_CTL 11 12 ENET1_TX_CTL ENET 1.8 V O H28 G31 I 1.8 V ENET ENET1_RXD0 13 14 ENET1_TXD0 ENET 1.8 V O F32 C33 I 1.8 V ENET ENET1_RXD1 15 16 ENET1_TXD1 ENET 1.8 V O J29 K28 I 1.8 V ENET ENET1_RXD2 17 18 ENET1_TXD2 ENET 1.8 V O G29 B34 I 1.8 V ENET ENET1_RXD3 19 20 ENET1_TXD3 ENET 1.8 V O E31

– P 0 V Ground GND 21 22 GND Ground 0 V P – P34 I/O 1.8 V M4 GPIO M4_GPIO0_IO02 23 24 GPIO0_IO30 GPIO 1.8 V I/O L35 R33 I/O 1.8 V M4 GPIO M4_GPIO0_IO03 25 26 GPIO0_IO31 GPIO 1.8 V I/O N35 R31 I/O 1.8 V M4 I2C M4_I2C_SDA 27 28 GPIO1_IO07 GPIO 1.8 V I/O R35 P30 I/O 1.8 V M4 I2C M4_I2C_SCL 29 30 PMIC_PGOOD CONFIG 1.8 V O –

– P 0 V Ground GND 31 32 GND Ground 0 V P – H34 O 1.8 V UART UART1_TX 33 34 SPI2_SCK SPI 1.8 V O R29

L31 I 1.8 V UART UART1_RX 35 36 SPI2_SDO SPI 1.8 V O P32 N29 O 1.8 V UART UART1_RTS# 37 38 SPI2_SDI SPI 1.8 V I N31 K32 I 1.8 V UART UART1_CTS# 39 40 SPI2_CS0# SPI 1.8 V O P28

– P 0 V Ground GND 41 42 SPI1_CS0# SPI 1.8 V O M34 D30 O 1.8 V ENET ENET0_MDC 43 44 SPI1_CS1# SPI 1.8 V O M32 B32 I/O 1.8 V ENET ENET0_MDIO 45 46 SPI1_SDO SPI 1.8 V O K34

– P 0 V Ground GND 47 48 SPI1_SDI SPI 1.8 V I J35

F28 O 1.8 V ENET ENET0_REFCLK_OUT 49 50 SPI1_SCK SPI 1.8 V O L33

– P 0 V Ground GND 51 52 GND Ground 0 V P – D28 I 1.8 V ENET ENET0_RXC 53 54 ENET0_TXC ENET 1.8 V O H24

– P 0 V Ground GND 55 56 GND Ground 0 V P – B30 I 1.8 V ENET ENET0_RX_CTL 57 58 ENET0_TX_CTL ENET 1.8 V O A29

– P 0 V Ground GND 59 60 GND Ground 0 V P – A31 I 1.8 V ENET ENET0_RXD0 61 62 ENET0_TXD0 ENET 1.8 V O G25 C29 I 1.8 V ENET ENET0_RXD1 63 64 ENET0_TXD1 ENET 1.8 V O B28 G27 I 1.8 V ENET ENET0_RXD2 65 66 ENET0_TXD2 ENET 1.8 V O E27 H26 I 1.8 V ENET ENET0_RXD3 67 68 ENET0_TXD3 ENET 1.8 V O F26

– P 0 V Ground GND 69 70 GND Ground 0 V P – G17 I 3.3 V USB USB_OTG1_ID 71 72 USB_OTG2_ID USB 3.3 V I F16 H18 P 5 V USB USB_OTG1_VBUS 73 74 USB_OTG2_VBUS USB 3.3 V P H16

F14 O 3.3 V USB USB_OTG1_PWR 75 76 USB_OTG2_PWR USB 3.3 V O H14

G15 I 3.3 V USB USB_OTG1_OC 77 78 USB_OTG2_OC USB 3.3 V I C15

– P 0 V Ground GND 79 80 GND Ground 0 V P – E19 I/O 3.3 V USB USB_OTG1_DN 81 82 USB_OTG2_DN USB 3.3 V I/O D16 D18 I/O 3.3 V USB USB_OTG1_DP 83 84 USB_OTG2_DP USB 3.3 V I/O E17

– P 0 V Ground GND 85 86 GND Ground 0 V P – C25 I/O 1.8/3.3 V SD SD1_CMD 87 88 USB_SS_TX_P USB 1.0 V O B16

– P 0 V Ground GND 89 90 USB_SS_TX_N USB 1.0 V O A35 G23 O 1.8/3.3 V SD SD1_CLK 91 92 GND Ground 0 V P –

– P 0 V Ground GND 93 94 USB_SS_RX_P USB 1.0 V I A19 A27 I/O 1.8/3.3 V SD SD1_DATA0 95 96 USB_SS_RX_N USB 1.0 V I B18 B26 I/O 1.8/3.3 V SD SD1_DATA1 97 98 GND Ground 0 V P – D26 I/O 1.8/3.3 V SD SD1_DATA2 99 100 PCIE_TX_N PCIe 1.0 V O A9 E25 I/O 1.8/3.3 V SD SD1_DATA3 101 102 PCIE_TX_P PCIe 1.0 V O B10

– P 0 V Ground GND 103 104 GND Ground 0 V P – D24 I 1.8 V SD SD1_WP 105 106 PCIE_RX_N PCIe 1.0 V I B12 A25 I 1.8 V SD SD1_VSELECT 107 108 PCIE_RX_P PCIe 1.0 V I A13 E23 I 1.8 V SD SD1_CD# 109 110 GND Ground 0 V P – B24 O 1.8 V GPIO GPIO4_IO19 111 112 PCIE_REFCLK_N PCIe 1.8 V O D12

– P 0 V Ground GND 113 114 PCIE_REFCLK_P PCIe 1.8 V O E11 D10 I 3.3 V PCIe PCIE_CLKREQ# 115 116 GND Ground 0 V P – H10 O 3.3 V PCIe PCIE_PERST# 117 118 IMX_ONOFF CONFIG 1.8 V I AH28 A11 I 3.3 V PCIe PCIE_WAKE# 119 120 GND Ground 0 V P –

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3.1.3 Connector X2

Table 3: Pinout connector X2

Ball I/O Level Group Signal Pin Signal Group Level I/O Ball

– P 3.3 V Power V_3V3_IN 1 2 V_3V3_IN Power 3.3 V P –

– P 3.3 V Power V_3V3_IN 3 4 V_3V3_IN Power 3.3 V P –

– P 3.3 V Power V_3V3_IN 5 6 V_3V3_IN Power 3.3 V P –

– P 0 V Ground GND 7 8 GND Ground 0 V P –

– P 0 V Ground GND 9 10 GND Ground 0 V P –

– P 1.8 V Power V_1V8_OUT2 11 12

AJ31 I 1.8 V CONFIG BOOT_MODE0 13 14 GND Ground 0 V P – AK32 I 1.8 V CONFIG BOOT_MODE1 15 16 MCLK_OUT0 CLK 1.8 V O L29 AL31 I 1.8 V CONFIG BOOT_MODE2 17 18 MCLK_IN1 CLK 1.8 V I M28 AJ29 I 1.8 V CONFIG BOOT_MODE3 19 20 MCLK_IN0 CLK 1.8 V I G35

– P 1.8 V Power V_1V8_ANA 21 22 GND Ground 0 V P –

– P 3 V Power LICELL 23 24 GPIO3_IO05 GPIO 1.8 V I/O AP26

– O 1.8 V CONFIG PMIC_FSOB_EWARN 25 26 GPIO3_IO06 GPIO 1.8 V I/O AM24

AR31 I 1.8 V CONFIG PMIC_PWRON 27 28 SCU_UART_RX SCU UART 1.8 V I AF28

– P 0 V Ground GND 29 30 SCU_UART_TX SCU UART 1.8 V O AH30

AM22 I 1.8 V CSI MIPI_CSI_DN0 31 32 RESET_IN# CONFIG 3.0 V I AG31

AP22 I 1.8 V CSI MIPI_CSI_DP0 33 34 RESET_OUT# CONFIG 3.0 V O –

– P 0 V Ground GND 35 36 GND Ground 0 V P –

AM20 I 1.8 V CSI MIPI_CSI_DN1 37 38 I2C2_SCL I2C 1.8 V I/O AD30

AP20 I 1.8 V CSI MIPI_CSI_DP1 39 40 I2C2_SDA I2C 1.8 V I/O AF34

– P 0 V Ground GND 41 42 GND Ground 0 V P –

AN23 I 1.8 V CSI MIPI_CSI_DN2 43 44 SPI3_SCK SPI 1.8 V O H32

AR23 I 1.8 V CSI MIPI_CSI_DP2 45 46 SPI3_SDO SPI 1.8 V O F34

– P 0 V Ground GND 47 48 SPI3_SDI SPI 1.8 V I G33

AN19 I 1.8 V CSI MIPI_CSI_DN3 49 50 SPI3_CS0# SPI 1.8 V O J31

AR19 I 1.8 V CSI MIPI_CSI_DP3 51 52 SPI3_CS1# SPI 1.8 V O K30

– P 0 V Ground GND 53 54 PMIC_AMUX_VSD CONFIG – O –

AN21 I 1.8 V CSI MIPI_CSI_CLKN 55 56 GND Ground 0 V P –

AR21 I 1.8 V CSI MIPI_CSI_CLKP 57 58 MIPI_CSI_MCLK CSI 1.8 V O AN25

– P 0 V Ground GND 59 60 GND Ground 0 V P –

AN15 O 1.8 V DSI / LVDS MIPI_DSI1_DN0 61 62 MIPI_DSI0_DN0 DSI / LVDS 1.8 V O AJ21

AR15 O 1.8 V DSI / LVDS MIPI_DSI1_DP0 63 64 MIPI_DSI0_DP0 DSI / LVDS 1.8 V O AK22

– P 0 V Ground GND 65 66 GND Ground 0 V P –

AN17 O 1.8 V DSI / LVDS MIPI_DSI1_DN1 67 68 MIPI_DSI0_DN1 DSI / LVDS 1.8 V O AJ17

AR17 O 1.8 V DSI / LVDS MIPI_DSI1_DP1 69 70 MIPI_DSI0_DP1 DSI / LVDS 1.8 V O AK18

– P 0 V Ground GND 71 72 GND Ground 0 V P –

AM14 O 1.8 V DSI / LVDS MIPI_DSI1_DN2 73 74 MIPI_DSI0_DN2 DSI / LVDS 1.8 V O AJ23

AP14 O 1.8 V DSI / LVDS MIPI_DSI1_DP2 75 76 MIPI_DSI0_DP2 DSI / LVDS 1.8 V O AK24

– P 0 V Ground GND 77 78 GND Ground 0 V P –

AM18 O 1.8 V DSI / LVDS MIPI_DSI1_DN3 79 80 MIPI_DSI0_DN3 DSI / LVDS 1.8 V O AJ15

AP18 O 1.8 V DSI / LVDS MIPI_DSI1_DP3 81 82 MIPI_DSI0_DP3 DSI / LVDS 1.8 V O AK16

– P 0 V Ground GND 83 84 GND Ground 0 V P –

AM16 O 1.8 V DSI / LVDS MIPI_DSI1_CLKN 85 86 MIPI_DSI0_CLKN DSI / LVDS 1.8 V O AJ19

AP16 O 1.8 V DSI / LVDS MIPI_DSI1_CLKP 87 88 MIPI_DSI0_CLKP DSI / LVDS 1.8 V O AK20

– P 0 V Ground GND 89 90 GND Ground 0 V P –

AK26 I/O 1.8 V SCU GPIO GPIO3_IO00 91 92 GPIO3_IO02 SCU GPIO 1.8 V I/O AP28

AM26 I/O 1.8 V SCU GPIO GPIO3_IO01 93 94 GPIO3_IO03 SCU GPIO 1.8 V I/O AR27

– P 0 V Ground GND 95 96 GND Ground 0 V P –

AK10 I 1.8 V QSPI QSPIB_DQS 97 98 SAI1_TXC SAI 1.8 V O Y34

– P 0 V Ground GND 99 100 SAI1_TXFS SAI 1.8 V O Y32

AR11 O 1.8 V QSPI QSPIB_SCLK 101 102 SAI1_TXD SAI 1.8 V O AA33

– P 0 V Ground GND 103 104 GND Ground 0 V P –

AM10 I/O 1.8 V QSPI QSPIB_DATA0 105 106 SAI1_RXC SAI 1.8 V I AA31

AL9 I/O 1.8 V QSPI QSPIB_DATA1 107 108 SAI1_RXFS SAI 1.8 V I AB34

AJ11 I/O 1.8 V QSPI QSPIB_DATA2 109 110 SAI1_RXD SAI 1.8 V I AA35 AM8 I/O 1.8 V QSPI QSPIB_DATA3 111 112 GPIO3_IO07 GPIO 1.8 V I/O AP24

AH10 O 1.8 V QSPI QSPIB_SS0# 113 114 GPIO3_IO08 GPIO 1.8 V I/O AR25

AJ9 O 1.8 V QSPI QSPIB_SS1# 115 116 I2C1_SDA I2C 1.8 V I/O AE35

AK12 O 1.8 V QSPI QSPIA_SS1# 117 118 I2C1_SCL I2C 1.8 V I/O AD32

– P 0 V Ground GND 119 120 GND Ground 0 V P –

V_1V8_OUT2

Power 1.8 V P –

2: Maximum load on pins 11 and 12 is 1 A.

Page 13

3.1.4 Connector X3

Table 4: Pinout connector X3

Ball I/O Level Group Signal Pin Signal Group Level I/O Ball

– P 0 V Ground GND 1 2 GND Ground 0 V P –

W29 I/O 1.8 V GPIO GPIO1_IO14 3 4 JTAG_TCK JTAG 1.8 V I AE31

V34 I/O 1.8 V GPIO GPIO1_IO13 5 6 JTAG_TDI JTAG 1.8 V I AH34

– P 0 V Ground GND 7 8 JTAG_TDO JTAG 1.8 V O AF32

AE33 I/O 1.8 V GPIO GPIO1_IO29 9 10 JTAG_TMS JTAG 1.8 V I AG35

AC29 I/O 1.8 V GPIO GPIO1_IO30 11 12 JTAG_TRST# JTAG 1.8 V I AD28

AC31 I/O 1.8 V GPIO GPIO1_IO25 13 14 GND Ground 0 V P –

AB28 I/O 1.8 V GPIO GPIO1_IO26 15 16 CAN0_RX CAN 1.8 V I AB32

– P 0 V Ground GND 17 18 CAN0_TX CAN 1.8 V O AA29

AK28 O 1.8 V TAMPER TAMPER_OUT0 19 20 CAN1_RX CAN 1.8 V I AD34

AL29 O 1.8 V TAMPER TAMPER_OUT1 21 22 CAN1_TX CAN 1.8 V O AC35

AP30 O 1.8 V TAMPER TAMPER_OUT2 23 24 GND Ground 0 V P –

AJ27 O 1.8 V TAMPER TAMPER_OUT3 25 26 ADC_IN0 ADC 1.8 V I U35

AN29 O 1.8 V TAMPER TAMPER_OUT4 27 28 ADC_IN1 ADC 1.8 V I U33

AM30 I 1.8 V TAMPER TAMPER_IN0 29 30 ADC_IN2 ADC 1.8 V I V32

AJ25 I 1.8 V TAMPER TAMPER_IN1 31 32 ADC_IN3 ADC 1.8 V I V30

AM28 I 1.8 V TAMPER TAMPER_IN2 33 34 V_ADC_IN ADC 1.8 V I U29

AR29 I 1.8 V TAMPER TAMPER_IN3 35 36 PMIC_I2C_SDA SCU I2C 1.8 V I/O AH32

AL27 I 1.8 V TAMPER TAMPER_IN4 37 38 PMIC_I2C_SCL SCU I2C 1.8 V I/O AJ35

– P 0 V Ground GND 39 40 GND Ground 0 V P –

Page 14

3.2 System components

3.2.1 i.MX 8X CPU

3.2.1.1 i.MX 8X derivatives

Depending on the TQMa8Xx version, one of the following i.MX 8X derivatives is assembled.

Table 5: i.MX 8X derivatives

TQ-variant CPU derivative Cortex™ A35 clock Cortex™-M4 clock Tj, temp. range

TQMa8XD-xx i.MX 8DualX 1.2 GHz 266 MHz –40 °C to +125 °C

TQMa8XDP-xx i.MX 8DualXPlus 1.2 GHz 266 MHz –40 °C to +125 °C

TQMa8XQP-xx i.MX 8QuadXPlus 1.2 GHz 266 MHz –40 °C to +125 °C

3.2.1.2 i.MX 8X errata

Attention: Malfunction

Please take note of the current i.MX 8X errata (3).

3.2.1.3 Boot modes

After release of PMIC_POR#, the System Controller (SCU) starts from the internal ROM. Depending on the OTP fuses (eFuse) and the boot mode settings of the system controller, the TQMa8Xx boots from the specified

boot source:

• eMMC

• QSPI-NOR flash

• SD card

More information about boot interfaces and its configuration is to be taken from the i.MX 8X Data Sheet (1) and the i.MX 8X Reference Manual (2). Alternatively, an image can be loaded into the internal RAM via serial downloader.

In the following chapters, the configurations for the following possible boot devices are described exemplarily:

Table 6: Boot-Mode / BT_FUSE_SEL

BOOT_MODE[3:0] Boot source

0000 0001 0010 0011 010x 011x

Note: Field software updates

When designing a carrier board, it is recommended to have a redundant update concept for field software updates.

Boot from eFuse

Serial Downloader (USB)

Boot from eMMC

Boot from SD card

Boot from NAND

Boot from QSPI

Page 15

3.2.2 Memory

3.2.2.1 DDR3L SDRAM

Depending on the ECC option, the TQMa8Xx can be equipped with two or three DDR3L memory chips with an effective memory width of 32 bits. The third DDR3L memory chip for the ECC option uses 8 bits.

The interface timing complies with JEDEC standard DDR3-1866 with a maximum clock rate of 933 MHz.

Illustration 3: Block diagram DDR3L interface

3.2.2.2 eMMC NAND flash

An eMMC is available on the TQMa8Xx as non-volatile memory for programs and data (e.g. bootloader, operating system, application).

The following illustration shows the interface of the eMMC to the i.MX 8X:

Illustration 4: Block diagram eMMC interface

The i.MX 8X supports MMC card transmission modes up to the current eMMC standard v5.1 or SD card standard 3.0. The I/O voltage is 1.8 V to support the maximum clock rate of 200 MHz. This allows a data rate of up to 400 Mbyte/s in DDR mode

(HS400). The eMMC can be used as boot medium. The boot configuration is described in 3.2.1.3.

Page 16

3.2.2.3 QSPI NOR flash

The i.MX 8X provides two QSPI interfaces, which can be combined to an Octal-SPI or Twin-Quad-SPI on the TQMa8Xx. NOR flashes using one or both QSPI interfaces are used on the TQMa8Xx. The second QSPI interface may be available on the module connector.

i.MX8X

QSPIA_SCLK

QSPIA_DATA[3:0]

QSPIA_DQS

QSPIA_SS[1:0]_B

D[3:0]

DQS

S1#

SPINOR

QSPINOR

QSPIB_SCLK

QSPIB_DATA[3:0]

QSPIB_SS[1:0]_B

QSPIB_DQS

D[7:4]

S2#

Octal/TwinQuad

Connector

QSPIA_SS1#

QSPIB_SCLK

QSPIB_DATA[3:0]

QSPIB_SS[1:0]#

QSPIB_DQS

Illustration 5: Block diagram QSPI interface

3.2.2.4 EEPROM

A serial EEPROM, controlled by the I2C1 bus, is assembled. Write-Protect (WP#) is not supported. To store data “read-only”, the EEPROM with temperature sensor must be used, see 3.2.2.5.

Illustration 6: Block diagram EEPROM interface

The following table shows details of the EEPROM.

Table 7: EEPROM

Manufacturer Part number Size Temperature range

Microchip 24LC64T-I/MC MCH 64 Kbit –45 °C to +85 °C

 The EEPROM has I2C address 0x57 / 101 0111b

Page 17

3.2.2.5 EEPROM with temperature sensor

A serial EEPROM including temperature sensor, controlled by the I2C1 bus, is assembled. The lower 128 bytes (addresses 00h to 7Fh) can be set to Permanent Write Protected (PWP) mode or Reversible Write Protected

(RWP) mode by software. The upper 128 bytes (addresses 80h to FFh) cannot be write-protected and can be used for general data storage. The EEPROM also provides a temperature sensor to monitor the temperature of the TQMa8Xx.

The following table shows details of the Manufacturer EEPROM.

Table 8: Manufacturer EEPROM

Manufacturer Part number Size Temperature range

NXP SE97BTP 2 × 128 bytes –45 °C to +85 °C

 The device has the following I

C addresses:

o EEPROM (normal): 0x51 / 101 0001b o EEPROM (Protection mode): 0x31 / 011 0001b o Temperature sensor: 0x19 / 001 1001b

The following illustration shows the interface of the temperature sensor to the i.MX 8X.

Illustration 7: Block diagram temperature sensor interface

The EEPROM with temperature sensor (D7) is assembled on the bottom side of the TQMa8Xx, see Illustration 15. The overtemperature output of the sensor is connected as open drain to connector X1-4 (TEMP_EVENT#). A pull-up to a maximum voltage of 3.6 V must be provided on the carrier board. The following table shows details of the temperature sensor.

Table 9: Temperature sensor SE97BTP

Manufacturer Part number Resolution Accuracy Temperature range

NXP SE97BTP 11 bits Max. ±3 °C –40 °C to +125 °C

3.2.3 RTC

In addition to the i.MX 8X-internal RTC, the TQMa8Xx provides a discrete RTC DS1339U as assembly option. The accuracy of the RTC is essentially determined by the characteristics of the quartz used. The quartzes used on the TQMa8Xx have a standard frequency tolerance of ±20 ppm at +25 °C. The RTC is connected to the I2C1 bus.

 The RTC has I2C address 0x68 / 110 1000b

Note: Power supply for i.MX 8X-internal RTC

The i.MX 8X-internal RTC can always be used in ON mode, but resets itself when the module supply is switched off, since the SNVS domain of the i.MX 8X is then no longer supplied.

Page 18

3.2.4 Interfaces

(TBD)

3.2.5 Reset

Reset inputs and outputs are available on the TQMa8Xx connectors. The following table describes the reset and config signals available on the TQMa8Xx connector.

Table 10: Reset and config signals

Signal Dir. Power domain Function TQMa8Xx Remark

RESET_IN# I VDD_ANA1_1P8 i.MX 8X reset input X2-32

RESET_OUT# O External defined Open-Drain output X2-34

IMX_ONOFF I V_SNVS_CAP ON / OFF signal of i.MX 8X X1-118

Low Active signal Deactivate: float or connect to 1.8 V / 3.3 V

Low Active signal Requires Pull-Up on carrier board (to max. 6.5 V)

Low Active signal Deactivate: float

Illustration 8: Block diagram Reset

Page 19

3.2.6 Power

3.2.6.1 Power supply

The TQMa8Xx only requires a single power supply of 3.3 V ±5 %. The following illustration shows the structure of the TQMa8Xx supply:

VCC1

Connector

3.3 V

PMIC

PF8100/

PF8200

VCC2

VCCn

i.MX8X

Module

components

Illustration 9: Block diagram power supply

3.2.6.2 Power consumption

The power consumption of the TQMa8Xx strongly depends on the application, the mode of operation and the operating system. For this reason the given values have to be seen as approximate values.

The following table shows power supply and power consumption parameters of the TQMa8Xx:

Table 11: TQMa8Xx power consumption @ 3.3 V

Mode of operation TQMa8XD TQMa8XDP TQMa8XQP Remark

Theoretical calculated peak 1440 mA 4752 mW 1440 mA 4752 mW 1440 mA 4752 mW –

U-Boot prompt 115 mA 380 mW 115 mA 380 mW 130 mA 429 mW –

Linux prompt 95 mA 314 mW 95 mA 314 mW 100 mA 330 mW –

Linux 100 % CPU load 200 mA 660 mW 200 mA 660 mW 220 mA 726 mW –

Reset 26 mA 86 mW 26 mA 86 mW 21 mA 69 mW RESET_IN# = low

Off-Mode 6 mA 20 mW 6 mA 20 mW 6 mA 20 mW PMIC_PWRON = low

3.2.6.3 LICELL

Coin cells can be connected to the LICELL input of the TQMa8Xx connector (X2-23). Depending on the TQMa8Xx variant, the SNVS domain of the i.MX 8X or the external RTC DS1339U is thus supplied. The following table shows details of the power consumption at the LICELL pin.

Table 12: TQMa8Xx LICELL

Current consumption Function

Typical 7 µA, max. 10 µA LICELL supplies the i.MX 8X SNVS-Domain via the PMIC‘s VSNVS regulator.

Typical 0.4 µA, max. 7 µA

LICELL supplies the DS1339U RTC on the TQMa8Xx. The i.MX 8X SNVS domain is only supplied when the TQMa8Xx supply of 3.3 V is present.

Note: Functional scope of RTC

Depending on the TQMa8Xx variant, the range of functions is reduced in battery mode (only LICELL supplied), since no SNVS function of the i.MX 8X is available when using the DS1339U.

Page 20

3.2.6.4 ADC input voltage V_ADC_IN

The voltage input V_ADC_IN at TQMa8Xx connector X3-34 serves as voltage reference for the ADC of the i.MX 8X. This voltage is filtered and connected to pin V_ADC_VREFH of the i.MX 8X. V_ADC_IN must typically be supplied with 1.8 V in order to use the ADC function of the i.MX 8X. Depending on the accuracy requirements, V_1V8_OUT can be used for this. Further information about the ADC can be found in the data sheet of the i.MX 8X (1).

3.2.6.5 USB_OTG[2:1]_VBUS

The voltage inputs USB_OTG1_VBUS and USB_OTG2_VBUS are used to detect the voltage USB-VBUS. They are usually connected to the VBUS voltage switched by the USB host. Due to the different implementations of the OTG PHYs in the i.MX 8X, different voltages must be used for this.

Table 13: USB_OTG[2:1]_VBUS

Signal TQMa8Xx Voltage Usage

USB_OTG1_VBUS X1-73 5 V Input for VBUS comparator OTG1

USB_OTG2_VBUS X1-74 3.3 V Input for VBUS comparator OTG2

3.2.6.6 Provided TQMa8Xx voltages

In addition to the TQMa8Xx supply input, some TQMa8Xx-internal voltages are available on the TQMa8Xx connectors. The following table shows these voltages:

Table 14: Provided TQMa8Xx voltages

Voltage TQMa8Xx Max. current Usage

V_1V8 X2-11, X2-12 1 A Internal supply for periphery and I/O, should be used on carrier board

V_1V8_ANA X2-21 25 mA Pull-Up voltage for pins BOOT_MODE[3:0]

Voltage V_1V8 has to be used to switch the supply on the carrier board.

Note: Voltages V_1V8 and V_1V8_ANA

Up to 1 A can be drawn from V_1V8, which increases the PMIC's power consumption and thus the TQMa8Xx’s self-heating.

The BOOT_MODE pins should be pulled-up to V_1V8_ANA, or a voltage switched by V_1V8_ANA. This ensures that the boot mode pins are read-in correctly and that no cross-supply occurs. The voltages mentioned are outputs and must not be supplied externally under any circumstances.

3.2.6.7 Voltage monitoring

The 3.3 V input voltage is monitored on the TQMa8Xx. If the input voltage is too low, a reset is triggered until the input voltage is within the defined range again.

Attention: Malfunction or destruction

The voltage monitoring does not detect an exceedance of the maximum permitted input voltage. An excessively high supply voltage can lead to malfunctions, untimely aging or destruction of the

TQMa8Xx.

Page 21

3.2.6.8 Power-Up sequence TQMa8Xx / carrier board

The TQMa8Xx meets the required sequencing of the i.MX 8X by using the PMIC (4). Since the TQMa8Xx operates at 3.3 V and the 1.8 V I/O voltage of the CPU signals is generated on the TQMa8Xx, the carrier board

design must meet requirements regarding the chronological behaviour of the voltages generated on the carrier board. The 3.3 V carrier board supply may only be enabled via TQMa8Xx output V_1V8 (X2-11, X2-12). The following illustration shows the voltage regulator control of a carrier board.

Illustration 10: Block diagram power supply carrier board

Attention: Power-Up sequence

The TQMa8Xx I/O pins may not be driven by external components during power-up in order to avoid cross-supply and thus errors during the power-up sequence.

To ensure a correct power-up, the following sequence must be met on the carrier board: The supply voltage of 3.3 V for the TQMa8Xx is present and the carrier board supply of 3.3 V

is activated with TQMa8Xx voltage V_1V8, pins X2-11, and X2-12.

3.2.6.9 Power modes

(TBD)

3.2.6.10 PMIC

On the TQMa8Xx the PMIC PF8100 is assembled. The PF8100 is connected to a dedicated I2C bus of the i.MX 8X (PMIC_I2C) intended for power management. Alternatively, the PF8200 can be assembled. The PF8200 offers additional safety and monitoring functions that may be used as part of an ASIL requirement.

The following PMIC and power management signals are routed to the connectors:

Table 15: Provided PMIC signals

Signal I/O Power domain Remark

PMIC_PGOOD O V_1V8_ANA

PMIC_FSOB_EWARN O V_1V8_ANA

PMIC_I2C_SDA PMIC_I2C_SCL

I/O V_1V8_ANA

PMIC_PWRON I V_SNVS_CAP

Attention: Malfunction or destruction

The PMIC can be controlled via the dedicated i.MX 8X I2C bus (PMIC_I2C). Improper PMIC programming may cause the i.MX 8X or other peripherals on the TQMa8Xx to operate outside their specification. This can lead to malfunction, deterioration or destruction of the TQMa8Xx.

• PMIC power monitor output

• Requires pull-up on carrier board

• See PMIC data sheet (4)

• Assembly option: Connection to FSOB (standard) or EWARN of PMIC

• See PMIC data sheet (4)

• Dedicated PMIC interface

• Can be used for further power management on carrier board

• Enable signal for PMIC (High-Active)

• Activated by default when V_3V3_IN is switched on

• To activate: Float or with 3.3 V

• To deactivate: Connect to GND

Page 22

4. MECHANICS

4.1 Connectors

The TQMa8Xx is connected to the carrier board with 280 pins on three connectors.

The following table shows details of the connectors used:

Table 16: TQMa8Xx connectors

Manufacturer Part number Remark

TE connectivity

40-pin: 5177985-1 120-pin: 5177985-5

The TQMa8Xx is held in the mating connectors with a retention force of approximately 28 N. To avoid damaging the connectors of the TQMa8Xx as well as the connectors on the carrier board while removing the TQMa8Xx

the use of the extraction tool MOZI8XXL is strongly recommended. See chapter 4.8 for further information.

Attention: Note with respect to the component placement on the carrier board

• 0.8 mm pitch

• Plating: Gold 0.2 µm

• –40 °C to +125 °C

2.5 mm should be kept free on the carrier board, on both long sides of the TQMa8Xx for the extraction tool MOZI8XXL.

The following table shows some suitable mating connectors for the carrier board.

Table 17: Carrier board mating connectors

Manufacturer Part number Remark Stack height (X)

TE connectivity

40-pin: 5177986-1 120-pin: 5177986-5

40-pin: 1-5177986-1 120-pin: 1-5177986-5

40-pin: 2-5177986-1 120-pin: 2-5177986-5

40-pin: 3-5177986-1 120-pin: 3-5177986-5

On MBa8Xx 5 mm

– 6 mm

– 7 mm

– 8 mm

The pins assignment listed in Table 2, Table 3, and Table 4 refer to the corresponding

BSP provided by TQ-Systems GmbH.

For information regarding I/O pins in Table 2, Table 3 and Table 4, refer to the i.MX 8X Data Sheet (1).

Page 23

4.2 Dimensions

Illustration 11: TQMa8Xx dimensions, side view

Illustration 12: TQMa8Xx CPU position, top view

Illustration 13: TQMa8Xx dimensions, top view through TQMa8Xx

Page 24

4.3 Component placement

Illustration 14: TQMa8Xx, component placement top

119

AK3

119 1

120

Illustration 15: TQMa8Xx, component placement bottom

The labels on the TQMa8Xx show the following information:

Table 18: Labels on TQMa8Xx

2120

Label Text

AK1 TQMa8Xx Serial number

AK2 TQMa8Xx MAC address (+ additional reserved MAC addresses), tests performed

AK3 TQMa8Xx version, revision

Page 25

4.4 Adaptation to the environment

The TQMa8Xx has overall dimensions (length × width × height) of 55 × 44 × 8 mm. The TQMa8Xx has a maximum height above the carrier board of approximately 9.4 mm. The TQMa8Xx weighs approximately 17 grams.

4.5 Protection against external effects

As an embedded module, the TQMa8Xx is not protected against dust, external impact and contact (IP00). Adequate protection has to be guaranteed by the surrounding system.

4.6 Thermal management

To cool the TQMa8Xx, a calculated theoretical maximum of approximately 4.7 W have to be dissipated, see Table 11. The cooling solution must be able to dissipate this power peak; it will never occur permanently in normal operation. The power dissipation originates primarily in the i.MX 8X, the DDR3L SDRAM and the PMIC. The power dissipation also depends on the software used and can vary according to the application. See i.MX 8X Data Sheet (1) for further information.

Attention: Destruction or malfunction

The TQMa8Xx belongs to a performance category in which a cooling system is essential in most applications. It is the user’s sole responsibility to define a suitable heat sink (weight and mounting position) depending on the specific mode of operation (e.g., dependence on clock frequency, stack height, airflow, and software). Particularly the tolerance chain (PCB thickness, board warpage, BGA balls, BGA package, thermal pad, heatsink) as well as the maximum pressure on the i.MX 8X must be taken into consideration when connecting the heat sink.

The i.MX 8X is not necessarily the highest component. Inadequate cooling connections can lead to overheating of the TQMa8Xx and thus malfunction, deterioration or destruction.

4.7 Structural requirements

The TQMa8Xx is held in the mating connectors by the retention force of the pins (280). For high requirements with respect to vibration and shock firmness, an additional holder has to be provided in the final product to hold the TQMa8Xx in its position.

4.8 Notes of treatment

To avoid damage caused by mechanical stress, the TQMa8Xx may only be extracted from the carrier board by using the extraction tool MOZI8XXL that can also be obtained separately.

Attention: Note with respect to the component placement on the carrier board

2.5 mm should be kept free on the carrier board, on both long sides of the TQMa8Xx for the extraction tool MOZI8XXL.

5. SOFTWARE

The TQMa8Xx is delivered with a preinstalled boot loader U-Boot and a TQ-BSP, which is tailored for the MBa8Xx. The boot loader U-Boot provides TQMa8Xx-specific as well as board-specific settings, e.g.:

• i.MX 8X configuration

• PMIC configuration

• SDRAM configuration and timing

• eMMC configuration

• Multiplexing

• Clocks

• Pin configuration

• Driver strengths

These settings have to be adapted, in case another bootloader is used. More information can be found in the

Support Wiki for the TQMa8Xx.

Page 26

6. SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS

6.1 EMC

The TQMa8Xx was developed according to the requirements of electromagnetic compatibility (EMC). Depending on the target system, anti-interference measures may still be necessary to guarantee the adherence to the limits for the overall system.

Following measures are recommended:

• Robust ground planes (adequate ground planes) on the printed circuit board

• A sufficient number of blocking capacitors in all supply voltages

• Fast or permanently clocked lines (e.g., clock signals) should be kept short;

avoid interference of other signals by distance and/or shielding, also pay attention to frequencies and signal rise times

• Filtering of all signals, which can be connected externally

(also "slow signals" and DC can radiate RF indirectly)

6.2 ESD

In order to avoid interspersion on the signal path from the input to the protection circuit in the system, the protection against electrostatic discharge should be provided directly at the inputs of a system. As these measures always have to be implemented on the carrier board, no special protective measures were provided on the TQMa8Xx.

The following measures are recommended for a carrier board:

• Generally applicable: Shielding of inputs (shielding connected well to ground / housing on both ends)

• Supply voltages: Protection by suppressor diode(s)

• Slow signals: RC filtering, possibly Zener diode(s)

• Fast signals: Integrated protection components (e.g., suppressor diode arrays)

6.3 Operational safety and personal security

Due to the occurring voltages (≤5 V DC), tests with respect to the operational and personal safety have not been carried out.

Page 27

6.4 Climate and operational conditions

The operating temperature range for the TQMa8Xx strongly depends on the installation situation (heat dissipation by heat conduction and convection); hence, no fixed value can be given for the whole assembly.

In general, a reliable operation is given when following conditions are met:

Table 19: Climate and operational conditions extended temperature range –25 °C to +85 °C

Parameter Range Remark

Environmental temperature –25 °C to +60 °C –

Tj i.MX 8X TBD –

Tj PMIC TBD –

Case temperature DDR3L SDRAM –40 °C to +95 °C –

Case temperature other ICs TBD –

Storage temperature TQMa8Xx TBD –

Relative humidity (operating / storage) 10 % to 90 % Not condensing

Table 20: Climate and operational conditions industrial temperature range –40 °C to +85 °C

Parameter Range Remark

Environmental temperature –25 °C to +60 °C –

Tj i.MX 8X TBD –

Tj PMIC TBD –

Case temperature DDR3L SDRAM –40 °C to +95 °C –

Case temperature other ICs TBD –

Storage temperature TQMa8Xx TBD –

Relative humidity (operating / storage) 10 % to 90 % Not condensing

Detailed information concerning the thermal characteristics of the i.MX 8X is to be taken from the NXP documents (1), and (2).

Attention: Destruction or malfunction

The i.MX 8X is not necessarily the highest component. Inadequate cooling connections can lead to overheating of the TQMa8Xx and thus malfunction, deterioration or destruction.

6.5 Reliability and service life

The MTBF of the TQMa8Xx is estimated to be 1,000,000 hours @ +40 °C environmental temperature, ground benign. The TQMa8Xx is designed to be insensitive to shock and vibration. High quality industrial grade connectors are assembled on the TQMa8Xx.

Page 28

7. ENVIRONMENT PROTECTION

7.1 RoHS

The TQMa8Xx is manufactured RoHS compliant.

• All components and assemblies are RoHS compliant

• The soldering processes are RoHS compliant

7.2 WEEE

The final distributor is responsible for compliance with the WEEE® regulation. Within the scope of the technical possibilities, the TQMa8Xx was designed to be recyclable and easy to repair.

7.3 REACH

The EU-chemical regulation 1907/2006 (REACH® regulation) stands for registration, evaluation, certification and restriction of substances SVHC (Substances of very high concern, e.g., carcinogen, mutagen and/or persistent, bio accumulative and toxic). Within the scope of this juridical liability, TQ-Systems GmbH meets the information duty within the supply chain with regard to the SVHC substances, insofar as suppliers inform TQ-Systems GmbH accordingly.

7.4 EuP

The Ecodesign Directive, also Energy using Products (EuP), is applicable to products for the end user with an annual quantity >200,000. The TQMa8Xx must therefore always be seen in conjunction with the complete device. The available standby and sleep modes of the components on the TQMa8Xx enable compliance with EuP requirements for the TQMa8Xx.

7.5 Battery

No batteries are assembled on the TQMa8Xx.

7.6 Packaging

By environmentally friendly processes, production equipment and products, we contribute to the protection of our environment. To be able to reuse the TQMa8Xx, it is produced in such a way (a modular construction) that it can be easily repaired and disassembled. The energy consumption of this subassembly is minimised by suitable measures. The TQMa8Xx is delivered in reusable packaging.

7.7 Other entries

The energy consumption of this subassembly is minimised by suitable measures. Because currently there is still no technical equivalent alternative for printed circuit boards with bromine-containing flame

protection (FR-4 material), such printed circuit boards are still used. No use of PCB containing capacitors and transformers (polychlorinated biphenyls). These points are an essential part of the following laws:

• The law to encourage the circular flow economy and assurance of the environmentally

acceptable removal of waste as at 27.9.94 (Source of information: BGBl I 1994, 2705)

• Regulation with respect to the utilization and proof of removal as at 1.9.96

(Source of information: BGBl I 1996, 1382, (1997, 2860))

• Regulation with respect to the avoidance and utilization of packaging waste as at 21.8.98

(Source of information: BGBl I 1998, 2379)

• Regulation with respect to the European Waste Directory as at 1.12.01

(Source of information: BGBl I 2001, 3379)

This information is to be seen as notes. Tests or certifications were not carried out in this respect.

Page 29

8. APPENDIX

8.1 Acronyms and definitions

The following acronyms and abbreviations are used in this document:

Table 21: Acronyms

Acronym Meaning

ADC Analog/Digital Converter ASIL Automotive Safety Integrity Level BGA Ball Grid Array BIOS Basic Input/Output System BSP Board Support Package CAN Controller Area Network CMOS Complementary Metal Oxide Semiconductor CPU Central Processing Unit DDR Double Data Rate DDR3L DDR3 Low voltage DNC Do Not Connect DSI Display Serial Interface DVI Digital Visual Interface ECC Error-Correcting Code EEPROM Electrically Erasable Programmable Read-only Memory EMC Electromagnetic Compatibility eMMC embedded Multimedia Card ESD Electrostatic Discharge EU European Union EuP Energy using Products GPI General-Purpose Input GPIO General-Purpose Input/Output GPMC General-Purpose Memory Controller GPO General-Purpose Output HDMI High Definition Multimedia Interface I/O Input/Output I2C Inter-Integrated Circuit I2S Inter-IC Sound IP00 Ingress Protection 00 JEDEC Joint Electronic Device Engineering Council JTAG® Joint Test Action Group LCD Liquid Crystal Display LVDS Low-Voltage Differential Signalling MAC Media Access Control MCASP Multichannel Audio Serial Port MIPI Mobile Industry Processor Interface MMC Multimedia Card MOZI Module extractor (Modulzieher) MTBF Mean operating Time Between Failures

Page 30

Table 21: Acronyms (continued)

Acronym Meaning

NAND Not-And NOR Not-Or OTG On-The-Go OTP One-Time Programmable PCB Printed Circuit Board PCIe Peripheral Component Interconnect Express PCMCIA People Can't Memorize Computer Industry Acronyms PHY Physical (layer of the OSI model) PMIC Power Management Integrated Circuit PRU Programmable Real-Time Unit PWM Pulse-Width Modulation PWP Permanent Write Protected QSPI Quad Serial Peripheral Interface RAM Random Access Memory REACH® Registration, Evaluation, Authorisation (and restriction of) Chemicals RF Radio Frequency RFU Reserved for Future Usage RGB Red Green Blue RMII Reduced Media-Independent Interface RoHS Restriction of (the use of certain) Hazardous Substances ROM Read-Only Memory RTC Real-Time Clock RWP Reversible Write Protected SAI Serial Audio Interface SATA Serial ATA SCU System Control Unit SD Secure Digital SDIO Secure Digital Input/Output SDRAM Synchronous Dynamic Random Access Memory SPI Serial Peripheral Interface TBD To Be Determined UART Universal Asynchronous Receiver / Transmitter UM User's Manual USB Universal Serial Bus WEEE® Waste Electrical and Electronic Equipment

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8.2 References

Table 22: Further applicable documents

No. Name Rev., Date Company

(1) i.MX 8X Data Sheet Rev. C, 11/2017 NXP

(2) i.MX 8X Reference Manual – NXP

(3) i.MX 8X Chip Errata – NXP

(4) Power management integrated circuit PF8100 Rev. 2.0, 26 January 2018 NXP

(5) MBa8Xx User’s Manual – current – TQ-Systems

(6) Support-Wiki for the TQMa8Xx – current – TQ-Systems

Page 32

TQ-Systems GmbH

Mühlstraße 2 l Gut Delling l 82229 Seefeld

Info@TQ-Group | TQ-Group

TQ-Systems TQMa8Xx Preliminary User's Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1. ABOUT THIS MANUAL

1.1 Copyright and license expenses

1.2 Registered trademarks

1.3 Disclaimer

1.4 Imprint

1.5 Tips on safety

1.6 Symbols and typographic conventions

1.7 Handling and ESD tips

1.8 Naming of signals

1.9 Further applicable documents / presumed knowledge

2. BRIEF DESCRIPTION

2.1 Block diagram i.MX 8X

2.2 Key functions and characteristics

3. ELECTRONICS

3.1 Interfaces to other systems and devices

3.1.1 Pin multiplexing

3.1.2 Connector X1

3.1.3 Connector X2

3.1.4 Connector X3

3.2 System components

3.2.1 i.MX 8X CPU

3.2.1.1 i.MX 8X derivatives

3.2.1.2 i.MX 8X errata

3.2.1.3 Boot modes

3.2.2 Memory

3.2.2.1 DDR3L SDRAM

3.2.2.2 eMMC NAND flash

3.2.2.3 QSPI NOR flash

3.2.2.4 EEPROM

3.2.3 RTC

3.2.4 Interfaces

3.2.5 Reset

3.2.6 Power

3.2.6.1 Power supply

3.2.6.2 Power consumption

3.2.6.3 LICELL

3.2.6.4 ADC input voltage V_ADC_IN

3.2.6.5 USB_OTG[2:1]_VBUS

3.2.6.6 Provided TQMa8Xx voltages

3.2.6.7 Voltage monitoring

3.2.6.8 Power-Up sequence TQMa8Xx / carrier board

3.2.6.9 Power modes

3.2.6.10 PMIC

4. MECHANICS

4.1 Connectors

4.2 Dimensions

4.3 Component placement

4.4 Adaptation to the environment

4.5 Protection against external effects

4.6 Thermal management

4.7 Structural requirements

4.8 Notes of treatment

5. SOFTWARE

6. SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS

6.1 EMC

6.2 ESD

6.3 Operational safety and personal security

6.4 Climate and operational conditions

6.5 Reliability and service life

7. ENVIRONMENT PROTECTION

7.1 RoHS

7.4 EuP

7.5 Battery

7.6 Packaging

7.7 Other entries

8. APPENDIX

8.1 Acronyms and definitions

8.2 References