TOWA MECCS TMM1000 Hardware Manual
TMM1000
HARDWARE MANUAL
2003
/07/
04
INDEX
1. Introduction................................................................................................................................. 1
1-1. Outline .................................................................................................................................. 1
1-2. Features................................................................................................................................1
1-3. Specifications ...................................................................................................................... 2
1-4. Composition......................................................................................................................... 3
2. I/O ................................................................................................................................................. 4
2-1. Memory, I/O map.................................................................................................................. 4
2-2. Detailed I/O area .................................................................................................................. 5
2-3. IRQ ........................................................................................................................................ 5
2-4. I/O built-in CPU .................................................................................................................... 6
3. I/O terminals................................................................................................................................7
4. LAN-LED display ...................................................................................................................... 16
-1-
1. Introduction
1-1. Outline
TMM-1000 is the CPU board for installing in the device, in which HITACHI CPU SH3
(HD6417709S) microcomputer is adopted.
It includes LAN, USB and a storage medium (compact flash), and has scalability.
By using it, it has become possible to make a deep cut of man-hour for development of
similar control boards, and to realize easily sophisticated application software such as
TCP/IP with utilizing high grade OS such as LINUX, etc.
1-2. Features
a) As HITACHI SH microcomputer is adopted, low power consumption and no fan can be
realized.
b) As compact flash interface is included as standard equipment, no drive member exists such
as hard disk and so on.
c) High-speed drawing is possible because the video chip with graphic accelerator is adopted.
d) A USB port with high scalability is supported normally. (Please inquire the peripherals to
connect with.)
e) A touch panel interface is supported normally.
f) By installing an expansion board, it is possible to add PS2 keyboard, centronics interface and
RS232 ports.
g) Ether ports of 100/10BaseT are included as standard equipment.
-2-
1-3. Specifications
CPU: HD6417709SF133B
Working speed: CPU clock: 133.32MHz
CPU IO: 33.33MHz
Bus clock: 66.66MHz
Memory: Boot: F-EP ROM, 4M Byte (Max. 32M Byte)
D-RAM: S-DRAM, 32M Byte (Max 128M Byte)
S-RAM: S-RAM, 512K Byte (Optional)
Display: For NEC LCD panel (640 x 480) IF
S1D13508F00A100 EPSON
LAN: 100/10BaseT X 1ch LAN91C111 SMSC
I/O: Compact flash X 1
Serial 0 3.3V-IF, built-in SCI
Serial 1 (D-SUB 9-pin, built-in SCIF)
Serial 2 Built-in SCI
Touch panel scan IF
USB: SL811HST
Others: Sound: Monaural 8-bit DA Output: 300mW
Debugging terminal, H-UDL
Power source: +5V, single source
In static condition: 500mA In operation: 850mA
Size of size: 210 X 122mm (Except raised portions)
Operating temperature limit: 0 to 50 degree C
Operating and storage humidity limits: 5 to 90 percent
(without condensation)
Storage temperature limit: -20 to +70 degree C
-3-
1-4. Composition
PN2
CPU
SH3 133M
VIDEO
S1D13806
S-RAM
512Kbyte
SDRAM
32Mbyte
F-EP ROM
4Mbyte
USB
PN10 PN16
CONTROL
PN5
PN4
PN15
PN12
PN9
S
W
LCD
Other
Ext Power
PN14 PN7
Touch Panel
Speaker
PN17 PN13 PN11 PN18 PN19
COM1 COM2
COM0
Expansion
terminal
LAN USB
Ether-net
LAN91C11
PN1
CF
Optional
-4-
2. I/O
I/O in the board is composed with built-in I/O in CPU and I/O added outside.
Even if a sub-board does not exist when initializing, the movement for initializing is executed
to IC's installed in the sub-board.
In the manual, it is explained on CPU board only.
CPU has DMA function, but it cannot be used on the board.
The circuit of LCA chip is not published.
Here, I/O's are explained except I/O built-in SH-3.
Please refer to SH-3 hardware manual on I/O built-in SH-3.
2-1. Memory, I/O map
Regarding I/O, the memory mapped I/O is adopted, and the allocation is as follows:
Physical mapping on area
Area Address Bus width
Area 0 H'00000000 to H'03FFFFFF 16 F-EPROM 4M Byte to H'003FFFFF
Area 1 H'04000000 to H'07FFFFFF I/O built-in CPU
Area 2 H'0８000000 to H'0BFFFFFF 32 S-DRAM, spare, unpopulated
Area 3 H'0C000000 to H'0FFFFFFF 32 S-DRAM, 32M, populated
Area 4 H'10000000 to H'13FFFFFF 16 I/O area
Area 5 H'14000000 to H'17FFFFFF 16 S-RAM 512K Byte
Area 6 H'18000000 to H'19FFFFFF 16 Used in CF
Area 7 H'1C000000 to H'1FFFFFFF Reserved
Above mapping can be traced on bigger number addresses.
Therefore, if you operate memory directly through OS, use the image in the range.
Please designate the address offset in which the absolute address can be
designated in case you adopt OS to use MMU such as LINUX.
Example: LINUX
Area 4 H'B0000000 to H'B3FFFFFF I/O area
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