TOSHIBA TMP86PS23UG Technical data

8 Bit Microcontroller

TLCS-870/C Series

TMP86PS23UG

The information contained herein is subject to change without notice. 021023_D

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless,
semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and
vulnerability to physical stress.
It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards
of safety in making a safe design for the entire system, and to avoid situations in which a malfunction
or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating
ranges as set forth in the most recent TOSHIBA products specifications.

Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A

The TOSHIBA products listed in this document are intended for usage in general electronics
applications (computer, personal equipment, office equipment, measuring equipment, industrial
robotics, domestic appliances, etc.).
These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of

human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments,
combustion control instruments, medical instruments, all types of safety devices, etc. Unintended
Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.
021023_B

The products described in this document shall not be used or embedd ed to any downstream prod ucts of
which manufacture, use and/or sale are prohibited under any applicable laws and regulations.
060106_Q

The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third
parties which may result from its use. No license is granted by implication or otherwise under any
patents or other rights of TOSHIBA or the third parties. 070122_C

The products described in this document are subject to foreign exchange and foreign trade control
laws. 060925_E

For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3
of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S

© 2007 TOSHIBA CORPORATION

All Rights Reserved

Revision History

Date Revision

2006/8/24 1 First Release

2007/10/25

2008/8/29

2 Contents Revised
3 Contents Revised

Caution in Setting the UART Noise Rejection Time

When UART is used, settings of RXDNC are limited depending on the transfer clock specified by BRG. The com-

bination "O" is available but please do not select the combination "–".

The transfer clock generated by timer/counter interrupt is calculated by the following equation :
Transfer clock [Hz] = Timer/counter source clock [Hz] ÷ TTREG set value

RXDNC setting

BRG setting

000 fc/13 O O O –
110

(When the transfer clock gen-

erated by timer/counter inter-

rupt is the same as the right

side column)
The setting except the aboveOOOO

Transfer

clock [Hz]

fc/8 O – – –

fc/16 O O – –

fc/32OOO–

00

(No noise rejection)

(Reject pulses shorter
than 31/fc[s] as noise)

01

(Reject pulses shorter
than 63/fc[s] as noise)

10

(Reject pulses shorter

11

than 127/fc[s] as

noise)

Table of Contents

TMP86PS23UG

1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2. Operational Description

2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Memory Address Map............................................................................................................................... 9

2.1.2 Program Memory (OTP) ........................................................................................................................... 9

2.1.3 Data Memory (RAM)................................................................................................................................. 9

2.2 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.2.1 Clock Generator...................................................................................................................................... 10

2.2.2 Timing Generator.................................................................................................................................... 12

2.2.2.1 Configuration of timing generator

2.2.2.2 Machine cycle

2.2.3 Operation Mode Control Circuit .............................................................................................................. 13

2.2.3.1 Single-clock mode

2.2.3.2 Dual-clock mode

2.2.3.3 STOP mode

2.2.4 Operating Mode Control ......................................................................................................................... 18

2.2.4.1 STOP mode

2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode

2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0)

2.2.4.4 SLOW mode

2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.3.1 External Reset Input ............................................................................................................................... 31

2.3.2 Address trap reset .................................................................................................................................. 32

2.3.3 Watchdog timer reset.............................................................................................................................. 32

2.3.4 System clock reset.................................................................................................................................. 32

3. Interrupt Control Circuit

3.1 Interrupt latches (IL19 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2 Interrupt enable register (EIR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.1 Interrupt master enable flag (IMF) .......................................................................................................... 36

3.2.2 Individual interrupt enable flags (EF19 to EF4) ...................................................................................... 37

Note 3: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.3 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.3.1 Interrupt acceptance processing is packaged as follows........................................................................ 39

3.3.2 Saving/restoring general-purpose registers............................................................................................ 40

3.3.2.1 Using PUSH and POP instructions

3.3.2.2 Using data transfer instructions

3.3.3 Interrupt return........................................................................................................................................ 41

3.4 Software Interrupt (INTSW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.4.1 Address error detection .......................................................................................................................... 42

3.4.2 Debugging .............................................................................................................................................. 42

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3.5 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.6 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.7 External Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4. Special Function Register (SFR)

4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.2 DBR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5. I/O Ports

5.1 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

5.2 Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

5.3 Port P3 (P37 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

5.4 Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.5 Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

5.6 Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.7 Port P8 (P87 to P80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

6. Time Base Timer (TBT)

6.1 Time Base Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

6.1.1 Configuration .......................................................................................................................................... 65

6.1.2 Control .................................................................................................................................................... 65

6.1.3 Function.................................................................................................................................................. 66

6.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

6.2.1 Configuration .......................................................................................................................................... 67

6.2.2 Control .................................................................................................................................................... 67

7. Watchdog Timer (WDT)

7.1 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

7.2 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

7.2.1 Malfunction Detection Methods Using the Watchdog Timer................................................................... 70

7.2.2 Watchdog Timer Enable ......................................................................................................................... 71

7.2.3 Watchdog Timer Disable ........................................................................................................................ 72

7.2.4 Watchdog Timer Interrupt (INTWDT)...................................................................................................... 72

7.2.5 Watchdog Timer Reset........................................................................................................................... 73

7.3 Address Trap. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

7.3.1 Selection of Address Trap in Internal RAM (ATAS)................................................................................ 74

7.3.2 Selection of Operation at Address Trap (ATOUT).................................................................................. 74

7.3.3 Address Trap Interrupt (INTATRAP)....................................................................................................... 74

7.3.4 Address Trap Reset................................................................................................................................ 75

8. 18-Bit Timer/Counter (TC1)

8.1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

8.2 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

8.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

ii

8.3.1 Timer mode............................................................................................................................................. 81

8.3.2 Event Counter mode............................................................................................................................... 82

8.3.3 Pulse Width Measurement mode............................................................................................................ 83

8.3.4 Frequency Measurement mode.............................................................................................................. 84

9. 8-Bit TimerCounter (TC3, TC4)

9.1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

9.2 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

9.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

9.3.1 8-Bit Timer Mode (TC3 and 4)................................................................................................................ 93

9.3.2 8-Bit Event Counter Mode (TC3, 4) ........................................................................................................ 94

9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)..................................................................... 94

9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4).................................................................. 97

9.3.5 16-Bit Timer Mode (TC3 and 4).............................................................................................................. 99

9.3.6 16-Bit Event Counter Mode (TC3 and 4) .............................................................................................. 100

9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)........................................................ 100

9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4)............................................. 103

9.3.9 Warm-Up Counter Mode....................................................................................................................... 105

9.3.9.1 Low-Frequency Warm-up Counter Mode

9.3.9.2 High-Frequency Warm-Up Counter Mode

(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)

10. 8-Bit TimerCounter (TC5, TC6)

10.1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

10.2 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

10.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

10.3.1 8-Bit Timer Mode (TC5 and 6)............................................................................................................ 113

10.3.2 8-Bit Event Counter Mode (TC5, 6) .................................................................................................... 114

10.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC5, 6)................................................................. 114

10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC5, 6).............................................................. 117

10.3.5 16-Bit Timer Mode (TC5 and 6).......................................................................................................... 119

10.3.6 16-Bit Event Counter Mode (TC5 and 6) ............................................................................................ 120

10.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)...................................................... 120

10.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6)........................................... 123

10.3.9 Warm-Up Counter Mode..................................................................................................................... 125

10.3.9.1 Low-Frequency Warm-up Counter Mode

10.3.9.2 High-Frequency Warm-Up Counter Mode

(NORMAL1 → NORMAL2 → SLOW2 → SLOW1)
(SLOW1 → SLOW2 → NORMAL2 → NORMAL1)

11. Asynchronous Serial interface (UART )

11.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

11.2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

11.3 Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

11.4 Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

11.5 Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

11.6 STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

11.7 Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

11.8 Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

11.8.1 Data Transmit Operation .................................................................................................................... 132

11.8.2 Data Receive Operation ..................................................................................................................... 132

11.9 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

iii

11.9.1 Parity Error.......................................................................................................................................... 133

11.9.2 Framing Error...................................................................................................................................... 133

11.9.3 Overrun Error...................................................................................................................................... 133

11.9.4 Receive Data Buffer Full..................................................................................................................... 134

11.9.5 Transmit Data Buffer Empty ............................................................................................................... 134

11.9.6 Transmit End Flag .............................................................................................................................. 135

12. Synchronous Serial Interface (SIO)

12.1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

12.2 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12.3 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

12.3.1 Clock source....................................................................................................................................... 139

12.3.1.1 Internal clock

12.3.1.2 External clock

12.3.2 Shift edge............................................................................................................................................ 141

12.3.2.1 Leading edge

12.3.2.2 Trailing edge

12.4 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

12.5 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

12.6 Transfer Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

12.6.1 4-bit and 8-bit transfer modes............................................................................................................. 142

12.6.2 4-bit and 8-bit receive modes ............................................................................................................. 144

12.6.3 8-bit transfer / receive mode............................................................................................................... 145

13. 10-bit AD Converter (ADC)

13.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

13.2 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

13.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

13.3.1 Software Start Mode........................................................................................................................... 151

13.3.2 Repeat Mode ...................................................................................................................................... 151

13.3.3 Register Setting ................................................................................................................................ 152

13.4 STOP/SLOW Modes during AD Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . 153

13.5 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 154

13.6 Precautions about AD Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

13.6.1 Restrictions for AD Conversion interrupt (INTADC) usage................................................................. 155

13.6.2 Analog input pin voltage range ........................................................................................................... 155

13.6.3 Analog input shared pins .................................................................................................................... 155

13.6.4 Noise Countermeasure....................................................................................................................... 155

14. Key-on Wakeup (KWU)

14.1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14.2 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

14.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

15. LCD Driver

15.1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

15.2 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

15.2.1 LCD driving methods .......................................................................................................................... 161

15.2.2 Frame frequency................................................................................................................................. 162

iv

15.2.3 LCD drive voltage ............................................................................................................................... 163

15.2.4 Adjusting the LCD panel drive capability ............................................................................................ 163

15.3 LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164

15.3.1 Display data setting ............................................................................................................................ 164

15.3.2 Blanking.............................................................................................................................................. 164

15.4 Control Method of LCD Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

15.4.1 Initial setting........................................................................................................................................ 165

15.4.2 Store of display data........................................................................................................................... 165

15.4.3 Example of LCD driver output............................................................................................................. 167

16. Real-Time Clock

16.1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

16.2 Control of the RTC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

16.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

17. Multiply-Accumulate (MAC) Unit

17.1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

17.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

17.2.1 Command Register............................................................................................................................. 175

17.2.2 Status Register ................................................................................................................................... 176

17.2.3 Multiplier data Register....................................................................................................................... 176

17.2.4 Multiplicand data Register .................................................................................................................. 176

17.2.5 Result Register ................................................................................................................................... 176

17.2.6 Addend Register................................................................................................................................. 176

17.3 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

17.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

17.4.1 EMAC ................................................................................................................................................. 178

17.4.2 CMOD................................................................................................................................................. 178

17.4.3 RCLR.................................................................................................................................................. 178

17.5 Arithmetic Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

17.5.1 Unsigned Multiply Mode ..................................................................................................................... 179

17.5.2 Signed Multiply Mode ......................................................................................................................... 179

17.5.3 Unsigned Multiply-Accumulate Mode ................................................................................................. 179

17.5.4 Signed Multiply-Accumulate Mode ..................................................................................................... 180

17.5.5 Valid Numerical Ranges ..................................................................................................................... 180

17.6 Status Flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

17.6.1 Operation Status Flag (CALC)............................................................................................................ 181

17.6.2 Overflow Flag (OVRF) ........................................................................................................................ 181

17.6.3 Carry Flag (CARF).............................................................................................................................. 181

17.6.4 Sign Flag (SIGN) ................................................................................................................................ 181

17.6.5 Zero Flag (ZERF)................................................................................................................................ 181

17.7 Example of Software Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

18. OTP operation

18.1 Operating mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

18.1.1 MCU mode.......................................................................................................................................... 183

18.1.1.1 Program Memory

18.1.1.2 Data Memory

18.1.1.3 Input/Output Circuiry

18.1.2 PROM mode....................................................................................................................................... 185

18.1.2.1 Programming Flowchart (High-speed program writing)

18.1.2.2 Program Writing using a General-purpose PROM Programmer

v

19. Input/Output Circuitry

19.1 Control Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

19.2 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

20. Electrical Characteristics

20.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

20.2 Operating Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

20.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

20.4 AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

20.5 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

20.6 Timer Counter 1 input (ECIN) Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 196

20.7 DC Characteristics, AC Characteristics (PROM mode). . . . . . . . . . . . . . . . . . . 197

20.7.1 Read operation in PROM mode.......................................................................................................... 197

20.7.2 Program operation (High-speed) ........................................................................................................ 198

20.8 Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

20.9 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

21. Package Dimensions

This is a technical document that describes the operating functions and electrical
specifications of the 8-bit microcontroller series TLCS-870/C (LSI).

vi

TMP86PS23UG

CMOS 8-Bit Microcontroller

TMP86PS23UG

The TMP86PS23UG is a single-chip 8-bit high-speed and high-functionality microcomputer incorporatin g 61440
bytes of One-Time PROM. It is pin-compatible with the TMP86CP23AUG (Mask ROM version). The
TMP86PS23UG can realize operations equivalent to those of the TMP86CP23AUG by programming the on-chip
PROM.

Product No.

TMP86PS23UG

1.1 Features

1. 8-bit single chip microcomputer TLCS-870/C series

- Instruction execution time :

- 132 types & 731 basic instructions

2. 20interrupt sources (External : 5 Internal : 15)

3. Input / Output ports (I/O : 48 pins Output : 3 pins)
Large current output: 5pins (Typ. 20mA), LED direct drive

4. Prescaler

- Time base timer

- Divider output function

5. Watchdog Timer

6. 18-bit Timer/Counter : 1ch

- Timer Mode

- Event Counter Mode

- Pulse Width Measurement Mode

- Frequency Measurement Mode

ROM

(EPROM)

61440

bytes

RAM Package MASK ROM MCU Emulation Chip

2048
bytes

0.25 µs (at 16 MHz)
122 µs (at 32.768 kHz)

LQFP64-P-1010-0.50E TMP86CP23AUG TMP86C923XB

• The information contained herein is subject to change without notice. 021023_D

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can
malfunction or fail due to their inherent electrical sensitivity and vulner ability to ph ysical stress. It is the responsibility of the buye r, when
utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations
in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equip­ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither
intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of
which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments,
airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instru­ments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's
own risk. 021023_B

• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or
sale are prohibited under any applicable laws and regulations. 060106_Q

• The information contained herein is presented only as a guid e for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third p arties which may result from its use. No license is granted by impli­cation or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C

• The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E

• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and
Reliability Assurance/Handling Precautions. 030619_S

Page 1

1.1 Features
TMP86PS23UG

7. 8-bit timer counter : 4 ch

- Timer, Event counter, Programmable divider output (PDO),
Pulse width modulation (PWM) output,
Programmable pulse generation (PPG) modes

8. 8-bit UART : 1 ch

9. 8-bit SIO: 1 ch

10.10-bit successive approximation type AD converter

- Analog input: 8 ch

11.Key-on wakeup : 4 ch

12.LCD driver/controller

- LCD direct drive capability (MAX 32 seg × 4 com)

- 1/4,1/3,1/2duties or static drive are programmably selectable

13.Multiply accumulate unit (MAC)

- Multiply or MAC mode are selectable

- Signed or unsigned operation are selectable

14. Clock operation
Single clock mode
Dual clock mode

15. Low power consumption operation
STOP mode: Oscillation stops. (Battery/Capacitor back-up.)
SLOW1 mode: Low power consumption operation using low-frequency clock.(Hi gh-frequency clock

stop.)

SLOW2 mode: Low power consumption operation using low-frequency clock.(Hi gh-frequency clock

oscillate.)

IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high fre-

quency clock. Release by falling edge of the source clock which is set by TBTCR<TBTCK>.

IDLE1 mode: CPU stops and peripherals operate using high frequency clock. Release by interru-

puts(CPU restarts).

IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by inter-

ruputs. (CPU restarts).

SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low fre-

quency clock.Release by falling edge of the source clock which is set by TBTCR<TBTCK>.

SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interru-

put.(CPU restarts).

SLEEP2 mode: CPU stops and peripherals operate using high and low frequenc y clock. Release by

interruput.

16.Wide operation voltage:

3.5 V to 5.5 V at 16MHz /32.768 kHz

2.7 V to 5.5 V at 8 MHz /32.768 kHz

1.8 V to 5.5 V at 4.2MHz /32.768 kHz

Page 2

1.2 Pin Assignment

TMP86PS23UG

P74 (SEG11)

P73 (SEG12)

P72 (SEG13)

P71 (SEG14)

P70 (SEG15)

P57 (SEG16)

P56 (SEG17)

P84 (SEG3)

P83 (SEG4)

P82 (SEG5)

P81 (SEG6)

P80 (SEG7)

P77 (SEG8)

P76 (SEG9)

P75 (SEG10)

P55 (SEG18)

(TC6/

PDO6/PWM6/PPG6) P33

(TC5/

PDO5/PWM5) P34

PDO4/PWM4/PPG4) P35

(

PDO3/PWM3) P36

(

(SEG2) P85
(SEG1) P86
(SEG0) P87

COM3
COM2

COM1
COM0

VLC

(TC4/SI) P30

(TC3/SO) P31

SCK) P32

(

DVO) P37

(

484746454443424140393837363534

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

123456789

XIN

VSS

TEST

XOUT

VDD

(XTIN) P21

RESET

(XTOUT) P22

(INT5/STOP) P20

10111213141516

AVDD

VAREF

(AIN0) P60

INT0/AIN3) P63

(

(ECIN/AIN1) P61

(ECNT/AIN2) P62

Figure 1-1 Pin Assignment

33

32

P54(SEG19)

31

P53(SEG20)

30

P52(SEG21)

29

P51(SEG22)

28

P50(SEG23)

27

P17(SEG24)

26

P16(SEG25)

25

P15(SEG26)
P14(SEG27/INT3)

24

P13(SEG28/INT2)

23
22

P12(SEG29/INT1)

21

P11(SEG30/TXD)

20

P10(SEG31/RXD/BOOT)

19

P67(AIN7/STOP5)

18

P66(AIN6/STOP4)

17

P65(AIN5/STOP3)

(STOP2/AIN4) P64

Page 3

1.3 Block Diagram

1.3 Block Diagram

TMP86PS23UG

Figure 1-2 Block Diagram

Page 4

1.4 Pin Names and Functions

The TMP86PS23UG has MCU mode and PROM mode. Table 1-1 shows the pin functions in MCU mode. The

PROM mode is explained later in a separate chapter.

Table 1-1 Pin Names and Functions(1/3)

Pin Name Pin Number Input/Output Functions

TMP86PS23UG

P17
SEG24

P16
SEG25

P15
SEG26

P14
SEG27
INT3

P13
SEG28
INT2

P12
SEG29
INT1

P11
SEG30
TXD

P10
SEG31
RXD

P22
XTOUT

27

26

25

24

23

22

21

20

7

IOOPORT17

LCD segment output 24

IOOPORT16

LCD segment output 25

IOOPORT15

LCD segment output 26

IO

PORT14

O

LCD segment output 27

I

External interrupt 3 input

IO

PORT13

O

LCD segment output 28

I

External interrupt 2 input

IO

PORT12

O

LCD segment output 29

I

External interrupt 1 input

IO

PORT11

O

LCD segment output 30

O

UART data output

IO

PORT10

O

LCD segment output 31

I

UART data input

PORT22

IO

Resonator connecting pins(32.768kHz) for inputtin g external

O

clock

P21
XTIN

P20

STOP
INT5

P37

DVO

P36

PDO3/PWM3

P35

PDO4/PWM4/PPG4

P34

PDO5/PWM5

TC5

P33

PDO6/PWM6/PPG6

TC6

P32

SCK

PORT21

6

9

64

63

62

61

60

59

IO

Resonator connecting pins(32.768kHz) for inputtin g external

I

clock

IO

PORT20

I

STOP mode release signal input

I

External interrupt 5 input

OOPORT37

Divider Output

OOPORT36

PDO3/PWM3 output

OOPORT35

PDO4/PWM4/PPG4 output

IO

PORT34

O

PDO5/PWM5 output

I

TC5 input

IO

PORT33

O

PDO6/PWM6/PPG6 output

I

TC6 input

IOIOPORT32

Serial Clock I/O

Page 5

1.4 Pin Names and Functions

Table 1-1 Pin Names and Functions(2/3)

Pin Name Pin Number Input/Output Functions

TMP86PS23UG

P31
SO
TC3

P30
SI
TC4

P57
SEG16

P56
SEG17

P55
SEG18

P54
SEG19

P53
SEG20

P52
SEG21

P51
SEG22

P50
SEG23

IO

PORT31

58

57

35

34

33

32

31

30

29

28

O

Serial Data Output

I

TC3 input

IO

PORT30

I

Serial Data Input

I

TC4 input

IOOPORT57

LCD segment output 16

IOOPORT56

LCD segment output 17

IOOPORT55

LCD segment output 18

IOOPORT54

LCD segment output 19

IOOPORT53

LCD segment output 20

IOOPORT52

LCD segment output 21

IOOPORT51

LCD segment output 22

IOOPORT50

LCD segment output 23

P67
AIN7
STOP5

P66
AIN6
STOP4

P65
AIN5
STOP3

P64
AIN4
STOP2

P63
AIN3

INT0

P62
AIN2
ECNT

P61
AIN1
ECIN

P60
AIN0

IO

PORT67

19

18

17

16

15

14

13

12

I

Analog Input7

I

STOP5 input

IO

PORT66

I

Analog Input6

I

STOP4 input

PORT65

IO

I

Analog Input5

I

STOP3 input

IO

PORT64

I

Analog Input4

I

STOP2 input

IO

PORT63

I

Analog Input3

I

External interrupt 0 input

IO

PORT62

I

Analog Input2

I

ECNT input

IO

PORT61

I

Analog Input1

I

ECIN input

IOIPORT60

Analog Input0

P77
SEG8

P76
SEG9

43

42

IOOPORT77

LCD segment output 8

IOOPORT76

LCD segment output 9

Page 6

Table 1-1 Pin Names and Functions(3/3)

Pin Name Pin Number Input/Output Functions

TMP86PS23UG

P75
SEG10

P74
SEG11

P73
SEG12

P72
SEG13

P71
SEG14

P70
SEG15

P87
SEG0

P86
SEG1

P85
SEG2

P84
SEG3

41

40

39

38

37

36

51

50

49

48

IOOPORT75

LCD segment output 10

IOOPORT74

LCD segment output 1 1

IOOPORT73

LCD segment output 12

IOOPORT72

LCD segment output 13

IOOPORT71

LCD segment output 14

IOOPORT70

LCD segment output 15

IOOPORT87

LCD segment output 0

IOOPORT86

LCD segment output 1

IOOPORT85

LCD segment output 2

IOOPORT84

LCD segment output 3

P83
SEG4

P82
SEG5

P81
SEG6

P80
SEG7

COM3 52 O LCD common output 3

COM2 53 O LCD common output 2

COM1 54 O LCD common output 1

COM0 55 O LCD common output 0

XIN 2 I Resonator connecting pins for high-frequency clock

XOUT 3 O Resonator connecting pins for high-frequency clock

RESET 8 I Reset signal

TEST 4 I Test pin for out-going test. Normally, be fixed to low.

VAREF 11 I Analog Base Voltage Input Pin for A/D Conversion

AVDD 10 I Analog Power Supply

47

46

45

44

IOOPORT83

LCD segment output 4

IOOPORT82

LCD segment output 5

IOOPORT81

LCD segment output 6

IOOPORT80

LCD segment output 7

VDD 5 I +5V

VSS 1 I 0(GND)

Page 7

1.4 Pin Names and Functions
TMP86PS23UG

Page 8

2. Operational Description

2.1 CPU Core Functions

The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit.

2.1.1 Memory Address Map

The TMP86PS23UG memory is composed OTP, RAM, DBR(Data buffer register) and SFR(Special func-

tion register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86PS23UG memory
address map.

0000

SFR

RAM

003F

0040

083F

H

64 bytes

H
H

2048

bytes

H

Special function register includes:

SFR:

I/O ports
Peripheral control registers
Peripheral status registers
System control registers
Program status word
Random access memory includes:

RAM:

Data memory
Stack

TMP86PS23UG

0F80

H

DBR

OTP

0FFF

1000

FFB0

FFBF
FFC0

FFDF

FFE0
FFFF

H
H

H

H
H

H
H

H

bytes

61440

bytes

Figure 2-1 Memory Address Map

2.1.2 Program Memory (OTP)

128

DBR: Data buffer register includes:

Peripheral control registers
Peripheral status registers
LCD display memory

OTP:

Program memory

Vector table for interrupts
(16 bytes)

Vector table for vector call instructions
(32 bytes)

Vector table for interrupts
(32 bytes)

The TMP86PS23UG has a 61440 bytes (Address 1000H to FFFFH) of program memory (OTP ).

2.1.3 Data Memory (RAM)

The TMP86PS23UG has 2048 bytes (Address 0040H to 083FH) of internal RAM. The first 192 bytes
(0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are
available against such an area.

Page 9

2. Operational Description

2.2 System Clock Controller

The data memory contents become unstable when the power supply is turned on; therefore, the data memory
should be initialized by an initialization routine.

Example :Clears RAM to “00H”. (TMP86PS23UG)

SRAMCLR: LD (HL), A

2.2 System Clock Controller

The system clock controller consists of a clock generator, a timing generator, and a standby controller.

TMP86PS23UG

LD HL, 0040H ; Start address setup
LD A, H ; Initial value (00H) setup
LD BC, 07FFH

INC HL
DEC BC
JRS F, SRAMCLR

XIN

High-frequency
clock oscillator

XOUT

XTIN

Low-frequency
clock oscillator

XTOUT

2.2.1 Clock Generator

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core
and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the
low-frequency clock. Power consumption can be reduced by switching of the standby co ntroller to l ow-power
operation based on the low-frequency clock.

Timing generator control register

Clock

generator

fc

TBTCR

0036

Timing

generator

fs

System clocks

Clock generator control

Figure 2-2 System Colck Control

H

Standby controller

0038

H

0039

H

SYSCR2SYSCR1

System control registers

The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator
between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also
possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.

Page 10

TMP86PS23UG

(a) Crystal/Ceramic

resonator

Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis-

abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse
which the fixed frequency is outputted to the port by the program.
The system to require the adjustment of the oscillation frequency should create the program for the adjust­ment in advance.

High-frequency clock

XOUTXIN

(b) External oscillator

Figure 2-3 Examples of Resonator Connection

XOUTXIN

(Open)

Low-frequency clock

XTIN

(c) Crystal (d) External oscillator

XTOUT

XTIN

XTOUT

(Open)

Page 11

2. Operational Description

2.2 System Clock Controller

2.2.2 Timing Generator

The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware
from the basic clock (fc or fs). The timing generator provides the following functions.

2.2.2.1 Configuration of timing generator

1. Generation of main system clock

2. Generation of divider output (

DVO) pulses

3. Generation of source clocks for time base timer

4. Generation of source clocks for watchdog timer

5. Generation of internal source clocks for timer/counters

6. Generation of warm-up clocks for releasing STOP mode

7. LCD

TMP86PS23UG

SYSCK
DV7CK

High-frequency

clock fc

Low-frequency

clock fs

The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator,

and machine cycle counters.

An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2<SYSCK> and
TBTCR<DV7CK>, that is shown in Figure 2-4. As reset and STOP mode started/canceled, the prescaler
and the divider are cleared to “0”.

fc or fs

S

fc/4

1 21 432 87 109 1211 1413 1615

5 6 17 18 19 20 21

A

Y

B

Multi-

plexer

Machine cycle countersMain system clock generator

Divider

B0
B1

A0
A1

S

Y0
Y1

Multiplexer

Warm-up
controller

Watchdog
timer

Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions)

Figure 2-4 Configuration of Timing Generator

Page 12

Timing Generator Control Registe r

TMP86PS23UG

TBTCR

(0036H)

Note 1: In single clock mode, do not set DV7CK to “1”.
Note 2: Do not set “1” on DV7CK while the low-frequency clock is not operated stably.
Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don’t care
Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after

76543210

(DVOEN) (DVOCK) DV7CK (TBTEN) (TBTCK) (Initial value: 0000 0000)

DV7CK

release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.

Selection of input to the 7th stage
of the divider

0: fc/2
1: fs

8

[Hz]

2.2.2.2 Machine cycle

Instruction execution and peripheral hardware operation are synchronized with the main system clock.

The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different
types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instru ctions which require one
machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A
machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.

1/fc or 1/fs [s]

R/W

Main system clock

State

Machine cycle

Figure 2-5 Machine Cycle

2.2.3 Operation Mode Control Circuit

The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low­frequency clocks, and switches the main system clock. There are three operating modes: Single clock mode,
dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and
SYSCR2). Figure 2-6 shows the operating mode transition diagram.

2.2.3.1 Single-clock mode

Only the oscillation circuit for the high-frequency clock is used, and P21 (X TIN) and P22 (XTOUT)
pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In
the single-clock mode, the machine cycle time is 4/fc [s].

S3S2S1S0 S3S2S1S0

(1) NORMAL1 mode

In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock.

The TMP86PS23UG is placed in this mode after reset.

Page 13

2. Operational Description

2.2 System Clock Controller
TMP86PS23UG

(2) IDLE1 mode

In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are

halted; however on-chip peripherals remain active (Operate using the high-frequency clock).

IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1
mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF
(Interrupt master enable flag) is “1” (Interrupt enable), the execution will resume with the acceptance
of the interrupt, and the operation will return to normal after the interrupt service is completed. When
the IMF is “0” (Interrupt disable), the execution will resume with the instruction which follows the
IDLE1 mode start instruction.

(3) IDLE0 mode

In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation.

This mode is enabled by SYSCR2<TGHALT> = "1".

When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.

When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back
again. IDLE0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF =
“1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro­cessing is performed. When IDLE0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to NORMAL1 mode.

2.2.3.2 Dual-clock mode

Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and
P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the
high-frequency clock in NORMAL2 and IDLE2 modes, and is o btained from the low -frequency clock in
SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and
4/fs [s] (122 µs at fs = 32.768 kHz) in the SLOW and SLEEP modes.

The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the low­frequency oscillator should be turned on at the start of a program.

(1) NORMAL2 mode

In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate

using the high-frequency clock and/or low-frequency clock.

(2) SLOW2 mode

In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency
clock and the low-frequency clock are operated. As the SYSCR2<SYSCK> becomes "1", the hard­ware changes into SLOW2 mode. As the SYSCR2<SYSCK> becomes “0”, the hardware changes
into NORMAL2 mode. As the SYSCR2<XEN> becomes “0”, the hardware changes into SLOW1
mode. Do not clear SYSCR2<XTEN> to “0” during SLOW2 mode.

(3) SLOW1 mode

This mode can be used to reduce power-consumption by turning off oscillation of the high-fre­quency clock. The CPU core and on-chip peripherals operate using the low-frequency clock.

Page 14

TMP86PS23UG

Switching back and forth between SLOW1 and SLOW2 modes are performed by
SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is
stopped; output from the 1st to 6th stages is also stopped.

(4) IDLE2 mode

In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are
halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or
the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode,
except that operation returns to NORMAL2 mode.

(5) SLEEP1 mode

In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU,
the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; how­ever, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releas­ing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW1 mode.
In SLOW1 and SLEEP1 modes, the input clock to the 1st stage of the divider is stopped; output from
the 1st to 6th stages is also stopped.

(6) SLEEP2 mode

The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the
SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high­frequency clock.

(7) SLEEP0 mode

In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode
is enabled by setting “1” on bit SYSCR2<TGHALT>.

When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the
peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected
with TBTCR<TBTCK>, the timing generator starts feeding the clock to all peripheral circuits.

When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back
again. SLEEP0 mode is entered and returned regardless of how TBTCR<TBTEN> is set. When IMF
= “1”, EF6 (TBT interrupt individual enable flag) = “1”, and TBTCR<TBTEN> = “1”, interrupt pro­cessing is performed. When SLEEP0 mode is entered while TBTCR<TBTEN> = “1”, the INTTBT
interrupt latch is set after returning to SLOW1 mode.

2.2.3.3 STOP mode

In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The

internal status immediately prior to the halt is held with a lowest power consumption during STOP mode.

STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a

inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the

STOP pin. After

the warm-up period is completed, the execution resumes with the instruction which follows the STOP
mode start instruction.

Page 15

2. Operational Description

2.2 System Clock Controller
TMP86PS23UG

IDLE1

mode

(a) Single-clock mode

IDLE2

mode

SLEEP2

mode

SLEEP1

mode

(b) Dual-clock mode

SYSCR2<TGHALT> = "1"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<XTEN> = "0"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<SYSCK> = "0"

SYSCR2<IDLE> = "1"

Interrupt

SYSCR2<XEN> = "1"

SYSCR2<IDLE> = "1"

Interrupt

Note 2

IDLE0

mode

NORMAL1

mode

NORMAL2

mode

SLOW2

mode

SLOW1

mode

Reset release

Note 2

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<XTEN> = "1"

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<SYSCK> = "1"

SYSCR2<XEN> = "0"

SYSCR1<STOP> = "1"

STOP pin input

SYSCR2<TGHALT> = "1"

RESET

STOP

SLEEP0

mode

Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1

and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.

Note 2: The mode is released by falling edge of TBTCR<TBTCK> setting.

Figure 2-6 Operating Mode Transition Diagram

Table 2-1 Operating Mode and Conditions

Operating Mode

Single clock

Dual clock

Oscillator

High

Frequency
RESET
NORMAL1 Operate
IDLE1

STOP Stop Halt –

NORMAL2

IDLE2 Halt

SLOW2

SLEEP2 Halt

SLOW1

SLEEP1

STOP Stop Halt –

Oscillation

Oscillation

Stop

Low

Frequency

Stop

Oscillation

CPU Core TBT

Reset Reset Reset

Operate

HaltIDLE0

Operate with

high frequency

Operate with

low frequency

Operate

Operate with

low frequency

HaltSLEEP0

Other

Peripherals

Operate

Halt

Operate

Halt

Machine Cycle

Time

4/fc [s]

4/fc [s]

4/fs [s]

Page 16

System Control Register 1

SYSCR176543210

(0038H) STOP RELM RETM OUTEN WUT (Initial value: 0000 00**)

TMP86PS23UG

STOP STOP mode start

RELM

RETM

OUTEN Port output during STOP mode

WUT

Release method for STOP
mode

Operating mode after STOP
mode

Warm-up time at releasing
STOP mode

0: CPU core and peripherals remain active
1: CPU core and peripherals are halted (Start STOP mode)

0: Edge-sensitive release
1: Level-sensitive release

0: Return to NORMAL1/2 mode
1: Return to SLOW1 mode

0: High impedance
1: Output kept

Return to NORMAL mode Return to SLOW mode

00
01
10

11

3 x 2

2

3 x 2

2

16

/fc

16

/fc

14

/fc

14

/fc

3 x 2

2

3 x 2

R/W

R/W

R/W

R/W

13

/fs

13

/fs

6

/fs

6

/fs

2

R/W

Note 1: Always set RETM to “0” when transiting from NORMAL mode to STOP mode. Always set RETM to “1” when transiting

from SLOW mode to STOP mode.

Note 2: When STOP mode is released with

RESET pin input, a return is made to NORMAL1 regardless of the RETM contents.

Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don’t care
Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed.
Note 5: As the hardware becomes STOP mode under OUTEN = “0”, input value is fixed to “0”; therefore it may cause external

interrupt request on account of falling edge.
Note 6: When the key-on wakeup is used, RELM should be set to "1".
Note 7: Port P20 is used as

STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes

High-Z mode.
Note 8: The warmig-up time should be set correctly for using oscillator.

System Control Register 2

SYSCR2

(0039H)

Note 1: A reset is applied if both XEN and XTEN are cleared to “0”, XEN is cleared to “0” when SYSCK = “0”, or XTEN is cleared

Note 2: *: Don’t care, TG: Timing generator, *; Don’t care
Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value.
Note 4: Do not set IDLE and TGHALT to “1” simultaneously.
Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period

Note 6: When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to “0”.
Note 7: When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to “0”.
Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals

76543210

XEN XTEN SYSCK IDLE

XEN High-frequency oscillat or control

XTEN Low-frequency oscillator control

Main system clock select

SYSCK

IDLE

TGHALT

(Write)/main system clock moni­tor (Read)

CPU and watchdog timer control
(IDLE1/2 and SLEEP1/2 modes)

TG control (IDLE0 and SLEEP0
modes)

TGHALT

0: Turn off oscillation
1: Turn on oscillation

0: Turn off oscillation
1: Turn on oscillation

0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2)
1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2)

0: CPU and watchdog timer remain active
1: CPU and watchdog timer are stopped (St art IDLE1/2 and SLEEP1/2 modes)

0: Feeding clock to all peripherals from TG
1: Stop feeding clock to peripherals except TBT from TG.
(Start IDLE0 and SLEEP0 modes)

(Initial value: 1000 *0**)

to “0” when SYSCK = “1”.

of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR<TBTCK>.

may be set after IDLE0 or SLEEP0 mode is released.

R/W

R/W

Page 17

2. Operational Description

2.2 System Clock Controller

2.2.4 Operating Mode Control

2.2.4.1 STOP mode

TMP86PS23UG

STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input
(STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR).
The

STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin . STOP mode is

started by setting SYSCR1<STOP> to “1”. During STOP mode, the following status is maintained.

1. Oscillations are turned off, and all internal operations are halted.

2. The data memory, registers, the program status word and port output latches are all held in the
status in effect before STOP mode was entered.

3. The prescaler and the divider of the timing generator are cleared to “0”.

4. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7])
which started STOP mode.

STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be
selected with the SYSCR1<RELM>. Do not use any key-on wakeup input (STOP5 to STOP2) for releas­ing STOP mode in edge-sensitive mode.

Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2).

However, because the STOP pin is different from the key-on wakeup and can not inhibit the release
input, the STOP pin must be used for releasing STOP mode.

Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external

interrupt pin signal, interrupt latches may be set to “1” and interrupts may be accepted immediately
after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before
enabling interrupts after STOP mode is released, clear unnecessary interrupt latches.

(1) Level-sensitive release mode (RELM = “1”)

In this mode, STOP mode is released by setting the

STOP pin high or setting the STOP5 to STOP2

pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main
power supply is cut off and long term battery backup.

Even if an instruction for starting STOP mode is executed while

to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immedi-

ately . Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to
first confirm that the
methods can be used for confirmation.

1. Testing a port.

2. Using an external interrupt input

Example 1 :Starting STOP mode from NORMAL mode by testing a port P20.

STOP pin input is low or STOP5 to STOP2 input is high. The following two

INT5 (INT5 is a falling edge-sensitive input).

STOP pin input is high or STOP5

LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode

SSTOPH: TEST (P2PRD). 0 ; Wait until the

JRS F, SSTOPH

DI ; IMF ← 0

SET (SYSCR1). 7 ; Starts STOP mode

Page 18

STOP pin input goes low level

Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt.

PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if

JRS F, SINT5 port P20 is at high

LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode.

DI ; IMF ← 0

SET (SYSCR1). 7 ; Starts STOP mode

SINT5: RETI

V

STOP pin

XOUT pin

IH

TMP86PS23UG

NORMAL

operation

Confirm by program that the
STOP pin input is low and start
STOP mode.

STOP

operation

Figure 2-7 Level-sensitive Release Mode

Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted.
Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release

mode is not switched until a rising edge of the

(2) Edge-sensitive release mode (RELM = “0”)

In this mode, STOP mode is released by a rising edge of the
cations where a relatively short program is executed repeatedly at periodic intervals. This periodic
signal (for example, a clock from a low-power consumption oscillator) is input to the
the edge-sensitive release mode, STOP mode is started even when the
Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode.

Example :Starting STOP mode from NORMAL mode

Warm up

STOP mode is released by the hardware.

Always released if the STOP
pin input is high.

STOP pin input is detected.

NORMAL
operation

STOP pin input. This is used in appli-

STOP pin input is high level.

STOP pin. In

STOP pin

XOUT pin

STOP mode started
by the program.

DI ; IMF ← 0

LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive release mode

V

IH

NORMAL
operation

STOP

operation

Warm up

STOP mode is released by the hardware at the rising
edge of STOP pin input.

NORMAL
operation

Figure 2-8 Edge-sensitive Release Mode

Page 19

STOP

operation