Toshiba TLP510E, TLP511E, TLP510U, TLP511U User Manual

FILE NO. 336-9707

TECHNICAL TRAINING MANUAL

3 LCD D ATA PROJECTOR

TLP511U
TLP510U

TLP511E
TLP510E

PRINTED IN JAPAN, Nov., 1997

S

CONTENTS

1. MAIN POWER SUPPLY

CIRCUIT .....................................1-1

1-1. Description .................................................1-1

1-2. Output Control ..........................................1-1

1-3. Voltage Switching ...................................... 1-1

1-4. Over-voltage Protection............................ 1-1

1-5. Over-current Protection ........................... 1-2

1-6. Overheat Protection ..................................1-2

2. LAMP POWER SUPPLY

CIRCUIT (LAMP DRIVER).....2-1

2-1. Configuration.............................................2-1

3. OPTICAL SYSTEM...................3 -1

3-1. Configuration.............................................3-1

4. R.G.B. DRIVE CIRCUIT...........4-1

4-1. Outline ........................................................ 4-1

4-2. Operation Description .............................. 4-3

5. MICROPROCESSOR................5-1

5-1. System Outline...........................................5-1

5-2. System Microprocessor.............................5-3

5-3. Power Supply Reset Process..................... 5-4

5-4. Non-volatile Memory Process ..................5-4

5-5. Remote Control Reception Process..........5-4

5-6. RS-232C T ransmission/

Reception Process...................................... 5-4

5-7. Status Read Process .................................. 5-4

5-8. Status Display Process ..............................5-5

5-9. On-screen Display Process........................ 5-5

5-10. Video System Control Process.................. 5-6

5-11. Panel System Control Process.................. 5-6

5-12. Drive System Control Process.................. 5-7

5-13. Various Display Modes .............................5-7

5-14. Applicable Signal.......................................5-8

5-15. RS-232C Control Method ......................... 5-9

6. DIGITAL CIRCUIT ...................6-1

6-1. Outline ........................................................ 6-1

6-2. Each IC Description ..................................6-3

7. VIDEO SIGNAL PROCESS

CIRCUIT .....................................7-1

7-1. Circuit Component.................................... 7-1

7-2. Input Signal Switch Section...................... 7-3

7-3. Video Demodulation Block....................... 7-5

7-4. RGB Signal Amplification Section.........7-12

7-5. Microprocessor Interface .......................7-14

8. CCD CAMERA CIRCUIT

(For TLP511)...............................8 -1

8-1. Outline ........................................................ 8-1

9. FLUORESCENT LAMP
INVERTER CIRCUIT

(For TLP511)...............................9 -1

9-1. Operation Description .............................. 9-1

9-2. Troubleshooting .........................................9-2

9-3. Circuit Diagram......................................... 9-3

i

1. MAIN POWER SUPPLY CIRCUIT

1-3. Voltage Switching

1-1. Description

This power supply boosts up at boost-up-converter just
after bridge-rectifying AC input voltage, supplies the
voltage smoothed to DC 350V to the lamp output. Then
current resonance DC-DC converter which uses the DC
350V as an input converts the voltage and supplies S6V,
+6V, +10V, +13V, +15.5V and –12V.

The boost-up-converter control IC, IC301, stabilizes AC
rectified voltage to DC 350V. The current resonance DC­DC converter, IC303, turns FET Q102 and Q103 “ON/
OFF” alternately using the drive transformer T103 and
converts the voltage to secondary side through the
converter transformer T101. At this time, the voltage of
S6V at the secondary side is detected by IC402, the
negative feedback to IC303 is carried out at photo
coupler PH301 and then the voltage is stabilized. Other
outputs are determined by the turn ratio of secondary
side of T101, and the voltage rectified, smoothed, but not
stabilized are stabilized through the series regulator.
(+10V is stabilized at IC203, +13V at IC202, +15.5V at
IC201.)

The voltage rectified and smoothed by D105 and C113 at
primary winding of T101 is supplied as a VCC voltage of
IC301, IC302 and IC303 on primary side ICs, and also
the voltage rectified and smoothed by D106 and C114 is
supplied as a gate bias voltage of D306 TRIAC (triode
AC switch) which short-circuits the inrush current
limiting resistor R305. Therefore, when the electric
current resonance DC-DC converter stops to oscillate, the
VCC voltage is not supplied so that the boost-up­converter stops to operate.

1-2. Output Control

When the voltage switching terminal of connector C
opens, pin 1 develops low, since the pin 2 of IC401 is 6V,
higher than pin 2 (3V), the voltage adjusted to 16.3V is
directly developed from IC201, since the status of Q205
turns off. When the voltage switching terminal develops
ground potential, since pin 2 of IC401 develops 0V and
the voltage of pin 2 develops low, pin 1 develops high,
Q205 turns on, voltage-set-up resistor of R201 is short­circuited and the voltage of IC201 rises from 16.3V to

18.0V.

1-4. Over-voltage Pr otection

When the negative feedback circuit of current resonance
DC-DC converter is shut down, the secondary side
voltage control is unable to operate, the voltage begins to
develop high without any restriction. At this time, when
the voltage of S6V and +6V exceeds 8.5V, the base of
transistor Q401 is biased through the zener diode D201,
and turns on, and then the voltage higher than 7V is
added to pin 6 (OVP) of IC303 through the photo coupler
PH302. When the voltage higher than 7V is added to pin
6, IC303 is latched, all outputs are shut down. ( Boost­up-converter stops simultaneously, too.)

When the voltage is added to +10V, +13V, +15.5V lines
from external side, (exceeding +15V for +10V line, 13V
for +13 line and 20V for +15.5V line), on each line
respectively through the zener diodes D202, D203 and
D204, the base voltage of Q401 is biased passing, IC303
is latched in the same way as the above-mentioned, all
outputs are shut down. When releasing the latch opera­tion, stop to supply the commercial power supply and
then re-supply the commercial power after more than
approx. 120 seconds.

When the output control 1 and 2 of connector A develops
low, the voltage of approx. 14V is added to Q203 gate
and pins 4 of IC203, IC201, and IC202 through R205
and R206 respectively, since the transistors Q201 and
Q202 turn off. In this case, Q204, IC201, IC202 and
IC203 turn off, the voltages of +6V, +10V, +15.5V and
+13V are not developed.

When the output control 1 and 2 develop high, the
transistors Q201 and Q202 turn on, so no voltage is
added to the gate Q203, IC201, IC202 and IC203,
described above, and the voltage of +6V, +10V, –15.5V
and +13V are developed.

1-1

1-5. Over-curr ent Protection

In S6V and +6V lines, the voltage drop owing to the
current flowing in L203 is detected by pins 5 and 6 of
IC401, when the total current amount exceeds 8A, pin 7
develops high and the voltage biasses the base voltage of
transistor Q401 passing through the zener diode D402
and diode D401. In the same way as described in the
item of the over-voltage protection, IC303 is latched and
all outputs are shutdown. The method to release the latch
operation is the same as the item of the over-voltage
protection.

Over-current protection at +10V, +13V, +15.5V lines are
carried out by the over-current protection characteristic
provided with the series regulator ICs (IC203, IC202 and
IC201). Refer to Fig. 1-5-1.

In this case, as only the line short-circuiting or overload­ing is protected, no effect appears on other outputs. The
protection is released by removing the over current
flowing condition.

When short-circuiting or overloading continues, the IC
overheats and the overheat protection circuit inside the
IC works to shut down the output voltage. In this case,
the overheat protection is released by unloading the
current and removing the overheat of IC.

100

80

60

40

20

Relative output voltage (%)

0

0 1.0 2.0 3.0 4.0

Output current Io (A)

Fig. 1-5-1

<Supplement>

The over-current protection for lamp output detects the
voltage drop of the current detection resistor R113 at
between pins 9 and 10 of IC302. When voltage switching
terminal of connector C opens (at 16.3V), the photo
coupler PH303 turns off since pin 1 of IC401 develops
low and the voltage of drop voltage at R113 is directly
compared at pin 10 of IC302. When the lamp output
current is from 0.7 to 0.9A, pin 8 develops high and the
voltage higher than 7V is added to pin 6 of IC303. Then
IC303 is latched and all outputs are shut down.

When the voltage switching terminal of connector C
develops the ground potential (at 18.0V), pin 1 of IC401
develops high, PH303 turns on and the voltage of drop
voltage at R113 and the voltage divided by R317 and
R327 are compared at pin 10 of IC302. When the lamp
output is from 1.05 to 1.35A, pin 8 of IC302 develops
high, IC303 is latched and all outputs are shut down. The
method to release the latch operation is the same as the
over-voltage protection description.

1-6. Overheat Protection

As an overheat protection of the power supply, the
temperature of switching FET Q301 of the boost-up­converter is detected. Positive characteristic thermistor
TH301 for temperature detection is attached on the heat
sink of Q301. When Q301 is overheated owing to the
overload and/or defect of cooling fan, etc., the resistor
value of TH301 increases abruptly, while the surface
temperature exceeds approx. 120°C. Then the transistor
Q302 turns on, the voltage higher than 7V is added to the
pin 6 (OVP) of IC303, IC303 is latched and all outputs
are shut down.

When releasing the latch operation, stop to supply the
commercial power by canceling, cool enough after more
than approx. 120 seconds, and then re-supply the
commercial power.

1-2

2. LAMP POWER SUPPLY CIRCUIT
(LAMP DRIVER)

2-1. Configuration

The lamp power supply cicrcuit receives a DC220 to
390V (primary side) from the system power supply and
provides a AC voltage (70 to 100VAC at ever turning on
the lamp) to turn on the lamp. Fig. 2-1-1 shows the block
diagram.

Lamp Driver

L1

Stabilizer Igniter

R1

C1

Power

input

C2

CsRs

CB3

EMC GND

(optional)

I122

1K

CB2-1

SCI

The DC voltage is supplied to CB1 from the main power
supply unit through an interlock switch. This voltage
becomes AC input x 2Ö2 (= 340V for AC120V input)
when the lamp is off. CB2 is a connector for the lamp on
control signal input (SCI) and lamp off control signal
output (FLAG). When +5V is applied to SCI (CB2-1) in
the standby on, I122 FET transistor turns on, the igniter
develops a high voltage pulse (5 to 25 kV), and the lamp
starts to light up.

Commu-

tator

Control

100nF

CB2-2

Common Flag

Fig. 2-1-1

The pulse normally continues to be developed until the
lamp turns on (for max. 3s.). But if the lamp does not
turn on, I121 does not turn on, the voltage of CB2-3
develops high. I121 turns on and develops low after the
lamp turned on, the igniter circuit stops the operation.
Then the AC70 to 100V is applied to the lamp.

I121

L1

L2

Lamp

Mains
isolated

2-1

3. OPTICAL SYSTEM

3-1. Configuration

Lamp
unit

Mirror
box
unit

Prism
unit

Projec­tion
lens

No.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Name

UHP lamp

Parabolic
reflector

UV IR filter

Multi-lenses
A, B

Polarization
light beam
splitter (PBS)

Phase
difference
plate

Condenser
lens

Dichroic
mirror

Full reflection
mirror

Field lens

Relay lens

Incident side
polarized
plate/Phase
difference
plate

Liquid crystal
panel

Cross prism

Projection
lens

Description

Light source of the optical system. AC lighting system 120W, arc length 1.3 mm.
As the arc length is shorter than the conventional metal halide lamp, the light source
operates as an ideal light point source and this improves the light convergence factor.
Also, the color temperature gets higher and this allows to reproduce more natural
white color.

Parabolic reflector converges light emitted from the UHP lamp forward in approximate
parallel light beams and illuminates the liquid crystal panel.

Optical filter to pass necessary visible rays and cut unnecessary ultraviolet rays and
infrared rays among light emitted from the UHP lamp.

Tw o multi-lenses A and B allow a circular beam light emitted from the light source to
illuminate the square liquid crystal panel evenly, thus providing projected pictures
with less brightness variation.

Separates the illuminating light from the light source into P polarization light and S
polarization light and leads both light to the multi-lens B with a little angle.

Converts the polarization direction of incident light via the multi-lens B into another
direction. Here, P polarization light waveform separated by PBS is converted into
another S polarization light waveform.

Converges the illuminating light emitted from the light source into the liquid crystal
panel.

Separates the white light emitted from the light source into RGB three primary colors.
The white light emitted from the light source reflects B light using a dichroic mirror 1
and the RG lights pass through the dichroic mirror 1. Of the RG lights passed, G light
is reflected by the dichroic mirror 2 and R light passes.

Reflection mirror to lead the R and B lights separated by the dichroic mirrors 1 and 2
to the liquid crystal panel.

Light transmitted through liquid crystal panel is converged in direction of focal point
and effectively entered entrance pupil of the projection lens.

In the R axis optical path which is longer than those of G, B, the relay lens works as
a correction lens to arrange the illumination distribution of the liquid crystal panel
surface with that of other liquid crystal panel.

The illumination lights separated into RGB have the S polarizing waveform compo­nent in processing the PBS and phase difference plate operation previously de­scribed.
The incident side polarized plate arranges the illumination light more effective direct
polarizing waveform. The phase difference plate used works to converge the S
polarizing waveform into the P polarizing waveform which fits to the transparent axis
of the liquid crystal panel.
Since the phase difference plate possesses the wavelength characteristics for light,
each RGB axis employs exclusive phase difference plate. These polarizing plates
and difference plates are constructed in one plate by attaching each other, and put
on a glass plate.
To increase the color pur ity ratio of three primar y colors, the glass plate possess the
dichroic filter characteristics for RG axis.

Light exit side polarized plate is put on the light exit plane. When no signal voltage is
applied, the polarization direction of transmission light rotates by 90 degrees. When a
voltage is applied, the polarization direction is controlled owing to the voltage
applied. That is, the liquid crystal panel employs such general TN type liquid crystal.
In this model, the incidence/exit polarization plate is placed (in normally white mode)
so that the light transmission amount becomes maximum (white) when no voltage is
added and the light transmission amount becomes minimum (black) when maximum
voltage is added.
According to the liquid crystal panel specification, exclusive panel for each RGB axis
is employed and shown by identification seals.

Works to mix RGB lights passed through the liquid crystal panel.
Demodulated by the video signal on the liquid crystal panel and projects pictures

displayed on the liquid crystal at a screen. Light axis of the projection lens is set at
upper side of center of the liquid crystal panel and this realizes easy viewing of the
panel because the projected screen position is upper than the unit position. The
projected light shows S polarizing waveform and is compatible with the polarizing
screen.
The projection lens employs the zoom & focus system and allows to project enlarging
a picture upto maximum approx. 300 inch.

3-1

15

XGA 1.3 inch 3 plates system

14

10

9

9

11

-2

13

-3

10

12

12

9

-1

13

13

10

8

8

-2

-1

7

6

1

UHP (120W)

2

3

4

A

5

4

B

Fig. 3-1-1 Optical configuration diagram

3-2

4. R.G.B. DRIVE CIRCUIT

1

1022 1023 1024

23

1st line

768 lines

768th line

1024 pixels

4-1. Outline

The outline of RGB drive circuit is described below
using the G process of the RGB drive circuit as an
example.

Odd number

pixel memory

Even number
pixel memory

Frame inverted

Digital PC board Drive PC board

SW2

SW1

1

DAC1 Amp.

2

1

DAC2

2

Q502

Q504

Amp.

Line inverted

Q505,Q506,Q507

Normal

amp.1

Q508,Q509,Q510

Inverted

amp.1

Q511,Q512,Q513

Normal

amp.2

Q523,Q524,Q510

Inverted

amp.2

1

2

1

2

Q514

SW3

Q514
SW4

Exclusive for odd number pixel

Q515

SW5

1

2

1

2

12-phase decomposite

Q516

&

Sample hold

1

Q515

SW6

even number pixel

&

Sample hold

2

Q517

Exclusive for

6-Phase decomposite

6-Phase decomposite

(12-phase collectively input)

Panel

VIDEO
input

12-phase composite

1
2
3
4
5
6
7
8

9
10
11
12

In the panel, 1024 pixels are arranged in a horizontal
direction and 768 lines of the pixels are in a vertical as
shown in Fig. 4-1-2.

As an H inverted drive system is employed, the panel
input signal waveform is as shown in Fig. 4-1-3.

Black level

White level

Center voltage

1st line

2nd line

White level

Black level

1st frame 2nd frame

Fig. 4-1-3

1st line

2nd line

Fig. 4-1-1

Fig. 4-1-2

4-1

The signal as shown in Fig. 4-1-1 is separated into the
odd and even pixels at the digital PC board. After the
signal process is carried out in the drive PC board, the
odd and even pixel signals are synthesized to
decomposite the signal on the panel.

Referring to Fig. 4-1-1, the operation principle is
described.

When assuming;

1) the signal passing through DAC1 ® Q502 ® Normal
amp. 1 ® SW31 ® SW5 ® Q516 to the positive
phase 1,

2) the signal passing through DAC1 ® Q502 ® inverted
amp. 1 ® SW32 ® SW5 ® Q516 to the inverted
phase 1,

<1st frame>

3) the signal passing through DAC2 ® Q504 ® Normal
amp. 1 ® SW41 ® SW6 ® Q517 to the positive
phase 2 and

4) the signal passing through DAC2 ® Q504 ® inverted
amp. 2 ® SW42 ® SW6 ® Q517 to inverted phase
2,

the AC and DC levels of the positive phases 1, 2 and the
inverted phases 1, 2 are expected to be the same.

However, each voltage will vary slightly owing to the
adjustment variation. In this case, each frame signal is
assumed as follows.

Center voltage

Normal phase 1
voltage
Normal phase 2
voltage

<2nd line>

Inverted phase 2
voltage

Inverted phase 1
voltage

Center voltage

Inverted phase
2 voltage

Inverted phase
1 voltage

12345 6 7 8 9 10 11 12 Pixel

1st line

1 2 3 4 5 6 7 8 9 10 11 12 Pixel

1st line

Normal phase 1
voltage
Normal phase 2
voltage

123

1 2 3 4 5 6 7 8 9 10 11 12 Pixel

456789101112 Pixel

2nd line

2nd line

As shown in Fig. 4-1-4, even if a slight level difference
occurs among the positive phases 1, 2 and inverted
phases 1, 2 signals (approx. 100 mV), the level differ­ence will be decreased visually by reducing the level

Fig. 4-1-4

variation of the same line between each frame and
inverting the pixel voltage of the adjacent lines (1st line
and 2nd line) between each frame.

4-2

4-2. Operation Description

The video signal of the odd number pixel (even number
pixel) is sent to Q501 (Q503) base and supplied to pin 16
of Q502 (Q504), LM1201M. The signal is clamped at
pin 16 and the pedestal voltage is adjusted at pin 6 after
the DC level is stabilized and then AC level is adjusted at
pin 3.

The signal is developed from pin 8, supplied to the buffer
circuits of Q505 – Q507 and Q511 – Q513, and supplied
to the inverted circuits of Q508, Q509, Q510, Q523,
Q525 and Q510. These signals are supplied to pins 5, 6,
8, 13, 15 and 16 of 12 phases development IC.
CXA2504N, Q516 and Q517 of sample-and-hold passing
through the SW circuit composed of Q514 and Q515.
The signals are developed from pins 37, 35, 33, 25 and
23 for each input.

The signals at pins 4, 7, 14 are used as bias input and the
bias inputs set the center DC voltage of output equal to
the bias voltage.

Q519 works to suppress the noise occurred at 12 phases
collective input process of the panel.

4-2-1. Outline of Liquid Crystal Panel

The liquid crystal panel module is an active matrix panel
with a built-in driver of multi-crystal silicon. The liquid
crystal panel module is designed for use of color projec­tors in combination with an enlargement projection
system and dichroic mirror.

<Basic specification>

(1) Screen size 26.624 (W) x 19.968 (H)
(2) Pixel number 1024 (W) x 768 (H)
(3) Applicable to XGA
(4) Monochrome panel
(5) Drive system H inverted drive
(6) Dot clock 65 MHz
(7) Inverted function for UP/DOWN/LEFT/RIGHT di-

rections

4-2-2. Basic Component

Pin No.

1
2
3
4
5
6
7
8
9

Name

DT
CLY
CLY

VDDY
NRS2
NRS1

LCCOM

VID11

VID9

Pin No.

10
11
12
13
14
15
16
17
18

Table 4-2-1 Terminal description

Name

VID7
VID5
VID3
VID1

VSSX

CLX
CLX

DX

VDDX

Pin No.

19
20
21
22
23
24
25
26
27

Name

DIRX

DIRX
ENB2
ENB1
VSSX

VID2
VID4
VID6
VID8

Pin No.

28
29
30
31
32
33
34
35
36

Name

VID10
VID12

LCCOM

N.C.

NRG

DY
DIRY
DIRY

VSSY

4-3

Table 4-2-2 Input terminal function description

Name

DX

CLX, CLX

DIRX, DIRX

ENB1 – ENB2

VID1 – VID12

DY

CLY , CLY

DIRY, DIRY

LCCOM

VDDX
VDD Y
VSSX
VSSY

NRG

NRS1 – NRS2

Function

Start pulse input ter minal of X shift register composing X driver.
Transfer clock input terminal X shift register composing X driver
X driver driving direction switch input terminal (DIRX = H R shift, DIRX = L L shift)
X driver enable pulse input terminal
X driver video signal input terminal
Start pulse input ter minal of Y shift register composing Y dr iver.
Transfer clock input terminal of Y shift register composing Y driver.
Transfer clock input terminal of Y shift register composing Y driver. (DIRX = H Down shift,

DIRX = L Up shift)
Diagonal electrode potential input terminal of liquid crystal panel
X driver positive power supply input terminal
Y driver positive power supply input terminal
X driver negative power supply input terminal
Y driver negative power supply input terminal
Drive signal input terminal for auxiliary signal circuit
Auxiliary signal input terminal

4-4

5. MICROPROCESSOR

5-1. System Outline

The system microprocessor has features as shown below.
In considering easy maintenance for specification

modification, etc., the program content is written in the
built-in non-volatile memory.

The program is also developed in considering use of
structured notation, parts modularity, and multi filling
system.

Major functions of the system microprocessor are as
follows.

5-1-1. System Control

• Microprocessor program write process

• Non-volatile memory control process

• Remote control reception process

• RS-232C transmission/reception process

• Status read process

• On-screen display process

5-1-3. Adjustment Control

• Video controls (high & low brightness ratio,
brightness, color density, tint, sharpness)

• Panel adjustments (V position, H position,
phase, clock, user registration, user read-out)

• Mode adjustments (Wide, MIC, OSD mute,
projection)

• Language adjustments (English, Japanese,
French, German, Spanish, Italian)

5-1-4. Adjustment Control at Factory Delivery

• Video sub adjustments (RGB gain, sub-bright)

• Drive adjustments (each item for panel controls,
RGB trimming)

Fig. 5-1-1 shows the system block diagram.

5-1-2. Normal Control

• Power ON/OFF
(Main/Fan/Lamp)

• Input switch (RGB/Video/Camera)

• Sound volume control UP/DOWN

• Menu

• Adjust (Up/Down/Left/Right)

• All mute ON/OFF

• Audio mute ON/OFF

• Display ON/OFF

• Freeze ON/OFF

• Resize ON/OFF

• Focus UP/DOWN
(at camera use)

• Zoom UP/DOWN
(at camera use)

5-1

PL004PL010

5-2

PL001

2

/

3

/

PL006 QL003

PQ20VZ1U

PL001

HC125

QL012

HC125

QL005PL003

HC14

QL004

RN5VD27A

19

2

/

2

/

5

/

DRIVE

SENSOR

PL009

/

/

/

2

2

10117978457

77

QL002

HD64F3337YF16

1

16 17 24232221

25 26 27 28 44

12

/

/

4

4342414039

/

3

2

/

55596063646566676869707172747576

54

496162

58
57

53
52
51

48

6

/

2

QL010

HC165

3

/

PL002

/

2

CAT24C16J

QL006

/

8

SW LED

Fig. 5-1-1 System block diagram

HC541

6

/

QL007

5-2. System Microprocessor

The system microprocessor QL002 employs an 8 bit
micro-controller (HD64F3337YF16).

In this system microprocessor, a program area is pro­vided inside the non-volatile memory.

Table 5-2-1 Terminal functions of the system microprocessor

Using an exclusive data-writer allows easy maintenance
of the system microprocessor when specification modifi­cation, bug correction, etc. will occur.

Table 5-2-1 shows the terminal functions of the system
microprocessor.

Pin No.

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Name

RES

XTAL

EXTAL

MD1
MD0

NMI
FVPF
VCC1

WDT
RXD0
TXD0
GND1

SDA

f

SEL
EEPCK
EEPDT

VD

REMOCON

AUX
KEY0
KEY1
KEY2
KEY3
KEY4
KEY5
KEY6
KEY7
AVCC

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7

AGND

LED0
LED1

Function

Reset input
Clock input for oscillation
Clock output for oscillation
Mode 1
Mode 2
Priority interruption
Memory write voltage
Digital power supply
Not used
RS-232C reception for camera
RS-232C transfer for camera
Digital ground
Not used
Oscillation clock
Remote controller selection
Non-volatile memory clock
Non-volatile memory data
Not used
Remote controller reception
Not used
Key input 0
Key input 1
Key input 2
Key input 3
Key input 4
Key input 5
Key input 6
Key input 7
Analog power supply
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Analog ground
LED data 0
LED data 1

I/O

O

O

O

I/O

O
O
O

I/O

O

O
O

Pin No.

I
I

I
I
I
I
I

I

I

I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

Name

LED2
LED3
LED4
LED5

MAIN. PW

FAN. PW

V

CC2

LAMP. PW

OSDL
DDCV
SENL
SENC
SEND
VD0C
VD0D
GND2
DRVC
DRVD
OSDC
OSDD

PLLU
SYGL
SYGC
SYGD

D0
D1
D2
D3
D4
D5
D6
D7

GND3

CLK
R/W
ENB
RST

TXD1
RXD1

SCL

Function

LED data 2
LED data 3
LED data 4
LED data 5
Main power supply swtich
Fan power supply switch
Digital power supply
Lamp power supply switch
OSD load
Not used
Sensor load
Used for sensor
Used for sensor
Video I2C clock
Video I2C data
Digital ground
Drive I2C clock
Drive I2C data
OSD clock
OSD data
PLL enable
SYG load
SYG clock
SYG data
T-FORC data 0
T-FORC data 1
T-FORC data 2
T-FORC data 3
T-FORC data 4
T-FORC data 5
T-FORC data 6
T-FORC data 7
Digital ground
T-FORC clock
T-FORC read/write
T-FORC enable
T-FORC reset
RS-232C transfer for control
RS-232C reception for control
Not used

I/O

O
O
O
O
O
O

I
O
O

I
O
O

I
O

I/O

I
O
O
O
O
O
O
O

I/O

O
O
O
O
O
O
O
O

I
O
O
O
O
O

I
O

5-3

5-3. Power Supply Reset Process

5-5. Remote Control Reception Process

In the power supply reset process, power supply reset IC
(RN5VD27A), QL004 is employed.

The reset IC,QL004, develops the reset signal when the
power supply voltage for the microprocessor varies and
becomes lower than the specified voltage, and sends the
signal to the reset terminal of the system microprocessor
(QL002).

5-4. Non-volatile Memory Control Process

In the non-volatile memory process, data reading and
saving for various adjustments are carried out on the
non-volatile memory, QL006 (CAT24C16J).

When the power (AC) is on, all the adjustment data are
read out by the system microprocessor (QL002), then the
previous status is realized.

When saving the data, all the adjustment data are written
by the system microprocessor (QL002), then the current
status is preserved.

However, if a failure (such as power interruption due to
lightning, etc.) occurs during the adjustment data writing,
a data error may occur. If the data is determined as
incorrect, the initial data memorized on the system
microprocessor (QL002) is read out and stored on the
non-volatile memory.

In the remote control reception process, a remote control
unit (CT-9925) connected to the remote control terminal
emits a remote control signal and a remote control signal
receive section on the front panel, the rear panel or the
camera arm (for TLP511) decodes the signal.

The remote control signals for rear panel and camera
section (for TLP511) are selected by QL012 buffer
(TC74HC125AF). Then both signals are mixed with the
remote control signal for front panel through QL005
buffer (74HC14AF).

Finally, the signal mixed is supplied to the remote control
terminal of the system microprocessor (QL002).

5-6. RS-232C Transmission/Reception

Process

In the RS-232C transmission/reception process, an RS­232C signal entered through the RS-232C connector (D­SUB 9P) is decoded in the RS-232C interface
(mPD4721), and fed to RXD1 terminal of the system
microprocessor (QL002).

In the RS-232C transmission process, RS-232C signal
developed from TXD0 terminal of the system micropro­cessor (QL002) is decoded in the RS-232C interface
(mPD4721) and fed to the camera microprocessor
section.

Signal name

Pin No.

QL010

(L)

(H)

A

11
FAN1. ER
Abnormal

Normal

5-7. Status Read Process

In the status read process, the following status shown in
the table below are read by QL010 (74HC165AF) and
the error process corresponding to each status is carried
out.

Table 5-7-1 shows the contents of the status read signals
and the logic.

Table 5-7-1 The contents of the status read signals and the logic

B

12

FAN1. SW

Normal

Abnormal

C

13
FAN2. ER
Abnormal

Normal

D

14

E
3

TEMP1. ER

Normal

Abnormal

F
4

G

5
LAMP. ER
Abnormal

Normal

H

6
MAIN. ER
Abnormal

Normal

5-4