Toshiba TLCS-900, TMP92CM22FG User Manual

TOSHIBA Original CMOS 32-Bit Microcontroller

TLCS-900/H1 Series

TMP92CM22FG

Semiconductor Company

Preface

Thank you very much for making use of Toshiba microcomputer LSIs.

Before use this LSI, refer the section, “Points of Note and Restrictions”.

CMOS 32-Bit Microcontrollers

TMP92CM22FG

1. Outline and Device Characteristics

TMP92CM22 is high-speed advanced 32-bit microcontroller developed for controlling equipment,

which processes mass data.

TMP92CM22FG is a microcontroller, which has a high-performance CPU (900/H1 CPU) and

various built-in I/Os. TMP92CM22F is housed in a 100-pin flat package.

Device characteristics are as follows:

(1) CPU: 32-bit CPU (900/H1 CPU)

• Compatible with TLCS-900, 900/L, 900/L1, 900/H, and 900/H2’s instruction code

• 16 Mbytes of linear address space

• General-purpose register and register banks

TMP92CM22

• Micro DMA: 8 channels (250 ns/4 bytes at f

(2) Minimum instruction execution time: 50 ns (at f

= 20 MHz, best case)

SYS

= 20 MHz)

SYS

(3) Internal memory

• Internal RAM: 32 Kbytes (32-bit 1-clock access, programmable)

• Internal ROM: None

RESTRICTIONS ON PRODUCT USE

• The information contained herein is subject to change without notice. 021023_D

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity an d vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failur e of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk.

021023_A

021023_B

070208EBP

• The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties.

021023_C

• The products described in this document are subject to foreign exchange and foreign trade control laws.

• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter

entitled Quality and Reliability Assurance/Handling Precautions. 030619_S

92CM22-1

060925_E

2007-02-16

TMP92CM22

(4) External memory expansion

• Expandable up to 16 Mbytes (Shared program/data area)

• Can simultaneously support 8-/16-bit width external data bus

･･･Dynamic data bus sizing

• Separate bus system

(5) Memory controller

• Chip select output: 4 channels

(6) 8-bit timers: 4 channels

(7) 16-bit timers: 2 channels

(8) General-purpose serial interface: 2 channels

• UART/synchronous mode

• IrDA

(9) Serial bus interface: 1 channel

C bus mode

• I

• Clock synchronous mode

(10) 10-bit AD converter: 8 channels

(11) Watchdog timer

(12) Interrupts: 41 interrupts

• 9 CPU interrupts: Software interrupt instruction and illegal instruction

• 25 internal interrupts: Seven selectable priority levels

• 7 external interrupts: Seven selectable priority levels (INT0 to INT5 and

NMI )

(INT0 to INT3 selectable edge or level interrupt)

(13) Input/output ports: 50 pins (exclude Data bus 8-bit, Address bus 24-bit and

RD pin)

(14) Standby function

• Three HALT modes: IDLE2 (Programmable), IDLE1, STOP

(15) Dual-clock controller

• PLL: fc = f

× 4 (fc = 40 MHz at f

OSCH

= 10 MHz)

• Clock gear function: Select a high-frequency clock fc to fc/16

(16) Operating voltage

• DVCC = 3.0 V to 3.6 V (fc max = 40 MHz)

(17) Package

• 100-pin QFP: P-LQFP100-1414-0.50F

92CM22-2

2007-02-16

(

PG0 to PG7

(AN0 to AN7)

ADTRG )

PG3 (

AVCC

AVSS

VREFH

VREFL

PF0 (TXD0)

PF1 (RXD0)

PF2 (SCLK0/ CTS0 )

PF3 (TXD1)

PF4 (RXD1)

PF5 (SCLK1/ CTS1 )

PF6 to PF7

P90

SCK)

P91 (SO/SDA)

P92 (SI/SCL)

PC0 (TA0IN)

PC1 (TA1OUT/INT1)

PC5 (TA3OUT/INT2)

PC6 (TB00UT0/INT3)

PD0 (TB1IN0/INT4) PD1 (TB1IN1/INT5)

PD2 (TB1OUT0) PD3 (TB1OUT1)

10-bit 8-ch

converter

Serial I/O

SIO0

Serial I/O

SIO1

Port F

Serial

bus I/F

SBI0

8-bit timer

(Timer A0)

8-bit timer

(Timer A1)

8-bit timer

(Timer A2)

8-bit timer

(Timer A3)

16-bit timer

(Timer B0)

16-bit timer

(Timer B1)

XWA

XBC XDE XHL

XIX XI XIZ

XSP

TMP92CM22

DVCC [3]

900/H1 CPU

PLL

AW CB ED LH

32 bits

P C

Watchdog timer

32-Kbyte RAM

H-OSC

Clock gear

Mode

controller

Interrupt

controller

Data bus

Port 1

Port 4

Port 5

Port 6

Port 7

Port 8

Port A

DVSS [4]

X1 X2

RESET

AM0 AM1

NMI

PC3(INT0)

D0 to D7 P10 to P17

(D8 to D15) P40 to P47

(A0 to A7) P50 to P57

(A8 to A15) P60 to P67

(A16 to A23)

P70 (

RD ) WRLL )

P71 ( P72 (

WRLU )

P73 P74 (CLKOUT) P75 (R/ W ) P76 ( WAIT )

P80 ( CS0 ) P81 ( CS1 )

CS2 )

P82 ( P83 ( CS3 )

PA0 to PA2 PA7

Figure 1.1 TMP92CM22 Block Diagram

92CM22-3

2007-02-16

2. Pin Assignment and Functions

The assignment of input/output pins for the TMP92CM22FG, their names and functions are as

follows.

2.1 Pin Assignment

Figure 2.1.1 shows the pin assignment of the TMP92CM22FG.

TMP92CM22

VREFL

VREFH PG0/AN0 PG1/AN1 PG2/AN2

PG3/AN3/

PC1/TA1OUT/INT1 PC5/TA3OUT/INT2

PC6/TB0OUT0/INT3

PF2/SCLK0/

PF5/SCLK1/

ADTRG

PG4/AN4 PG5/AN5 PG6/AN6 PG7/AN7

PA7

PC0/TA0IN

PF0/TXD0

PF1/RXD0

CTS0

PF3/TXD1

PF4/RXD1

CTS1

PF6 PF7

NMI

DVCC1

VCC AVSS

100

PA2

PA1

PA0

PD3/TB1OUT1

PD2/TB1OUT0

PD1/TB1IN1/INT5

PD0/TB1IN0/INT4

CS3

P90/SCK

P92/SI/SCL

P83/

P91/SO/SD

TMP92CM22

QFP100

Top view

CS2

P82/

CS1

P81/

DVSS4

CS0

P80/

WAIT

P76/

P74/CLKOUT

P75/R/

P73

WRLU

P72/

WRLL

P71/

P70/

P67/A23

P66/A22 P65/A21 P64/A20 DVCC3 P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/A7 P46/A6 P45/A5 P44/A4 P43/A3 P42/A2 P41/A1 P40/A0 DVSS3

DVSS1

AM1

AM0

RESET

PC3/INT0

D0D1D2D3D4D5D6

DVSS2

DVCC2

P10/D8

P11/D9

P12/D10

P13/D11

P14/D12

P15/D13

P16/D14

P17/D15

Figure 2.1.1 Pin Assignment Diagram (100-Pin QFP)

92CM22-4

2007-02-16

2.2 Pin Names and Functions

The following tables show the names and functions of the input/output pins.

Table 2.2.1 Pin Names and Functions (1/2)

TMP92CM22

Pin Names

D0 to D7 8 I/O Data (Lower): Data bus D0 to D7. P10 to P17

D8 to D15 P40 to P47 A0 to A7 P50 to P57 A8 to A15 P60 to P67 A16 to A23 P70

P71

WRLL

P72

WRLU

P73 1 Output Port 73: Output port. P74 CLKOUT P75

R/ P76

WAIT

P80

CS0

P81

CS1

P82

CS2

P83

CS3

P90 SCK P91 SO SDA

P92 SI SCL

PA0 to PA2, PA7

Number

of Pins

4 Input Port A0 to A2, A7: Input port (with pull-up resistor).

I/O Functions

I/O

I/O I/O

Output

I/O

Output

I/O Output Output Output Output Output Output Output

Output Output Output Output

I/O

Input Output Output Output Output Output Output Output Output

I/O I/O I/O

Output

I/O

Input

I/O

Port 1: I/O port that allows I/O to be selected at the bit level. (when used to the external 8-bit bus.) Data: Data bus D8 to D15. Port 4: I/O port. Address: Address bus A0 to A7. Port 5: I/O port. Address: Address bus A8 to A15. Port 6: I/O port. Address: Address bus A16 to A23. Port 70: Output port. Read: Strobe signal for reading external memory. Port 71: Output port. Write: Strobe signal for writing data to pins D0 to D7. Port 72: Output port. Write: Strobe signal for writing data to pins D8 to D15.

Port 74: Output port. Clock: Output system clock. Port 75: Output port. Read/write: This port is 1 when read and dummy cycle. This port is 0 when write cycle. Port 76: I/O port. Wait: Pin used to request bus wait to CPU. Port 80: Output port. Chip select 0: Outputs 0 when address is within specified address area. Port 81: Output port. Chip select 1: Outputs 0 when address is within specified address area. Port 82: Output port. Chip select 2: Outputs 0 when address is within specified address area. Port 83: Output port. Chip select 3: Outputs 0 when address is within specified address area. Port 90: I/O port. Serial bus interface clock I/O data at SIO mode. Port 91: I/O port. Serial bus interface send data at SIO mode. Serial bus interface send/receive data at I

(Open-drain output mode by programmable.) Port 92: I/O port. Serial bus interface receive data at SIO mode. Serial bus interface clock I/O data at I (Open-drain output mode by programmable.)

C mode.

92CM22-5

2007-02-16

TMP92CM22

Table 2.2.2 Pin Names and Functions (2/2)

Pin Names

Number

I/O Functions

of Pins

PC0 TA0IN PC1 INT1 TA1OUT PC3 INT0 PC5 INT2 TA3OUT PC6 INT3 TB0OUT0 PD0 INT4 TB1IN0 PD1 INT5 TB1IN1 PD2 TB1OUT0 PD3 TB1OUT1 PF0 TXD0 PF1 RXD0 PF2 SCLK0

0CTS

PF3 TXD1 PF4 RXD1 PF5 SCLK1

1CTS

PF6 to PF7 2 I/O Port F6 to F7: I/O port. PG0 to PG7 AN0 to AN7

ADTRG NMI 1 Input Non-Maskable interrupt request pin.

AM0, AM1 2 Input

X1/X2 2 I/O High-frequency oscillator connection pin.

RESET 1 Input Reset: Initialize TMP92CM22 (Schmitt input, with pull-up resistor).

VREFH 1 Input Pin for reference voltage input to AD converter (H). VREFL 1 Input Pin for reference voltage input to AD converter (L). AVCC 1 Power supply pin for AD converter. AVSS 1 GND pin for AD converter (0 V). DVCC 3 Power supply pins (All Vcc pins should be connected with the power supply pin). DVSS 4 − GND pins (0 V) (All DVSS pins should be connected with GND (0 V)).

I/O

Input

I/O

Input

Output

I/O

Input

I/O

Input

Output

I/O

Input

Output

I/O Input Input

I/O

Output

I/O

Output

I/O

Output

I/O Input

I/O

I/O Input

I/O

Output

I/O Input

I/O

I/O Input

Input Input Input

Port C0: I/O port. Timer input: 8-bit timer A0 input.

Port C1: I/O port. Interrupt request pin 1: Interrupt request pin with programmable level/rising edge/falling edge.

Timer output: 8-bit timer A0 or timer A1 output. Port C3: I/O port.

Interrupt request pin 0: Interrupt request pin with programmable level/rising edge/falling edge. Port C5: I/O port. Interrupt request pin 2: Interrupt request pin with programmable level/rising edge/falling edge. Timer output: 8-bit timer A2 or timer A3 output. Port C6: I/O port. Interrupt request pin 3: Interrupt request pin with programmable level/rising edge/falling edge. Timer output: 16-bit timer B0 output. Port D0: I/O port. Interrupt request pin 4: Interrupt request pin with programmable rising edge/falling edge. Timer input: 16-bit timer B1 input 0. Port D1: I/O port. Interrupt request pin 5: Interrupt request pin with programmable rising edge/falling edge. Timer input: 16-bit timer B1 input 1. Port D2: I/O port. Timer output: 16-bit timer B1 output 0. Port D3: I/O port. Timer output: 16-bit timer B1 output 1. Port F0: I/O port. Serial send data 0: (Open-drain output mode by programmable.) Port F1: I/O port. Serial receive data 0. Port F2: I/O port. Serial 0 clock I/O. Serial data send enable 0 (Clear to send). Port F3: I/O port. Serial send data 1: (Open-drain output mode by programmable.) Port F4: I/O port. Serial receive data 1. Port F5: I/O port. Serial 1 clock I/O. Serial data send enable 1 (Clear to send).

Port G0 to G7: Input port. Analog input 0 to 7: Pin used to input to AD converter. AD trigger: Pin used to request AD converter start (Share with PG3).

Operation mode: Fixed to AM1 = “0”, AM0 = “1”: External 16-bit bus start, 8-/16-bit dynamic sizing. Fixed to AM1 = “1”, AM0 = “0”: External 8-bit bus start, 8-/16-bit dynamic sizing.

92CM22-6

2007-02-16

TMP92CM22

3. Operation

This section describes the basic components, functions and operation of the TMP92CM22.

3.1 CPU

The TMP92CM22 incorporates a high-performance 32-bit CPU (The TLCS-900/H1 CPU). For a description of this CPU’s operation, please refer to the section of this data book which describes the TLCS-900/H1 CPU.

The following sub-sections describe functions peculiar to the CPU used in the TMP92CM22; these functions are not covered in the section devoted to the TLCS-900/H1 CPU.

3.1.1 Outline

“TLCS-900/H1 CPU” is high-speed and high-performance CPU based on “TLCS-900/L1 CPU”. “TLCS-900/H1 CPU” has expanded 32-bit internal and external

data bus to process instructions more quickly.

Outline of “TLCS-900/H1” CPU are as follows:

Table 3.1.1 Outline of CPU

Width of CPU address bus 24 bits Width of CPU data bus 32 bits Internal operating frequency 20 MHz Minimum bus cycle 1-clock access

(50 ns at 20 MHz) Function of data bus sizing 8 bits Internal RAM 32 bits

1-clock access Internal I/O 8-/16-bit 2-clock access 900/H1 I/O 8-/16-bit 5-to 6-clock access 900/H1 I/O External device 8 bits

2-clock access (can insert some waits) Minimum instruction execution cycle 1 clock (50 ns at 20 MHz) Conditional jump 2 clocks (100 ns at 20 MHz) Instruction queue buffer 12 bytes Instruction set Compatible with TLCS-900, 900/L, 900/H, 900/L1, and 900/H2

CPU mode Only maximum mode Micro DMA 8 channels

instruction codes (However, NORMAL, MAX, MIN, and LDX

instructions is deleted)

92CM22-7

2007-02-16

3.1.2 Reset Operation

When resetting the TMP92CM22 microcontroller, ensure that the power supply voltage

is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low for at least 20 system clocks (16 μs at fc = 40 MHz).

When the reset has been accepted, the CPU performs the following:

• Sets the program counter (PC) as follows in accordance with the reset vector stored

at address FFFF00H to FFFF02H:

• Sets the stack pointer (XSP) to 00000000H.

• Sets bits <IFF0:2> of the status register (SR) to 111 (Thereby setting the interrupt

level mask register to level 7).

• Clears bits <RFP0:1> of the status register to 00 (Thereby selecting register bank

0).

When the reset is released, the CPU starts executing instructions according to the program counter settings. CPU internal registers not mentioned above do not change when the reset is released.

When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.

• Initializes the internal I/O registers as “Table of Special Function Registers

(SFRs)” in Section 5.

• Sets the input or output port to general-purpose input port.

Internal reset is released as soon as external reset is released and RESET input pin is set to “H”.

The operation of memory controller cannot be insured until power supply becomes stable after power-on reset. The external RAM data provided before turning on the TMP92CM22 may be spoiled because the control signals are unstable until power supply becomes stable after power on reset.

Figure 3.1.1 shows the timing of a reset for the TMP92CM22.

TMP92CM22

PC<7:0> ← Data in location FFFF00H PC<15:8> ← Data in location FFFF01H PC<23:16> ← Data in location FFFF02H

92CM22-8

2007-02-16

TMP92CM22

3.3 V

RESET

operation time + 20 system clocks

Oscillator

0[s] (Min)

Figure 3.1.1 Reset Timing Example

3.1.3 Outline of Operation Mode

Set AM1 and AM0 pins to “10” to use 8-bit external bus, or set it to “01” to use 16-bit external bus.

Table 3.1.2 Operation Mode Setup Table

Operation

16-bit external bus start

8-/16-bit dynamic bus sizing

8-bit external bus start

8-/16-bit dynamic bus sizing

Mode Setting Input Pin

RESET AM1 AM0

0 1

1 0

92CM22-9

2007-02-16

3.2 Memory Map

Figure 3.2.1 shows memory map of TMP92CM22.

TMP92CM22

000000H

000100H

001FE0H

002000H

00A000H

010000H

F00000H

F10000H

FFFF00H FFFFFFH

Internal I/O

(8 Kbytes)

Internal RAM

(32 Kbytes)

External memory

Provisinal emulator

External memory

Vector table (256 bytes)

control area

(64 Kbytes)

Direct area(n)

(

64-Kbyte area

(nn)

16-Mbyte area (R) ( − R) (R + ) (R + R8/16) (R + d8/16)

Internal area)

(nnn)

Figure 3.2.1 Memory Map

Note 1: Whe n use em ulator, optional 64 Kbytes of 16-Mbyte a rea are used to control emulator.

Therefore, don’t use this area. Note 2: Don’t use the last 16-byte area (FFFFF0H to FFFFFFH). This area is reserved. Note 3: On emulator

WRLL signal, WRLU signal and RD signal are asserted, when provisional

emulator control area is accessed.

Be careful to use extend memory.

92CM22-10

2007-02-16

3.3 Clock Function and Standby Function

TMP92CM22 contains (1) Clock gear, (2) Standby controller and (3) Noise-reducing circuit. It

is used for low-power, low-noise systems.

This chapter is organized as follows:

3.3.1 Block Diagram of System Clock

3.3.2 SFRs

3.3.3 System Clock Controller

3.3.4 Clock Doubler (PLL)

3.3.5 Noise Reduction Circuits

3.3.6 Standby Controller

TMP92CM22

92CM22-11

2007-02-16

(

)

TMP92CM22

The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1, X2 pins and PLL). Figure 3.3.1 shows a transition figure.

IDLE2 mode

(I/O operation)

IDLE1 mode

(Operate only oscillator)

IDLE2 mode

I/O operation

IDLE1 mode

(Operate only oscillator)

IDLE2 mode

(I/O operation)

IDLE1 mode

(Operate

oscillator and PLL )

Instruction

Interrupt

Instruction Interrupt

(a) Single clock mode transition figure

Instruction Interrupt

Instruction

Interrupt

Instruction Interrupt

(b) Dual clock mode transition figure

Reset

OSCH

NORMAL mode

/gear value/2)

OSCH

Reset

OSCH

Release reset

NORMAL mode

/gear value/2)

OSCH

NORMAL mode

(4 × f

/gear value/2)

OSCH

(Using PLL)

/32)

Release reset

/32)

Instruction

Interrupt

Instruction

Interrupt

STOP mode

(Stop all circuit )

STOP mode

(Stop all circuit )

Figure 3.3.1 System Clock Block Diagram

The clock frequency input from the X1 and X2 pins is called f SYSCR1<GEAR2:0> is called the clock f one cycle of f

is defined to as one state.

SYS

. The system clock f

FPH

and the clock frequency selected by

OSCH

is defined as the divided 2 clocks of f

SYS

FPH

, and

92CM22-12

2007-02-16

3.3.1 Block Diagram of System Clock

TMP92CM22

SYSCR2<WUPTM1:0> PLLCR<PLUPFG>

Warm-up timer (for high-frequency

oscillator)/lockup (for PLL) timer

÷2

÷8

φT φT0

SYS

X1 X2

High-

frequency

oscillator

= f

PLL

PLLCR<PLLON>

PLL

(Clock doubler)

OSCH

PLLCR<FCSEL>

fc/2

fc/4

Clock gear

fc/8

fc/16

SYSCR1<GEAR2:0>

÷16÷8÷4÷2

FPH

÷2

÷4

SYS

φT0

φT

TMRA0 to TMRA3 and TMRB0 to TMRB1

Prescaler

SIO0 and SIO1

Prescaler

SBI

Prescaler

CPU

RAM

Interrupt

controller

ADC

I/O port

WDT

Figure 3.3.2 Block Diagram of Dual Clock and System Clock

92CM22-13

2007-02-16

3.3.2 SFRs

SYSCR0

(10E0H)

SYSCR1

(10E1H)

SYSCR2

(10E2H)

Bit symbol − − Read/Write R/W R/W After reset 1 0 Function Always

Bit symbol − GEAR2 GEAR1 GEAR0 Read/Write R/W After reset 0 1 0 0 Function Always

Bit symbol − WUPTM1 WUPTM0 HALTM1 HALTM0 SELDRV DRVE Read/Write R/W R/W After reset 0 1 0 1 1 0 0 Function Always

TMP92CM22

7 6 5 4 3 2 1 0

write “1”.

write “0”.

Always

write “0”.

Select WUP time for

oscillator 00: Reserved

/Input frequency

01: 2

/Input frequency

10: 2

/Input frequency

11: 2

Select HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode

write “0”.

Select gear value of highfrequency oscillator

000: High-frequency oscillator 001: High-frequency oscillator/2 010: High-frequency oscillator/4 011: High-frequency oscillator/8 100: High-frequency oscillator/16 101: 110: Reserved 111:

<DRVE> Select

using mode

0: STOP 1: IDLE1

1: Pin state control in STOP/

IDLE1 mode

Note: The unassigned register, S YSCR0<bit6:3>, SYSCR0<bit1:0>, SYSCR1<bit7:4>, and SYSCR2<bit6> are

RD as undefined value.

Figure 3.3.3 SFR for System Clock

92CM22-14

2007-02-16

PLLCR

(10E8H)

EMCCR0

(10E3H)

EMCCR1

(10E4H)

EMCCR2

(10E5H)

TMP92CM22

7 6 5 4 3 2 1 0

Bit symbol PLLON FCSEL LWUPFG Read/Write R/W R After reset 0 0 0 Function 0: PLL

stop 1: PLL run

Note: Logic of PLLCR<LWUPFG> is different DFM of 900/L1.

0: fc = OSCH 1: fc = PLL (× 4)

PLL warm-up

flag 0: Don’t

end up or stop

1: End up

Figure 3.3.4 SFR for PLL

7 6 5 4 3 2 1 0

Bit symbol PROTECT EXTIN DRVOSCH − Read/Write R R/W After reset 0 0 1 1 Function Protect

0: OFF 1: ON

Bit symbol Read/Write After reset Function Bit symbol Read/Write After reset Function

Note: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set

EMCCR0<DRVOSCH>, <DRVOSCL>= “1”.

Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY

1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write

1: fc external clock

fc oscillator driver ability 1: Normal 0: Weak

Always write “1”.

Figure 3.3.5 SFR for Noise

92CM22-15

2007-02-16

3.3.3 System Clock Controller

TMP92CM22

The system clock controller generates the system clock signal (f

) for the CPU core and

SYS

internal I/O. It is used as input that fc outputted from high-frequency oscillation circuit and PLL (Clock doubler) SYSCR1<GEAR2:0>, SYSCR1<GEAR2:0> sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4, fc/8, or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed.

Single clock mode is set by resetting, initialized to <GEAR2:0> = “100”. This setting will

cause the system clock (f

For example, f

is set to 1.25 MHz when the 40MHz oscillator is connected to the X1

SYS

) to be set to fc/32 (fc/16×1/2).

SYS

and X2 pins.

(1) Clock gear controller

is set according to the contents of the clock gear select register

FPH

SYSCR1<GEAR2:0> to either fc, fc/2, fc/4, fc/8, or fc/16. Using the clock gear to select a lower value of f

reduces power consumption.

FPH

Example: Changing to a high-frequency gear SYSCR1 EQU 10E1H LD (SYSCR1), XXXX0100B ; Changes system clock f X: Don’t care

SYS

to fc/32.

(High-speed clock gear changing)

To change the clock gear, write the register value to the SYSCR1<GEAR2:0> register. It is necessary the warm-up time until changing after writing the register value.

There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing. To execute the instruction next to the clock gear switching instruction by the clock gear after changing, input the dummy instruction as follows (Instruction to execute the write cycle).

Example: SYSCR1 EQU 10E1H LD (SYSCR1), XXXX0001B ; Changes f LD (DUMMY), 00H ; Dummy instruction.

Instruction to be executed

after clock gear has changed.

SYS

to fc/4.

92CM22-16

2007-02-16

3.3.4 Clock Doubler (PLL)

TMP92CM22

<PLLON>

PLL outputs the f

clock signal, which is four times as fast as f

PLL

. A reset initializes

OSCH

PLL to stop status, setting to PLLCR register is needed before use.

Like an oscillator, this circuit requires time to stabilize. This is called the lockup time.

Note 1: Input frequency limitation for PLL

The limitation of input frequency (High-frequency oscillation) for PLL is the following. f

= 4 to 10 MHz (Vcc = 3.0 V to 3.6 V)

OSCH

Note 2: PLLCR<LWUPFG>

The logic of PLLCR<LUPFG> is different from 900/L1’s DFM. Be careful to judge an end of lockup time.

The following is a setting example for PLL starting and PLL stopping.

Example 1: PLL starting PLLCR EQU 10E8H

LD (PLLCR), 10XXXXXXXB ; Enables PLL operation and starts lockup. LUP: BIT 5, (PLLCR) ; JR Z, LUP ; LD (PLLCR), 11XXXXXXB ; Changes fc from 10 MHz to 40 MHz. X: Don’t care

Detects end of lockup.

<FCSEL>

PLL output: f

Lockup timer

<LWUPFG> System clock f

PLL

SYS

Count-up by f

During lockup

Starts PLL operation and starts lockup.

OSCH

After lockup

Changes from 10 MHz to 40 MHz.

Ends of lockup

92CM22-17

2007-02-16

<FCSEL>

<PLLON>

PLL output: f System clock f

Example 2: PLL stopping

PLLCR EQU 10E8H LD (PLLCR), 10XXXXXXB ; Changes fc from 40 MHz to10 MHz. LD (PLLCR), 00XXXXXXB ; Stop PLL. X: Don’t care

PLL

SYS

Changes from 40 MHz to 10 MHz.

Stops PLL operation.

TMP92CM22

Limitation point on the use of PLL

1. When PLL is started, don’t set fc from f

Don’t setting:

LD (PLLCR), 00H LD (PLLCR), C0H

2. When PLL is started, don’t set fc from f

Don’t setting:

LD (PLLCR), C0H LD (PLLCR), 00H

OSCH

to f

at same time.

PLL

at same time.

PLL

92CM22-18

2007-02-16

3.3.5 Noise Reduction Circuits

Noise reduction circuits are built in for reduction EMI (Unnecessary radius noise) and reinforcement EMS (Measure of endure noise), allowing implementation of the following features.

(1) Reduced drivability for high-frequency oscillator

(2) Single drive for high-frequency oscillator

(3) SFR protection of register contents

These functions need setting by EMCCR0 to EMCCR2.

(1) Reduced drivability for high-frequency oscillator

(Purpose)

Reduces noise and power for oscillator when connect oscillator to outside.

(Block diagram)

Oscillator

(Setting method)

X1 pin

X2 pin

OSCH

Oscillation enable ( EMCCR0<DRVOSCH>

TMP92CM22

)

><+ EXTINEMCCR0STOP

The drivability of the oscillator is reduced by writing “0” to EMCCR0<DRVOSCH> register. By reset, <DRVOSCH> is initialized to “1” and the oscillator starts oscillation by normal drivability when the power supply is on.

Note: When use drivability reduction function of oscillator, please use in case of

= 4 MHz to 10 MHz condition.

OSCH

92CM22-19

2007-02-16

TMP92CM22

(2) Single drive for high-frequency oscillator

(Purpose)

Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external oscillator is used.

(Block diagram)

X1 pin

X2 pin

OSCH

Oscillation enable (

EMCCR0<DRVOSCH>

><+ EXTINEMCCR0STOP )

(Setting method)

The oscillator is disabled and starts operation as buffer by writing “1” to EMCCR0<EXTIN> register. X2 pin is always outputted “1”.

By reset, <EXTIN> is initialized to “0”.

92CM22-20

2007-02-16

TMP92CM22

(3) Runaway provision with SFR protection register

(Purpose)

Provision in runaway of program by noise mixing.

Write operation to specified SFR is prohibited so that provision program in runaway prevents that is in the state which is fetch impossibility by stopping of clock, memory control register (Memory controller) is changed.

And error handling in runaway becomes easy by INTP0 interruption.

Specified SFR list

1. Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BEXCSL/H, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, and PMEMCR

2. Clock gear (EMCCR1, EMCCR2 write enable) SYSCR0, SYSCR1, SYSCR2, and EMCCR0

(Operation explanation)

Execute and release of protection (write operation to specified SFR) becomes

possible by setting up a double key to EMCCR1 and EMCCR2 registers.

(Double key)

1st-KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2. 2nd-KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2.

A state of protection can be confirmed by reading EMCCR0<PROTECT>. By reset, protection becomes OFF. And INTP0 interruption occurs when write operation to specified SFR was

executed with protection on state.

92CM22-21

2007-02-16

3.3.6 Standby Controller

(1) HALT modes

When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1, or STOP mode, depending on the contents of the SYSCR2<HALTM1:0> register.

The subsequent actions performed in each mode are as follows:

a. IDLE2: Only the CPU halts.

The internal I/O is available to select operation during IDLE2 mode by setting the following register. Table 3.3.1 shows the registers of setting ope ration during IDLE2 mode.

Table 3.3.1 SFR Seting Operation during IDLE2 Mode

b. IDLE1: Only internal oscillator operates. c. STOP: All internal circuit stop.

Internal I/O SFR

TMRA01 TA01RUN<I2TA01> TMRA23 TA23RUN<I2TA23> TMRB0 TB0RUN<I2TB0> TMRB1 TB1RUN<I2TB1> SIO0 SC0MOD1<I2S0> SIO1 SC1MOD1<I2S1> AD converter ADMOD1<I2AD> WDT WDMOD<I2WDT> SBI SBI0BR0<I2SBI0>

The operation of each of the different HALT modes is described in

TMP92CM22

Table 3.3.2.

Table 3.3.2 Each Block Operation in HALT Mode

HALT Mode IDLE2 IDLE1 STOP

SYSCR2<HALTM1:0> 11 10 01

CPU Stop I/O port Keep the state when the HALT

TMRA, TMRB SIO, *SBI AD converter

Operation block

WDT

instruction is executed.

* Selection enable operation

block to programmable

*: Except clocked-synchronous 8 -bit SIO mode for SBI.

Refer

Table 3.3.5, Table 3.3.6

Stop

92CM22-22

2007-02-16

(2) How to release the HALT mode

These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register <IFF2:0> and the HALT modes. The details for release the halt status are shown in

• Released by requesting an interrupt

The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of interrupt mask register, the interrupt due to the source is processed after release the HALT mode, and CPU status executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, release the HALT mode is not executed. (In non-maskable interrupts, interrupt processing is processed after release the HALT mode regardless of the value of the mask register.) However only for INT0 to INT3 interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, release the HALT mode is executed. In this case, interrupt processing, and CPU starts executing the instruction next to the HALT instruction, but the interrupt request flag is held at “1”.

Table 3.3.3.

TMP92CM22

• Release by resetting

Release all halt status is executed by resetting.

When the STOP mode is released by RESET, it is necessary enough resetting time (Refer

When release the HALT mode by resetting, the internal RAM data keeps the state before the “HALT” instruction is executed. However the other settings contents are initialized. (Release due to interrupts keeps the state before the “HALT” instruction is executed.)

Table 3.3.4) to set the operation of the oscillator to be stable.

92CM22-23

2007-02-16

Table 3.3.3 Source of Halt State Release and Halt Release Operation

TMP92CM22

Status of Received Interrupt

Interrupt Enable

(Interrupt level) ≥ (Interrupt mask)

Interrupt Disable

(Interrupt level) < (Interrupt mask)

HALT Mode Programmable IDLE2 IDLE1 STOP Programmable IDLE2 IDLE1 STOP

NMI INTWDT INT0 to 3 (Note1) INT4 to 5 INTTA0 to 3,

Interrupt

INTTB00, 01, 10, 11, O0, O1 INTRX0 to 1, TX0 to 1 INTAD INTSBE0

Source of HALT state release

Reset Initialize LSI

♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

♦

× × × × × ×

♦*1

× × × × × ×

−

○

× × × × × ×

−

○

× × × × × ×

♦: After release the HALT mode, CPU starts interrupt processing.

○: After release the HALT mode, CPU resumes executing starting from instruction following the HALT

instruction. (Interrupt don’t process.)

×: It can not be used to release the HALT mode.

−: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority

level. There is not this combination type.

−

○*1

× × × × × ×

*1: Release the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is released by INT0 to INT3 interrupts of the level mode in the interrupt

enabled status, hold this level until starting interrupt pro cessing. Changing level before holding level, interrupt processing is correctly started.

Note 2: When use external interrupt INT4 to INT5 are used during IDLE2 mode, set 16-bit timer RUN

(Example release HALT mode)

An INT0 interrupt release the halt state when the device is in IDLE1 mode.

Address 8203H LD (IIMC), 00H ; Selects INT0 interrupt rising edge.

8206H LD (INTE0AD), 06H ; Sets INT0 interrupt level to 6. 8209H EI 5 ; Sets CPU interrupt level to 5. 820BH LD (SYSCR2), 28H ; Sets HALT mode to IDLE1 mode. 820EH HALT ; Halts CPU.

INT0 INT0 interrupt routine

RETI 820FH LD XX, XX

92CM22-24

2007-02-16

TMP92CM22

(3) Operation

a. IDLE2 mode

In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops.

Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt.

A0 to A23

D0 to D15

Interrupt o

releasing halt

Data

IDLE2

mode

Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Released by Interrupt

b. IDLE1 mode

In IDLE1 mode, only the internal oscillator operates. The system clock stops.

And, pin state in IDLE1 mode depend on setting SYSCR2<SELDRV, DRVE> register.

Table 3.3.5, Table 3.3.6 shows pin state in IDLE1 mode.

In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the halt state (e.g., restart of operation) is synchronous with it.

Figure 3.3.7 shows the timing for release of the IDLE1 mode halt state by an interrupt.

A0 to A23

D0 to D15

Interrupt o

releasing halt

Data

IDLE1 mode

Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Released by Interrupt

92CM22-25

2007-02-16

TMP92CM22

c. STOP mode

When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2<SELDRV, DRVE> register.

Table 3.3.5, Table 3.3.6 shows the state of

these pins in STOP mode.

After STOP mode has been released system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Warm-up time set by SYSCR2<WUPTM1:0> register. See the sample warm-up times in

Table

3.3.4.

Figure 3.3.8 illustrates the timing for release of the STOP mode halt state by an interrupt.

War m -up time

A0 to A23

D0 to D15

Interrupt o

releasing halt

Data Data

STOP mode

Figure 3.3.8 Timing Chart for STOP Mode Halt State Released by Interrupt

Table 3.3.4 Sample Warm-up Times after Rrelease of STOP Mode

at f

OSCH

= 10 MHz

SYSCR2<WUPTM1:0>

01 (28) 10 (214) 11 (216)

25.6 μs 1.638 ms 6.554 ms

92CM22-26

2007-02-16

TMP92CM22

Table 3.3.5 Input Buffer State Table

Input Buffer State

Port

Name

D0-D7 D0-D7 − − − −

P10-P17 D8-D15

Input

Function

Name

During

Reset

OFF

P40-P47 − P50-P57 − P60-P67 −

P76 WAIT OFF P90 SCK P91 SDA

P92

PA0-PA7(*1) − − − ON − ON − ON

PC0 TA0IN OFF OFF PC1 INT1 PC3 INT0 ON ON ON PC5 INT2 PC6 INT3

PD0

PD1 PD2 −

PD3 −

PF0 − PF1 RXD0

PF2 PF3 − − − OFF − −

PF4 RXD1 PF5 PF6 −

PF7 −

PG0-2,

PG4-7(*2)

PG3(*2) ADTRG

−

NMI

RESET(*1) −

AM0,1 −

SCL

INT4,

TB1IN0

INT5,

TB1IN1

SCLK0,

CTS0

SCLK1,

CTS1

−

OFF

ON: The buffer is always turned on. A current flows

Input Buffer State Input Buffer State

When Used as function

When

Used as

Input

Port

When Used as function

When

Used as

Input

Port

upon

external

OFF OFF OFF

read

− − − −

OFF

OFF OFF OFF

ON ON

OFF

− −

ON ON ON OFF OFF

ON ON OFF OFF

− − − −

upon

port

OFF

read

−

*1: Port having a pull-up/pull-down resistor.

the input buffer if the input pin is not driven. OFF: The buffer is always turned off.

*2: AIN input does not cause a current to flow through the buffer.

−: No applicable

In HALT mode (IDLE1/STOP)

Condition A (Note) Condition B (Note)

When Used as function

OFF

When

Used as

Input

Port

OFF

When Used as function

OFF

When

Used as

Input

Port

OFF

ON ON

OFF OFF

− −

OFF OFF

−

Note: Condition A/B are as follows.

SYSCR2 register setting HALT mode

<DRVE> <SELDRV> IDLE1 STOP

0 0 Condition B 0 1 Condition A 1 0 1 1

Condition A

Condition B Condition B

92CM22-27

2007-02-16

TMP92CM22

Table 3.3.6 Output Buffer State Table

Output Buffer State

Port

Name

D0-D7 D0-D7 − − − − P10-P17 D8-D15 P40-P47 A0-A7

P50-P57 A8-A15 P60-P67 A16-A23

P70 P71 WRLL P72 WRLU P73 WRUL P74 WRUU P75 R/W P76 − OFF − − − − P80 CS0 P81 CS1 P82 CS2 P83 CS3 P90 SCK P91 SO P92 SCL PC0 − − − − − PC1 TA1OUT ON ON OFF ON PC3 − − − − − PC5 TA3OUT PC6 TB0OUT PD0 − PD1 − PD2 TB1OUT0 ON PD3 TB1OUT1 PF0 TXD0 ON PF1 − − − − − PF2 SCLK0 PF3 TXD1 PF4 − − − − − PF5 SCLK1 ON ON OFF ON PF6 − PF7 −

X2 − − ON − IDLE1: ON, STOP: High level output

Note: Condition A/B are as follows.

Output

Function

Name

ON: The buffer is always turned on. When the bus is released, however ,output buffers for some pins are turned off.

OFF: The buffer is always turned off.

−: No applicable

SYSCR2 register setting HALT mode

<DRVE> <SELDRV> IDLE1 STOP

0 0 Condition B 0 1 Condition A 1 0 1 1

During

Reset

OFF

ON ON ON

OFF

When the CPU is

Operating

When

Used as

Function

ON upon

external

read

ON ON OFF ON

− − − −

ON ON OFF ON

−

When

Used as

Output

Port

Condition B Condition B

In HALT

mode(IDLE2)

When

Used as

Function

OFF

ON OFF ON

−

Condition A

When

Used as

Output

Port

Used as Function

In HALT mode (IDLE1/STOP)

Condition A (Note) Condition B (Note)

When

OFF

−

When

Used as

Output

Port

OFF

When Used as Function

OFF

−

When

Used as

Output

Port

92CM22-28

2007-02-16

+ 230 hidden pages