TOSHIBA TC90A66F Technical data
TC90A66F
y
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
Preliminar
T C 9 0 A 6 6 F
PAP/PIP/POP Controller for Wide-Screen TVs (PAL/NTSC)
With built-in AD and DA converters (ADC/DAC), the TC90A66F is a picture-and-picture (PAP)/picture-in-picture
(PIP)/picture-out-picture (POP) controller IC for PAL and NTSC
formats. It is used in combination with field memory, video signal
processor ICs.
The TC90A66F enables a variety of picture display functions.
The IC is optimal to provide wide-screen TVs with additional
functionality.
Features
• Two-channel 8-bit ADC, three-channel 8-bit DAC, clamp
circuit, and multiplexer integrated on single chip
• External field memory
Recommended memory: MSM51V8221, MSM51V8222 (By Oki)
• Picture display functions
PAP display Half-picture left and right sides of 16:9 screen
(Motion Picture mode or Still mode selectable)
PIP display 4:3 or 16:9 aspect ratio
(Motion Picture mode or Still mode selectable)
POP display 4:3 aspect ratio
(3 pictures in Still mode, 1 picture in Motion Picture mode and 2 pictures in Still mode, or
Strobe mode selectable)
Multi-picture still Display of up to 24 still pictures per screen
Channel search 9, 12, or 16 picture search
(Still mode, Strobe mode, or 1 picture in Motion Picture mode selectable)
• Variable frame width and frame color
• Built-in horizontal and vertical filters
2
• I
C bus for micro controller interface
• 3.3-V single power supply
• Package: QFP144
Weight: 4.64 g (typ.)
1
2001-06-07
Pin Assignment
Y
Y
TC90A66F
TESO
IICNR
SADSEL
SACN
V
SCL
SDA
TEST4
TEST3
TEST2
TEST1
TEST0
V
T107
T106
T105
T104
T103
T102
T101
T100
CNT6
CNT5
CNT4
CNT3
V
DAV
YOUT
DAV
IOUT
DAV
QOUT
VB2
VB1
VREF
ADBIAS
SS
DD
SS
DD
SS
DD
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
108
TIMRST
107
PWRST
106
HYOJUN
105
KAYS
YS
104
103
RVD
102
RHD
101
V
DD
100
SS
RMCK
ERRST
EREN
RRST
REN
RDAY7
RDAY6
RDAY5
RDAY4
RCK
RHREF
RMCKI
V
99
98
97
96
95
94
93
92
91
90
RDAY3
89
88
87
86
TC90A66F
RDAY2
DD
RDAY1
RDAY0
V
RDAC7
RDAC6
RDAC5
RDAC4
RDAC3
RDAC2
RDAC1
RDAC0
WDAY0
WDAY1
85
84
83
82
81
80
79
78
77
76
75
74
73
72
WDAY2
71
WDAY3
70
WDAY4
69
WDAY5
68
WDAY6
67
WDAY7
66
V
SS
65
WDAC0
64
WDAC1
63
WDAC2
62
WDAC3
61
WDAC4
60
WDAC5
59
WDAC6
58
WDAC7
57
WRST
56
WEN
55
WIEN
54
EWRST
53
EWEN
52
EWIEN
51
V
SS
50
WMCK
49
V
SS
48
EWMCK
47
V
DD
46
WHREFS
45
WCKS
44
V
SS
43
WHDS
42
WVDS
41
MOH
40
HRST
39
V
DD
38
WHREFE
37
WCKE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SS
DD
IINS
YINS
ADV
ADV
SS
DD
QINS
VRT
VRTC
VRB
ADV
ADV
VRBC
SS
DD
IINE
YINE
ADV
ADV
AV
DD
QINE
AV
SS
DD
V
CNT2
TIN9
TIN8
TIN7
TIN6
TIN5
TIN4
TIN3
TIN2
TIN1
CNT1
CNT0
CLAMP
TIN0
SS
V
WVDE
WHDE
2001-06-07 2
System Block Diagram
Y
K
Y
K
SCL
SDA
µ-COM
TC90A66F
Output signal
Y
I
Q
PLL circuit
YIN
CIN
Sub picture (S)
Image input signal
YIN
CIN
Sub picture (E)
Image input signal
YOUT IOUT QOUT
SDA
SCL
SUB VCD1
TA1270AF
YIN
CIN
HD VD
SDA
SCL
SUB VCD2
TA1270AF
YIN
CIN
HD VD
Y1IN
I1IN
Q1IN
YS
Y2IN
I2IN
Q2IN
YOUT
IOUT
QOUT
YOUT
IOUT
QOUT
SDA SCL
YOUT
IOUT
QOUT
YS
YINS
IINS
QINS
WVDS
WHDS
RVD
RHD
YINE
IINE
QINE
WVDE WHDE WHREFSWCKS
PAP/PIP/POP
TC90A66F
RHREF RCK
WHREFEWCKE
RDA
RDAC
RMC
WDA
WDAC
WMC
2M MEMORY*2
MSM51V8221
PLL circuit
PLL circuit
3
2001-06-07
TC90A66F Block Diagram
TC90A66F
(not required in 2M mode)
MAIN
µ-COM
SDA
SCL
YIN (S)
IIN (S)
QIN (S)
YIN (E)
IIN (E)
QIN (E)
Sub picture S
WVDS
WHDS
WCKS
WHREF
Sub picture E
WVDE
WHDE
WCKE
WHREFE
Main picture
RVD
RHD
RCK
RHREF
2M memory
(MSM51V8221)
IN OUT
IIC BUS
A
RMCK
1200 fh
(4M/2M)
WIE
REN
Code processor
C
L
M
P
C
L
M
P
detector circuit
Generates system
clock for write
2400 fh (4M/2M)
Generates system
clock for write
2400 fh (4M/2M)
Generates system
clock for read
2400 fh (4M/2M)
M
A/D
P
X
M
A/D
P
X
Odd/Even
Horizontal
filter
Line memory
Line memory
Generates control
signal for write
Generates control
signal for read
Vertical
filter
Vertical
filter
Y/IQ
separator
Output processor
(frame color select,
Y/C phase adjustment)
Stand processor
A
Control signals for write
Control signals for read
WDAY
7 to 0
WMCK
1200 fh
(4M/2M)
WRST
WENY
WENC
RRST
IN OUT
RDAY
7 to 0
2M memory
(MSM51V8221)
WDAC
7 to 0
D/A
D/A
D/A
Picture display
switch signal
Memory use
switch signal
RMCKI
RDAC
7 to 0
YOUT
IOUT
QOUT
VREF
VB1
VB2
YS
PWRST
MOH
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2001-06-07
TC90A66F
Pin Functions
Pin
Number
Pin Name I/O Function
1 ADVDD Power supply for A/D (3.3 V)
2 YINS I A/D Y signal (S system) input
3 ADVSS GND for A/D
4 IINS I A/D I signal or R-Y signal (S system) input
5 ADVDD Power supply for A/D (3.3 V)
6 QINS I A/D Q signal or B-Y signal (S system) input
7 ADVSS GND for A/D
8 VRTY I Reference voltage for A/D Y signal (top)
9 VRBY I Reference voltage for A/D Y signal (bottom)
10 VRTC I Reference voltage for A/D I, Q signal (top)
11 VRBC I Reference voltage for A/D I, Q signal (bottom)
12 ADVDD Power supply for A/D (3.3 V)
13 YINE I A/D Y signal (E system) input
14 ADVSS GND for A/D
15 IINE I A/D I signal or R-Y signal (E system) input
16 AVDD Power supply for analog circuit (3.3 V)
17 QINE I A/D Q signal or B-Y signal (E system) input
18 AVSS GND for analog circuit
19 VDD Power supply (3.3 V)
20 CNT2 O Test output pin
21 CNT1 O Test output pin
22 CNT0 O Test output pin
23 CLAMP O Clamp signal monitor output
24 TIN9 I Test input pin (connect to GND)
25 TIN8 I Test input pin (connect to GND)
26 TIN7 I Test input pin (connect to GND)
27 TIN6 I Test input pin (connect to GND)
28 TIN5 I Test input pin (connect to GND)
29 TIN4 I Test input pin (connect to GND)
30 TIN3 I Test input pin (connect to GND)
31 TIN2 I Test input pin (connect to GND)
32 TIN1 I Test input pin (connect to GND)
33 TIN0 I Test input pin (connect to GND)
34 WVDE I (E system) vertical sync signal input (It can be inverted using I2C bus) (Note1)
35 WHDE I (E system) horizontal sync signal input (It can be inverted using I2C bus) (Note1)
36 VSS GND
37 WCKE I (E system) system clock input (Note1)
38 WHREFE I/O (E system) PLL phase comparison output
39 VDD Power supply (3.3 V)
40 HRST O Unit adjusting pin
41 MOH O Memory use switch signal [(YCS (L)㨯TC90A66F (H))
(144-pin QFP)
Note1: Supports 5 V interface.
5
2001-06-07
TC90A66F
Pin
Number
Pin Name I/O Function
42 WVDS I (S system) vertical sync signal input (It can be inverted using I2C bus) (Note1)
43 WHDS I (S system) horizontal sync signal input (It can be inverted using I2C bus) (Note1)
44 VSS GND
45 WCKS I (S system) system clock input (Note1)
46 WHREFS O (S system) PLL phase comparison output
47 VDD Power supply (3.3 V)
48 EWMCK O (E system) write clock output for field memory
49 VSS GND
50 WMCK O (S system) write clock output for field memory
51 VSS GND
52 EWIEN O (E system) field memory input enable
53 EWEN O (E system) field memory write enable
54 EWRST O (E system) field memory write reset
55 WIEN O (S system) field memory input enable
56 WEN O (S system) field memory write enable
57 WRST O (S system) field memory write reset
58 WDAC7 O IQ or sub picture (E system) signal output (field memory write signal/MSB)
59 WDAC6 O IQ or sub picture (E system) signal output (field memory write signal/ : )
60 WDAC5 O IQ or sub picture (E system) signal output (field memory write signal/ : )
61 WDAC4 O IQ or sub picture (E system) signal output (field memory write signal/ : )
62 WDAC3 O IQ or sub picture (E system) signal output (field memory write signal/ : )
63 WDAC2 O IQ or sub picture (E system) signal output (field memory write signal/ : )
64 WDAC1 O IQ or sub picture (E system) signal output (field memory write signal/ : )
65 WDAC0 O IQ or sub picture (E system) signal output (field memory write signal/LSB)
66 VSS GND
67 WDAY7 O Y or sub picture (S system) signal output (field memory write signal/MSB)
68 WDAY6 O Y or sub picture (S system) signal output (field memory write signal/ : )
69 WDAY5 O Y or sub picture (S system) signal output (field memory write signal/ : )
70 WDAY4 O Y or sub picture (S system) signal output (field memory write signal/ : )
71 WDAY3 O Y or sub picture (S system) signal output (field memory write signal/ : )
72 WDAY2 O Y or sub picture (S system) signal output (field memory write signal/ : )
73 WDAY1 O Y or sub picture (S system) signal output (field memory write signal/ : )
74 WDAY0 O Y or sub picture (S system) signal output (field memory write signal/LSB)
75 RDAC0 I IQ or sub picture (E system) signal input (field memory read signal/LSB) (Note1)
76 RDAC1 I IQ or sub picture (E system) signal input (field memory read signal/ : ) (Note1)
77 RDAC2 I IQ or sub picture (E system) signal input (field memory read signal/ : ) (Note1)
78 RDAC3 I IQ or sub picture (E system) signal input (field memory read signal/ : ) (Note1)
79 RDAC4 I IQ or sub picture (E system) signal input (field memory read signal/ : ) (Note1)
80 RDAC5 I IQ or sub picture (E system) signal input (field memory read signal/ : ) (Note1)
81 RDAC6 I IQ or sub picture (E system) signal input (field memory read signal/ : ) (Note1)
82 RDAC7 I IQ or sub picture (E system) signal input (field memory read signal/MSB) (Note1)
83 VDD Power supply (3.3 V)
84 RDAY0 I Y or sub picture (S system) signal input (field memory read signal/LSB) (Note1)
Note1: Supports 5 V interface.
6
2001-06-07
TC90A66F
Pin
Number
Pin Name I/O Function
85 RDAY1 I Y or sub picture (S system) signal input (field memory read signal/ :) (Note1)
86 RDAY2 I Y or sub picture (S system) signal input (field memory read signal/ : ) (Note1)
87 RDAY3 I Y or sub picture (S system) signal input (field memory read signal/ : ) (Note1)
88 RDAY4 I Y or sub picture (S system) signal input (field memory read signal/ : ) (Note1)
89 RDAY5 I Y or sub picture (S system) signal input (field memory read signal/ : ) (Note1)
90 RDAY6 I Y or sub picture (S system) signal input (field memory read signal/ : ) (Note1)
91 RDAY7 I Y or sub picture (S system) signal input (field memory read signal/MSB) (Note1)
92 REN O (S system) field memory read enable
93 RRST O (S system) field memory read reset
94 EREN O (E system) field memory read enable
95 ERRST O (E system) field memory read reset
96 RMCK O (S/E system) read clock output for field memory
97 RMCKI I RMCK input (phase adjustment)
98 VSS GND
99 RHREF O PLL phase comparison output for main picture
100 RCK I System clock input for main picture (Note1)
101 VDD Power supply (3.3 V)
102 RHD I Horizontal sync single input for main picture (It can be inverted using I2C bus) (Note1)
103 RVD I Vertical sync single input for main picture (It can be inverted using I2C bus) (Note1)
104 YS O YS signal output
105 KAYS O Wallpaper YS signal output
106 HYOJUN O Standard/non-standard signal output [standard (L)/non-standard (H)]
107 PWRST I System reset input [reset (L)]
108 TIMRST I Test reset input [reset (H)/normal (L)]
109 TESO O Test monitor output
110 IICNR I I2C bus noise reduction circuit [on (H)/off (L)]
111 SADSEL I Main/sub sub address switch [main (H)/sub (L)]
112 SACN O I2C bus acknowledge output pin
113 VSS GND
114 SCL I I2C bus serial clock input (Note1)
115 SDA I/O I2C bus serial data input (IN)/acknowledge (OUT) (Note1)
116 TEST4 I Test input pin (connect to GND)
117 TEST3 I Test input pin (connect to GND)
118 TEST2 I Test input pin (connect to GND)
119 TEST1 I Test input pin (connect to GND)
120 TEST0 I Test input pin (connect to GND)
121 VDD Power supply (3.3 V)
122 TIO7 I/O Test input/output pin (normally, open)
123 TIO6 I/O Test input/output pin (normally, open)
124 TIO5 I/O Test input/output pin (normally, open)
125 TIO4 I/O Test input/output pin (normally, open)
126 TIO3 I/O Test input/output pin (normally, open)
127 TIO2 I/O Test input/output pin (normally, open)
Note1: Supports 5 V interface.
7
2001-06-07
Pin
Number
Pin Name I/O Function
128 TIO1 I/O Test input/output pin (normally, open)
129 TIO0 I/O Test input/output pin (normally, open)
130 CNT6 O Test output pin
131 CNT5 O Test output pin
132 CNT4 O Test output pin
133 CNT3 O Test output pin
134 VSS GND
135 DAVDD Power supply for D/A (3.3 V)
136 YOUT O Y Signal output
137 DAVSS D/A GND
138 IOUT O I signal or R-Y signal output
139 DAVDD Power supply for D/A (3.3 V)
140 QOUT O Q signal or B-Y signal output
141 VB2 D/A bias
142 VB1 D/A bias
143 VREF I D/A reference bias (supply 2.3 V)
144 ADBIAS A/D bias
TC90A66F
8
2001-06-07
Pin Description
Pin Number Pin Name Function
2 YINS Y-signal (S system) analog input
Input amplitude is 1 V
4 IINS I or R-Y signal (S system) analog input
Input amplitude is 1 V
6 QINS Q or B-Y signal (S system) analog input
Input amplitude is 1 V
8 VRTY High-level reference power supply pin for ADC Y signal. Sets the upper limit of the ADC dynamic
range. Fixed to 2.2 V (typ.) by internal resistance type potential division. Connect 0.1 µF bypass
capacitor between the pin and GND.
9 VRBY Low-level reference power supply voltage for ADC Y signal. Sets the lower limit of the ADC dynamic
range. Fixed to 1.1 V (typ.) by internal resistance type potential division. Connect 0.1 µF bypass
capacitor between the pin and GND.
10 VRTC High-level reference power supply pin for ADC IQ signal. Sets the upper limit of the ADC dynamic
range. Fixed to 2.2 V (typ.) by internal resistance type potential division. Connect 0.1 µF bypass
capacitor between the pin and GND.
11 VRBC Low-level reference power supply voltage for ADC IQ signal. Sets the lower limit of the ADC dynamic
range. Fixed to 1.1 V (typ.) by internal resistance type potential division. Connect 0.1 µF bypass
capacitor between the pin and GND.
13 YINE Y signal (E system) analog input
Input amplitude is 1 V
15 IINE I or R-Y signal (E system) analog input
Input amplitude is 1 V
17 QINE Q or B-Y signal (E system) analog input
Input amplitude is 1 V
23 CLAMP Clamp signal monitor output pin.
Can monitor clamp pulse start/stop position set at 24h or 25h.
Outputs signal for the last data (S or E system) transfer.
34 WVDE (E system) vertical sync signal input pin. (It can be inverted using I2C bus)
Inputs vertical sync signal from VCD for sub picture E. It is composing 5 V interface. For negative
polarity input, set sub address [26H: EVINV] to L (negative polarity input).
35 W HDE (E system) horizontal sync signal input pin. (It can be inverted using I2C bus)
Inputs horizontal sync signal from VCD for sub picture E. It is composing 5 V interface. For negative
polarity input, set sub address [26H: EHINV] to L (negative polarity input).
37 WCKE (E system) write clock input pin. Inputs from the external PLL circuit. It is composing 5 V interface.
Inputs 2400 fH for both 4M and 2M memory mode.
38 WHREFE (E system) PLL phase comparison output.
The HREF signal obtained by the I/N divider circuit or the phase comparison result of sub picture (E)
horizontal sync signal.
40 HRST Unit adjustment (WS/WE/R switch able)
41 MOH External field memory use signal output pin.
Output amplitude is 3.3 V
Setting sub address [21H: MOH] to H uses TC90A66F; setting to L sets all memory output pins to Hi-Z.
42 WVDS (S system) vertical sync signal input pin. (It can be inverted using I2C bus)
Inputs vertical sync signal from VCD for sub picture S. It is composing 5 V interface. For negative
polarity input, set sub address [27H: WVINV] to L (negative polarity input).
43 W HDS (S system) horizontal sync signal input pin. (It can be inverted using I2C bus)
Inputs horizontal sync signal from VCD for sub picture S. It is composing 5 V interface. For negative
polarity input, set sub address [27H: WHINV] to L (negative polarity input).
45 WCKS (S system) write clock input pin. Inputs from the external PLL circuit. It is composing 5 V interface.
Inputs 2400 fH for both 4M and 2M memory mode.
typical.
p-p
typical.
p-p
typical.
p-p
typical.
p-p
typical.
p-p
typical.
p-p
typical.
p-p
TC90A66F
9
2001-06-07
Pin Number Pin Name Function
46 WHREFS (S system) PLL phase comparison output.
The HREF signal obtained by the I/N divider circuit or the phase comparison result of sub picture (S)
horizontal sync signal. This signal is used to control the external VCO voltage.
48 EWMCK Outputs sub picture E write clock to external field memory.
Output amplitude is 3.3 V
typical.
p-p
50 WMCK Outputs sub picture S write clock to external field memory.
Output amplitude is 3.3 V
typical.
p-p
52 EWIEN Control signal output pin for external field memory (sub picture E).
Output amplitude is 3.3 V
typical.
p-p
53 EWEN Control signal output pin for external field memory (sub picture E).
Output amplitude is 3.3 V
typical.
p-p
54 EWRST Control signal output pin for external field memory (sub picture E).
Output amplitude is 3.3 V
typical.
p-p
55 WIEN Control signal output pin for external field memory (sub picture S).
Output amplitude is 3.3 V
typical.
p-p
56 WEN Control signal output pin for external field memory (sub picture S).
Output amplitude is 3.3 V
typical.
p-p
57 WRST Control signal output pin for external field memory (sub picture S).
Output amplitude is 3.3 V
typical.
p-p
58 to 65 WDAC7-0 Output signal to write to external field memory. (I, Q or E system).
Output amplitude is 3.3 V
typical.
p-p
Connect only when using 4M memory.
MSB: WDAC7, LSB: WDAC0
67 to 75 WDAY7-0 Output signal to write to external field memory. (Y or S system).
Output amplitude is 3.3 V
typical.
p-p
MSB: WDAY7, LSB: WDAY0
75 to 82 RDAC0-7 Input signal to read from external field memory (I, Q or E system).
It is composing 5 V interface.
Connect only when using 4M memory.
MSB: RDAC7, LSB: RDAC0
84 to 91 RDAY0-7 Input signal to read from external field memory (Y or S system).
It is composing 5 V interface.
MSB: RDAY7, LSB: RDAY0
92 REN Control signal output pin for external field memory (sub picture S).
Output amplitude is 3.3 V
typical.
p-p
93 RRST Control signal output pin for external field memory (sub picture S).
Output amplitude is 3.3 V
typical.
p-p
94 EREN Control signal output pin for external field memory (sub picture E).
Output amplitude is 3.3 V
typical.
p-p
95 ERRST Control signal output pin for external field memory (sub picture E).
Output amplitude is 3.3 V
typical.
p-p
96 RMCK Outputs read clock to external field memory.
Output amplitude is 3.3 V
typical.
p-p
Outputs 1200 fH for both 4M and 2M memory.
97 RMCKI RMCK phase adjustment input pin. Inputs RMCK.
TC90A66F
10
2001-06-07
Pin Number Pin Name Function
99 RHREF PLL phase compare output pin for main picture.
The HREF signal obtained by the I/N divider circuit or the phase comparison result of RHD signal. This
signal is used to control the external VCO voltage.
100 RCK Read clock input pin. It is composing 5 V interface.
Inputs from the external PLL circuit.
Inputs 2400 fH for both 4M and 2M memory.
102 RHD Horizontal sync signal input pin for main picture (read). Inputs horizontal sync signal from VCD for main
picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub
address [28H: RHINV] to non-inversion (L).
103 RVD Vertical sync signal input pin for main picture (read). Inputs vertical sync signal from VCD for main
picture. It is composing 5 V interface (negative polarity input). For negative polarity input, set sub
address [28H: RVINV] to non-inversion (L).
104 YS Main/sub picture switch timing signal output pin. Output amplitude is 3.3 V
signal is High, displays sub picture.
105 KAYS Wallpaper YS signal output.
106 HYOJUN Standard/non-standard signal output pin [standard (L)/non-standard (H)]
107 PWRST System reset input pin. When low input, it carries out the reset.
At least 1 V is required as reset duration.
110 IICNR I2C bus noise reduction circuit setting pin.
When set to on (connect to V
When set to off (connect to GND), data are written to register directly.
111 SADSEL Sub address of main/sub picture switching pin. [main (H)/sub (L)]
Normally, set to L (enables sub addresses 00h to 7Fh).
112 SACN I2C bus acknowledge output pin.
114 SCL I2C bus serial clock input pin. It is composing 5 V interface.
115 SDA I2C bus serial data input/acknowledge output pin.
It is composing 5 V interface.
136 YOUT Y signal output pin. Output amplitude is 0.9 V
138 IOUT I signal output pin. Output amplitude is 0.9 V
140 QOUT Q signal output pin. Output amplitude is 0.9 V
141 to 142 VB2-1 Bias pin for DAC.
Connect a 0.1 µF bypass capacitor between the pins and GND.
143 VREF DAC reference voltage input pin.
Reference voltage is 2.3 V typical.
144 ADBIAS Bias pin for ADC.
Connect a 0.1 µF bypass capacitor between the pin and AGND.
), data are latched once by the internal clock, then written to register.
DD
typical.
p-p
typical.
p-p
typical.
p-p
typical. When the YS
p-p
TC90A66F
11
2001-06-07
Example of Typical A/D Converter Input Level for Luminance Signal
2.2 V
100 (IRE)
TC90A66F
Dec. HEX
255
FFH
228
E4H
1.1 V
1.1 V
0.71 V
0 (IRE)
0.27 V
−40 (IRE)
signal amplitude: 1.0 V
(100% white)
p-p
pedestal clamp value
Example of Typical A/D Converter Input Level for Chrominance Signal
2.2 V
0.5 V
1.1 V
0.5 V
reference potential
clamp value
63
3FH
0
00H
Dec. HEX
255
FFH
251
EBH
136 88H
21
15H
0
1.1 V
signal amplitude: 1.0 V
p-p
00H
12
2001-06-07
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