TOSHIBA TC74LCX16373AFT Technical data
TC74LCX16373AFT
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74LCX16373AFT
Low-Voltage 16-Bit D-Type Latch with 5-V Tolerant Inputs and Outputs
The TC74LCX16373AFT is a high-performance CMOS 16-bit
D-type latch. Designed for use in 3.3-V systems, it achieves
high-speed operation while maintaining the CMOS low power
dissipation.
The device is designed for low-voltage (3.3 V) V
but it could be used to interface to 5-V supply environment for
both inputs and outputs.
This 16-bit D-type latch is controlled by a latch enable input
(LE) and an output enable input (
byte. It can be used as two 8-bit latches or one 16-bit latch. When
OE
the
discharge.
input is high, the outputs are in a high-impedance state.
All inputs are equipped with protection circuits against static
OE
) which are common to each
Features
applications,
CC
Weight: 0.25 g (typ.)
• Low-voltage operation: VCC = 2.0 to 3.6 V
• High-speed operation: t
• Ouput current: |I
• Latch-up performance: −500 mA
• Package: TSSOP
• Power-down protection provided on all inputs and outputs
OH
= 7.0 ns (max) (VCC = 3.0 to 3.6 V)
pd
|/IOL = 24 mA (min) (VCC = 3.0 V)
1
2007-10-19
TC74LCX16373AFT
Pin Assignment
1
OE1
2
1Q1
3
1Q2
4
GND
5
1Q3
1Q4
6
V
7
CC
1Q5
8
1Q6
9
GND
10
11
1Q7
1Q8
12
13
2Q1
(top view)
IEC Logic Symbol
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
C3
2EN
C4
3D
4D
47
46
45
44
43
42
41
40
39
38
37
36
1LE 48
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
OE1
1LE
OE2
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
2
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
14
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
OE2
15
16
17
18
19
20
21
22
23
24
35
34
33
32
31
30
29
28
27
26
25
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
2
2007-10-19
Truth Table
1LE 1D1-1D8 1Q1-1Q8
OE1
H X X Z
L L X Qn
L H L L
L H H H
2LE 2D1-2D8 2Q1-2Q8
OE2
H X X Z
L L X Qn
L H L L
L H H H
X: Don’t care
Z: High impedance
TC74LCX16373AFT
Inputs Outputs
Inputs Outputs
Qn: Q outputs are latched at the time when the LE input is taken to a low logic level
System Diagram
1LE
OE1
2LE
48
1
25
47
36
1D1
2D1
1D2
46 44 43 41 40 38 37
D
LE
Q
2
1Q1
2D2
35 33 32 30 29 27 26
D
LE
Q
D
LE
D
LE
Q
Q
3
1Q2
1D3
2D3
D
LE
D
LE
Q
Q
5
1Q3
1D4
2D4
LE
LE
1D5
D
Q
6
1Q4
2D5
D
Q
LE
LE
1D6
D
LE
Q
8
1Q5
2D6
D
LE
Q
1D7
D
Q
9
1Q6
2D7
D
Q
LE
LE
1D8
D
D
Q
11
Q
1Q7
2D8
D
LE
D
LE
Q
12
1Q8
Q
24
OE2
13
2Q1
14
2Q2
16
2Q3
17
2Q4
19
2Q5
20
2Q6
22
2Q7
23
2Q8
3
2007-10-19
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