TOSHIBA TB62300FG Technical data
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TOSHIBA BiCD IC Silicon Monolithic
TB62300FG
Dual Full-Bridge Driver for DC Motor
The TB62300FG is a dual brushed DC motors driver IC
employing a chopper-based forward/reverse full-bridge
mechanism. It controls two brushed DC motors at high precision.
The motor supply voltage is up to 40 V and the V
voltage is 5.0 V.
Features
• A single IC can drive two brushed DC motors.
• Monolithic Bi-CMOS IC
• Low ON-resistance (R
• Selectable current control: PWM current control using the
PHASE pin or serial control
• 5-bit DA converter for specifying current value and 2-bit DA converter for determining torque
• MIXED DECAY mode enables specification of current decay rate in four steps.
• Self-oscillation chopping frequency with external resistor and capacitor
• High-speed chopping at 100 kHz or higher
• ISD, TSD, and POR (V
• Charge pump circuit (two external capacitors) for driving output
• 36-pin package: HSOP36 with heat sink
• Output voltage: 40 V (max)
• Output current: 2.5 A max (in steady-state phase) or 8 A max (pulsed output)
) = 0.3 Ω (Tj = 25°C at 2.0 A typ.)
on
) protection circuits
DD/VM
supply
DD
Weight: 0.79 g (typ.)
TB62300FG
Note: The values specified in this document are designed values, which are not guaranteed.
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Block Diagram
TB62300FG
1.
Sleep
DATA
STROBE
Overview (for single axis)
Current control data logic circuit
Circuits used to set current value
CLK
V
ref
R
VM
Mixed decay timming,
table logic circuit
Current feedback circuit
S
16-bit shift register
Current range
controller
(2-bit D/A)
V
circuit
RS
Current value controller
(5-bit D/A)
16-bit latch
RS comparator
circuit
Chopping reference
circuit
Chopping
waveform
generator
circuit
Waveform
squaring
circuit
Output control circuit
Mixed decay control
Output pre driver
VDD
CR
MODE
PHASE
ENABLE
BRAKE
Ccp 2
Ccp 1
Charge pump
circuit
High-voltage (VM)
Logic data
Analog data
IC pin
Output circuit
(H-bridge)
Brushed DC
Motor
Out X
ISD
circuit
V
DDR/VMR
circuit
Protection circuit
TSD
circuit
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Pin Assignment
TB62300FG
R
S A
V
REF A
V
REF B
CR
V
M
Ccp 1
Ccp 2
Ccp 3
VDD
LGND
NC
TSTO
TSTI
BRAKE A
BRAKE B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
36
R
35
SLEEP
34
ENABLE B
33
ENABLE A
32
PHASE B
31
PHASE A
30
DATA B
29
DATA A
28
CLK B
LGND
27
CLK A
26
STROBE B
25
STROBE A
24
MODE B
23
MODE A
S B
22
21
20
19
NC
OUT B
PGND
OUT B
−
+
OUT A
PGND
OUT A
NC
15
16
−
17
18
+
Note: When designing a ground line, make sure that all ground pins are connected to the same ground trail and
remember to take heat radiation into account.
When pins that are used to toggle between modes are controlled by a switch, pull up or down the pins to avoid
high impedance.
The IC may be destroyed due to short circuit between outputs, to supply, or to ground. Design output lines,
V
(VM) lines and ground lines with great care.
DD
When power supply pins (V
, RS, OUT, P-GND, VSS and CCP) that are exposed to high current, or logic input
M
pins are not connected correctly, excessive current or malfunction may cause the IC to break down.
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Pin Description
TB62300FG
Pin
Number
1 R
2 V
3 V
4 CR External chopping reference pin Pin used to set the chopping frequency
5 VM Supply voltage monitor pin Monitor (reference) pin for motor supply voltage
6 Ccp 1 Charge pump capacitor pin Pin for connecting a charge pump capacitor
7 Ccp 2 Charge pump capacitor pin Pin for connecting a charge pump capacitor
8 Ccp 3 Charge pump capacitor pin Pin for connecting a charge pump capacitor
9 VDD Logic power supply Logic supply current input pin
10 NC NC pin Note: Usually, leave this pin open.
11 TSTO Test pin (usually not used) Note: Usually, leave this pin open.
12 TSTI Test pin (usually not used) Note: Usually, connect this pin to LGND.
13 BRAKE A A-ch brake mode pin Forced brake mode
14 BRAKE B B-ch brake mode pin Forced brake mode
15 NC NC pin Note: Usually, leave this pin open.
16 OUT A − A-ch negative output pin A − output pin
17
18
19 OUT B + B-ch positive output pin B + output pin
20 PGND VM ground Power ground
21 OUT B − B-ch negative output pin B − output pin
22 NC NC pin Note: Usually, leave this pin open.
23 MODE A A-ch data mode switching pin Pin used to toggle between serial input and PWM control
24 MODE B B-ch data mode switching pin Pin used to toggle between serial input and PWM control
25 STROBE A A-ch latch signal input pin Data input: latched on rising edge
26 STROBE B B-ch latch signal input pin Data input: latched on rising edge
27 CLK A A-ch clock input pin Data input: referred to rising edge
28 CLK B B-ch clock input pin Data input: referred to rising edge
29 DATA A A-ch data input pin Data input:
30 DATA B B-ch data input pin Data input:
31 PHASE A A-ch phase switching pin PWM signal input pin:
32 PHASE B B-ch phase switching pin PWM signal input pin::
33 ENABLE A A-ch output forced OFF pin L: output stopped
34 ENABLE B B-ch output forced OFF pin L: output stopped
35 SLEEP Operation stopped mode Internal logic cleared and charge pump stopped
36 R
FIN1 LGND Logic ground Logic ground
FIN2 LGND Logic ground Logic ground
Symbol Function Remarks
S A
A-ch reference voltage input pin Reference power supply pin for A-axis current
REF A
B-ch reference voltage input pin Reference power supply pin for B-axis current
REF B
PGND
+
OUT A
S B
A-ch output power supply pin (current
detection pin)
VM ground Power ground
A-ch positive output pin A
B-ch output power supply pin (current
detection pin)
Reference pin for A-axis supply voltage
+ output pin
Reference pin for B-axis supply voltage
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TB62300FG
Pin Description
(Supplementary)
Pull-up/pull-down status and operation within the IC for input pins
Pin
Number
10 NC Open
11 TSTO Output pin (usually low)
12 TSTI
13 BRAKE A No pull-up or down
14 BRAKE B No pull-up or down
15 NC Open
22 NC Open
23 MODE A No pull-up or down
24 MODE B No pull-up or down
25 STROBE A No pull-up or down
26 STROBE B No pull-up or down
27 CLK A No pull-up or down
28 CLK B No pull-up or down
29 DATA A No pull-up or down
30 DATA B No pull-up or down
31 PHASE A No pull-up or down
32 PHASE B No pull-up or down
33 ENABLE A No pull-up or down
34 ENABLE B No pull-up or down
35 SLEEP Pull-down with a 50-kΩ
Symbol Internal Pull-up/down Output Operation at High Output Operation at Low
Does not affect normal operation of
the IC.
Does not affect normal operation of
the IC (with the same withstand
Input pin (no pull-up or
down)
resistor
voltage as for V
Toshiba test mode Normal operation mode
Does not affect normal operation of
the IC.
Does not affect normal operation of
the IC.
DD
).
Does not affect normal operation of
the IC.
Does not affect normal operation of
the IC.
Does not affect normal operation of
the IC.
Does not affect normal operation of
the IC.
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Truth Table (1)
Pin logic overview
Pin
Number
23 MODE A A-ch data mode switching pin
24 MODE B B-ch data mode switching pin
25 STROBE A A-ch latch signal input pin
26 STROBE B B-ch latch signal input pin
31 PHASE A A-ch phase switching pin
32 PHASE B B-ch phase switching pin
35 SLEEP Operation stopped mode
33 ENABLE A A-ch output forced OFF pin
34 ENABLE B B-ch output forced OFF pin
13 BRAKE A A-ch brake mode pin
14 BRAKE B B-ch brake mode pin
Symbol Function Logic
Truth Table (2)
TB62300FG
H : Serial signal input control
L : PWM control
Note: When PWM control is selected, serial data
bits D0 to D6 are valid while D7 to D13 are
invalid.
H : Latched on rising edge
L : Pass-through
H : Positive phase
L : Negative phase
H : Sleep released
L : Sleep state
All internal circuits, including charge pumps, are
stopped.
H : Output enabled
Output transistors turned on
L : Output disabled
Output transistors turned off
H : Brake applied
PHASE and ENABLE pins disabled
L : Brake released
Overall logic
SLEEP ENABLE
0 X X X X X Sleep mode
1
External Pins Serial Status
A/B
0 X X X X Disable mode
1
BRAKE
A/B
1 X X X Breake ON
0
MODE
A/B
0 1 X Forward
0 0 X Reverse
1 X 1 Forward
1 X 0 Reverse
PHASE
A/B
PHASE
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IC State for Each Function
Function Internal Logic Output Charge Pump OSC Recovery Time
TB62300FG
SLEEP Reset OFF OFF OFF t
ENABLE Maintained OFF Operating Operating N/A
POR Reset
ISD Reset OFF OFF OFF t
TSD Reset OFF OFF OFF t
OFF OFF OFF t
ONG
ONG
ONG
ONG
Serial Input Signals
Order of data
input
Data Bit Name Function
0 TBlank 0 0
1 TBlank 1 1
2 TBlank 2
3 Torque 0
4 Torque 1
5 Decay mode 0 1
6 Decay mode 1
7 Current 0 1
8 Current 1 1
9 Current 2 1
10 Current 3 1
11 Current 4
12 Phase Switch phase 0 Negative Disabled
13 ⎯ ⎯ ⎯ ⎯ ⎯
14 ⎯ ⎯ ⎯ ⎯ ⎯
15 ⎯ ⎯ ⎯ ⎯ ⎯
Set blanking time to prevent
false detection due to noise
Set current range
Set decay mode
Set current
= 2.0 ms (typ.)/4.0 ms (max)
= 2.0 ms (typ.)/4.0 ms (max)
= 2.0 ms (typ.)/4.0 ms (max)
= 2.0 ms (typ.)/4.0 ms (max)
Initial
Value
1
0
0
0
1
Initial State
÷ fchop ÷ 16 × 7 Enabled
1
25% Enabled
Mixed decay mode
(37.5%)
100% Disabled
When PWM is
Operating
Enabled
Strobe
Data
Clock
Register
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Notes on TBlank Setting
When using PWM control and serial control simultaneously, constant-current chopping may be disabled
depending on the TBlank setting. Using constant-current chopping requires the following phase width in
Fast Decay mode:
(TBlank setting + 2/fcr) × 2
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TB62300FG
Setting Table (1): D0, D1, D2
Blanking time settings
Data Bit Name Function TBlank 2 TBlank 1 TBlank 0 Setting TBlank (typ.)
0
1
2
TBlank 0
TBlank 1
TBlank 2
Set blanking time to prevent
false detection due to noise
0 0 0 1 ÷ f
0 0 1 1 ÷ f
0 1 0 1 ÷ f
0 1 1 1 ÷ f
1 0 0 1 ÷ f
1 0 1 1 ÷ f
1 1 0 1 ÷ f
1 1 1 1
Setting Table (2): D3, D4
Torque settings
Data Bit Name Function Torque 1 Torque 0 Setting Torque (typ.)
3
4
Torque 0
Torque 1
Set current range
0 0 25%
0 1 50%
1 0 75%
1 1 100%
Setting Table (3): D5, D6
÷ f
Chop
Chop
Chop
Chop
Chop
Chop
Chop
Chop
÷ 16 × 1
÷ 16 × 2
÷ 16 × 3
÷ 16 × 4
÷ 16 × 5
÷ 16 × 6
÷ 16 × 7
÷ 16 × 8
Decay mode settings
Data Bit Name Function
5
6
Decay mode 0
Decay mode 1
Set decay mode
Torque
Mode 1
0 0 Slow decay mode
0 1 Mixed decay mode: 37.5%
1 0 Mixed decay mode: 75.0%
1 1 Fast decay mode
Torque
Mode 0
Setting Decay Mode
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TB62300FG
Setting Table (4): D7, D8, D9, D10, D11
Current settings
Data Bit Name Function Current 4 Current 3 Current 2 Current 1 Current 0 Setting Current
7
8
9
10
11
Current 0
Current 1
Current 2
Current 3
Current 4
Set current
Setting Table (5): D12
0 0 0 0 0 0%
0 0 0 0 1 3%
0 0 0 1 0 6%
0 0 0 1 1 9%
0 0 1 0 0 12%
0 0 1 0 1 16%
0 0 1 1 0 19%
0 0 1 1 1 22%
0 1 0 0 0 25%
0 1 0 0 1 29%
0 1 0 1 0 32%
0 1 0 1 1 35%
0 1 1 0 0 38%
0 1 1 0 1 41%
0 1 1 1 0 45%
0 1 1 1 1 48%
1 0 0 0 0 51%
1 0 0 0 1 54%
1 0 0 1 0 58%
1 0 0 1 1 61%
1 0 1 0 0 64%
1 0 1 0 1 67%
1 0 1 1 0 70%
1 0 1 1 1 74%
1 1 0 0 0 77%
1 1 0 0 1 80%
1 1 0 1 0 83%
1 1 0 1 1 87%
1 1 1 0 0 90%
1 1 1 0 1 93%
1 1 1 1 0 96%
1 1 1 1 1 100%
Phase settings
Data Bit Name Function Phase Setting Phase
12 Phase Switch phase
0 Negative
1 Positive
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