Toshiba Satellite U940, Satellite U945, Compal LA-9161P Schematic

A

1 1

B

C

D

E

VCUAA

Metis 10F/10FG

2 2

LA-9161P REV 1.0 Schematic

Intel Processor (Ivy Bridge) / PCH(Panther Point)

2012-08-07 Rev 1.0

3 3

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

Cover Page

Cover Page

VCUAA

VCUAA

VCUAA

153Tuesday, October 16, 2012

153Tuesday, October 16, 2012

153Tuesday, October 16, 2012

E

1.0

1.0

1.0

of

of

of

A

B

C

D

E

Intel CPU

PCI-Express 16X Gen2

1 1

VGA (DDR3)

nVIDIA N13P-GL with 2GB

page 13,14,15,16,17,18,19,20,21

Ivy Bridge
17W

FDI X8

2.7GT/s

BGA-1023

31mm*24mm

page 5,6,7,8,9,10

DMI X4

5GT/s

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12

GCLK

SLG3NB300VTR page 34

USB30 2x

5V 5GT/s

LVDS Conn.

page 22

Intel PCH

2 2

TP/B

page 41

3 3

LED+LID/B

page 41

RTC CKT.

page 24

HDMI Conn.

page 23

RJ45

page 35

RTL8105E-VD 10/100M

PCIe port 1

page 35

SPI ROM
(4MB + 2MB)

page 24

PCIe Gen1 1x

1.5V 5GT/s

Debug Port

page 41

Panther Point

FCBGA-989

25mm*25mm

page 24,25,26,27,28,29,30,31,32

LPC BUS

3.3V 33 MHz

KB9012

page 40

HD Audio

3.3V 24MHz

USB20 3x

5V 480MHz

USB20 2x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

SATA Gen3 port 0

5V 6GHz(600MB/s)

SATA Gen3 port 1

5V 3GHz(300MB/s)

HDA Codec

ALC259

page 38

USB Left

USB20 port 2

page 37

CardReader RTS5137

PCIeMini Card
WLAN

SATA HDD

SATA mSATA

PCIe port 2

page 34

SATA port 0

page 33

SATA port 1

page 34

USB Right

USB20 port 0,1
USB30 port 1,2

page 37

USB20 port 8

page 36

Int. Camera

USB port 11

page 22

DC/DC Interface CKT.

page 42

Power Circuit DC/DC

page 43,44,45,46,47,48,
49,50,51

Touch Pad

Int.KBD

page 41page 41

SPK Conn

page 39

JPIO
(HP & MIC)

page 39

Power On/Off CKT.

4 4

page 41

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

Block Diagram

Block Diagram

VCUAA

VCUAA

VCUAA

253Tuesday, October 16, 2012

253Tuesday, October 16, 2012

253Tuesday, October 16, 2012

E

1.0

1.0

1.0

of

of

of

5

4

3

2

1

DESIGN CURRENT 0.1A

B+

D D

Ipeak=8.13A, Imax=5.69A, Iocp min=8.7

SUSP#

SY8033BDBC

DESIGN CURRENT 0.1A

DESIGN CURRENT 5A

DESIGN CURRENT 2A

+3VL
+5VL

+5VALW

+1.8VS

SUSP

N-CHANNEL

SI4800

RT8205LZQW

C C

VCCP_PWRGOOD

SY8037

Ipeak=6A, Imax=4.A, Iocp min=8

Ipeak=5A, Imax=3.5A, Iocp min=6.2A

SUSP

N-CHANNEL

SI4800

WOL_EN#

P-CHANNEL

AO-3413

LCD_ENVDD

P-CHANNEL

AO-3413

DGPU_PWR_EN

P-CHANNEL

AO-3413

VR_ON

PJ6

NCP6132A

DESIGN CURRENT 4A

DESIGN CURRENT 6A

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

DESIGN CURRENT 60mA

DESIGN CURRENT 2A

DESIGN CURRENT 94A

DESIGN CURRENT 33A

+5VS

+VCCSA

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+3VS_DGPU

+3V_WLAN

+CPU_CORE
+GFX_CORE

SUSP#

B B

TPS51212

Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A

VGA_PWROK

P-CHANNEL

AO-3413

DESIGN CURRENT 60mA

+1.05VS_VCCP

+1.05VS_DGPU

SYSON

RT8207M

Ipeak=15A, Imax=10.5A, Iocp min=18A

SUSP

N-CHANNEL
FDS6676AS

PJ1

SUSP or 0.75VR_EN#

DESIGN CURRENT 10A

DESIGN CURRENT 2A

DESIGN CURRENT 2A

DESIGN CURRENT 1.5A

+1.5V

+1.5V_CPU

+1.5VS

+0.75VS

VGA_PWROK

A A

SUSP#

TPS51518RUKR

5

N-CHANNEL
FDS6676AS

Ipeak=33.8A, Imax=23.4A, Iocp min=40A

4

DESIGN CURRENT 8.6A

DESIGN CURRENT 20.5A

+VRAM_1.5VS

+VGA_CORE

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

2

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

Power Tree

Power Tree

Power Tree

VCUAA

VCUAA

VCUAA

1

of

353Tuesday, October 16, 2012

of

353Tuesday, October 16, 2012

of

353Tuesday, October 16, 2012

1.0

1.0

1.0

A

Voltage Rails

power
plane

1 1

State

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+5VL
+3VL

+5VALW
+3VALW
+VSB

B

Platform

+1.5V

+5VS
+3VS
+1.8VS
+1.5VS
+1.05VS
+0.75VS
+CPU_CORE
+VGA_CORE
+GFX_CORE
+VTT
+VRAM_1.5VS
+3VS_DGPU
+1.05VS_DGPU

Chief River

BTO Option Table

Function

description

explain

BTO

C

SKU CPU PCH

Ivy Bridge i3
(CPUI3@)
Ivy Bridge i5
(CPUI5@)

SKU MIC

HM77C1(HM77@)
HM77C1_R1(HM77R1@)
HM77C1_R3(HM77R3@)

LAN

D

E

VGA

nVIDIA N13P-GL
(N13PGL@)

S0

S1

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery
don't exist

O
O
O
O
O
O

O
O
O
O
O

X

O
O
O
O
O

X

O
O
O
O

X
X

O

XX
X
XX

OO
OO

X

Function

description

X

explain

BTO

Function

PCH SM Bus Address

Power

+3VS
+3VS

Device

DDR SO-DIMM 0
DDR SO-DIMM 1

HEX

Address

1010 0000 bA0 H
1010 0100 bA4 H

description

explain

BTO

Function

3 3

description

explain

BTO

EC SM Bus1 Address

Device Address Address

+3VL

EC SM Bus2 Address

HEX HEX

16 H

0001 0110 bSmart Battery

12 HSmart Charger 0001 0010 b+3VL

PowerPower

+3VS
+3VS

HEXDevice AddressPower

Device

96 H

NVIDIA GPU 1001 1010 b

9E H

STATE

Full ON

1001 0110 bPCH

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

SIGNAL

SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

HIGH HIGHHIGH

HIGH

LOW LOWLOW

HIGH

HIGH

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

Notes List

Notes List

VCUAA

VCUAA

VCUAA

453Tuesday, October 16, 2012

453Tuesday, October 16, 2012

453Tuesday, October 16, 2012

E

1.0

1.0

1.0

of

of

of

A

@

@

PM_DRAM_PWRGD_R

CC621000P_0402_50V7K

CC621000P_0402_50V7K

12

@

@

12

1 1

+1.05VS_VCCP

RC44 62_0402_5%RC44 62_0402_5%

RC45 10K_0402_5%RC45 10K_0402_5%

2 2

+3VALW_PCH

RC11 200_0402_5%RC11 200_0402_5%

PM_PWROK<26,40>
DRAMPWROK<26>

3 3

12

12

@

@

12

@

@

12

@

@

12

Please place near JCPU

DRAMPWROK

12

10K_0402_5%

10K_0402_5%

RC13

RC13

+3VS

1 2

RC12 0_0402_5%@RC12 0_0402_5%@

CC631000P_0402_50V7K

CC631000P_0402_50V7K

CC701000P_0402_50V7K

CC701000P_0402_50V7K

CC671000P_0402_50V7K

CC671000P_0402_50V7K

CC661000P_0402_50V7K

CC661000P_0402_50V7K

12

1 2

RC184

RC184

SUSP<34,42,9>

H_PWRGOOD_R

H_PROCHOT#

H_PWRGOOD

H_PM_SYNC

BUF_CPU_RST#

+3VALW_PCH

5

1

P

B

2

A

G

3

H_PECI

12

0.1U_0402_10V7K

0.1U_0402_10V7K
CC33

CC33

UC3

UC3
74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

PM_SYS_PWRGD_BUF

4

O

0_0402_5%@

0_0402_5%@

SUSP

QC2

QC2

2

G

G

12

RC25

RC25
39_0402_5%

39_0402_5%
@

@

13

D

D

2N7002KW_SOT323-3

2N7002KW_SOT323-3

@

@

S

S

Buffered Rest to CPU

+3VS

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CC36

CC36

PLT_RST# <28,34,35,40,41>

UC2

PLT_RST#

4 4

UC2

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

74AHC1G125GW_SOT353-5

2

5

VCC

BUFO_CPU_RST# BUF_CPU_RST#

4

OUT

+1.05VS_VCCP

12

RC38

RC38
75_0402_5%

75_0402_5%

43_0402_1%

43_0402_1%

1 2

RC35

RC35

12

RC40

RC40
0_0402_5%

0_0402_5%
@

@

H_PROCHOT#<40>

H_THERMTRIP#<29>

H_PM_SYNC<26>

H_PWRGOOD<29>

+1.5V_CPU

12

RC14

RC14
200_0402_5%

200_0402_5%

B

H_SNB_IVB#<29>

T1 PADT1 PAD

T2 PADT2 PAD

H_PECI<40>

1 2

RC170 130_0402_5%RC170 130_0402_5%

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

H_PECI

RC159

RC159

H_PROCHOT#_R

1 2

56_0402_5%

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

@

@

H_PWRGOOD_R

1 2

RC183 0_0402_5%

RC183 0_0402_5%

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

UC1B

UC1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

XDP Connector

C

MISC THERMAL PWR MANAGEMENT

MISC THERMAL PWR MANAGEMENT

CLOCKS

CLOCKS

DDR3

DDR3

JTAG & BPM

JTAG & BPM

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISC

MISC

BCLK

BCLK#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#

PREQ#

TCK
TMS

TRST#

TDO

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

J3
H2

AG3
AG1

AT30

BF44
BE43
BG43

N53
N55

L56
L55
J58

M60

TDI

L59

K58

G58
E55
E59
G55
G59
H60
J59
J61

10U_0805_10V6K

10U_0805_10V6K

D

100 MHz

CLK_CPU_DMI
CLK_CPU_DMI#

DPLL_REF_CLK
DPLL_REF_CLK#

H_DRAMRST#

SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2

XDP_TCK
XDP_TMS
XDP_TRST#

XDP_TDI
XDP_TDO

RC56 140_0402_1%RC56 140_0402_1%
RC59 25.5_0402_1%RC59 25.5_0402_1%
RC61 200_0402_1%RC61 200_0402_1%

CLK_CPU_DMI <25>
CLK_CPU_DMI# <25>

H_DRAMRST# <7>

12
12
12

T3 PAD@T3 PAD@
T4 PAD@T4 PAD@

1 2

RC55 51_0402_5%RC55 51_0402_5%

T6 PAD@T6 PAD@
T7 PAD@T7 PAD@

Close to CPU side

+5VS +3VS

1A

@

@

2

C3

C3

1

@

@

1 2

R1 0_0603_5%

R1 0_0603_5%

+FAN1

FAN_SPEED1<40>

DPLL_REF_CLK#
DPLL_REF_CLK

H_DRAMRST#

RC157 1K_0402_5%RC157 1K_0402_5%
RC158 1K_0402_5%RC158 1K_0402_5%

CC34 180P_0402_50V8J

CC34 180P_0402_50V8J

by ESD requestion and place near CPU

DDR3 Compensation Signals
Layout Note:Place these
resistors near Processor

Routed as a single daisy chain

FAN Control Circuit

12

R2

R2
10K_0402_5%

10K_0402_5%

FANPWM<40>

D1

D1

BAS16_SOT23-3

BAS16_SOT23-3

+FAN1

1

C4

C4

0.01U_0402_25V7K

0.01U_0402_25V7K
@

@

2

E

1 2
1 2

@

@

1 2

12

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

C5

C5

+1.05VS_VCCP

JFAN

@JFAN

@

7

GND2

6

GND1

5

5

4

4

3

3

2

2

1

1

ACES_88266-05001

ACES_88266-05001

1

C6

C6

2

1000P_0402_50V7K

1000P_0402_50V7K

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_JTAG/XDP/FAN

Ivy Bridge_JTAG/XDP/FAN

Ivy Bridge_JTAG/XDP/FAN

VCUAA

VCUAA

VCUAA

E

of

of

of

553Tuesday, October 16, 2012

553Tuesday, October 16, 2012

553Tuesday, October 16, 2012

1.0

1.0

1.0

A

B

C

D

E

+1.05VS_VCCP

RC1

RC1

24.9_0402_1%

UC1A

UC1A

1 1

2 2

+1.05VS_VCCP
+1.05VS_VCCP

3 3

DMI_PTX_CRX_N0<26>
DMI_PTX_CRX_N1<26>
DMI_PTX_CRX_N2<26>
DMI_PTX_CRX_N3<26>

DMI_PTX_CRX_P0<26>
DMI_PTX_CRX_P1<26>
DMI_PTX_CRX_P2<26>
DMI_PTX_CRX_P3<26>

DMI_CTX_PRX_N0<26>
DMI_CTX_PRX_N1<26>
DMI_CTX_PRX_N2<26>
DMI_CTX_PRX_N3<26>

DMI_CTX_PRX_P0<26>
DMI_CTX_PRX_P1<26>
DMI_CTX_PRX_P2<26>
DMI_CTX_PRX_P3<26>

FDI_CTX_PRX_N0<26>
FDI_CTX_PRX_N1<26>
FDI_CTX_PRX_N2<26>
FDI_CTX_PRX_N3<26>
FDI_CTX_PRX_N4<26>
FDI_CTX_PRX_N5<26>
FDI_CTX_PRX_N6<26>
FDI_CTX_PRX_N7<26>

FDI_CTX_PRX_P0<26>
FDI_CTX_PRX_P1<26>
FDI_CTX_PRX_P2<26>
FDI_CTX_PRX_P3<26>
FDI_CTX_PRX_P4<26>
FDI_CTX_PRX_P5<26>
FDI_CTX_PRX_P6<26>
FDI_CTX_PRX_P7<26>

FDI_FSYNC0<26>
FDI_FSYNC1<26>

FDI_INT<26>
FDI_LSYNC0<26>

FDI_LSYNC1<26>

RC2 24.9_0402_1%RC2 24.9_0402_1%

1 2

RC333 1K_0402_5%RC333 1K_0402_5%

1 2

DMI_PTX_CRX_N0
DMI_PTX_CRX_N1
DMI_PTX_CRX_N2
DMI_PTX_CRX_N3

DMI_PTX_CRX_P0
DMI_PTX_CRX_P1
DMI_PTX_CRX_P2
DMI_PTX_CRX_P3

DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3

DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3

FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7

FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7

FDI_FSYNC0
FDI_FSYNC1

FDI_INT
FDI_LSYNC0

FDI_LSYNC1

EDP_COMP

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

DMI Intel(R) FDI

DMI Intel(R) FDI

eDP

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PCI EXPRESS -- GRAPHICS

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

G3
G1
G4

PCIE_GTX_C_CRX_N0

H22

PCIE_GTX_C_CRX_N1

J21

PCIE_GTX_C_CRX_N2

B22

PCIE_GTX_C_CRX_N3

D21

PCIE_GTX_C_CRX_N4

A19

PCIE_GTX_C_CRX_N5

D17

PCIE_GTX_C_CRX_N6

B14

PCIE_GTX_C_CRX_N7

D13

PCIE_GTX_C_CRX_N8

A11

PCIE_GTX_C_CRX_N9

B10

PCIE_GTX_C_CRX_N10

G8

PCIE_GTX_C_CRX_N11

A8

PCIE_GTX_C_CRX_N12

B6

PCIE_GTX_C_CRX_N13

H8

PCIE_GTX_C_CRX_N14

E5

PCIE_GTX_C_CRX_N15

K7

PCIE_GTX_C_CRX_P0

K22

PCIE_GTX_C_CRX_P1

K19

PCIE_GTX_C_CRX_P2

C21

PCIE_GTX_C_CRX_P3

D19

PCIE_GTX_C_CRX_P4

C19

PCIE_GTX_C_CRX_P5

D16

PCIE_GTX_C_CRX_P6

C13

PCIE_GTX_C_CRX_P7

D12

PCIE_GTX_C_CRX_P8

C11

PCIE_GTX_C_CRX_P9

C9

PCIE_GTX_C_CRX_P10

F8

PCIE_GTX_C_CRX_P11

C8

PCIE_GTX_C_CRX_P12

C5

PCIE_GTX_C_CRX_P13

H6

PCIE_GTX_C_CRX_P14

F6

PCIE_GTX_C_CRX_P15

K6

PCIE_CTX_GRX_N0

G22

PCIE_CTX_GRX_N1

C23

PCIE_CTX_GRX_N2

D23

PCIE_CTX_GRX_N3

F21

PCIE_CTX_GRX_N4

H19

PCIE_CTX_GRX_N5

C17

PCIE_CTX_GRX_N6

K15

PCIE_CTX_GRX_N7

F17

PCIE_CTX_GRX_N8

F14

PCIE_CTX_GRX_N9

A15

PCIE_CTX_GRX_N10

J14

PCIE_CTX_GRX_N11

H13

PCIE_CTX_GRX_N12

M10

PCIE_CTX_GRX_N13

F10

PCIE_CTX_GRX_N14

D9

PCIE_CTX_GRX_N15

J4

PCIE_CTX_GRX_P0

F22

PCIE_CTX_GRX_P1

A23

PCIE_CTX_GRX_P2

D24

PCIE_CTX_GRX_P3

E21

PCIE_CTX_GRX_P4

G19

PCIE_CTX_GRX_P5

B18

PCIE_CTX_GRX_P6

K17

PCIE_CTX_GRX_P7

G17

PCIE_CTX_GRX_P8

E14

PCIE_CTX_GRX_P9

C15

PCIE_CTX_GRX_P10

K13

PCIE_CTX_GRX_P11

G13

PCIE_CTX_GRX_P12

K10

PCIE_CTX_GRX_P13

G10

PCIE_CTX_GRX_P14

D8

PCIE_CTX_GRX_P15

K4

PEG_COMP

24.9_0402_1%

CC8 0.22U_0402_16V7KOPT@CC8 0.22U_0402_16V7KOPT@
CC11 0.22U_0402_16V7KOPT@CC11 0.22U_0402_16V7KOPT@
CC16 0.22U_0402_16V7KOPT@CC16 0.22U_0402_16V7KOPT@
CC20 0.22U_0402_16V7KOPT@CC20 0.22U_0402_16V7KOPT@
CC27 0.22U_0402_16V7KOPT@CC27 0.22U_0402_16V7KOPT@
CC30 0.22U_0402_16V7KOPT@CC30 0.22U_0402_16V7KOPT@
CC1 0.22U_0402_16V7KOPT@CC1 0.22U_0402_16V7KOPT@
CC4 0.22U_0402_16V7KOPT@CC4 0.22U_0402_16V7KOPT@
CC15 0.22U_0402_16V7KOPT@CC15 0.22U_0402_16V7KOPT@
CC18 0.22U_0402_16V7KOPT@CC18 0.22U_0402_16V7KOPT@
CC22 0.22U_0402_16V7KOPT@CC22 0.22U_0402_16V7KOPT@
CC24 0.22U_0402_16V7KOPT@CC24 0.22U_0402_16V7KOPT@
CC29 0.22U_0402_16V7KOPT@CC29 0.22U_0402_16V7KOPT@
CC26 0.22U_0402_16V7KOPT@CC26 0.22U_0402_16V7KOPT@
CC3 0.22U_0402_16V7KOPT@CC3 0.22U_0402_16V7KOPT@
CC32 0.22U_0402_16V7KOPT@CC32 0.22U_0402_16V7KOPT@

CC10 0.22U_0402_16V7KOPT@CC10 0.22U_0402_16V7KOPT@
CC5 0.22U_0402_16V7KOPT@CC5 0.22U_0402_16V7KOPT@
CC6 0.22U_0402_16V7KOPT@CC6 0.22U_0402_16V7KOPT@
CC7 0.22U_0402_16V7KOPT@CC7 0.22U_0402_16V7KOPT@
CC12 0.22U_0402_16V7KOPT@CC12 0.22U_0402_16V7KOPT@
CC9 0.22U_0402_16V7KOPT@CC9 0.22U_0402_16V7KOPT@
CC19 0.22U_0402_16V7KOPT@CC19 0.22U_0402_16V7KOPT@
CC14 0.22U_0402_16V7KOPT@CC14 0.22U_0402_16V7KOPT@
CC13 0.22U_0402_16V7KOPT@CC13 0.22U_0402_16V7KOPT@
CC17 0.22U_0402_16V7KOPT@CC17 0.22U_0402_16V7KOPT@
CC21 0.22U_0402_16V7KOPT@CC21 0.22U_0402_16V7KOPT@
CC23 0.22U_0402_16V7KOPT@CC23 0.22U_0402_16V7KOPT@
CC28 0.22U_0402_16V7KOPT@CC28 0.22U_0402_16V7KOPT@
CC25 0.22U_0402_16V7KOPT@CC25 0.22U_0402_16V7KOPT@
CC2 0.22U_0402_16V7KOPT@CC2 0.22U_0402_16V7KOPT@
CC31 0.22U_0402_16V7KOPT@CC31 0.22U_0402_16V7KOPT@

PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils)
PEG_ICOMPO signals should be routed with ­max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

PCIE_GTX_C_CRX_N[0..15] <13>

PCIE_GTX_C_CRX_P[0..15] <13>

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2

PCIE_CTX_C_GRX_N0
PCIE_CTX_C_GRX_N1
PCIE_CTX_C_GRX_N2
PCIE_CTX_C_GRX_N3
PCIE_CTX_C_GRX_N4
PCIE_CTX_C_GRX_N5
PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N7
PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_N9
PCIE_CTX_C_GRX_N10
PCIE_CTX_C_GRX_N11
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_N15

PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P2
PCIE_CTX_C_GRX_P3
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P5
PCIE_CTX_C_GRX_P6
PCIE_CTX_C_GRX_P7
PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_P9
PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_P15

PCIE_CTX_C_GRX_N[0..15] <13>

PCIE_CTX_C_GRX_P[0..15] <13>

PEG DG suggest AC cap

IVY Bridge

Gen1/Gen2

Gen3

SANDY Bridge Gen1/Gen2 180 nF~265 nF

NV N13X Gen1/2/3 Suggest 220 nF

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

75 nF~265 nF

180 nF~265 nF

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DMI/PEG/FDI

Ivy Bridge_DMI/PEG/FDI

Ivy Bridge_DMI/PEG/FDI

VCUAA

VCUAA

VCUAA

653Tuesday, October 16, 2012

653Tuesday, October 16, 2012

653Tuesday, October 16, 2012

E

of

of

of

1.0

1.0

1.0

A

DDR_A_D[0..63]<11>

UC1C

UC1C

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6

1 1

2 2

DDR_A_BS0<11>
DDR_A_BS1<11>

3 3

DDR_A_BS2<11>

DDR_A_CAS#<11>
DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#

AP11

AJ10

AR11

AT13
AU13

BA13
BB11

AY13
AV14
AR14
AY17
AR19
BA14
AU14
BB14
BB17
BA45
AR43

AW48

BC48
BC45
AR45
AT48
AY48
BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56
AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53
AN55
AN52
AG55
AK56

BD37

BF36

BA28

BE39
BD39
AT41

AG6

AU6
AR6

BC7

AJ6
AL6
AJ8

AL8
AL7

AP6
AV9
AP8

BB7

BA7
BA9
BB9

SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]
SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

DDR SYSTEM MEMORY A

B

SA_CK[0]
SA_CK#[0]
SA_CKE[0]

SA_CK[1]
SA_CK#[1]
SA_CKE[1]

SA_CS#[0]
SA_CS#[1]

SA_ODT[0]
SA_ODT[1]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

C

DDR_B_D[0..63]<12>

UC1D

UC1D

DDRA_CLK0

AU36

DDRA_CLK0#

AV36

DDRA_CKE0

AY26

DDRA_CLK1 DDRB_CLK1

AT40

DDRA_CLK1# DDRB_CLK1#

AU40

DDRA_CKE1 DDRB_CKE1

BB26

DDRA_SCS0# DDRB_SCS0#

BB40

DDRA_SCS1#

BC41

DDRA_ODT0 DDRB_ODT0

AY40

DDRA_ODT1

BA41

DDR_A_DQS#0

AL11

DDR_A_DQS#1

AR8

DDR_A_DQS#2

AV11

DDR_A_DQS#3

AT17

DDR_A_DQS#4

AV45

DDR_A_DQS#5

AY51

DDR_A_DQS#6

AT55

DDR_A_DQS#7

AK55

DDR_A_DQS0

AJ11

DDR_A_DQS1

AR10

DDR_A_DQS2

AY11

DDR_A_DQS3

AU17

DDR_A_DQS4

AW45

DDR_A_DQS5

AV51

DDR_A_DQS6

AT56

DDR_A_DQS7

AK54

DDR_A_MA0

BG35

DDR_A_MA1

BB34

DDR_A_MA2

BE35

DDR_A_MA3

BD35

DDR_A_MA4

AT34

DDR_A_MA5

AU34

DDR_A_MA6

BB32

DDR_A_MA7

AT32

DDR_A_MA8

AY32

DDR_A_MA9

AV32

DDR_A_MA10

BE37

DDR_A_MA11

BA30

DDR_A_MA12

BC30

DDR_A_MA13

AW41

DDR_A_MA14

AY28

DDR_A_MA15

AU26

DDRA_CLK0 <11> DDRB_CLK0 <12>
DDRA_CLK0# <11>
DDRA_CKE0 <11> DDRB_CKE0 <12>

DDRA_CLK1 <11>
DDRA_CLK1# <11> DDRB_CLK1# <12>
DDRA_CKE1 <11>

DDRA_SCS0# <11>
DDRA_SCS1# <11> DDRB_SCS1# <12>

DDRA_ODT0 <11> DDRB_ODT0 <12>
DDRA_ODT1 <11> DDRB_ODT1 <12>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_BS0<12>
DDR_B_BS1<12>
DDR_B_BS2<12>

DDR_B_CAS#<12>
DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#

BD13
BF12

BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14
BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53
BF56
BE57
BC59
AY60
BE54
BG54

BA58
AW59
AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58
AG58
AG59

AM60

AL59
AF61
AH60

BG39
BD42
AT22

AV43
BF40
BD45

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17]
SB_DQ[18]
SB_DQ[19]

BF8

SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

SB_BS[0]
SB_BS[1]
SB_BS[2]

SB_CAS#
SB_RAS#
SB_WE#

D

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1]

BB36

SB_CK#[1]

BF27

SB_CKE[1]

BE41

SB_CS#[0]

BE47

SB_CS#[1]

AT43

SB_ODT[0]

BG47

SB_ODT[1]

AL3

SB_DQS#[0]

AV3

SB_DQS#[1]

BG11

SB_DQS#[2]

BD17

SB_DQS#[3]

BG51

SB_DQS#[4]

BA59

SB_DQS#[5]

AT60

SB_DQS#[6]

AK59

SB_DQS#[7]

AM2

SB_DQS[0]

AV1

SB_DQS[1]

BE11

SB_DQS[2]

BD18

SB_DQS[3]

BE51

SB_DQS[4]

BA61

SB_DQS[5]

AR59

SB_DQS[6]

AK61

SB_DQS[7]

DDR SYSTEM MEMORY B

DDR SYSTEM MEMORY B

BF32

SB_MA[0]

BE33

SB_MA[1]

BD33

SB_MA[2]

AU30

SB_MA[3]

BD30

SB_MA[4]

AV30

SB_MA[5]

BG30

SB_MA[6]

BD29

SB_MA[7]

BE30

SB_MA[8]

BE28

SB_MA[9]

BD43

SB_MA[10]

AT28

SB_MA[11]

AV28

SB_MA[12]

BD46

SB_MA[13]

AT26

SB_MA[14]

AU22

SB_MA[15]

DDRB_CLK0
DDRB_CLK0#
DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8

DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15

E

DDRB_CLK0# <12>

DDRB_CLK1 <12>
DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

+1.5V

RC75

RC75

0_0402_5%

0_0402_5%

1 2

@

@

QC3

QC3

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

G

G

2

1

CC37

CC37

0.047U_0402_25V6K

0.047U_0402_25V6K

2

H_DRAMRST#<5>

RC78

RC78

4.99K_0402_1%

4.99K_0402_1%

4 4

@

@

@

@

DRAMRST_CNTRL

DRAMRST_CNTRL_PCH<11,25>

EC_DRAMRST_CNTRL_PCH<40>

1 2

RC73 0_0402_5%

RC73 0_0402_5%

1 2

RC3 0_0402_5%

RC3 0_0402_5%

A

RC76

RC76

1K_0402_5%

1K_0402_5%

12

1 2

B

RC77

RC77
1K_0402_5%

1K_0402_5%

1

2

Request by ESD

SM_DRAMRST# <11,12>

CC35

CC35
180P_0402_50V8J

180P_0402_50V8J

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DDR3

Ivy Bridge_DDR3

Ivy Bridge_DDR3

VCUAA

VCUAA

VCUAA

753Tuesday, October 16, 2012

753Tuesday, October 16, 2012

753Tuesday, October 16, 2012

E

of

of

of

1.0

1.0

1.0

A

B

C

D

E

+CPU_CORE +1.05VS_VCCP

1 1

2 2

3 3

4 4

A

UC1F

UC1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

POWER

POWER

CORE SUPPLY

CORE SUPPLY

8.5A33A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]

VCCIO50
VCCIO51

1mA

VCCIO_SEL

VCCPQE[1]
VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20
AG15
AG16
AG17
AG20
AG21
AJ14
AJ15

+1.05VS_VCCP

W16
W17

BC22

+1.05VS_VCCP

AM25
AN22

H_CPU_SVIDALRT#

A44

H_CPU_SVIDCLK

B43

H_CPU_SVIDDAT

C44

VCCSENSE_R

F43

VSSSENSE_R

G43

AN16
AN17

Close to CPU

PEG IO AND DDR IO

PEG IO AND DDR IO

RAILS

RAILS

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

SENSE LINES SVID QUIET

B

For DDR

For PEG

1

CC71

CC71
1U_0402_6.3V6K

1U_0402_6.3V6K

2

RC94 0_0402_5%@RC94 0_0402_5%@
RC95 0_0402_5%

RC95 0_0402_5%

VCCIO_SENSE

VCCIO_SENSE_VSS

12
RC96

RC96
10_0402_1%

10_0402_1%

12
RC98

RC98
10_0402_1%

10_0402_1%

0.1U_0402_10V7K

0.1U_0402_10V7K
1 2

CC50

CC50

@

@

12

RC91

RC91
130_0402_5%

130_0402_5%

RC90 43_0402_1%RC90 43_0402_1%
RC88 0_0402_5%

RC88 0_0402_5%
RC92 0_0402_5%

+CPU_CORE

1 2

@

@

1 2

VCCIO_SENSE <47>

+1.05VS_VCCP

VCCIO_SENSE_VSS <47>

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC92 0_0402_5%

RC93

RC93
100_0402_1%

100_0402_1%

1 2

12

RC97

RC97
100_0402_1%

100_0402_1%

Close to CPU

C

+1.05VS_VCCP+1.05VS_VCCP

12

1 2

@

@

1 2

@

@

1 2

VCCSENSE <49>
VSSSENSE <49>

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Reserve 0.1u to avoid noise

0.1U_0402_10V7K

0.1U_0402_10V7K
1 2

CC49

CC49

@

@

RC89

RC89
75_0402_5%

75_0402_5%

VR_SVID_ALRT# <49>
VR_SVID_CLK <49>
VR_SVID_DAT <49>

Pull high resistor on VR side

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_POWER-1

Ivy Bridge_POWER-1

Ivy Bridge_POWER-1

VCUAA

VCUAA

VCUAA

853Tuesday, October 16, 2012

853Tuesday, October 16, 2012

853Tuesday, October 16, 2012

E

1.0

1.0

1.0

of

of

of

A

B

C

D

E

+GFX_CORE

UC1G

UC1G

29A

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

1 1

2 2

+GFX_CORE

12

RC105

RC105
100_0402_1%

100_0402_1%

Close to CPU

CC41

CC41

1

2

CC76

CC76

1

2

CC59

CC59
1

2

10U_0805_10V6K

10U_0805_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VCC_AXG_SENSE
VSS_AXG_SENSE

1 2

+1.8VS_VCCPLL

CC60

CC60
1

2

10U_0805_10V6K

10U_0805_10V6K

CC43

CC43
1

@

@

2

10U_0805_10V6K

10U_0805_10V6K

CC75

CC75
1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

RC106

RC106
100_0402_1%

100_0402_1%

CC61

CC61
1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

CC40

CC40

CC58

CC58

1

1

@

@

2

2

10U_0805_10V6K

10U_0805_10V6K

CC74

CC74

CC73

CC73

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0805_10V6K

10U_0805_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VCC_AXG_SENSE<49>
VSS_AXG_SENSE<49>

3 3

4 4

VCCPLL Decoupling:
1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

+VCCSA Decoupling:

@

@

1 2

RC119 0_0805_5%

RC119 0_0805_5%

+VCCSA

1
CC44

CC44

+

+

@

@

2

330U_D2_2VM_R6M

330U_D2_2VM_R6M

Place TOP IN BGA

CC42

CC42
1

2

10U_0805_10V6K

10U_0805_10V6K

Place BOT OUT BGA

CC77

CC77
1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

1.2A

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

6A

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

POWER

POWER

VREF

VREF

DDR3 - 1.5V RAILS

DDR3 - 1.5V RAILS

GRAPHICS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

1.8V RAIL

SA RAIL

SA RAIL

VCCSA VID

VCCSA VID

SM_VREF

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

VDDQ[1]
VDDQ[2]
VDDQ[3]
VDDQ[4]
VDDQ[5]
VDDQ[6]
VDDQ[7]
VDDQ[8]

VDDQ[9]
VDDQ[10]
VDDQ[11]
VDDQ[12]
VDDQ[13]
VDDQ[14]
VDDQ[15]
VDDQ[16]
VDDQ[17]
VDDQ[18]
VDDQ[19]
VDDQ[20]
VDDQ[21]
VDDQ[22]
VDDQ[23]
VDDQ[24]
VDDQ[25]
VDDQ[26]

1mA

VCCDQ[1]
VCCDQ[2]

QUIET RAILS

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

SENSE LINES

VCCSA_VID[0]
VCCSA_VID[1]

lines

lines

5A

+V_SM_VREF should
have 20 mil trace width

AY43

BE7
BG7

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

AM28
AN26

BC43
BA43

U10

D48
D49

+V_SM_VREF

+VREF_DQA_M3
+VREF_DQB_M3

CC57

CC57
1

2

CC82

CC82
1

2

+1.5V_CPU

1

CC72

CC72
1U_0402_6.3V6K

1U_0402_6.3V6K

2

1 2

RC111 0_0402_5%

RC111 0_0402_5%

H_VCCSA_VID0
H_VCCSA_VID1

Please kindly check whether
there is pull-down resister
in PWR-side or HW-side

CC65

CC65
1

2

0.1U_0402_10V7K

0.1U_0402_10V7K

Place TOP IN BGA

CC52

CC52

CC51

CC51

1

1

2

2

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

10U_0805_10V6K

CC80

CC80

CC81

CC81

1

1

2

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCSA_SENSE <48>

@

@

H_VCCSA_VID0 <48>
H_VCCSA_VID1 <48>

RC120 1K_0402_0.5%RC120 1K_0402_0.5%

RC109 1K_0402_0.5%RC109 1K_0402_0.5%

+1.5V_CPU Decoupling:
1X 330U (6m ohm), 6X 10U, 8X 1U

CC55

CC55
1

2

10U_0805_10V6K

10U_0805_10V6K

Place BOT OUT BGA

CC79

CC79
1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+1.5V_CPU

1 2
1 2

+1.5V_CPU

CC56

CC56

CC54

CC54
1

2

10U_0805_10V6K

10U_0805_10V6K

CC78

CC78
1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

VCCSA_VID0

10U_0805_10V6K

10U_0805_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

CC87

CC87
1

2

0

0

1

+

+

10U_0805_10V6K

10U_0805_10V6K

CC86

CC86
1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

CC53

CC53

@

@

330U_D2_2VM_R6M

330U_D2_2VM_R6M

2

ESR 6mohm

CC85

CC85
1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

VCCSA_VID1

0

1

0

CC84

CC84
1

@

@

2

11

+1.5V_CPU +1.5V

CC46 0.1U_0402_10V7KCC46 0.1U_0402_10V7K

1 2

CC47 0.1U_0402_10V7KCC47 0.1U_0402_10V7K

1 2

CC48 0.1U_0402_10V7KCC48 0.1U_0402_10V7K

1 2

CC45 0.1U_0402_10V7KCC45 0.1U_0402_10V7K

1 2

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

SUSP

CC83

CC83
1

@

@

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

+VCCSA

0.90 V

0.80 V

0.725 V

0.675 V

Vgs=10V,Id=14.5A,Rds=6mohm

RC203

RC203

470_0805_5%

470_0805_5%

1 2
34

QC5B

QC5B

5

For Sandy Bridge

1

CC68

CC68
10U_0805_10V6K

10U_0805_10V6K
@

@

2

0.1U_0402_25V6

0.1U_0402_25V6

CC69

CC69

2

JUMP_43X118

JUMP_43X118
QC4

QC4

1

S

2

S

3

S

4

G

FDS6676AS_SO8

FDS6676AS_SO8

1

2

PJ1

@PJ1

@

112

8

D

7

D

6

D

5

D

RUN_ON_CPU1.5VS3

12

RC205

RC205
820K_0402_5%

820K_0402_5%

+1.5VS+1.5V_CPU

C464

C464

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 2

C463

C463

+1.5V

1 2

1U_0402_6.3V6K

1U_0402_6.3V6K

1 2

C469

C469

4.7U_0805_10V4Z

4.7U_0805_10V4Z

220K_0402_5%

220K_0402_5%

61

QC5A

QC5A

2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

@

@

@

@

RC204

RC204

1 2

SUSP

2

+VSB

SUSP <34,42,5>

1X 330U (6m ohm), 3X 10U, 5X 1U

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_POWER-2

Ivy Bridge_POWER-2

Ivy Bridge_POWER-2

VCUAA

VCUAA

VCUAA

953Tuesday, October 16, 2012

953Tuesday, October 16, 2012

953Tuesday, October 16, 2012

E

1.0

1.0

1.0

of

of

of

UC1H

UC1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

AA13
AA50
AA51
AA52
AA53
AA55
AA56

AB16
AB18
AB21
AB48
AB61
AC10
AC14
AC46

AD17
AD20

AD61
AE13

AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59
AG10
AG14
AG18
AG47
AG52
AG61

AG7
AH4

AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AK1

AK52

AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47

AL61
AM13
AM20
AM22
AM26
AM30
AM34

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]

AA8

VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]

AC6

VSS[30]
VSS[31]
VSS[32]

AD4

VSS[33]
VSS[34]
VSS[35]

AE8

VSS[36]

AF1

VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]

AJ7

VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]

1 1

2 2

3 3

A

VSS

VSS

VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]

AM38
AM4
AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54
AP10
AP51
AP55
AP7
AR13
AR17
AR21
AR41
AR48
AR61
AR7
AT14
AT19
AT36
AT4
AT45
AT52
AT58
AU1
AU11
AU28
AU32
AU51
AU7
AV17
AV21
AV22
AV34
AV40
AV48
AV55
AW13
AW43
AW61
AW7
AY14
AY19
AY30
AY36
AY4
AY41
AY45
AY49
AY55
AY58
AY9
BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53
BC13
BC5
BC57
BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56
BD8
BE5
BG13

UC1I

UC1I

BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53

BG9
C29
C35
C40
D10
D14
D18
D22
D26
D29
D35

D4
D40
D43
D46
D50
D54
D58

D6

E25
E29

E3
E35
E40
F13
F15
F19
F29
F35
F40
F55

G51

G6
G61
H10
H14
H17
H21

H4
H53
H58

J1
J49
J55
K11
K21
K51

K8
L16
L20
L22
L26
L30
L34
L38
L43
L48
L61

M11
M15

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]

B

VSS

VSS

VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8

VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11

NCTF

NCTF

VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14

M4
M58
M6
N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61
P14
P16
P18
P21
P58
P59
P9
R17
R20
R4
R46
T1
T47
T50
T51
T52
T53
T55
T56
U13
U8
V20
V61
W13
W15
W18
W21
W46
W8
Y4
Y47
Y58
Y59
G48

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

C

UC1E

UC1E

CFG0

B50

T89 PAD@T89 PAD@

CFG2
CFG4

CFG5
CFG6
CFG7

@

T87PAD@T87PAD

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

BCLK_ITP

BCLK_ITP#

RSVD30
RSVD31
RSVD32
RSVD33

RSVD34
RSVD35
RSVD36
RSVD37
RSVD38

RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44

RESERVED

RESERVED

RSVD45

These pins are for solder joint
reliability and non-critical to
function. For BGA only.

DC_TEST_A4
DC_TEST_C4
DC_TEST_D3

DC_TEST_D1
DC_TEST_A58
DC_TEST_A59
DC_TEST_C59
DC_TEST_A61
DC_TEST_C61
DC_TEST_D61

DC_TEST_BD61
DC_TEST_BE61
DC_TEST_BE59
DC_TEST_BG61
DC_TEST_BG59
DC_TEST_BG58

DC_TEST_BG4
DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

D

N59
N58

N42
L42
L45
L47

M13
M14
U14
W14
P13

AT49
K24

AH2
AG13
AM14
AM15

N50

A4
C4

DC_TEST_C4_D3

D3
D1
A58
A59

DC_TEST_A59_C59

C59
A61

DC_TEST_A61_C61

C61
D61
BD61
BE61

DC_TEST_BE61_BE59

BE59
BG61

DC_TEST_BG61_BG59

BG59
BG58
BG4
BG3

DC_TEST_BG3_BE3

BE3
BG1

DC_TEST_BG1_BE1

BE1
BD1

E

CFG Straps for Processor

(CFG[17:0] internal pull high 5~15K to VCCIO)

CFG2

12

RC79

RC79
1K_0402_1%

1K_0402_1%
OPT@

OPT@

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition

CFG2

matches socket pin map definition
0:Lane Reversed

*

CFG4

12

RC82

RC82
1K_0402_1%

1K_0402_1%
@

@

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port

*

CFG4

attached to Embedded Display Port
0 : Enabled; An external Display Port

device is connected to the Embedded
Display Port

CFG7

12

RC85

RC85
1K_0402_1%

1K_0402_1%
@

@

PEG DEFER TRAINING

1: (Default) PEG Train immediately

*

CFG7

following xxRESETB de assertion
0: PEG Wait for BIOS for training

CFG6
CFG5

1K_0402_1%

1K_0402_1%

RC83

RC83

12

12

RC84

RC84
1K_0402_1%

1K_0402_1%

@

@

@

@

PCIE Port Bifurcation Straps

IVY-BRIDGE_BGA1023 <BOM>

IVY-BRIDGE_BGA1023 <BOM>

CFG[6:5]

4 4

11: (Default) x16 - Device 1 functions 1 and 2

*

disabled
10: x8, x8 - Device 1 function 1 enabled;

function 2 disabled
01: Reserved - (Device 1 function 1 disabled;

function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_GND/RSVD/CFG

Ivy Bridge_GND/RSVD/CFG

Ivy Bridge_GND/RSVD/CFG

VCUAA

VCUAA

VCUAA

E

of

of

of

10 53Tuesday, October 16, 2012

10 53Tuesday, October 16, 2012

10 53Tuesday, October 16, 2012

1.0

1.0

1.0

A

+VREF_DQA

1

CD1

CD1

CD2

CD2

0.1U_0402_10V7K

0.1U_0402_10V7K
2

1 1

Close to JDDR3R.1

DDR_A_BS2<7>

2 2

DDRA_CLK0<7>
DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

3 3

+3VS

CD25

CD25

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

@

@

4 4

DDR_A_D0
DDR_A_D1

1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
2

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D9

DDR_A_DQS#1
DDR_A_DQS1

DDR_A_D10
DDR_A_D11

DDR_A_D16
DDR_A_D17

DDR_A_DQS#2
DDR_A_DQS2

DDR_A_D18
DDR_A_D19

DDR_A_D24
DDR_A_D25

DDR_A_D26
DDR_A_D27

DDRA_CKE0

DDR_A_BS2
DDR_A_MA12

DDR_A_MA9
DDR_A_MA8

DDR_A_MA5
DDR_A_MA3

DDR_A_MA1
DDRA_CLK0

DDRA_CLK0#
DDR_A_MA10

DDR_A_BS0
DDR_A_WE#

DDR_A_CAS#
DDR_A_MA13

DDRA_SCS1#

DDR_A_D32
DDR_A_D33

DDR_A_DQS#4
DDR_A_DQS4

DDR_A_D34
DDR_A_D35

DDR_A_D40
DDR_A_D41

DDR_A_D42
DDR_A_D43

DDR_A_D48
DDR_A_D49

DDR_A_DQS#6
DDR_A_DQS6

DDR_A_D50
DDR_A_D51

DDR_A_D56
DDR_A_D57

DDR_A_D58
DDR_A_D59

RD8

RD8

1 2

10K_0402_5%

10K_0402_5%

1

1

CD26

CD26

10K_0402_5%

10K_0402_5%

2

2

0.1U_0402_10V7K

0.1U_0402_10V7K

SPD setting (SA0, SA1)
PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

RD9

RD9

12

+0.75VS

+1.5V

JDDR3R

JDDR3R

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103
@

@

VSS
DQ4
DQ5
VSS

DQS0#

DQS0

VSS
DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

RESET#

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3#

DQS3

VSS
DQ30
DQ31

VSS

CKE1

VDD

VDD

VDD

VDD

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD
ODT1

VDD

VREF_CA

VSS
DQ36
DQ37

VSS

DM4

VSS
DQ38
DQ39

VSS
DQ44
DQ45

VSS

DQS5#

DQS5

VSS
DQ46
DQ47

VSS
DQ52
DQ53

VSS

DM6

VSS
DQ54
DQ55

VSS
DQ60
DQ61

VSS

DQS7#

DQS7

VSS
DQ62
DQ63

VSS

EVENT#

SDA

SCL

VTT
GND2

BOSS2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84

A11

86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108
110
112
114
116
118
120
122

NC

124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206
208

+1.5V

DDR_A_D4
DDR_A_D5

DDR_A_DQS#0
DDR_A_DQS0

DDR_A_D6
DDR_A_D7

DDR_A_D12
DDR_A_D13

SM_DRAMRST#
DDR_A_D14

DDR_A_D15
DDR_A_D20

DDR_A_D21

DDR_A_D22
DDR_A_D23

DDR_A_D28
DDR_A_D29

DDR_A_DQS#3
DDR_A_DQS3

DDR_A_D30
DDR_A_D31

DDRA_CKE1
DDR_A_MA15

DDR_A_MA14
DDR_A_MA11

DDR_A_MA7
DDR_A_MA6

DDR_A_MA4
DDR_A_MA2

DDR_A_MA0
DDRA_CLK1

DDRA_CLK1#
DDR_A_BS1

DDR_A_RAS#
DDRA_SCS0#

DDRA_ODT0
DDRA_ODT1

+VREF_CAA
DDR_A_D36

DDR_A_D37

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

DDR_A_DQS#5
DDR_A_DQS5

DDR_A_D46
DDR_A_D47

DDR_A_D52
DDR_A_D53

DDR_A_D54
DDR_A_D55

DDR_A_D60
DDR_A_D61

DDR_A_DQS#7
DDR_A_DQS7

DDR_A_D62
DDR_A_D63

PM_SMBDATA
PM_SMBCLK

+0.75VS

B

B

DDR3 SO-DIMM A
Reverse Type

Intel DDR Vref M3

SM_DRAMRST# <12,7>

DDRA_CKE1 <7>DDRA_CKE0<7>

DDRA_CLK1 <7>
DDRA_CLK1# <7>

DDR_A_BS1 <7>
DDR_A_RAS# <7>

DDRA_SCS0# <7>
DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

CD15

CD15

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

close to JDDR3R.126

PM_SMBDATA <12,25,34,41>
PM_SMBCLK <12,25,34,41>

1

CD16

CD16

0.1U_0402_10V7K

0.1U_0402_10V7K

2

2

C

DDR_A_DQS[0..7] <7>
DDR_A_DQS#[0..7] <7>
DDR_A_D[0..63] <7>
DDR_A_MA[0..15] <7>

@

@

12

0_0402_5%

0_0402_5%

RC115

RC115

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

QC7

QC7

D

S

D

S

+VREF_DQA_M3

@

@

1 2

RC117 1K_0402_1%

RC117 1K_0402_1%

@

@

1 2

RC118 1K_0402_1%

RC118 1K_0402_1%

+VREF_DQB_M3

+1.5V

12

RD6

RD6

1K_0402_1%

1K_0402_1%

12

RD7

RD7

1K_0402_1%

1K_0402_1%

Layout Note:
Place near JDDRH

+1.5V

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

@

@

1 2

CD3 330U_D2_2VM_R6M

CD3 330U_D2_2VM_R6M

+

+

CD8 10U_0603_6.3V6MCD8 10U_0603_6.3V6M

1 2

CD9 10U_0603_6.3V6MCD9 10U_0603_6.3V6M

1 2

CD10 10U_0603_6.3V6MCD10 10U_0603_6.3V6M

1 2

CD11 10U_0603_6.3V6MCD11 10U_0603_6.3V6M

1 2

CD12 10U_0603_6.3V6MCD12 10U_0603_6.3V6M

1 2

CD13 10U_0603_6.3V6MCD13 10U_0603_6.3V6M

1 2

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

13

G

G

2

G

G

2

13

D

S

D

S

QC8

QC8

BSS138_NL_SOT23-3

BSS138_NL_SOT23-3

@

@

12

0_0402_5%

0_0402_5%

RC116

RC116

+1.5V

1 2

CD50 33P_0402_50V8KCD50 33P_0402_50V8K

1 2

CD51 33P_0402_50V8KCD51 33P_0402_50V8K

1 2

CD52 33P_0402_50V8KCD52 33P_0402_50V8K

1 2

CD53 33P_0402_50V8KCD53 33P_0402_50V8K

1 2

CD54 33P_0402_50V8KCD54 33P_0402_50V8K

1 2

CD55 33P_0402_50V8KCD55 33P_0402_50V8K

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

+VREF_DQA

DRAMRST_CNTRL_PCH <25,7>

+VREF_DQB

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMA

+1.5V +0.75VS

CD20 0.1U_0402_10V7KCD20 0.1U_0402_10V7K

1 2

CD17 0.1U_0402_10V7KCD17 0.1U_0402_10V7K

1 2

CD18 0.1U_0402_10V7KCD18 0.1U_0402_10V7K

1 2

CD19 0.1U_0402_10V7KCD19 0.1U_0402_10V7K

1 2

D

E

+1.5V

12

+VREF_DQA

+VREF_DQB

please place these caps near the
reference power plane of CMD/AD

Layout Note:
Place near JDDRH.203 and 204

CD56 10U_0603_6.3V6MCD56 10U_0603_6.3V6M

1 2

CD24 1U_0402_6.3V6KCD24 1U_0402_6.3V6K
CD21 1U_0402_6.3V6KCD21 1U_0402_6.3V6K
CD22 1U_0402_6.3V6KCD22 1U_0402_6.3V6K
CD23 1U_0402_6.3V6KCD23 1U_0402_6.3V6K

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM0

DDRIII-SODIMM0

DDRIII-SODIMM0

VCUAA

VCUAA

VCUAA

12

+1.5V

12

12

12
12
12
12

E

RD1

RD1

1K_0402_1%

1K_0402_1%

RD2

RD2

1K_0402_1%

1K_0402_1%

RD10

RD10

1K_0402_1%

1K_0402_1%

RD11

RD11

1K_0402_1%

1K_0402_1%

of

of

of

11 53Tuesday, October 16, 2012

11 53Tuesday, October 16, 2012

11 53Tuesday, October 16, 2012

1.0

1.0

1.0

A

+VREF_DQB

1

CD28

CD28

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M
2

1 1

Close to JDDR3S.1

DDRB_CKE0<7>

DDR_B_BS2<7>

2 2

DDRB_CLK0<7>
DDRB_CLK0#<7>

DDR_B_WE#<7>
DDR_B_CAS#<7>

DDRB_SCS1#<7>

3 3

+3VS

4 4

CD48

CD48

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

1

2

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K

CD27

CD27

0.1U_0402_10V7K

0.1U_0402_10V7K

CD49

CD49

1

2

RD14

RD14
10K_0402_5%

10K_0402_5%

RD15

RD15

1 2

10K_0402_5%

10K_0402_5%

DDR_B_D0
DDR_B_D1

DDR_B_D2
DDR_B_D3

DDR_B_D8
DDR_B_D9

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D10
DDR_B_D11

DDR_B_D16
DDR_B_D17

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19

DDR_B_D24
DDR_B_D25

DDR_B_D26
DDR_B_D27

DDRB_CKE0

DDR_B_BS2
DDR_B_MA12

DDR_B_MA9
DDR_B_MA8

DDR_B_MA5
DDR_B_MA3

DDR_B_MA1
DDRB_CLK0

DDRB_CLK0#
DDR_B_MA10

DDR_B_BS0
DDR_B_WE#

DDR_B_CAS#
DDR_B_MA13

DDRB_SCS1#

DDR_B_D32
DDR_B_D33

DDR_B_DQS#4
DDR_B_DQS4

DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41

DDR_B_D42
DDR_B_D43

DDR_B_D48
DDR_B_D49

DDR_B_DQS#6
DDR_B_DQS6

DDR_B_D50
DDR_B_D51

DDR_B_D56
DDR_B_D57

DDR_B_D58
DDR_B_D59

1 2

+0.75VS

+1.5V

JDDR3S

JDDR3S

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1
DQS129RESET#
VSS1131VSS12

33

DQ10

35

DQ11
VSS1337VSS14

39

DQ16

41

DQ17
VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25
VSS2261DQS#3

63

DM3
VSS2365VSS24

67

DQ26

69

DQ27
VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

LCN_DAN06-K4406-0102
@

@

DQ4
DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7
VSS8
DQ12
DQ13

VSS10

DM1

DQ14
DQ15

DQ20
DQ21

DM2

VSS17

DQ22
DQ23

VSS19

DQ28
DQ29

VSS21

DQS3

DQ30
DQ31

CKE1
VDD2

VDD4

VDD6

VDD8

VDD10

CK1
CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36
DQ37

VSS30

DM4

VSS31

DQ38
DQ39

VSS33

DQ44
DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46
DQ47

VSS40

DQ52
DQ53

VSS42

DM6

VSS43

DQ54
DQ55

VSS45

DQ60
DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62
DQ63

VSS52

EVENT#

SDA

SCL
VTT2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

74
76
78

A15

80

A14

82
84

A11

86

A7

88
90

A6

92

A4

94
96

A2

98

A0

100
102
104
106
108

BA1

110
112
114

S0#

116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

206

G2

B

+1.5V

DDR_B_D4
DDR_B_D5

DDR_B_DQS#0

DDR_B_DQS0

DDR_B_D6
DDR_B_D7

DDR_B_D12
DDR_B_D13

SM_DRAMRST#
DDR_B_D14

DDR_B_D15
DDR_B_D20

DDR_B_D21

DDR_B_D22
DDR_B_D23

DDR_B_D28
DDR_B_D29

DDR_B_DQS#3

DDR_B_DQS3

DDR_B_D30
DDR_B_D31

DDRB_CKE1
DDR_B_MA15

DDR_B_MA14
DDR_B_MA11

DDR_B_MA7
DDR_B_MA6

DDR_B_MA4
DDR_B_MA2

DDR_B_MA0
DDRB_CLK1

DDRB_CLK1#
DDR_B_BS1

DDR_B_RAS#
DDRB_SCS0#

DDRB_ODT0
DDRB_ODT1

+VREF_CAB
DDR_B_D36

DDR_B_D37

DDR_B_D38
DDR_B_D39

DDR_B_D44
DDR_B_D45

DDR_B_DQS#5

DDR_B_DQS5

DDR_B_D46
DDR_B_D47

DDR_B_D52
DDR_B_D53

DDR_B_D54
DDR_B_D55

DDR_B_D60
DDR_B_D61

DDR_B_DQS#7

DDR_B_DQS7

DDR_B_D62
DDR_B_D63

PM_SMBDATA
PM_SMBCLK

+0.75VS

Standard Type
DDR3 SO-DIMM B

SM_DRAMRST# <11,7>

DDRB_CKE1 <7>

DDRB_CLK1 <7>
DDRB_CLK1# <7>

DDR_B_BS1 <7>
DDR_B_RAS# <7>DDR_B_BS0<7>

DDRB_SCS0# <7>
DDRB_ODT0 <7>

DDRB_ODT1 <7>

1

CD47

CD47

1

CD46

CD46

0.1U_0402_10V7K

0.1U_0402_10V7K

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

Close to JDDR3S.126

PM_SMBDATA <11,25,34,41>
PM_SMBCLK <11,25,34,41>

2

2

+1.5V

12

1K_0402_1%

1K_0402_1%

12

1K_0402_1%

1K_0402_1%

C

RD12

RD12

RD13

RD13

+1.5V

CD31 330U_D2_2VM_R6M

CD31 330U_D2_2VM_R6M
CD41 10U_0603_6.3V6MCD41 10U_0603_6.3V6M
CD36 10U_0603_6.3V6MCD36 10U_0603_6.3V6M
CD37 10U_0603_6.3V6MCD37 10U_0603_6.3V6M
CD38 10U_0603_6.3V6MCD38 10U_0603_6.3V6M
CD39 10U_0603_6.3V6MCD39 10U_0603_6.3V6M
CD40 10U_0603_6.3V6MCD40 10U_0603_6.3V6M

Layout Note:
Place near JDDRL

1 2

+

+

1 2
1 2
1 2
1 2
1 2
1 2

D

DDR_B_DQS#[0..7] <7>
DDR_B_DQS[0..7] <7>
DDR_B_D[0..63] <7>
DDR_B_MA[0..15] <7>

Layout Note: Place these 4 Caps near
Command and Control signals of DIMMB

CD33 0.1U_0402_10V7KCD33 0.1U_0402_10V7K

1 2

CD29 0.1U_0402_10V7KCD29 0.1U_0402_10V7K

1 2

CD30 0.1U_0402_10V7KCD30 0.1U_0402_10V7K

1 2

CD32 0.1U_0402_10V7KCD32 0.1U_0402_10V7K

1 2

E

Layout Note:
Place near JDDRL.203 and 204

+0.75VS+1.5V

CD57 10U_0603_6.3V6MCD57 10U_0603_6.3V6M

1 2

CD45 1U_0402_6.3V6KCD45 1U_0402_6.3V6K

12

CD42 1U_0402_6.3V6KCD42 1U_0402_6.3V6K

12

CD43 1U_0402_6.3V6KCD43 1U_0402_6.3V6K

12

CD44 1U_0402_6.3V6KCD44 1U_0402_6.3V6K

12

SPD setting (SA0, SA1)
PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM1

DDRIII-SODIMM1

DDRIII-SODIMM1

VCUAA

VCUAA

VCUAA

12 53Tuesday, October 16, 2012

12 53Tuesday, October 16, 2012

12 53Tuesday, October 16, 2012

E

1.0

1.0

1.0

of

of

of

A

PCIE_CTX_C_GRX_P15
PCIE_CTX_C_GRX_N15
PCIE_CTX_C_GRX_P14
PCIE_CTX_C_GRX_N14
PCIE_CTX_C_GRX_P13
PCIE_CTX_C_GRX_N13
PCIE_CTX_C_GRX_P12
PCIE_CTX_C_GRX_N12
PCIE_CTX_C_GRX_P11
PCIE_CTX_C_GRX_N11

1 1

0.22U_0402_16V7K

PCIE_GTX_C_CRX_P15
PCIE_GTX_C_CRX_N15
PCIE_GTX_C_CRX_P14
PCIE_GTX_C_CRX_N14
PCIE_GTX_C_CRX_P13
PCIE_GTX_C_CRX_N13
PCIE_GTX_C_CRX_P12
PCIE_GTX_C_CRX_N12
PCIE_GTX_C_CRX_P11 PCIE_GTX_CRX_P11

2 2

PCIE_GTX_C_CRX_N11
PCIE_GTX_C_CRX_P10
PCIE_GTX_C_CRX_N10
PCIE_GTX_C_CRX_P9
PCIE_GTX_C_CRX_N9
PCIE_GTX_C_CRX_P8
PCIE_GTX_C_CRX_N8
PCIE_GTX_C_CRX_P7
PCIE_GTX_C_CRX_N7
PCIE_GTX_C_CRX_P6
PCIE_GTX_C_CRX_N6
PCIE_GTX_C_CRX_P5
PCIE_GTX_C_CRX_N5
PCIE_GTX_C_CRX_P4
PCIE_GTX_C_CRX_N4
PCIE_GTX_C_CRX_P3
PCIE_GTX_C_CRX_N3
PCIE_GTX_C_CRX_P2
PCIE_GTX_C_CRX_N2
PCIE_GTX_C_CRX_P1
PCIE_GTX_C_CRX_N1

PCIE_GTX_C_CRX_N0

3 3

CLK_REQ_VGA#<25>

4 4

2N7002KW_SOT323-3

2N7002KW_SOT323-3

CV35

OPT@ CV35

OPT@

CV37

OPT@ CV37

OPT@

CV39 0.22U_0402_16V7KOPT@ CV39 0.22U_0402_16V7KOPT@
CV45 0.22U_0402_16V7KOPT@ CV45 0.22U_0402_16V7KOPT@
CV93 0.22U_0402_16V7KOPT@ CV93 0.22U_0402_16V7KOPT@
CV98

OPT@ CV98

OPT@

CV94

OPT@ CV94

OPT@

CV99 0.22U_0402_16V7KOPT@ CV99 0.22U_0402_16V7KOPT@
CV107 0.22U_0402_16V7KOPT@ CV107 0.22U_0402_16V7KOPT@
CV105 0.22U_0402_16V7KOPT@ CV105 0.22U_0402_16V7KOPT@
CV199

OPT@ CV199

OPT@

CV108

OPT@ CV108

OPT@

CV200 0.22U_0402_16V7KOPT@ CV200 0.22U_0402_16V7KOPT@
CV202 0.22U_0402_16V7KOPT@ CV202 0.22U_0402_16V7KOPT@
CV201 0.22U_0402_16V7KOPT@ CV201 0.22U_0402_16V7KOPT@
CV204

OPT@ CV204

OPT@

CV203

OPT@ CV203

OPT@

CV205 0.22U_0402_16V7KOPT@ CV205 0.22U_0402_16V7KOPT@
CV207 0.22U_0402_16V7KOPT@ CV207 0.22U_0402_16V7KOPT@
CV206 0.22U_0402_16V7KOPT@ CV206 0.22U_0402_16V7KOPT@
CV209

OPT@ CV209

OPT@

CV208

OPT@ CV208

OPT@

CV210 0.22U_0402_16V7KOPT@ CV210 0.22U_0402_16V7KOPT@
CV212 0.22U_0402_16V7KOPT@ CV212 0.22U_0402_16V7KOPT@
CV211 0.22U_0402_16V7KOPT@ CV211 0.22U_0402_16V7KOPT@
CV214

OPT@ CV214

OPT@

CV213

OPT@ CV213

OPT@

CV215 0.22U_0402_16V7KOPT@ CV215 0.22U_0402_16V7KOPT@
CV217 0.22U_0402_16V7KOPT@ CV217 0.22U_0402_16V7KOPT@
CV216 0.22U_0402_16V7KOPT@ CV216 0.22U_0402_16V7KOPT@
CV219 0.22U_0402_16V7KOPT@ CV219 0.22U_0402_16V7KOPT@
CV220 0.22U_0402_16V7KOPT@ CV220 0.22U_0402_16V7KOPT@

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2
1 2
1 2
1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2
1 2
1 2
1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2
1 2
1 2
1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2
1 2
1 2
1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2
1 2
1 2
1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

0.22U_0402_16V7K

1 2
1 2
1 2
1 2
1 2
1 2

CLK_PCIE_VGA<25>

CLK_PCIE_VGA#<25>

1 2

RV16 200_0402_1%

RV16 200_0402_1%

PLTRST_VGA#<28>

13

D

D

S

S

QV3

QV3

OPT@

OPT@

RV182 0_0402_5%

RV182 0_0402_5%

1 2

2

G

G

1

CV46

CV46

0.1U_0402_10V7K

0.1U_0402_10V7K
@

@

2

PCIE_CTX_C_GRX_P10
PCIE_CTX_C_GRX_N10

PCIE_CTX_C_GRX_P9

PCIE_CTX_C_GRX_N9

PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_P7

PCIE_CTX_C_GRX_N7

PCIE_CTX_C_GRX_P6

PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P5

PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P4

PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P3

PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P2

PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P1

PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P0

PCIE_CTX_C_GRX_N0

PCIE_GTX_CRX_P15
PCIE_GTX_CRX_N15
PCIE_GTX_CRX_P14
PCIE_GTX_CRX_N14
PCIE_GTX_CRX_P13
PCIE_GTX_CRX_N13
PCIE_GTX_CRX_P12
PCIE_GTX_CRX_N12

PCIE_GTX_CRX_N11
PCIE_GTX_CRX_P10
PCIE_GTX_CRX_N10
PCIE_GTX_CRX_P9
PCIE_GTX_CRX_N9
PCIE_GTX_CRX_P8
PCIE_GTX_CRX_N8
PCIE_GTX_CRX_P7
PCIE_GTX_CRX_N7
PCIE_GTX_CRX_P6
PCIE_GTX_CRX_N6
PCIE_GTX_CRX_P5
PCIE_GTX_CRX_N5
PCIE_GTX_CRX_P4
PCIE_GTX_CRX_N4
PCIE_GTX_CRX_P3
PCIE_GTX_CRX_N3
PCIE_GTX_CRX_P2
PCIE_GTX_CRX_N2
PCIE_GTX_CRX_P1
PCIE_GTX_CRX_N1
PCIE_GTX_CRX_P0PCIE_GTX_C_CRX_P0
PCIE_GTX_CRX_N0

CLK_PCIE_VGA
CLK_PCIE_VGA#

OPT@

OPT@

CLK_REQ_GPU#
PEX_TSTCLK_OUT

PEX_TSTCLK_OUT#

+3VS_DGPU

@

@

1 2

RV19 2.49K_0402_1%

RV19 2.49K_0402_1%

@

@

+3VS_DGPU

1 2

RV179

RV179
10K_0402_5%

10K_0402_5%
OPT@

OPT@

CLK_REQ_GPU#

B

UV4A

UV4A

AN12

PEX_RX0

AM12

PEX_RX0_N

AN14

PEX_RX1

AM14

PEX_RX1_N

AP14

PEX_RX2

AP15

PEX_RX2_N

AN15

PEX_RX3

AM15

PEX_RX3_N

AN17

PEX_RX4

AM17

PEX_RX4_N

AP17

PEX_RX5

AP18

PEX_RX5_N

AN18

PEX_RX6

AM18

PEX_RX6_N

AN20

PEX_RX7

AM20

PEX_RX7_N

AP20

PEX_RX8

AP21

PEX_RX8_N

AN21

PEX_RX9

AM21

PEX_RX9_N

AN23

PEX_RX10

AM23

PEX_RX10_N

AP23

PEX_RX11

AP24

PEX_RX11_N

AN24

PEX_RX12

AM24

PEX_RX12_N

AN26

PEX_RX13

AM26

PEX_RX13_N

AP26

PEX_RX14

AP27

PEX_RX14_N

AN27

PEX_RX15

AM27

PEX_RX15_N

AK14

PEX_TX0

AJ14

PEX_TX0_N

AH14

PEX_TX1

AG14

PEX_TX1_N

AK15

PEX_TX2

AJ15

PEX_TX2_N

AL16

PEX_TX3

AK16

PEX_TX3_N

AK17

PEX_TX4

AJ17

PEX_TX4_N

AH17

PEX_TX5

AG17

PEX_TX5_N

AK18

PEX_TX6

AJ18

PEX_TX6_N

AL19

PEX_TX7

AK19

PEX_TX7_N

AK20

PEX_TX8

AJ20

PEX_TX8_N

AH20

PEX_TX9

AG20

PEX_TX9_N

AK21

PEX_TX10

AJ21

PEX_TX10_N

AL22

PEX_TX11

AK22

PEX_TX11_N

AK23

PEX_TX12

AJ23

PEX_TX12_N

AH23

PEX_TX13

AG23

PEX_TX13_N

AK24

PEX_TX14

AJ24

PEX_TX14_N

AL25

PEX_TX15

AK25

PEX_TX15_N

AJ11

PEX_WAKE_N

AL13

PEX_REFCLK

AK13

PEX_REFCLK_N

AK12

PEX_CLKREQ_N

AJ26

PEX_TSTCLK_OUT

AK26

PEX_TSTCLK_OUT_N

AJ12

PEX_RST_N

AP29

PEX_TERMP

N13P-PES-A2_FCBGA908 N13PGLR1@

N13P-PES-A2_FCBGA908 N13PGLR1@

Part 1 of 7

Part 1 of 7

GPIO

GPIO

DACs

DACs

120mA

PCI EXPRESS

PCI EXPRESS

60mA
45mA
45mA

CLK

CLK

1

CV48

CV48
18P_0402_50V8J

18P_0402_50V8J
NOGCLK@

NOGCLK@

2

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC
DACA_VSYNC

DACA_VDD
DACA_VREF
DACA_RSET

I2CA_SCL
I2CA_SDA

I2CB_SCL
I2CB_SDA

I2CC_SCL

I2C

I2C

I2CC_SDA

I2CS_SCL
I2CS_SDA

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_OUTBUFF

XTAL_SSIN

1

VGA_VID_4

P6

VGA_VID_3

M3
L6
P5
P7

VGA_VID_1

L7

VGA_VID_2

M7
N8

OVERT#_VGA

M1

GPU_EVENT

M2
L1

VGA_VID_0

M5

GPS_DOWN#

N3

VGA_VID_5

M4
N4
P2
R8
M6

HDMI_HPD_VGA

R1
P3
P4
P1

AK9
AL10
AL9

AM9
AN9

AG10
AP9
AP8

VGA_CRT_CLK

R4

VGA_CRT_DATA

R5

HDCP_SCL

R7

HDCP_SDA

R6

VGA_EDID_CLK

R2

VGA_EDID_DATA

R3
T4

T3

Internal Thermal Sensor

+PLLVDD

AD8
AE8
AD7

XTAL_OUTBUFF

XTAL_SSIN

NOGCLK@

NOGCLK@

GND

3

4

XTALIN

XTAL_OUT

RV52

OPT@ RV52

OPT@

3

18P_0402_50V8J

18P_0402_50V8J

H3
H2

J4
H1

YV3

YV3

1

GND

2

27MHZ_16PF_7V27000011

27MHZ_16PF_7V27000011

C

VGA_VID_4 <51>
VGA_VID_3 <51>

VGA_VID_1 <51>
VGA_VID_2 <51>

VGA_VID_0 <51>
VGA_VID_5 <51>

12

CV225

CV225
10K_0402_5%

10K_0402_5%
OPT@

OPT@

110804 check with NV pull down 10k if DAC unused

SMB_CLK_GPU
SMB_DATA_GPU

+GPU_PLLVDD

12

12

RV45

RV45

CV38,CV40, CV41 under GPU
close to ball : AE8,AD7

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

OPT@

OPT@

GPS_DOWN# <40>

EC GPS_DOWN# must be OD\Low
to avoid leakage on OPT SKU.

LVDS

CV1971 under GPU
close to ball : ADB

1

1

CV38

2

OPT@ CV38

OPT@

VGA_X1<34>

CV40

2

OPT@ CV40

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CV41

2

0.1U_0402_10V7K

0.1U_0402_10V7K

OPT@ CV41

OPT@

1 2

RV5 0_0402_5%

RV5 0_0402_5%

OPT@

OPT@

Close to VGA side

XTAL_OUTXTALIN

1

CV49

CV49

NOGCLK@

NOGCLK@

2

1

2

0.1U_0402_10V7K

0.1U_0402_10V7K

BLM18PG181SN1D_2P

BLM18PG181SN1D_2P

1 2

OPT@

OPT@

1

CV43

CV42

2

OPT@ CV43

OPT@

OPT@ CV42

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

XTALIN

+PLLVDD

LV15

LV15

PCIE_GTX_C_CRX_P[0..15]<6>

PCIE_GTX_C_CRX_N[0..15]<6>

PCIE_CTX_C_GRX_P[0..15]<6>

PCIE_CTX_C_GRX_N[0..15]<6>

1

2

+1.05VS_DGPU

1

CV197

2

0.1U_0402_10V7K

OPT@ CV197

0.1U_0402_10V7K

OPT@

1

CV44

2

OPT@ CV44

OPT@

SMB_CLK_GPU

SMB_DATA_GPU

D

1

CV109

2

OPT@ CV109

OPT@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

2.2K_0402_5%

2.2K_0402_5%

PCIE_GTX_C_CRX_P[0..15]

PCIE_CTX_C_GRX_P[0..15]

PCIE_CTX_C_GRX_N[0..15]

1 2

BLM18PG330SN1D_0603

BLM18PG330SN1D_0603

CV47

OPT@ CV47

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

+3VS_DGPU

RV22

RV22

OPT@

OPT@

1 2

PCIE_GTX_C_CRX_N[0..15]

+1.05VS_DGPU

LV10

LV10

OPT@

OPT@

RV24

RV24

2.2K_0402_5%

2.2K_0402_5%
OPT@

OPT@

1 2

OPT@

OPT@

QV1A

QV1A

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

1

2

+3VS_DGPU

4

2

2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6

61

E

+3VS_DGPU

OPT@

VGA_EDID_CLK

VGA_EDID_DATA
GPS_DOWN#
GPU_EVENT
OVERT#_VGA
HDCP_SCL
HDCP_SDA

VGA_CRT_DATA
VGA_CRT_CLK

HDMI_HPD_VGA

CV53

OPT@ CV53

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

5

OPT@

OPT@
QV1B

QV1B

3

EC_SMB_CK2 <25,40>

EC_SMB_DA2 <25,40>

OPT@

1 2

RV6 2.2K_0402_5%

RV6 2.2K_0402_5%

OPT@

OPT@

1 2

RV7 2.2K_0402_5%

RV7 2.2K_0402_5%

OPT@

OPT@

1 2

RV32 10K_0402_5%

RV32 10K_0402_5%

OPT@

OPT@

1 2

RV10 10K_0402_5%

RV10 10K_0402_5%

OPT@

OPT@

1 2

RV37 10K_0402_5%

RV37 10K_0402_5%

OPT@

OPT@

1 2

RV11 2.2K_0402_5%

RV11 2.2K_0402_5%

OPT@

OPT@

1 2

RV12 2.2K_0402_5%

RV12 2.2K_0402_5%

OPT@

OPT@

1 2

RV13 2.2K_0402_5%

RV13 2.2K_0402_5%

OPT@

OPT@

1 2

RV14 2.2K_0402_5%

RV14 2.2K_0402_5%

OPT@

OPT@

RV608 100K_0402_5%

RV608 100K_0402_5%

12

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

VGA_N13P PEG & DAC

VGA_N13P PEG & DAC

VGA_N13P PEG & DAC

13 53Tuesday, October 16, 2012

13 53Tuesday, October 16, 2012

E

13 53Tuesday, October 16, 2012

1.0

1.0

1.0

of

of

of

A

VRAM Interface

UV4B

UV4B

MDA0
MDA1
MDA2
MDA3
MDA4
MDA5
MDA6
MDA7
MDA8
MDA9
MDA10
MDA11
MDA12
MDA13
MDA14
MDA15
MDA16
MDA17
MDA18
MDA19
MDA20
MDA21
MDA22
MDA23
MDA24
MDA25
MDA26
MDA27
MDA28
MDA29
MDA30
MDA31
MDA32
MDA33
MDA34
MDA35
MDA36
MDA37
MDA38
MDA39
MDA40
MDA41
MDA42
MDA43

1 1

DQMA[3..0]<19>

DQMA[7..4]<18>

DQSA[3..0]<19>

DQSA[7..4]<18>

DQSA#[3..0]<19>

DQSA#[7..4]<18>

MDA44
MDA45
MDA46
MDA47
MDA48
MDA49
MDA50
MDA51
MDA52
MDA53
MDA54
MDA55
MDA56
MDA57
MDA58
MDA59
MDA60
MDA61
MDA62
MDA63

DQMA0
DQMA1
DQMA2DQMA2
DQMA3
DQMA4DQMA4
DQMA5
DQMA6
DQMA7

DQSA0
DQSA1
DQSA2
DQSA3
DQSA4
DQSA5
DQSA6
DQSA7

DQSA#0
DQSA#1
DQSA#2
DQSA#3
DQSA#4
DQSA#5
DQSA#6
DQSA#7

L28

FBA_D0

M29

FBA_D1

L29

FBA_D2

M28

FBA_D3

N31

FBA_D4

P29

FBA_D5

R29

FBA_D6

P28

FBA_D7

J28

FBA_D8

H29

FBA_D9

J29

FBA_D10

H28

FBA_D11

G29

FBA_D12

E31

FBA_D13

E32

FBA_D14

F30

FBA_D15

C34

FBA_D16

D32

FBA_D17

B33

FBA_D18

C33

FBA_D19

F33

FBA_D20

F32

FBA_D21

H33

FBA_D22

H32

FBA_D23

P34

FBA_D24

P32

FBA_D25

P31

FBA_D26

P33

FBA_D27

L31

FBA_D28

L34

FBA_D29

L32

FBA_D30

L33

FBA_D31

AG28

FBA_D32

AF29

FBA_D33

AG29

FBA_D34

AF28

FBA_D35

AD30

FBA_D36

AD29

FBA_D37

AC29

FBA_D38

AD28

FBA_D39

AJ29

FBA_D40

AK29

FBA_D41

AJ30

FBA_D42

AK28

FBA_D43

AM29

FBA_D44

AM31

FBA_D45

AN29

FBA_D46

AM30

FBA_D47

AN31

FBA_D48

AN32

FBA_D49

AP30

FBA_D50

AP32

FBA_D51

AM33

FBA_D52

AL31

FBA_D53

AK33

FBA_D54

AK32

FBA_D55

AD34

FBA_D56

AD32

FBA_D57

AC30

FBA_D58

AD33

FBA_D59

AF31

FBA_D60

AG34

FBA_D61

AG32

FBA_D62

AG33

FBA_D63

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

FBA_DQS_RN0

H30

FBA_DQS_RN1

E34

FBA_DQS_RN2

M34

FBA_DQS_RN3

AF30

FBA_DQS_RN4

AK31

FBA_DQS_RN5

AM34

FBA_DQS_RN6

AF32

FBA_DQS_RN7

N13P-PES-A2_FCBGA908 N13PGLR1@

N13P-PES-A2_FCBGA908 N13PGLR1@

MDA[15..0]<19>
MDA[31..16]<19>
MDA[47..32]<18>
MDA[63..48]<18>

Part 2 of 7

Part 2 of 7

FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30
FBA_CMD31

FBA_CMD_RFU0
FBA_CMD_RFU1

MEMORY INTERFACE

A

MEMORY INTERFACE

A

FBA_DEBUG0
FBA_DEBUG1

FBA_CLK0_N
FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

35mA

FB_DLL_AVDD

66mA

FBA_PLL_AVDD

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8
FBA_CMD9

FBA_CLK0
FBA_CLK1

FB_CLAMP

FB_VREF

MDA[15..0]
MDA[31..16]
MDA[47..32]
MDA[63..48]

CMDA0

U30

CMDA1

T31

CMDA2

U29

CMDA3

R34

CMDA4

R33

CMDA5

U32

CMDA6

U33

CMDA7

U28

CMDA8

V28

CMDA9

V29

CMDA10

V30

CMDA11

U34

CMDA12

U31

CMDA13

V34

CMDA14

V33

CMDA15

Y32

CMDA16

AA31

CMDA17

AA29

CMDA18

AA28

CMDA19

AC34

CMDA20

AC33

CMDA21

AA32

CMDA22

AA33

CMDA23

Y28

CMDA24

Y29

CMDA25

W31

CMDA26

Y30

CMDA27

AA34

CMDA28

Y31

CMDA29

Y34

CMDA30

Y33
V31

R32
AC32

FBA_DEBUG0 FBB_DEBUG0

R28
AC28

R30
R31
AB31
AC31

K31
L30
H34
J34
AG30
AG31
AJ34
AK34

J30
J31
J32
J33
AH31
AJ31
AJ32
AJ33

FB_CLAMP

E1

K27

+FB_AVDD

U27

H26

CMDA[30..0] <18,19>

RV57 60.4_0402_1%

RV57 60.4_0402_1%

@

@

12

@

@

12

RV59 60.4_0402_1%

RV59 60.4_0402_1%

CLKA0 <19>
CLKA0# <19>
CLKA1 <18>
CLKA1# <18>

OPT@

OPT@

1 2

RV7410K_0402_1%

RV7410K_0402_1%

CV51

1

2

0.1U_0402_10V7K

OPT@ CV51

0.1U_0402_10V7K

OPT@

+VRAM_1.5VS

1

CV50

CV50

2

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

MDC0
MDC1
MDC2
MDC3
MDC4
MDC5
MDC6
MDC7
MDC8
MDC9
MDC10
MDC11
MDC12
MDC13
MDC14
MDC15
MDC16
MDC17
MDC18
MDC19
MDC20
MDC21
MDC22
MDC23
MDC24
MDC25
MDC26
MDC27
MDC28
MDC29
MDC30
MDC31
MDC32
MDC33
MDC34
MDC35
MDC36
MDC37
MDC38
MDC39
MDC40
MDC41
MDC42
MDC43
MDC44
MDC45
MDC46
MDC47
MDC48
MDC49
MDC50
MDC51
MDC52
MDC53
MDC54
MDC55
MDC56
MDC57
MDC58
MDC59
MDC60
MDC61
MDC62

DQMC[3..0]<20>

DQMC[7..4]<21>

DQSC[3..0]<20>

DQSC[7..4]<21>

DQSC#[3..0]<20>

DQSC#[7..4]<21>

MDC63

DQMC0
DQMC1
DQMC2
DQMC3
DQMC4
DQMC5
DQMC6
DQMC7

DQSC0
DQSC1
DQSC2
DQSC3
DQSC4
DQSC5
DQSC6
DQSC7

DQSC#0
DQSC#1
DQSC#2
DQSC#3
DQSC#4
DQSC#5
DQSC#6
DQSC#7

MDC[15..0]<20>
MDC[31..16]<20>
MDC[47..32]<21>
MDC[63..48]<21>

UV4C

UV4C

G9

FBB_D0

E9

FBB_D1

G8

FBB_D2

F9

FBB_D3

F11

FBB_D4

G11

FBB_D5

F12

FBB_D6

G12

FBB_D7

G6

FBB_D8

F5

FBB_D9

E6

FBB_D10

F6

FBB_D11

F4

FBB_D12

G4

FBB_D13

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

E11

FBB_DQM0

E3

FBB_DQM1

A3

FBB_DQM2

C9

FBB_DQM3

F23

FBB_DQM4

F27

FBB_DQM5

C30

FBB_DQM6

A24

FBB_DQM7

D10

FBB_DQS_WP0

D5

FBB_DQS_WP1

C3

FBB_DQS_WP2

B9

FBB_DQS_WP3

E23

FBB_DQS_WP4

E28

FBB_DQS_WP5

B30

FBB_DQS_WP6

A23

FBB_DQS_WP7

D9

FBB_DQS_RN0

E4

FBB_DQS_RN1

B2

FBB_DQS_RN2

A9

FBB_DQS_RN3

D22

FBB_DQS_RN4

D28

FBB_DQS_RN5

A30

FBB_DQS_RN6

B23

FBB_DQS_RN7

N13P-PES-A2_FCBGA908 N13PGLR1@

N13P-PES-A2_FCBGA908 N13PGLR1@

MDC[15..0]
MDC[31..16]
MDC[47..32]
MDC[63..48]

Part 3 of 7

Part 3 of 7

FBB_CMD0
FBB_CMD1
FBB_CMD2
FBB_CMD3
FBB_CMD4
FBB_CMD5
FBB_CMD6
FBB_CMD7
FBB_CMD8

FBB_CMD9
FBB_CMD10
FBB_CMD11
FBB_CMD12
FBB_CMD13
FBB_CMD14
FBB_CMD15
FBB_CMD16
FBB_CMD17
FBB_CMD18
FBB_CMD19
FBB_CMD20
FBB_CMD21
FBB_CMD22
FBB_CMD23
FBB_CMD24
FBB_CMD25
FBB_CMD26
FBB_CMD27
FBB_CMD28
FBB_CMD29
FBB_CMD30
FBB_CMD31

FBB_CMD_RFU0
FBB_CMD_RFU1

FBB_DEBUG0

FBB_DEBUG1

MEMORY INTERFACE B

MEMORY INTERFACE B

FBB_CLK0

FBB_CLK0_N

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

66mA

FBB_PLL_AVDD

D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17

C12
C20

G14
G20

D12
E12
E20
F20

F8
E8
A5
A6
D24
D25
B27
C27

D6
D7
C6
B6
F26
E26
A26
A27

H17

12mil

FBB_DEBUG1FBA_DEBUG1

CMDC0
CMDC1
CMDC2
CMDC3
CMDC4
CMDC5
CMDC6
CMDC7
CMDC8
CMDC9
CMDC10

CMDC11

CMDC12
CMDC13
CMDC14
CMDC15
CMDC16
CMDC17
CMDC18
CMDC19
CMDC20
CMDC21
CMDC22
CMDC23
CMDC24
CMDC25
CMDC26
CMDC27
CMDC28
CMDC29
CMDC30

1

2

OPT@

OPT@

+FB_AVDD

CV52

CV52

0.1U_0402_10V7K

0.1U_0402_10V7K

CMDC[30..0] <20,21>

RV58 60.4_0402_1%

RV58 60.4_0402_1%

@

@

12

@

@

12

RV60 60.4_0402_1%

RV60 60.4_0402_1%

CLKC0 <20>
CLKC0# <20>
CLKC1 <21>
CLKC1# <21>

+1.05VS_DGPU

1

2

+VRAM_1.5VS

BLM18PG330SN1D_0603

BLM18PG330SN1D_0603

LV5

LV5

1 2

OPT@

OPT@

CV86

OPT@ CV86

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

+FB_AVDD

100mA

+FB_AVDD

1

CV233

2

OPT@CV233

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

Compal Electronics, Inc.

N13P VRAM Interface

N13P VRAM Interface

N13P VRAM Interface

of

of

of

14 53Tuesday, October 16, 2012

14 53Tuesday, October 16, 2012

14 53Tuesday, October 16, 2012

1.0

1.0

1.0

5

D D

C C

B B

A A

UV4D

UV4D

AM6

IFPA_TXC

AN6

IFPA_TXC_N

AP3

IFPA_TXD0

AN3

IFPA_TXD0_N

AN5

IFPA_TXD1

AM5

IFPA_TXD1_N

AL6

IFPA_TXD2

AK6

IFPA_TXD2_N

AJ6

IFPA_TXD3

AH6

IFPA_TXD3_N

AJ9

IFPB_TXC

AH9

IFPB_TXC_N

AP6

IFPB_TXD4

AP5

IFPB_TXD4_N

AM7

IFPB_TXD5

AL7

IFPB_TXD5_N

AN8

IFPB_TXD6

AM8

IFPB_TXD6_N

AK8

IFPB_TXD7

AL8

IFPB_TXD7_N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_I2CW_SCL

AG2

IFPC_AUX_I2CW_SDA_N

AK3

IFPD_AUX_I2CX_SCL

AK2

IFPD_AUX_I2CX_SDA_N

AB3

IFPE_AUX_I2CY_SCL

AB4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

N13P-PES-A2_FCBGA908 N13PGLR1@

N13P-PES-A2_FCBGA908 N13PGLR1@

Part 4 of 7

Part 4 of 7

TEST

TEST

SERIAL

SERIAL

LVDS/TMDS

LVDS/TMDS

GENERAL

GENERAL

MULTI_STRAP_REF0_GND

NC

NC

VDD_SENSE

GND_SENSE

TESTMODE

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST_N

ROM_CS_N
ROM_SCLK

ROM_SI

ROM_SO

BUFRST_N

CEC

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

THERMDP
THERMDN

4

P8

NC

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

H31

NC

T8

NC

V32

NC

L4

L5

AK11
AM10

AM11
AP12
AP11
AN11

H6
H4
H5
H7

L2
L3
J1

J2
J7
J6
J5
J3

K3
K4

GCORE_SEN_R

FB_GND_R

ROM_CS#
ROM_SCLK
ROM_SI
ROM_SO

MULTI_STRAP_REF0_GND

RV80 0_0402_5%

RV80 0_0402_5%

RV81 0_0402_5%

RV81 0_0402_5%

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST

RV84 10K_0402_5%

RV84 10K_0402_5%

@

@

1 2

RV85 10K_0402_5%

RV85 10K_0402_5%

STRAP0
STRAP1
STRAP2
STRAP3
STRAP4

@

@

1 2

@

@

1 2

RV82 10K_0402_5%OPT@RV82 10K_0402_5%OPT@

1 2

OPT@

OPT@

1 2

RV153 10K_0402_5%OPT@RV153 10K_0402_5%OPT@

1 2

RV86 10K_0402_5%N13PGL@RV86 10K_0402_5%N13PGL@

1 2

OPT@

OPT@

1 2

RV87 40.2K_0402_1%

RV87 40.2K_0402_1%

+VGA_CORE

RV15

RV15
100_0402_1%

100_0402_1%
OPT@

OPT@

1 2

100_0402_1%

100_0402_1%

+3VS_DGPU

OPT@

OPT@

12

RV17

RV17

PAD

PAD

TV4

TV4

PAD

PAD

TV1

TV1

PAD @

PAD @

TV2

TV2

PAD

PAD

TV3

3

VGA_VCC_SENSE <51>

VGA_VSS_SENSE <51>

@

@
@

@
@TV3

@

+3VS_DGPU

Physical
Strapping pin

ROM_SO

ROM_SCLK

ROM_SI

STRAP0

STRAP1

STRAP2

STRAP3
STRAP4

N13P-GL ES2

N13P-GS ES1

N13P-GS QS

N13P-GL

ROM_SI

2

Power Rail

+3VS_DGPU

+3VS_DGPU

Logical
Strapping Bit3

XCLK_417 for GL
, FB[1]

PCI_DEVID[4]

+3VS_DGPU

+3VS_DGPU
+3VS_DGPU 3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]

+3VS_DGPU
+3VS_DGPU SOR0_EXPOSEDSOR2_EXPOSED SOR1_EXPOSED
+3VS_DGPU DP_PLL_VDD33V

SKU

Device ID

MULTI LEVEL STRAPS

Straps

STRAP0
STRAP1
STRAP2

RV73

RV73

4.99K_0402_1%

4.99K_0402_1%
N13PGS@

N13PGS@

0x0DE9

0x0FDB

0x0FD2

12

OPT@

OPT@

RV64

RV64

12

@

@

RV72

RV72

USER[3]
3GIO_PADCFG[3]

PCI_DEVID[3]

SOR3_EXPOSED
RESERVED

biit5 to bit0

+3VS_DGPU

12
@

@

N13PGL@

N13PGL@

RV65

RV65

45.3K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

12

N13PGL@

N13PGL@

RV73

RV73

45.3K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

101001

011011

010010

12

RV79

RV79

15K_0402_1%

15K_0402_1%

N13PGS@

N13PGS@

1 2

10K_0402_1%

10K_0402_1%

RV54

RV54

Hynix (900MHZ)
64MX16 H5TQ1G63DFR-11C
SA000041S20

Hynix (900MHZ)
128MX16 H5TQ2G63BFR-11C
SA00003YO00

Hynix (900MHZ)
128MX16 H5TQ2G63DFR-11C
SA00003YO70

Samsung (900MHZ)
64MX16 K4W1G1646G-BC11
SA00004GS00

Samsung (900MHZ)
128M16 K4W2G1646C-HC11
SA000047Q00

Samsung (900MHZ)
128M16 K4W2G1646E-BC11

Logical
Strapping Bit2

FB_0_BAR_SIZE for GL
, FB[0]

SUB_VENDOR

PCIE_SPEED_CHANGE_GEN3

12

12

@

@

RV98

RV98

GSDIS@

GSDIS@

10K_0402_1%

10K_0402_1%

RV68

RV68

4.99K_0402_1%

4.99K_0402_1%
STRAP3

STRAP4

12

12

RV75

RV75

RV76

RV76

GSOPT@

GSOPT@

N13PGS@

N13PGS@

45.3K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

1GB

2GB

1GB

2GB

2GB

Resistor Values

5K
10K
15K
20K
25K
30K
35K
45K

ROM_SI
ROM_SO
ROM_SCLK

For X76

RV77 PD 15K

0010

01102GB

0101

0011

0111

0001

(SD034150280)

RV77 PD 34.8k
(SD034348280)

RV77 PD 30k
(SD034300280)

RV77 PD 20K
(SD034200280)

RV77 PD 45.3K
(SD034453280)

RV77 PD 10K
(SD028100280)

Logical
Strapping Bit1

SMB_ALT_ADDR

SLOT_CLK_CFG for GL
PCI_DEVID[5]

RAMCFG[1]RAMCFG[3] RAMCFG[2]

PCIE_MAX_SPEED

Pull-up to +3VS
_DGPU

1000
1001
1010
1011
1100
1101
1110
1111

+3VS_DGPU

12

12

N13PGS@

N13PGS@

4.99K_0402_1%

4.99K_0402_1%

12

N13PGL@

N13PGL@

34.8K_0402_1%

34.8K_0402_1%

10K_0402_1%

10K_0402_1%

RV78

RV78

10K_0402_1%

10K_0402_1%

RV89

RV89

12

1 2

@

@

RV69

RV69

12

@

@

RV77

RV77

1

Logical
Strapping Bit0

VGA_DEVICE

PEX_PLLEN_TERM

RAMCFG[0]

USER[0]USER[1]USER[2]

PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

N13PGS@

N13PGS@

RV70

RV70

4.99K_0402_1%

4.99K_0402_1%

RV53

RV53

N13PGL@

N13PGL@

15K_0402_1%

15K_0402_1%

Pull-down to Gnd

0000
0001
0010
0011
0100
0101
0110
0111

SA00005SH00

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA_N13P LVDS&TMDS

VGA_N13P LVDS&TMDS

VGA_N13P LVDS&TMDS

15 53Tuesday, October 16, 2012

15 53Tuesday, October 16, 2012

1

15 53Tuesday, October 16, 2012

1.0

1.0

1.0

of

of

of

5

4

3

2

1

+1.05VS_DGPU

1

CV58

CV59

2

OPT@ CV58

OPT@

OPT@ CV59

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

+1.05VS_DGPU

1

CV78

CV67

2

OPT@ CV78

OPT@

OPT@ CV67

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

+3VS_DGPU

CV82

N13PGS@

N13PGS@

OPT@ CV82

OPT@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M
RV101

RV101

0_0603_5%

0_0603_5%

LV7

LV7

BLM18PG121SN1D_0603

BLM18PG121SN1D_0603

N13PGL@

N13PGL@

CV89

OPT@ CV89

OPT@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1

CV95

CV92

2

0.1U_0402_10V7K

OPT@ CV95

0.1U_0402_10V7K

OPT@

0.1U_0402_10V7K

OPT@ CV92

0.1U_0402_10V7K

OPT@

1

CV60

2

OPT@ CV60

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

1

CV68

2

OPT@ CV68

OPT@

22U_0805_6.3V6M

22U_0805_6.3V6M

12

+1.05VS_DGPU

12

PCIE2.0 N13P-GL N13M-GS
PCIE3.0 N13P-GS/GT N13E-GE

+3VS_DGPU

Near GPU

1

1

2

CV96

OPT@ CV96

OPT@

CV97

2

OPT@ CV97

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1

CV56

2

OPT@ CV56

OPT@

1

CV76

2

OPT@ CV76

OPT@

1

CV87

2

OPT@ CV87

OPT@

1

CV90

2

OPT@ CV90

OPT@

midway between GPU
and Power supply

1

CV57

2

OPT@ CV57

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

midway between GPU
and Power supply

1

CV77

2

OPT@ CV77

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

Near GPU

1

CV81

2

OPT@ CV81

OPT@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

Near GPU

1

CV88

2

1U_0402_6.3V6K

1U_0402_6.3V6K

OPT@ CV88

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CV91

2

0.1U_0402_10V7K

OPT@ CV91

0.1U_0402_10V7K

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

2

1

2

1

2

1

2

1

2

Under GPU

1

CV54

2

OPT@ CV54

UV4E

AA27
AA30
AB27
AB33
AC27
AD27
AE27

AF27

AG27

M27
N27

R27

W27
W30
W33

H27

H25

UV4E

B13
B16
B19
E13
E16
E19
H10
H11
H12
H13
H14
H15
H16
H18
H19
H20
H21
H22
H23
H24

H8
H9

L27

P27
T27

T30
T33
V27

Y27

F1

F2

J27

Part 5 of 7

Part 5 of 7

7200 mA 3300 mA

FBVDDQ_0
FBVDDQ_1
FBVDDQ_2
FBVDDQ_3
FBVDDQ_4
FBVDDQ_5
FBVDDQ_6
FBVDDQ_7
FBVDDQ_8
FBVDDQ_9
FBVDDQ_10
FBVDDQ_11
FBVDDQ_12
FBVDDQ_13
FBVDDQ_14
FBVDDQ_15
FBVDDQ_16
FBVDDQ_17
FBVDDQ_18
FBVDDQ_19
FBVDDQ_20
FBVDDQ_21
FBVDDQ_22
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
FBVDDQ_30
FBVDDQ_31
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_40
FBVDDQ_41
FBVDDQ_42
FBVDDQ_43

FB_VDDQ_SENSE

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

PEX_IOVDD_0
PEX_IOVDD_1
PEX_IOVDD_2
PEX_IOVDD_3
PEX_IOVDD_4
PEX_IOVDD_5

3300mA

PEX_IOVDDQ_0
PEX_IOVDDQ_1
PEX_IOVDDQ_2
PEX_IOVDDQ_3
PEX_IOVDDQ_4
PEX_IOVDDQ_5
PEX_IOVDDQ_6
PEX_IOVDDQ_7
PEX_IOVDDQ_8

PEX_IOVDDQ_9
PEX_IOVDDQ_10
PEX_IOVDDQ_11
PEX_IOVDDQ_12
PEX_IOVDDQ_13

210mA

PEX_PLL_HVDD

210mA

PEX_SVDD_3V3

150mA

POWER

POWER

PEX_PLLVDD

85mA

VDD33_0
VDD33_1
VDD33_2
VDD33_3

125mA

IFPAB_PLLVDD

IFPAB_RSET

115mA

IFPA_IOVDD
IFPB_IOVDD

100mA

IFPC_PLLVDD

IFPC_RSET

72mA

IFPC_IOVDD

IFPD_PLLVDD

IFPD_RSET

IFPD_IOVDD

200mA

IFPEF_PLVDD

IFPEF_RSET

IFPE_IOVDD

144mA

IFPF_IOVDD

AG19
AG21
AG22
AG24
AH21
AH25

AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28

AH12

AG12

AG26

J8
K8
L8
M8

AH8
AJ8

AG8
AG9

AF7
AF8

AF6

AG7
AN2

AG6

AB8
AD6

AC7
AC8

total 6600mA
Design guide page.74

+3VS_DGPU

OPT@

OPT@

1 2

CV80 0.1U_0402_10V7K

CV80 0.1U_0402_10V7K

OPT@

OPT@

1 2

CV198 0.1U_0402_10V7K

CV198 0.1U_0402_10V7K

+PEX_PLLVDD

+3VS_DGPU

+IFPAB_PLLVDD

+IFPAB_IOVDD

+IFPC_PLLVDD

+IFPC_IOVDD

+IFPD_PLLVDD

+IFPD_IOVDD

+IFPEF_PLLVDD

+IFPEF_IOVDD

CV101 OPT@ 10K_0402_5%CV101 OPT@ 10K_0402_5%
RV90 1K_0402_5%@RV90 1K_0402_5%@

CV104 OPT@ 10K_0402_5%CV104 OPT@ 10K_0402_5%

RV298 10K_0402_5%OPT@RV298 10K_0402_5%OPT@

RV295 10K_0402_5%OPT@RV295 10K_0402_5%OPT@

RV297 10K_0402_5%OPT@RV297 10K_0402_5%OPT@

RV296 10K_0402_5%OPT@RV296 10K_0402_5%OPT@

CV286 OPT@ 10K_0402_5%CV286 OPT@ 10K_0402_5%
RV103 1K_0402_5%@RV103 1K_0402_5%@

CV234 OPT@ 10K_0402_5%CV234 OPT@ 10K_0402_5%

1 2
1 2

1 2

1 2

1 2

1 2

1 2

1 2
1 2

1 2

420mA

CV80,CV198 Under GPU
close to ball

85mA

D D

C C

B B

+VRAM_1.5VS

1

2

CV83

OPT@ CV83

OPT@

1

CV61

2

OPT@ CV61

OPT@

1

CV69

2

OPT@ CV69

OPT@

1

CV84

2

OPT@ CV84

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

1

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

1

2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

Near GPU

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

+VRAM_1.5VS

CV62

CV62

OPT@

OPT@

CV70

OPT@ CV70

OPT@

CV244

OPT@CV244

OPT@

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

Under GPU

1

CV63

2

OPT@ CV63

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

Under GPU

1

CV79

CV79

2

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CV243

2

OPT@CV243

OPT@

10U_0603_6.3V6M

10U_0603_6.3V6M

RV96 40.2_0402_1%

RV96 40.2_0402_1%

RV605 42.2_0402_1%

RV605 42.2_0402_1%

RV609 51.1_0402_1%

RV609 51.1_0402_1%

1

CV64

2

OPT@ CV64

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

1

CV71

CV71

2

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

CV231
@CV231

@

22U_0805_6.3V6M

22U_0805_6.3V6M

OPT@

OPT@

OPT@

OPT@

1 2

OPT@

OPT@

1 2

1

2

CV65

OPT@ CV65

OPT@

CV72

CV72

OPT@

OPT@

12

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

CV85
@ CV85

@

1

2

1

2

22U_0805_6.3V6M

22U_0805_6.3V6M

CV66

OPT@ CV66

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

CV73

CV73

OPT@

OPT@

0.1U_0402_10V7K

0.1U_0402_10V7K

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

OPT@

Under GPU

1

CV74

2

OPT@ CV74

OPT@

Near GPU

1

CV55

2

OPT@ CV55

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

Near GPU

1

CV75

2

OPT@ CV75

OPT@

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

Under GPU

Under GPU

N13P-PES-A2_FCBGA908 N13PGLR1@

N13P-PES-A2_FCBGA908 N13PGLR1@

A A

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/04/19 2015/04/19

2012/04/19 2015/04/19

2012/04/19 2015/04/19

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA_N13P POWER

VGA_N13P POWER

VGA_N13P POWER

1

1.0

1.0

1.0

of

of

of

16 53Tuesday, October 16, 2012

16 53Tuesday, October 16, 2012

16 53Tuesday, October 16, 2012