Toshiba Satellite U940, Satellite U945, Compal LA-9161P Schematic

A

1 1

B

C

D

E

VCUAA

Metis 10F/10FG

2 2

LA-9161P REV 1.0 Schematic

Intel Processor (Ivy Bridge) / PCH(Panther Point)

2012-08-07 Rev 1.0

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Cover Page

VCUAA

153Tuesday, October 16, 2012

E

1.0

of

A

B

C

D

E

Intel CPU

PCI-Express 16X Gen2

1 1

VGA (DDR3)

nVIDIA N13P-GL with 2GB

page 13,14,15,16,17,18,19,20,21

Ivy Bridge 17W

FDI X8

2.7GT/s

BGA-1023

31mm*24mm

page 5,6,7,8,9,10

DMI X4

5GT/s

Memory BUS(DDRIII)

Dual Channel

1.5V DDRIII 1066/1333/1600 MT/s

200pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 11,12

GCLK

SLG3NB300VTR page 34

USB30 2x

5V 5GT/s

LVDS Conn.

page 22

Intel PCH

2 2

TP/B

page 41

3 3

LED+LID/B

page 41

RTC CKT.

page 24

HDMI Conn.

page 23

RJ45

page 35

RTL8105E-VD 10/100M

PCIe port 1

page 35

SPI ROM (4MB + 2MB)

page 24

PCIe Gen1 1x

1.5V 5GT/s

Debug Port

page 41

Panther Point

FCBGA-989

25mm*25mm

page 24,25,26,27,28,29,30,31,32

LPC BUS

3.3V 33 MHz

KB9012

page 40

HD Audio

3.3V 24MHz

USB20 3x

5V 480MHz

USB20 2x

5V 480MHz

PCIe Gen1 1x

1.5V 5GT/s

SATA Gen3 port 0

5V 6GHz(600MB/s)

SATA Gen3 port 1

5V 3GHz(300MB/s)

HDA Codec

ALC259

page 38

USB Left

USB20 port 2

page 37

CardReader RTS5137

PCIeMini Card WLAN

SATA HDD

SATA mSATA

PCIe port 2

page 34

SATA port 0

page 33

SATA port 1

page 34

USB Right

USB20 port 0,1 USB30 port 1,2

page 37

USB20 port 8

page 36

Int. Camera

USB port 11

page 22

DC/DC Interface CKT.

page 42

Power Circuit DC/DC

page 43,44,45,46,47,48, 49,50,51

Touch Pad

Int.KBD

page 41page 41

SPK Conn

page 39

JPIO (HP & MIC)

page 39

Power On/Off CKT.

4 4

page 41

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Block Diagram

VCUAA

253Tuesday, October 16, 2012

E

1.0

of

5

4

3

2

1

DESIGN CURRENT 0.1A

B+

D D

Ipeak=8.13A, Imax=5.69A, Iocp min=8.7

SUSP#

SY8033BDBC

DESIGN CURRENT 0.1A

DESIGN CURRENT 5A

DESIGN CURRENT 2A

+3VL +5VL

+5VALW

+1.8VS

SUSP

N-CHANNEL

SI4800

RT8205LZQW

C C

VCCP_PWRGOOD

SY8037

Ipeak=6A, Imax=4.A, Iocp min=8

Ipeak=5A, Imax=3.5A, Iocp min=6.2A

SUSP

N-CHANNEL

SI4800

WOL_EN#

P-CHANNEL

AO-3413

LCD_ENVDD

P-CHANNEL

AO-3413

DGPU_PWR_EN

P-CHANNEL

AO-3413

VR_ON

PJ6

NCP6132A

DESIGN CURRENT 4A

DESIGN CURRENT 6A

DESIGN CURRENT 5A

DESIGN CURRENT 330mA

DESIGN CURRENT 4A

DESIGN CURRENT 1.5A

DESIGN CURRENT 60mA

DESIGN CURRENT 2A

DESIGN CURRENT 94A

DESIGN CURRENT 33A

+5VS

+VCCSA

+3VALW

+3V_LAN

+3VS

+LCD_VDD

+3VS_DGPU

+3V_WLAN

+CPU_CORE +GFX_CORE

SUSP#

B B

TPS51212

Ipeak=20.53A, Imax=14.37A, Iocp min=23.91A

VGA_PWROK

P-CHANNEL

AO-3413

DESIGN CURRENT 60mA

+1.05VS_VCCP

+1.05VS_DGPU

SYSON

RT8207M

Ipeak=15A, Imax=10.5A, Iocp min=18A

SUSP

N-CHANNEL FDS6676AS

PJ1

SUSP or 0.75VR_EN#

DESIGN CURRENT 10A

DESIGN CURRENT 2A

DESIGN CURRENT 1.5A

+1.5V

+1.5V_CPU

+1.5VS

+0.75VS

VGA_PWROK

A A

SUSP#

TPS51518RUKR

5

N-CHANNEL FDS6676AS

Ipeak=33.8A, Imax=23.4A, Iocp min=40A

4

DESIGN CURRENT 8.6A

DESIGN CURRENT 20.5A

+VRAM_1.5VS

+VGA_CORE

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Power Tree

VCUAA

1

of

353Tuesday, October 16, 2012

of

353Tuesday, October 16, 2012

of

353Tuesday, October 16, 2012

1.0

A

Voltage Rails

power plane

1 1

State

( O MEANS ON X MEANS OFF )

+RTCVCC

B+

+5VL +3VL

+5VALW +3VALW +VSB

B

Platform

+1.5V

+5VS +3VS +1.8VS +1.5VS +1.05VS +0.75VS +CPU_CORE +VGA_CORE +GFX_CORE +VTT +VRAM_1.5VS +3VS_DGPU +1.05VS_DGPU

Chief River

BTO Option Table

Function

description

explain

BTO

C

SKU CPU PCH

Ivy Bridge i3 (CPUI3@) Ivy Bridge i5 (CPUI5@)

SKU MIC

HM77C1(HM77@) HM77C1_R1(HM77R1@) HM77C1_R3(HM77R3@)

LAN

D

E

VGA

nVIDIA N13P-GL (N13PGL@)

S0

S1

S3

2 2

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery don't exist

O O O O O O

O O O O O

X

O O O O O

X

O O O O

X X

O

XX X XX

OO OO

X

Function

description

X

explain

BTO

Function

PCH SM Bus Address

Power

+3VS +3VS

Device

DDR SO-DIMM 0 DDR SO-DIMM 1

HEX

Address

1010 0000 bA0 H 1010 0100 bA4 H

description

explain

BTO

Function

3 3

description

explain

BTO

EC SM Bus1 Address

Device Address Address

+3VL

EC SM Bus2 Address

HEX HEX

16 H

0001 0110 bSmart Battery

12 HSmart Charger 0001 0010 b+3VL

PowerPower

+3VS +3VS

HEXDevice AddressPower

Device

96 H

NVIDIA GPU 1001 1010 b

9E H

STATE

Full ON

1001 0110 bPCH

S1(Power On Suspend)

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

G3 LOW LOWLOW

SIGNAL

SLP_S3#

SLP_S4# SLP_S5#

HIGH HIGHHIGH

LOW

LOW LOW

HIGH HIGHHIGH

HIGH

LOW LOWLOW

HIGH

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Notes List

VCUAA

453Tuesday, October 16, 2012

E

1.0

of

A

@

PM_DRAM_PWRGD_R

CC621000P_0402_50V7K

12

@

12

1 1

+1.05VS_VCCP

RC44 62_0402_5%RC44 62_0402_5%

RC45 10K_0402_5%RC45 10K_0402_5%

2 2

+3VALW_PCH

RC11 200_0402_5%RC11 200_0402_5%

PM_PWROK<26,40> DRAMPWROK<26>

3 3

12

@

12

@

12

@

12

Please place near JCPU

DRAMPWROK

12

10K_0402_5%

RC13

+3VS

1 2

RC12 0_0402_5%@RC12 0_0402_5%@

CC631000P_0402_50V7K

CC701000P_0402_50V7K

CC671000P_0402_50V7K

CC661000P_0402_50V7K

12

1 2

RC184

SUSP<34,42,9>

H_PWRGOOD_R

H_PROCHOT#

H_PWRGOOD

H_PM_SYNC

BUF_CPU_RST#

+3VALW_PCH

5

1

P

B

2

A

G

3

H_PECI

12

0.1U_0402_10V7K

0.1U_0402_10V7K CC33

CC33

UC3

UC3 74AHC1G09GW_TSSOP5

74AHC1G09GW_TSSOP5

PM_SYS_PWRGD_BUF

4

O

0_0402_5%@

SUSP

QC2

2

G

12

RC25

RC25 39_0402_5%

39_0402_5% @

@

13

D

2N7002KW_SOT323-3

@

S

Buffered Rest to CPU

+3VS

0.1U_0402_10V7K

1

CC36

PLT_RST# <28,34,35,40,41>

UC2

PLT_RST#

4 4

UC2

1

OE#

2

IN

3

GND

74AHC1G125GW_SOT353-5

2

5

VCC

BUFO_CPU_RST# BUF_CPU_RST#

4

OUT

+1.05VS_VCCP

12

RC38

RC38 75_0402_5%

75_0402_5%

43_0402_1%

1 2

RC35

12

RC40

RC40 0_0402_5%

0_0402_5% @

@

H_PROCHOT#<40>

H_THERMTRIP#<29>

H_PM_SYNC<26>

H_PWRGOOD<29>

+1.5V_CPU

12

RC14

RC14 200_0402_5%

200_0402_5%

B

H_SNB_IVB#<29>

T1 PADT1 PAD

T2 PADT2 PAD

H_PECI<40>

1 2

RC170 130_0402_5%RC170 130_0402_5%

H_SNB_IVB#

TP_SKTOCC#

H_CATERR#

H_PECI

RC159

H_PROCHOT#_R

1 2

56_0402_5%

H_THERMTRIP#

H_PM_SYNC

@

H_PWRGOOD_R

1 2

RC183 0_0402_5%

PM_DRAM_PWRGD_RPM_SYS_PWRGD_BUF

BUF_CPU_RST#

UC1B

F49

PROC_SELECT#

C57

PROC_DETECT#

C49

CATERR#

A48

PECI

C45

PROCHOT#

D45

THERMTRIP#

C48

PM_SYNC

B46

UNCOREPWRGOOD

BE45

SM_DRAMPWROK

D44

RESET#

IVY-BRIDGE_BGA1023 <BOM>

XDP Connector

C

MISC THERMAL PWR MANAGEMENT

CLOCKS

DDR3

JTAG & BPM

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

MISC

BCLK

BCLK#

SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2]

PRDY#

PREQ#

TCK TMS

TRST#

TDO

DBR#

BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7]

J3 H2

AG3 AG1

AT30

BF44 BE43 BG43

N53 N55

L56 L55 J58

M60

TDI

L59

K58

G58 E55 E59 G55 G59 H60 J59 J61

10U_0805_10V6K

D

100 MHz

CLK_CPU_DMI CLK_CPU_DMI#

DPLL_REF_CLK DPLL_REF_CLK#

H_DRAMRST#

SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2

XDP_TCK XDP_TMS XDP_TRST#

XDP_TDI XDP_TDO

RC56 140_0402_1%RC56 140_0402_1% RC59 25.5_0402_1%RC59 25.5_0402_1% RC61 200_0402_1%RC61 200_0402_1%

CLK_CPU_DMI <25> CLK_CPU_DMI# <25>

H_DRAMRST# <7>

12 12 12

T3 PAD@T3 PAD@ T4 PAD@T4 PAD@

1 2

RC55 51_0402_5%RC55 51_0402_5%

T6 PAD@T6 PAD@ T7 PAD@T7 PAD@

Close to CPU side

+5VS +3VS

1A

@

2

C3

1

@

1 2

R1 0_0603_5%

+FAN1

FAN_SPEED1<40>

DPLL_REF_CLK# DPLL_REF_CLK

H_DRAMRST#

RC157 1K_0402_5%RC157 1K_0402_5% RC158 1K_0402_5%RC158 1K_0402_5%

CC34 180P_0402_50V8J

by ESD requestion and place near CPU

DDR3 Compensation Signals Layout Note:Place these resistors near Processor

Routed as a single daisy chain

FAN Control Circuit

12

R2

R2 10K_0402_5%

10K_0402_5%

FANPWM<40>

D1

BAS16_SOT23-3

+FAN1

1

C4

0.01U_0402_25V7K

0.01U_0402_25V7K @

@

2

E

1 2 1 2

@

1 2

12

10U_0603_6.3V6M

1

2

C5

+1.05VS_VCCP

JFAN

@JFAN

@

7

GND2

6

GND1

5

4

3

2

1

ACES_88266-05001

1

C6

2

1000P_0402_50V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_JTAG/XDP/FAN

VCUAA

E

of

553Tuesday, October 16, 2012

1.0

A

B

C

D

E

+1.05VS_VCCP

RC1

24.9_0402_1%

UC1A

1 1

2 2

+1.05VS_VCCP +1.05VS_VCCP

3 3

DMI_PTX_CRX_N0<26> DMI_PTX_CRX_N1<26> DMI_PTX_CRX_N2<26> DMI_PTX_CRX_N3<26>

DMI_PTX_CRX_P0<26> DMI_PTX_CRX_P1<26> DMI_PTX_CRX_P2<26> DMI_PTX_CRX_P3<26>

DMI_CTX_PRX_N0<26> DMI_CTX_PRX_N1<26> DMI_CTX_PRX_N2<26> DMI_CTX_PRX_N3<26>

DMI_CTX_PRX_P0<26> DMI_CTX_PRX_P1<26> DMI_CTX_PRX_P2<26> DMI_CTX_PRX_P3<26>

FDI_CTX_PRX_N0<26> FDI_CTX_PRX_N1<26> FDI_CTX_PRX_N2<26> FDI_CTX_PRX_N3<26> FDI_CTX_PRX_N4<26> FDI_CTX_PRX_N5<26> FDI_CTX_PRX_N6<26> FDI_CTX_PRX_N7<26>

FDI_CTX_PRX_P0<26> FDI_CTX_PRX_P1<26> FDI_CTX_PRX_P2<26> FDI_CTX_PRX_P3<26> FDI_CTX_PRX_P4<26> FDI_CTX_PRX_P5<26> FDI_CTX_PRX_P6<26> FDI_CTX_PRX_P7<26>

FDI_FSYNC0<26> FDI_FSYNC1<26>

FDI_INT<26> FDI_LSYNC0<26>

FDI_LSYNC1<26>

RC2 24.9_0402_1%RC2 24.9_0402_1%

1 2

RC333 1K_0402_5%RC333 1K_0402_5%

1 2

DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3

DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7

FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7

FDI_FSYNC0 FDI_FSYNC1

FDI_INT FDI_LSYNC0

FDI_LSYNC1

EDP_COMP

M2

DMI_RX#[0]

P6

DMI_RX#[1]

P1

DMI_RX#[2]

P10

DMI_RX#[3]

N3

DMI_RX[0]

P7

DMI_RX[1]

P3

DMI_RX[2]

P11

DMI_RX[3]

K1

DMI_TX#[0]

M8

DMI_TX#[1]

N4

DMI_TX#[2]

R2

DMI_TX#[3]

K3

DMI_TX[0]

M7

DMI_TX[1]

P4

DMI_TX[2]

T3

DMI_TX[3]

U7

FDI0_TX#[0]

W11

FDI0_TX#[1]

W1

FDI0_TX#[2]

AA6

FDI0_TX#[3]

W6

FDI1_TX#[0]

V4

FDI1_TX#[1]

Y2

FDI1_TX#[2]

AC9

FDI1_TX#[3]

U6

FDI0_TX[0]

W10

FDI0_TX[1]

W3

FDI0_TX[2]

AA7

FDI0_TX[3]

W7

FDI1_TX[0]

T4

FDI1_TX[1]

AA3

FDI1_TX[2]

AC8

FDI1_TX[3]

AA11

FDI0_FSYNC

AC12

FDI1_FSYNC

U11

FDI_INT

AA10

FDI0_LSYNC

AG8

FDI1_LSYNC

AF3

eDP_COMPIO

AD2

eDP_ICOMPO

AG11

eDP_HPD#

AG4

eDP_AUX#

AF4

eDP_AUX

AC3

eDP_TX#[0]

AC4

eDP_TX#[1]

AE11

eDP_TX#[2]

AE7

eDP_TX#[3]

AC1

eDP_TX[0]

AA4

eDP_TX[1]

AE10

eDP_TX[2]

AE6

eDP_TX[3]

IVY-BRIDGE_BGA1023 <BOM>

DMI Intel(R) FDI

eDP

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8]

PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15]

PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8]

PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15]

PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8]

PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15]

PCI EXPRESS -- GRAPHICS

PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8]

PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15]

G3 G1 G4

PCIE_GTX_C_CRX_N0

H22

PCIE_GTX_C_CRX_N1

J21

PCIE_GTX_C_CRX_N2

B22

PCIE_GTX_C_CRX_N3

D21

PCIE_GTX_C_CRX_N4

A19

PCIE_GTX_C_CRX_N5

D17

PCIE_GTX_C_CRX_N6

B14

PCIE_GTX_C_CRX_N7

D13

PCIE_GTX_C_CRX_N8

A11

PCIE_GTX_C_CRX_N9

B10

PCIE_GTX_C_CRX_N10

G8

PCIE_GTX_C_CRX_N11

A8

PCIE_GTX_C_CRX_N12

B6

PCIE_GTX_C_CRX_N13

H8

PCIE_GTX_C_CRX_N14

E5

PCIE_GTX_C_CRX_N15

K7

PCIE_GTX_C_CRX_P0

K22

PCIE_GTX_C_CRX_P1

K19

PCIE_GTX_C_CRX_P2

C21

PCIE_GTX_C_CRX_P3

D19

PCIE_GTX_C_CRX_P4

C19

PCIE_GTX_C_CRX_P5

D16

PCIE_GTX_C_CRX_P6

C13

PCIE_GTX_C_CRX_P7

D12

PCIE_GTX_C_CRX_P8

C11

PCIE_GTX_C_CRX_P9

C9

PCIE_GTX_C_CRX_P10

F8

PCIE_GTX_C_CRX_P11

C8

PCIE_GTX_C_CRX_P12

C5

PCIE_GTX_C_CRX_P13

H6

PCIE_GTX_C_CRX_P14

F6

PCIE_GTX_C_CRX_P15

K6

PCIE_CTX_GRX_N0

G22

PCIE_CTX_GRX_N1

C23

PCIE_CTX_GRX_N2

D23

PCIE_CTX_GRX_N3

F21

PCIE_CTX_GRX_N4

H19

PCIE_CTX_GRX_N5

C17

PCIE_CTX_GRX_N6

K15

PCIE_CTX_GRX_N7

F17

PCIE_CTX_GRX_N8

F14

PCIE_CTX_GRX_N9

A15

PCIE_CTX_GRX_N10

J14

PCIE_CTX_GRX_N11

H13

PCIE_CTX_GRX_N12

M10

PCIE_CTX_GRX_N13

F10

PCIE_CTX_GRX_N14

D9

PCIE_CTX_GRX_N15

J4

PCIE_CTX_GRX_P0

F22

PCIE_CTX_GRX_P1

A23

PCIE_CTX_GRX_P2

D24

PCIE_CTX_GRX_P3

E21

PCIE_CTX_GRX_P4

G19

PCIE_CTX_GRX_P5

B18

PCIE_CTX_GRX_P6

K17

PCIE_CTX_GRX_P7

G17

PCIE_CTX_GRX_P8

E14

PCIE_CTX_GRX_P9

C15

PCIE_CTX_GRX_P10

K13

PCIE_CTX_GRX_P11

G13

PCIE_CTX_GRX_P12

K10

PCIE_CTX_GRX_P13

G10

PCIE_CTX_GRX_P14

D8

PCIE_CTX_GRX_P15

K4

PEG_COMP

24.9_0402_1%

CC8 0.22U_0402_16V7KOPT@CC8 0.22U_0402_16V7KOPT@ CC11 0.22U_0402_16V7KOPT@CC11 0.22U_0402_16V7KOPT@ CC16 0.22U_0402_16V7KOPT@CC16 0.22U_0402_16V7KOPT@ CC20 0.22U_0402_16V7KOPT@CC20 0.22U_0402_16V7KOPT@ CC27 0.22U_0402_16V7KOPT@CC27 0.22U_0402_16V7KOPT@ CC30 0.22U_0402_16V7KOPT@CC30 0.22U_0402_16V7KOPT@ CC1 0.22U_0402_16V7KOPT@CC1 0.22U_0402_16V7KOPT@ CC4 0.22U_0402_16V7KOPT@CC4 0.22U_0402_16V7KOPT@ CC15 0.22U_0402_16V7KOPT@CC15 0.22U_0402_16V7KOPT@ CC18 0.22U_0402_16V7KOPT@CC18 0.22U_0402_16V7KOPT@ CC22 0.22U_0402_16V7KOPT@CC22 0.22U_0402_16V7KOPT@ CC24 0.22U_0402_16V7KOPT@CC24 0.22U_0402_16V7KOPT@ CC29 0.22U_0402_16V7KOPT@CC29 0.22U_0402_16V7KOPT@ CC26 0.22U_0402_16V7KOPT@CC26 0.22U_0402_16V7KOPT@ CC3 0.22U_0402_16V7KOPT@CC3 0.22U_0402_16V7KOPT@ CC32 0.22U_0402_16V7KOPT@CC32 0.22U_0402_16V7KOPT@

CC10 0.22U_0402_16V7KOPT@CC10 0.22U_0402_16V7KOPT@ CC5 0.22U_0402_16V7KOPT@CC5 0.22U_0402_16V7KOPT@ CC6 0.22U_0402_16V7KOPT@CC6 0.22U_0402_16V7KOPT@ CC7 0.22U_0402_16V7KOPT@CC7 0.22U_0402_16V7KOPT@ CC12 0.22U_0402_16V7KOPT@CC12 0.22U_0402_16V7KOPT@ CC9 0.22U_0402_16V7KOPT@CC9 0.22U_0402_16V7KOPT@ CC19 0.22U_0402_16V7KOPT@CC19 0.22U_0402_16V7KOPT@ CC14 0.22U_0402_16V7KOPT@CC14 0.22U_0402_16V7KOPT@ CC13 0.22U_0402_16V7KOPT@CC13 0.22U_0402_16V7KOPT@ CC17 0.22U_0402_16V7KOPT@CC17 0.22U_0402_16V7KOPT@ CC21 0.22U_0402_16V7KOPT@CC21 0.22U_0402_16V7KOPT@ CC23 0.22U_0402_16V7KOPT@CC23 0.22U_0402_16V7KOPT@ CC28 0.22U_0402_16V7KOPT@CC28 0.22U_0402_16V7KOPT@ CC25 0.22U_0402_16V7KOPT@CC25 0.22U_0402_16V7KOPT@ CC2 0.22U_0402_16V7KOPT@CC2 0.22U_0402_16V7KOPT@ CC31 0.22U_0402_16V7KOPT@CC31 0.22U_0402_16V7KOPT@

PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical

12

impedance = 43 m ohm (4 mils) PEG_ICOMPO signals should be routed with max length = 500 mils

- typical impedance = 14.5 m ohm (12 mils)

PCIE_GTX_C_CRX_N[0..15] <13>

PCIE_GTX_C_CRX_P[0..15] <13>

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

PCIE_CTX_C_GRX_N0 PCIE_CTX_C_GRX_N1 PCIE_CTX_C_GRX_N2 PCIE_CTX_C_GRX_N3 PCIE_CTX_C_GRX_N4 PCIE_CTX_C_GRX_N5 PCIE_CTX_C_GRX_N6 PCIE_CTX_C_GRX_N7 PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_N9 PCIE_CTX_C_GRX_N10 PCIE_CTX_C_GRX_N11 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_N15

PCIE_CTX_C_GRX_P0 PCIE_CTX_C_GRX_P1 PCIE_CTX_C_GRX_P2 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_P4 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_P6 PCIE_CTX_C_GRX_P7 PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_P9 PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_P15

PCIE_CTX_C_GRX_N[0..15] <13>

PCIE_CTX_C_GRX_P[0..15] <13>

PEG DG suggest AC cap

IVY Bridge

Gen1/Gen2

Gen3

SANDY Bridge Gen1/Gen2 180 nF~265 nF

NV N13X Gen1/2/3 Suggest 220 nF

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

75 nF~265 nF

180 nF~265 nF

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DMI/PEG/FDI

VCUAA

653Tuesday, October 16, 2012

E

of

1.0

A

DDR_A_D[0..63]<11>

UC1C

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6

1 1

2 2

DDR_A_BS0<11> DDR_A_BS1<11>

3 3

DDR_A_BS2<11>

DDR_A_CAS#<11> DDR_A_RAS#<11>

DDR_A_WE#<11>

DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

DDR_A_BS0 DDR_A_BS1 DDR_A_BS2

DDR_A_CAS# DDR_A_RAS# DDR_A_WE#

AP11

AJ10

AR11

AT13 AU13

BA13 BB11

AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43

AW48

BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56

BD37

BF36

BA28

BE39 BD39 AT41

AG6

AU6 AR6

BC7

AJ6 AL6 AJ8

AL8 AL7

AP6 AV9 AP8

BB7

BA7 BA9 BB9

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

SA_BS[0] SA_BS[1] SA_BS[2]

SA_CAS# SA_RAS# SA_WE#

DDR SYSTEM MEMORY A

B

SA_CK[0] SA_CK#[0] SA_CKE[0]

SA_CK[1] SA_CK#[1] SA_CKE[1]

SA_CS#[0] SA_CS#[1]

SA_ODT[0] SA_ODT[1]

SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7]

SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

C

DDR_B_D[0..63]<12>

UC1D

DDRA_CLK0

AU36

DDRA_CLK0#

AV36

DDRA_CKE0

AY26

DDRA_CLK1 DDRB_CLK1

AT40

DDRA_CLK1# DDRB_CLK1#

AU40

DDRA_CKE1 DDRB_CKE1

BB26

DDRA_SCS0# DDRB_SCS0#

BB40

DDRA_SCS1#

BC41

DDRA_ODT0 DDRB_ODT0

AY40

DDRA_ODT1

BA41

DDR_A_DQS#0

AL11

DDR_A_DQS#1

AR8

DDR_A_DQS#2

AV11

DDR_A_DQS#3

AT17

DDR_A_DQS#4

AV45

DDR_A_DQS#5

AY51

DDR_A_DQS#6

AT55

DDR_A_DQS#7

AK55

DDR_A_DQS0

AJ11

DDR_A_DQS1

AR10

DDR_A_DQS2

AY11

DDR_A_DQS3

AU17

DDR_A_DQS4

AW45

DDR_A_DQS5

AV51

DDR_A_DQS6

AT56

DDR_A_DQS7

AK54

DDR_A_MA0

BG35

DDR_A_MA1

BB34

DDR_A_MA2

BE35

DDR_A_MA3

BD35

DDR_A_MA4

AT34

DDR_A_MA5

AU34

DDR_A_MA6

BB32

DDR_A_MA7

AT32

DDR_A_MA8

AY32

DDR_A_MA9

AV32

DDR_A_MA10

BE37

DDR_A_MA11

BA30

DDR_A_MA12

BC30

DDR_A_MA13

AW41

DDR_A_MA14

AY28

DDR_A_MA15

AU26

DDRA_CLK0 <11> DDRB_CLK0 <12> DDRA_CLK0# <11> DDRA_CKE0 <11> DDRB_CKE0 <12>

DDRA_CLK1 <11> DDRA_CLK1# <11> DDRB_CLK1# <12> DDRA_CKE1 <11>

DDRA_SCS0# <11> DDRA_SCS1# <11> DDRB_SCS1# <12>

DDRA_ODT0 <11> DDRB_ODT0 <12> DDRA_ODT1 <11> DDRB_ODT1 <12>

DDR_A_DQS#[0..7] <11>

DDR_A_DQS[0..7] <11>

DDR_A_MA[0..15] <11>

DDR_B_BS0<12> DDR_B_BS1<12> DDR_B_BS2<12>

DDR_B_CAS#<12> DDR_B_RAS#<12>

DDR_B_WE#<12>

DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63

DDR_B_BS0 DDR_B_BS1 DDR_B_BS2

DDR_B_CAS# DDR_B_RAS# DDR_B_WE#

BD13 BF12

BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54

BA58 AW59 AW58

AU58

AN61

AN59

AU59

AU61

AN58

AR58

AK58

AL58 AG58 AG59

AM60

AL59 AF61 AH60

BG39 BD42 AT22

AV43 BF40 BD45

AL4

SB_DQ[0]

AL1

SB_DQ[1]

AN3

SB_DQ[2]

AR4

SB_DQ[3]

AK4

SB_DQ[4]

AK3

SB_DQ[5]

AN4

SB_DQ[6]

AR1

SB_DQ[7]

AU4

SB_DQ[8]

AT2

SB_DQ[9]

AV4

SB_DQ[10]

BA4

SB_DQ[11]

AU3

SB_DQ[12]

AR3

SB_DQ[13]

AY2

SB_DQ[14]

BA3

SB_DQ[15]

BE9

SB_DQ[16]

BD9

SB_DQ[17] SB_DQ[18] SB_DQ[19]

BF8

SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

SB_BS[0] SB_BS[1] SB_BS[2]

SB_CAS# SB_RAS# SB_WE#

D

BA34

SB_CK[0]

AY34

SB_CK#[0]

AR22

SB_CKE[0]

BA36

SB_CK[1]

BB36

SB_CK#[1]

BF27

SB_CKE[1]

BE41

SB_CS#[0]

BE47

SB_CS#[1]

AT43

SB_ODT[0]

BG47

SB_ODT[1]

AL3

SB_DQS#[0]

AV3

SB_DQS#[1]

BG11

SB_DQS#[2]

BD17

SB_DQS#[3]

BG51

SB_DQS#[4]

BA59

SB_DQS#[5]

AT60

SB_DQS#[6]

AK59

SB_DQS#[7]

AM2

SB_DQS[0]

AV1

SB_DQS[1]

BE11

SB_DQS[2]

BD18

SB_DQS[3]

BE51

SB_DQS[4]

BA61

SB_DQS[5]

AR59

SB_DQS[6]

AK61

SB_DQS[7]

DDR SYSTEM MEMORY B

BF32

SB_MA[0]

BE33

SB_MA[1]

BD33

SB_MA[2]

AU30

SB_MA[3]

BD30

SB_MA[4]

AV30

SB_MA[5]

BG30

SB_MA[6]

BD29

SB_MA[7]

BE30

SB_MA[8]

BE28

SB_MA[9]

BD43

SB_MA[10]

AT28

SB_MA[11]

AV28

SB_MA[12]

BD46

SB_MA[13]

AT26

SB_MA[14]

AU22

SB_MA[15]

DDRB_CLK0 DDRB_CLK0# DDRB_CKE0

DDRB_SCS1#

DDRB_ODT1

DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7

DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7

DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8

DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15

E

DDRB_CLK0# <12>

DDRB_CLK1 <12> DDRB_CKE1 <12>

DDRB_SCS0# <12>

DDR_B_DQS#[0..7] <12>

DDR_B_DQS[0..7] <12>

DDR_B_MA[0..15] <12>

IVY-BRIDGE_BGA1023 <BOM>

+1.5V

RC75

0_0402_5%

1 2

@

QC3

D

S

D

S

DDR3_DRAMRST#_RH_DRAMRST#

1 2

13

BSS138_NL_SOT23-3

G

2

1

CC37

0.047U_0402_25V6K

2

H_DRAMRST#<5>

RC78

4.99K_0402_1%

4 4

@

DRAMRST_CNTRL

DRAMRST_CNTRL_PCH<11,25>

EC_DRAMRST_CNTRL_PCH<40>

1 2

RC73 0_0402_5%

1 2

RC3 0_0402_5%

A

RC76

1K_0402_5%

12

1 2

B

RC77

RC77 1K_0402_5%

1K_0402_5%

1

2

Request by ESD

SM_DRAMRST# <11,12>

CC35

CC35 180P_0402_50V8J

180P_0402_50V8J

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

IVY-BRIDGE_BGA1023 <BOM>

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_DDR3

VCUAA

753Tuesday, October 16, 2012

E

of

1.0

A

B

C

D

E

+CPU_CORE +1.05VS_VCCP

1 1

2 2

3 3

4 4

A

UC1F

A26

VCC[1]

A29

VCC[2]

A31

VCC[3]

A34

VCC[4]

A35

VCC[5]

A38

VCC[6]

A39

VCC[7]

A42

VCC[8]

C26

VCC[9]

C27

VCC[10]

C32

VCC[11]

C34

VCC[12]

C37

VCC[13]

C39

VCC[14]

C42

VCC[15]

D27

VCC[16]

D32

VCC[17]

D34

VCC[18]

D37

VCC[19]

D39

VCC[20]

D42

VCC[21]

E26

VCC[22]

E28

VCC[23]

E32

VCC[24]

E34

VCC[25]

E37

VCC[26]

E38

VCC[27]

F25

VCC[28]

F26

VCC[29]

F28

VCC[30]

F32

VCC[31]

F34

VCC[32]

F37

VCC[33]

F38

VCC[34]

F42

VCC[35]

G42

VCC[36]

H25

VCC[37]

H26

VCC[38]

H28

VCC[39]

H29

VCC[40]

H32

VCC[41]

H34

VCC[42]

H35

VCC[43]

H37

VCC[44]

H38

VCC[45]

H40

VCC[46]

J25

VCC[47]

J26

VCC[48]

J28

VCC[49]

J29

VCC[50]

J32

VCC[51]

J34

VCC[52]

J35

VCC[53]

J37

VCC[54]

J38

VCC[55]

J40

VCC[56]

J42

VCC[57]

K26

VCC[58]

K27

VCC[59]

K29

VCC[60]

K32

VCC[61]

K34

VCC[62]

K35

VCC[63]

K37

VCC[64]

K39

VCC[66]

K42

VCC[67]

L25

VCC[68]

L28

VCC[69]

L33

VCC[70]

L36

VCC[71]

L40

VCC[72]

N26

VCC[73]

N30

VCC[74]

N34

VCC[75]

N38

VCC[76]

IVY-BRIDGE_BGA1023 <BOM>

POWER

CORE SUPPLY

8.5A33A

AF46

VCCIO[1]

AG48

VCCIO[3]

AG50

VCCIO[4]

AG51

VCCIO[5]

AJ17

VCCIO[6]

AJ21

VCCIO[7]

AJ25

VCCIO[8]

AJ43

VCCIO[9]

AJ47

VCCIO[10]

AK50

VCCIO[11]

AK51

VCCIO[12]

AL14

VCCIO[13]

AL15

VCCIO[14]

AL16

VCCIO[15]

AL20

VCCIO[16]

AL22

VCCIO[17]

AL26

VCCIO[18]

AL45

VCCIO[19]

AL48

VCCIO[20]

AM16

VCCIO[21]

AM17

VCCIO[22]

AM21

VCCIO[23]

AM43

VCCIO[24]

AM47

VCCIO[25]

AN20

VCCIO[26]

AN42

VCCIO[27]

AN45

VCCIO[28]

AN48

VCCIO[29]

AA14

VCCIO[30]

AA15

VCCIO[31]

AB17

VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49]

VCCIO50 VCCIO51

1mA

VCCIO_SEL

VCCPQE[1] VCCPQE[2]

VIDALERT#

VIDSCLK

VIDSOUT

AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15

+1.05VS_VCCP

W16 W17

BC22

+1.05VS_VCCP

AM25 AN22

H_CPU_SVIDALRT#

A44

H_CPU_SVIDCLK

B43

H_CPU_SVIDDAT

C44

VCCSENSE_R

F43

VSSSENSE_R

G43

AN16 AN17

Close to CPU

PEG IO AND DDR IO

RAILS

VCC_SENSE VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

SENSE LINES SVID QUIET

B

For DDR

For PEG

1

CC71

CC71 1U_0402_6.3V6K

1U_0402_6.3V6K

2

RC94 0_0402_5%@RC94 0_0402_5%@ RC95 0_0402_5%

RC95 0_0402_5%

VCCIO_SENSE

VCCIO_SENSE_VSS

12 RC96

RC96 10_0402_1%

10_0402_1%

12 RC98

RC98 10_0402_1%

10_0402_1%

0.1U_0402_10V7K

0.1U_0402_10V7K 1 2

CC50

@

12

RC91

RC91 130_0402_5%

130_0402_5%

RC90 43_0402_1%RC90 43_0402_1% RC88 0_0402_5%

RC88 0_0402_5% RC92 0_0402_5%

+CPU_CORE

1 2

@

1 2

VCCIO_SENSE <47>

+1.05VS_VCCP

VCCIO_SENSE_VSS <47>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

RC92 0_0402_5%

RC93

RC93 100_0402_1%

100_0402_1%

1 2

12

RC97

RC97 100_0402_1%

100_0402_1%

Close to CPU

C

+1.05VS_VCCP+1.05VS_VCCP

12

1 2

@

1 2

@

1 2

VCCSENSE <49> VSSSENSE <49>

2012/04/19 2015/04/19

Reserve 0.1u to avoid noise

0.1U_0402_10V7K

0.1U_0402_10V7K 1 2

CC49

@

RC89

RC89 75_0402_5%

75_0402_5%

VR_SVID_ALRT# <49> VR_SVID_CLK <49> VR_SVID_DAT <49>

Pull high resistor on VR side

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_POWER-1

VCUAA

853Tuesday, October 16, 2012

E

1.0

of

A

B

C

D

E

+GFX_CORE

UC1G

29A

AA46

VAXG[1]

AB47

VAXG[2]

AB50

VAXG[3]

AB51

1 1

2 2

+GFX_CORE

12

RC105

RC105 100_0402_1%

100_0402_1%

Close to CPU

CC41

1

2

CC76

1

2

CC59

CC59 1

2

10U_0805_10V6K

1U_0402_6.3V6K

VCC_AXG_SENSE VSS_AXG_SENSE

1 2

+1.8VS_VCCPLL

CC60

CC60 1

2

10U_0805_10V6K

CC43

CC43 1

@

2

10U_0805_10V6K

CC75

CC75 1

2

1U_0402_6.3V6K

RC106

RC106 100_0402_1%

100_0402_1%

CC61

CC61 1

2

1U_0402_6.3V6K

CC40

CC58

1

@

2

10U_0805_10V6K

CC74

CC73

1

2

1U_0402_6.3V6K

10U_0805_10V6K

1U_0402_6.3V6K

VCC_AXG_SENSE<49> VSS_AXG_SENSE<49>

3 3

4 4

VCCPLL Decoupling: 1X 330U (6m ohm), 1X 10U, 2x1U

+1.8VS

+VCCSA Decoupling:

@

1 2

RC119 0_0805_5%

+VCCSA

1 CC44

CC44

+

@

2

330U_D2_2VM_R6M

Place TOP IN BGA

CC42

CC42 1

2

10U_0805_10V6K

Place BOT OUT BGA

CC77

CC77 1

2

1U_0402_6.3V6K

VAXG[4]

AB52

VAXG[5]

AB53

VAXG[6]

AB55

VAXG[7]

AB56

VAXG[8]

AB58

VAXG[9]

AB59

VAXG[10]

AC61

VAXG[11]

AD47

VAXG[12]

AD48

VAXG[13]

AD50

VAXG[14]

AD51

VAXG[15]

AD52

VAXG[16]

AD53

VAXG[17]

AD55

VAXG[18]

AD56

VAXG[19]

AD58

VAXG[20]

AD59

VAXG[21]

AE46

VAXG[22]

N45

VAXG[23]

P47

VAXG[24]

P48

VAXG[25]

P50

VAXG[26]

P51

VAXG[27]

P52

VAXG[28]

P53

VAXG[29]

P55

VAXG[30]

P56

VAXG[31]

P61

VAXG[32]

T48

VAXG[33]

T58

VAXG[34]

T59

VAXG[35]

T61

VAXG[36]

U46

VAXG[37]

V47

VAXG[38]

V48

VAXG[39]

V50

VAXG[40]

V51

VAXG[41]

V52

VAXG[42]

V53

VAXG[43]

V55

VAXG[44]

V56

VAXG[45]

V58

VAXG[46]

V59

VAXG[47]

W50

VAXG[48]

W51

VAXG[49]

W52

VAXG[50]

W53

VAXG[51]

W55

VAXG[52]

W56

VAXG[53]

W61

VAXG[54]

Y48

VAXG[55]

Y61

VAXG[56]

F45

VAXG_SENSE

G45

VSSAXG_SENSE

1.2A

BB3

VCCPLL[1]

BC1

VCCPLL[2]

BC4

VCCPLL[3]

6A

L17

VCCSA[1]

L21

VCCSA[2]

N16

VCCSA[3]

N20

VCCSA[4]

N22

VCCSA[5]

P17

VCCSA[6]

P20

VCCSA[7]

R16

VCCSA[8]

R18

VCCSA[9]

R21

VCCSA[10]

U15

VCCSA[11]

V16

VCCSA[12]

V17

VCCSA[13]

V18

VCCSA[14]

V21

VCCSA[15]

W20

VCCSA[16]

IVY-BRIDGE_BGA1023 <BOM>

POWER

VREF

DDR3 - 1.5V RAILS

GRAPHICS

SENSE

LINES

SENSE

LINES

1.8V RAIL

SA RAIL

VCCSA VID

SM_VREF

SA_DIMM_VREFDQ SB_DIMM_VREFDQ

VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8]

VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26]

1mA

VCCDQ[1] VCCDQ[2]

QUIET RAILS

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

SENSE LINES

VCCSA_VID[0] VCCSA_VID[1]

lines

5A

+V_SM_VREF should have 20 mil trace width

AY43

BE7 BG7

AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33

AM28 AN26

BC43 BA43

U10

D48 D49

+V_SM_VREF

+VREF_DQA_M3 +VREF_DQB_M3

CC57

CC57 1

2

CC82

CC82 1

2

+1.5V_CPU

1

CC72

CC72 1U_0402_6.3V6K

1U_0402_6.3V6K

2

1 2

RC111 0_0402_5%

H_VCCSA_VID0 H_VCCSA_VID1

Please kindly check whether there is pull-down resister in PWR-side or HW-side

CC65

CC65 1

2

0.1U_0402_10V7K

Place TOP IN BGA

CC52

CC51

1

2

10U_0805_10V6K

CC80

CC81

1

2

1U_0402_6.3V6K

+VCCSA_SENSE <48>

@

H_VCCSA_VID0 <48> H_VCCSA_VID1 <48>

RC120 1K_0402_0.5%RC120 1K_0402_0.5%

RC109 1K_0402_0.5%RC109 1K_0402_0.5%

+1.5V_CPU Decoupling: 1X 330U (6m ohm), 6X 10U, 8X 1U

CC55

CC55 1

2

10U_0805_10V6K

Place BOT OUT BGA

CC79

CC79 1

2

1U_0402_6.3V6K

+1.5V_CPU

1 2 1 2

+1.5V_CPU

CC56

CC54

CC54 1

2

10U_0805_10V6K

CC78

CC78 1

2

1U_0402_6.3V6K

VCCSA_VID0

10U_0805_10V6K

1U_0402_6.3V6K

1

2

CC87

CC87 1

2

0

1

+

10U_0805_10V6K

CC86

CC86 1

2

1U_0402_6.3V6K

1

CC53

@

330U_D2_2VM_R6M

2

ESR 6mohm

CC85

CC85 1

2

1U_0402_6.3V6K

VCCSA_VID1

0

1

0

CC84

CC84 1

@

2

11

+1.5V_CPU +1.5V

CC46 0.1U_0402_10V7KCC46 0.1U_0402_10V7K

1 2

CC47 0.1U_0402_10V7KCC47 0.1U_0402_10V7K

1 2

CC48 0.1U_0402_10V7KCC48 0.1U_0402_10V7K

1 2

CC45 0.1U_0402_10V7KCC45 0.1U_0402_10V7K

1 2

2N7002KDWH_SOT363-6

SUSP

CC83

CC83 1

@

2

1U_0402_6.3V6K

+VCCSA

0.90 V

0.80 V

0.725 V

0.675 V

Vgs=10V,Id=14.5A,Rds=6mohm

RC203

470_0805_5%

1 2 34

QC5B

5

For Sandy Bridge

1

CC68

CC68 10U_0805_10V6K

10U_0805_10V6K @

@

2

0.1U_0402_25V6

CC69

2

JUMP_43X118

JUMP_43X118 QC4

QC4

1

S

2

S

3

S

4

G

FDS6676AS_SO8

1

2

PJ1

@PJ1

@

112

8

D

7

D

6

D

5

D

RUN_ON_CPU1.5VS3

12

RC205

RC205 820K_0402_5%

820K_0402_5%

+1.5VS+1.5V_CPU

C464

4.7U_0805_10V4Z

4.7U_0805_10V4Z 1 2

C463

+1.5V

1 2

1U_0402_6.3V6K

1 2

C469

4.7U_0805_10V4Z

220K_0402_5%

61

QC5A

2N7002KDWH_SOT363-6

@

RC204

1 2

SUSP

2

+VSB

SUSP <34,42,5>

1X 330U (6m ohm), 3X 10U, 5X 1U

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_POWER-2

VCUAA

953Tuesday, October 16, 2012

E

1.0

of

UC1H

A13

VSS[1]

A17

VSS[2]

A21

VSS[3]

A25

VSS[4]

A28

VSS[5]

A33

VSS[6]

A37

VSS[7]

A40

VSS[8]

A45

VSS[9]

A49

AA13 AA50 AA51 AA52 AA53 AA55 AA56

AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46

AD17 AD20

AD61 AE13

AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61

AG7 AH4

AH58

AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48

AK1

AK52

AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47

AL61 AM13 AM20 AM22 AM26 AM30 AM34

VSS[10]

A53

VSS[11]

A9

VSS[12]

AA1

VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20]

AA8

VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29]

AC6

VSS[30] VSS[31] VSS[32]

AD4

VSS[33] VSS[34] VSS[35]

AE8

VSS[36]

AF1

VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69]

AJ7

VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90]

1 1

2 2

3 3

A

VSS

VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180]

AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13

UC1I

BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53

BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35

D4 D40 D43 D46 D50 D54 D58

D6

E25 E29

E3 E35 E40 F13 F15 F19 F29 F35 F40 F55

G51

G6 G61 H10 H14 H17 H21

H4 H53 H58

J1 J49 J55 K11 K21 K51

K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61

M11 M15

IVY-BRIDGE_BGA1023 <BOM>

VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249]

B

VSS

VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301]

VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8

VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11

NCTF

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14

M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48

A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61

C

UC1E

CFG0

B50

T89 PAD@T89 PAD@

CFG2 CFG4

CFG5 CFG6 CFG7

@

T87PAD@T87PAD

CFG[0]

C51

CFG[1]

B54

CFG[2]

D53

CFG[3]

A51

CFG[4]

C53

CFG[5]

C55

CFG[6]

H49

CFG[7]

A55

CFG[8]

H51

CFG[9]

K49

CFG[10]

K53

CFG[11]

F53

CFG[12]

G53

CFG[13]

L51

CFG[14]

F51

CFG[15]

D52

CFG[16]

L53

CFG[17]

H43

VCC_VAL_SENSE

K43

VSS_VAL_SENSE

H45

VAXG_VAL_SENSE

K45

VSSAXG_VAL_SENSE

F48

VCC_DIE_SENSE

H48

RSVD6

K48

RSVD7

BA19

RSVD8

AV19

RSVD9

AT21

RSVD10

BB21

RSVD11

BB19

RSVD12

AY21

RSVD13

BA22

RSVD14

AY22

RSVD15

AU19

RSVD16

AU21

RSVD17

BD21

RSVD18

BD22

RSVD19

BD25

RSVD20

BD26

RSVD21

BG22

RSVD22

BE22

RSVD23

BG26

RSVD24

BE26

RSVD25

BF23

RSVD26

BE24

RSVD27

IVY-BRIDGE_BGA1023 <BOM>

BCLK_ITP

BCLK_ITP#

RSVD30 RSVD31 RSVD32 RSVD33

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38

RSVD39 RSVD40

RSVD41 RSVD42 RSVD43 RSVD44

RESERVED

RSVD45

These pins are for solder joint reliability and non-critical to function. For BGA only.

DC_TEST_A4 DC_TEST_C4 DC_TEST_D3

DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61

DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58

DC_TEST_BG4 DC_TEST_BG3

DC_TEST_BE3

DC_TEST_BG1

DC_TEST_BE1

DC_TEST_BD1

D

N59 N58

N42 L42 L45 L47

M13 M14 U14 W14 P13

AT49 K24

AH2 AG13 AM14 AM15

N50

A4 C4

DC_TEST_C4_D3

D3 D1 A58 A59

DC_TEST_A59_C59

C59 A61

DC_TEST_A61_C61

C61 D61 BD61 BE61

DC_TEST_BE61_BE59

BE59 BG61

DC_TEST_BG61_BG59

BG59 BG58 BG4 BG3

DC_TEST_BG3_BE3

BE3 BG1

DC_TEST_BG1_BE1

BE1 BD1

E

CFG Straps for Processor

(CFG[17:0] internal pull high 5~15K to VCCIO)

CFG2

12

RC79

RC79 1K_0402_1%

1K_0402_1% OPT@

OPT@

PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition

CFG2

matches socket pin map definition 0:Lane Reversed

*

CFG4

12

RC82

RC82 1K_0402_1%

1K_0402_1% @

@

Embedded Display Port Presence Strap

1 : Disabled; No Physical Display Port

*

CFG4

attached to Embedded Display Port 0 : Enabled; An external Display Port

device is connected to the Embedded Display Port

CFG7

12

RC85

RC85 1K_0402_1%

1K_0402_1% @

@

PEG DEFER TRAINING

1: (Default) PEG Train immediately

*

CFG7

following xxRESETB de assertion 0: PEG Wait for BIOS for training

CFG6 CFG5

1K_0402_1%

RC83

12

RC84

RC84 1K_0402_1%

1K_0402_1%

@

PCIE Port Bifurcation Straps

IVY-BRIDGE_BGA1023 <BOM>

CFG[6:5]

4 4

11: (Default) x16 - Device 1 functions 1 and 2

*

disabled 10: x8, x8 - Device 1 function 1 enabled;

function 2 disabled 01: Reserved - (Device 1 function 1 disabled;

function 2 enabled) 00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

Ivy Bridge_GND/RSVD/CFG

VCUAA

E

of

10 53Tuesday, October 16, 2012

1.0

A

+VREF_DQA

1

CD1

CD2

0.1U_0402_10V7K

0.1U_0402_10V7K 2

1 1

Close to JDDR3R.1

DDR_A_BS2<7>

2 2

DDRA_CLK0<7> DDRA_CLK0#<7>

DDR_A_BS0<7>

DDR_A_WE#<7>

DDR_A_CAS#<7>

DDRA_SCS1#<7>

3 3

+3VS

CD25

2.2U_0402_6.3V6M

@

4 4

DDR_A_D0 DDR_A_D1

1

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M 2

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_DQS#1 DDR_A_DQS1

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_DQS#2 DDR_A_DQS2

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_D26 DDR_A_D27

DDRA_CKE0

DDR_A_BS2 DDR_A_MA12

DDR_A_MA9 DDR_A_MA8

DDR_A_MA5 DDR_A_MA3

DDR_A_MA1 DDRA_CLK0

DDRA_CLK0# DDR_A_MA10

DDR_A_BS0 DDR_A_WE#

DDR_A_CAS# DDR_A_MA13

DDRA_SCS1#

DDR_A_D32 DDR_A_D33

DDR_A_DQS#4 DDR_A_DQS4

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_DQS#6 DDR_A_DQS6

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_D58 DDR_A_D59

RD8

1 2

10K_0402_5%

1

CD26

10K_0402_5%

2

0.1U_0402_10V7K

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

RD9

12

+0.75VS

+1.5V

JDDR3R

1

VREF_DQ

3

VSS

5

DQ0

7

DQ1

9

VSS

11

DM0

13

VSS

15

DQ2

17

DQ3

19

VSS

21

DQ8

23

DQ9

25

VSS

27

DQS1#

29

DQS1

31

VSS

33

DQ10

35

DQ11

37

VSS

39

DQ16

41

DQ17

43

VSS

45

DQS2#

47

DQS2

49

VSS

51

DQ18

53

DQ19

55

VSS

57

DQ24

59

DQ25

61

VSS

63

DM3

65

VSS

67

DQ26

69

DQ27

71

VSS

73

CKE0

75

VDD

77

NC

79

BA2

81

VDD

83

A12/BC#

85

A9

87

VDD

89

A8

91

A5

93

VDD

95

A3

97

A1

99

VDD

101

CK0

103

CK0#

105

VDD

107

A10/AP

109

BA0

111

VDD

113

WE#

115

CAS#

117

VDD

119

A13

121

S1#

123

VDD

125

TEST

127

VSS

129

DQ32

131

DQ33

133

VSS

135

DQS4#

137

DQS4

139

VSS

141

DQ34

143

DQ35

145

VSS

147

DQ40

149

DQ41

151

VSS

153

DM5

155

VSS

157

DQ42

159

DQ43

161

VSS

163

DQ48

165

DQ49

167

VSS

169

DQS6#

171

DQS6

173

VSS

175

DQ50

177

DQ51

179

VSS

181

DQ56

183

DQ57

185

VSS

187

DM7

189

VSS

191

DQ58

193

DQ59

195

VSS

197

SA0

199

VDDSPD

201

SA1

203

VTT

205

GND1

207

BOSS1

LCN_DAN06-K4406-0103

LCN_DAN06-K4406-0103 @

@

VSS DQ4 DQ5 VSS

DQS0#

DQS0

VSS DQ6 DQ7

VSS DQ12 DQ13

VSS

DM1

RESET#

VSS DQ14 DQ15

VSS DQ20 DQ21

VSS

DM2

VSS DQ22 DQ23

VSS DQ28 DQ29

VSS

DQS3#

DQS3

VSS DQ30 DQ31

VSS

CKE1

VDD

CK1

CK1#

VDD

BA1

RAS#

VDD

S0#

ODT0

VDD ODT1

VDD

VREF_CA

VSS DQ36 DQ37

VSS

DM4

VSS DQ38 DQ39

VSS DQ44 DQ45

VSS

DQS5#

DQS5

VSS DQ46 DQ47

VSS DQ52 DQ53

VSS

DM6

VSS DQ54 DQ55

VSS DQ60 DQ61

VSS

DQS7#

DQS7

VSS DQ62 DQ63

VSS

EVENT#

SDA

SCL

VTT GND2

BOSS2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108 110 112 114 116 118 120 122

NC

124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206 208

+1.5V

DDR_A_D4 DDR_A_D5

DDR_A_DQS#0 DDR_A_DQS0

DDR_A_D6 DDR_A_D7

DDR_A_D12 DDR_A_D13

SM_DRAMRST# DDR_A_D14

DDR_A_D15 DDR_A_D20

DDR_A_D21

DDR_A_D22 DDR_A_D23

DDR_A_D28 DDR_A_D29

DDR_A_DQS#3 DDR_A_DQS3

DDR_A_D30 DDR_A_D31

DDRA_CKE1 DDR_A_MA15

DDR_A_MA14 DDR_A_MA11

DDR_A_MA7 DDR_A_MA6

DDR_A_MA4 DDR_A_MA2

DDR_A_MA0 DDRA_CLK1

DDRA_CLK1# DDR_A_BS1

DDR_A_RAS# DDRA_SCS0#

DDRA_ODT0 DDRA_ODT1

+VREF_CAA DDR_A_D36

DDR_A_D37

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_DQS#5 DDR_A_DQS5

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_DQS#7 DDR_A_DQS7

DDR_A_D62 DDR_A_D63

PM_SMBDATA PM_SMBCLK

+0.75VS

B

DDR3 SO-DIMM A Reverse Type

Intel DDR Vref M3

SM_DRAMRST# <12,7>

DDRA_CKE1 <7>DDRA_CKE0<7>

DDRA_CLK1 <7> DDRA_CLK1# <7>

DDR_A_BS1 <7> DDR_A_RAS# <7>

DDRA_SCS0# <7> DDRA_ODT0 <7>

DDRA_ODT1 <7>

1

CD15

2.2U_0402_6.3V6M

close to JDDR3R.126

PM_SMBDATA <12,25,34,41> PM_SMBCLK <12,25,34,41>

1

CD16

0.1U_0402_10V7K

2

C

DDR_A_DQS[0..7] <7> DDR_A_DQS#[0..7] <7> DDR_A_D[0..63] <7> DDR_A_MA[0..15] <7>

@

12

0_0402_5%

RC115

BSS138_NL_SOT23-3

QC7

D

S

D

S

+VREF_DQA_M3

@

1 2

RC117 1K_0402_1%

@

1 2

RC118 1K_0402_1%

+VREF_DQB_M3

+1.5V

12

RD6

1K_0402_1%

12

RD7

1K_0402_1%

Layout Note: Place near JDDRH

+1.5V

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

@

1 2

CD3 330U_D2_2VM_R6M

+

CD8 10U_0603_6.3V6MCD8 10U_0603_6.3V6M

1 2

CD9 10U_0603_6.3V6MCD9 10U_0603_6.3V6M

1 2

CD10 10U_0603_6.3V6MCD10 10U_0603_6.3V6M

1 2

CD11 10U_0603_6.3V6MCD11 10U_0603_6.3V6M

1 2

CD12 10U_0603_6.3V6MCD12 10U_0603_6.3V6M

1 2

CD13 10U_0603_6.3V6MCD13 10U_0603_6.3V6M

1 2

2012/04/19 2015/04/19

13

G

2

G

2

13

D

S

D

S

QC8

BSS138_NL_SOT23-3

@

12

0_0402_5%

RC116

+1.5V

1 2

CD50 33P_0402_50V8KCD50 33P_0402_50V8K

1 2

CD51 33P_0402_50V8KCD51 33P_0402_50V8K

1 2

CD52 33P_0402_50V8KCD52 33P_0402_50V8K

1 2

CD53 33P_0402_50V8KCD53 33P_0402_50V8K

1 2

CD54 33P_0402_50V8KCD54 33P_0402_50V8K

1 2

CD55 33P_0402_50V8KCD55 33P_0402_50V8K

Compal Secret Data

Deciphered Date

D

+VREF_DQA

DRAMRST_CNTRL_PCH <25,7>

+VREF_DQB

Layout Note: Place these 4 Caps near Command and Control signals of DIMMA

+1.5V +0.75VS

CD20 0.1U_0402_10V7KCD20 0.1U_0402_10V7K

1 2

CD17 0.1U_0402_10V7KCD17 0.1U_0402_10V7K

1 2

CD18 0.1U_0402_10V7KCD18 0.1U_0402_10V7K

1 2

CD19 0.1U_0402_10V7KCD19 0.1U_0402_10V7K

1 2

D

E

+1.5V

12

+VREF_DQA

+VREF_DQB

please place these caps near the reference power plane of CMD/AD

Layout Note: Place near JDDRH.203 and 204

CD56 10U_0603_6.3V6MCD56 10U_0603_6.3V6M

1 2

CD24 1U_0402_6.3V6KCD24 1U_0402_6.3V6K CD21 1U_0402_6.3V6KCD21 1U_0402_6.3V6K CD22 1U_0402_6.3V6KCD22 1U_0402_6.3V6K CD23 1U_0402_6.3V6KCD23 1U_0402_6.3V6K

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM0

VCUAA

12

+1.5V

12

12 12 12 12

E

RD1

1K_0402_1%

RD2

1K_0402_1%

RD10

1K_0402_1%

RD11

1K_0402_1%

of

11 53Tuesday, October 16, 2012

1.0

A

+VREF_DQB

1

CD28

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M 2

1 1

Close to JDDR3S.1

DDRB_CKE0<7>

DDR_B_BS2<7>

2 2

DDRB_CLK0<7> DDRB_CLK0#<7>

DDR_B_WE#<7> DDR_B_CAS#<7>

DDRB_SCS1#<7>

3 3

+3VS

4 4

CD48

2.2U_0402_6.3V6M

1

2

1

2

0.1U_0402_10V7K

CD27

0.1U_0402_10V7K

CD49

1

2

RD14

RD14 10K_0402_5%

10K_0402_5%

RD15

1 2

10K_0402_5%

DDR_B_D0 DDR_B_D1

DDR_B_D2 DDR_B_D3

DDR_B_D8 DDR_B_D9

DDR_B_DQS#1 DDR_B_DQS1

DDR_B_D10 DDR_B_D11

DDR_B_D16 DDR_B_D17

DDR_B_DQS#2 DDR_B_DQS2

DDR_B_D18 DDR_B_D19

DDR_B_D24 DDR_B_D25

DDR_B_D26 DDR_B_D27

DDRB_CKE0

DDR_B_BS2 DDR_B_MA12

DDR_B_MA9 DDR_B_MA8

DDR_B_MA5 DDR_B_MA3

DDR_B_MA1 DDRB_CLK0

DDRB_CLK0# DDR_B_MA10

DDR_B_BS0 DDR_B_WE#

DDR_B_CAS# DDR_B_MA13

DDRB_SCS1#

DDR_B_D32 DDR_B_D33

DDR_B_DQS#4 DDR_B_DQS4

DDR_B_D34 DDR_B_D35

DDR_B_D40 DDR_B_D41

DDR_B_D42 DDR_B_D43

DDR_B_D48 DDR_B_D49

DDR_B_DQS#6 DDR_B_DQS6

DDR_B_D50 DDR_B_D51

DDR_B_D56 DDR_B_D57

DDR_B_D58 DDR_B_D59

1 2

+0.75VS

+1.5V

JDDR3S

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

LCN_DAN06-K4406-0102

LCN_DAN06-K4406-0102 @

@

DQ4 DQ5

VSS3

DQS#0

DQS0

VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1 CK1#

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL VTT2

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72

74 76 78

A15

80

A14

82 84

A11

86

A7

88 90

A6

92

A4

94 96

A2

98

A0

100 102 104 106 108

BA1

110 112 114

S0#

116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

G2

B

+1.5V

DDR_B_D4 DDR_B_D5

DDR_B_DQS#0

DDR_B_DQS0

DDR_B_D6 DDR_B_D7

DDR_B_D12 DDR_B_D13

SM_DRAMRST# DDR_B_D14

DDR_B_D15 DDR_B_D20

DDR_B_D21

DDR_B_D22 DDR_B_D23

DDR_B_D28 DDR_B_D29

DDR_B_DQS#3

DDR_B_DQS3

DDR_B_D30 DDR_B_D31

DDRB_CKE1 DDR_B_MA15

DDR_B_MA14 DDR_B_MA11

DDR_B_MA7 DDR_B_MA6

DDR_B_MA4 DDR_B_MA2

DDR_B_MA0 DDRB_CLK1

DDRB_CLK1# DDR_B_BS1

DDR_B_RAS# DDRB_SCS0#

DDRB_ODT0 DDRB_ODT1

+VREF_CAB DDR_B_D36

DDR_B_D37

DDR_B_D38 DDR_B_D39

DDR_B_D44 DDR_B_D45

DDR_B_DQS#5

DDR_B_DQS5

DDR_B_D46 DDR_B_D47

DDR_B_D52 DDR_B_D53

DDR_B_D54 DDR_B_D55

DDR_B_D60 DDR_B_D61

DDR_B_DQS#7

DDR_B_DQS7

DDR_B_D62 DDR_B_D63

PM_SMBDATA PM_SMBCLK

+0.75VS

Standard Type DDR3 SO-DIMM B

SM_DRAMRST# <11,7>

DDRB_CKE1 <7>

DDRB_CLK1 <7> DDRB_CLK1# <7>

DDR_B_BS1 <7> DDR_B_RAS# <7>DDR_B_BS0<7>

DDRB_SCS0# <7> DDRB_ODT0 <7>

DDRB_ODT1 <7>

1

CD47

1

CD46

0.1U_0402_10V7K

2.2U_0402_6.3V6M

Close to JDDR3S.126

PM_SMBDATA <11,25,34,41> PM_SMBCLK <11,25,34,41>

2

+1.5V

12

1K_0402_1%

12

1K_0402_1%

C

RD12

RD13

+1.5V

CD31 330U_D2_2VM_R6M

CD31 330U_D2_2VM_R6M CD41 10U_0603_6.3V6MCD41 10U_0603_6.3V6M CD36 10U_0603_6.3V6MCD36 10U_0603_6.3V6M CD37 10U_0603_6.3V6MCD37 10U_0603_6.3V6M CD38 10U_0603_6.3V6MCD38 10U_0603_6.3V6M CD39 10U_0603_6.3V6MCD39 10U_0603_6.3V6M CD40 10U_0603_6.3V6MCD40 10U_0603_6.3V6M

Layout Note: Place near JDDRL

1 2

+

1 2 1 2 1 2 1 2 1 2 1 2

D

DDR_B_DQS#[0..7] <7> DDR_B_DQS[0..7] <7> DDR_B_D[0..63] <7> DDR_B_MA[0..15] <7>

Layout Note: Place these 4 Caps near Command and Control signals of DIMMB

CD33 0.1U_0402_10V7KCD33 0.1U_0402_10V7K

1 2

CD29 0.1U_0402_10V7KCD29 0.1U_0402_10V7K

1 2

CD30 0.1U_0402_10V7KCD30 0.1U_0402_10V7K

1 2

CD32 0.1U_0402_10V7KCD32 0.1U_0402_10V7K

1 2

E

Layout Note: Place near JDDRL.203 and 204

+0.75VS+1.5V

CD57 10U_0603_6.3V6MCD57 10U_0603_6.3V6M

1 2

CD45 1U_0402_6.3V6KCD45 1U_0402_6.3V6K

12

CD42 1U_0402_6.3V6KCD42 1U_0402_6.3V6K

12

CD43 1U_0402_6.3V6KCD43 1U_0402_6.3V6K

12

CD44 1U_0402_6.3V6KCD44 1U_0402_6.3V6K

12

SPD setting (SA0, SA1) PU/PD by Channel A/B

->Channel A 00

->Channel B 01

A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

DDRIII-SODIMM1

VCUAA

12 53Tuesday, October 16, 2012

E

1.0

of

A

PCIE_CTX_C_GRX_P15 PCIE_CTX_C_GRX_N15 PCIE_CTX_C_GRX_P14 PCIE_CTX_C_GRX_N14 PCIE_CTX_C_GRX_P13 PCIE_CTX_C_GRX_N13 PCIE_CTX_C_GRX_P12 PCIE_CTX_C_GRX_N12 PCIE_CTX_C_GRX_P11 PCIE_CTX_C_GRX_N11

1 1

0.22U_0402_16V7K

PCIE_GTX_C_CRX_P15 PCIE_GTX_C_CRX_N15 PCIE_GTX_C_CRX_P14 PCIE_GTX_C_CRX_N14 PCIE_GTX_C_CRX_P13 PCIE_GTX_C_CRX_N13 PCIE_GTX_C_CRX_P12 PCIE_GTX_C_CRX_N12 PCIE_GTX_C_CRX_P11 PCIE_GTX_CRX_P11

2 2

PCIE_GTX_C_CRX_N11 PCIE_GTX_C_CRX_P10 PCIE_GTX_C_CRX_N10 PCIE_GTX_C_CRX_P9 PCIE_GTX_C_CRX_N9 PCIE_GTX_C_CRX_P8 PCIE_GTX_C_CRX_N8 PCIE_GTX_C_CRX_P7 PCIE_GTX_C_CRX_N7 PCIE_GTX_C_CRX_P6 PCIE_GTX_C_CRX_N6 PCIE_GTX_C_CRX_P5 PCIE_GTX_C_CRX_N5 PCIE_GTX_C_CRX_P4 PCIE_GTX_C_CRX_N4 PCIE_GTX_C_CRX_P3 PCIE_GTX_C_CRX_N3 PCIE_GTX_C_CRX_P2 PCIE_GTX_C_CRX_N2 PCIE_GTX_C_CRX_P1 PCIE_GTX_C_CRX_N1

PCIE_GTX_C_CRX_N0

3 3

CLK_REQ_VGA#<25>

4 4

2N7002KW_SOT323-3

CV35

OPT@ CV35

OPT@

CV37

OPT@ CV37

OPT@

CV39 0.22U_0402_16V7KOPT@ CV39 0.22U_0402_16V7KOPT@ CV45 0.22U_0402_16V7KOPT@ CV45 0.22U_0402_16V7KOPT@ CV93 0.22U_0402_16V7KOPT@ CV93 0.22U_0402_16V7KOPT@ CV98

OPT@ CV98

OPT@

CV94

OPT@ CV94

OPT@

CV99 0.22U_0402_16V7KOPT@ CV99 0.22U_0402_16V7KOPT@ CV107 0.22U_0402_16V7KOPT@ CV107 0.22U_0402_16V7KOPT@ CV105 0.22U_0402_16V7KOPT@ CV105 0.22U_0402_16V7KOPT@ CV199

OPT@ CV199

OPT@

CV108

OPT@ CV108

OPT@

CV200 0.22U_0402_16V7KOPT@ CV200 0.22U_0402_16V7KOPT@ CV202 0.22U_0402_16V7KOPT@ CV202 0.22U_0402_16V7KOPT@ CV201 0.22U_0402_16V7KOPT@ CV201 0.22U_0402_16V7KOPT@ CV204

OPT@ CV204

OPT@

CV203

OPT@ CV203

OPT@

CV205 0.22U_0402_16V7KOPT@ CV205 0.22U_0402_16V7KOPT@ CV207 0.22U_0402_16V7KOPT@ CV207 0.22U_0402_16V7KOPT@ CV206 0.22U_0402_16V7KOPT@ CV206 0.22U_0402_16V7KOPT@ CV209

OPT@ CV209

OPT@

CV208

OPT@ CV208

OPT@

CV210 0.22U_0402_16V7KOPT@ CV210 0.22U_0402_16V7KOPT@ CV212 0.22U_0402_16V7KOPT@ CV212 0.22U_0402_16V7KOPT@ CV211 0.22U_0402_16V7KOPT@ CV211 0.22U_0402_16V7KOPT@ CV214

OPT@ CV214

OPT@

CV213

OPT@ CV213

OPT@

CV215 0.22U_0402_16V7KOPT@ CV215 0.22U_0402_16V7KOPT@ CV217 0.22U_0402_16V7KOPT@ CV217 0.22U_0402_16V7KOPT@ CV216 0.22U_0402_16V7KOPT@ CV216 0.22U_0402_16V7KOPT@ CV219 0.22U_0402_16V7KOPT@ CV219 0.22U_0402_16V7KOPT@ CV220 0.22U_0402_16V7KOPT@ CV220 0.22U_0402_16V7KOPT@

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

1 2 1 2 1 2 1 2

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

1 2 1 2 1 2 1 2

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

1 2 1 2 1 2 1 2

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

1 2 1 2 1 2 1 2

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

1 2 1 2 1 2 1 2

0.22U_0402_16V7K

1 2

0.22U_0402_16V7K

1 2 1 2 1 2 1 2 1 2 1 2

CLK_PCIE_VGA<25>

CLK_PCIE_VGA#<25>

1 2

RV16 200_0402_1%

PLTRST_VGA#<28>

13

D

S

QV3

OPT@

RV182 0_0402_5%

1 2

2

G

1

CV46

0.1U_0402_10V7K

0.1U_0402_10V7K @

@

2

PCIE_CTX_C_GRX_P10 PCIE_CTX_C_GRX_N10

PCIE_CTX_C_GRX_P9

PCIE_CTX_C_GRX_N9

PCIE_CTX_C_GRX_P8

PCIE_CTX_C_GRX_N8

PCIE_CTX_C_GRX_P7

PCIE_CTX_C_GRX_N7

PCIE_CTX_C_GRX_P6

PCIE_CTX_C_GRX_N6

PCIE_CTX_C_GRX_P5

PCIE_CTX_C_GRX_N5

PCIE_CTX_C_GRX_P4

PCIE_CTX_C_GRX_N4

PCIE_CTX_C_GRX_P3

PCIE_CTX_C_GRX_N3

PCIE_CTX_C_GRX_P2

PCIE_CTX_C_GRX_N2

PCIE_CTX_C_GRX_P1

PCIE_CTX_C_GRX_N1

PCIE_CTX_C_GRX_P0

PCIE_CTX_C_GRX_N0

PCIE_GTX_CRX_P15 PCIE_GTX_CRX_N15 PCIE_GTX_CRX_P14 PCIE_GTX_CRX_N14 PCIE_GTX_CRX_P13 PCIE_GTX_CRX_N13 PCIE_GTX_CRX_P12 PCIE_GTX_CRX_N12

PCIE_GTX_CRX_N11 PCIE_GTX_CRX_P10 PCIE_GTX_CRX_N10 PCIE_GTX_CRX_P9 PCIE_GTX_CRX_N9 PCIE_GTX_CRX_P8 PCIE_GTX_CRX_N8 PCIE_GTX_CRX_P7 PCIE_GTX_CRX_N7 PCIE_GTX_CRX_P6 PCIE_GTX_CRX_N6 PCIE_GTX_CRX_P5 PCIE_GTX_CRX_N5 PCIE_GTX_CRX_P4 PCIE_GTX_CRX_N4 PCIE_GTX_CRX_P3 PCIE_GTX_CRX_N3 PCIE_GTX_CRX_P2 PCIE_GTX_CRX_N2 PCIE_GTX_CRX_P1 PCIE_GTX_CRX_N1 PCIE_GTX_CRX_P0PCIE_GTX_C_CRX_P0 PCIE_GTX_CRX_N0

CLK_PCIE_VGA CLK_PCIE_VGA#

OPT@

CLK_REQ_GPU# PEX_TSTCLK_OUT

PEX_TSTCLK_OUT#

+3VS_DGPU

@

1 2

RV19 2.49K_0402_1%

@

+3VS_DGPU

1 2

RV179

RV179 10K_0402_5%

10K_0402_5% OPT@

OPT@

CLK_REQ_GPU#

B

UV4A

AN12

PEX_RX0

AM12

PEX_RX0_N

AN14

PEX_RX1

AM14

PEX_RX1_N

AP14

PEX_RX2

AP15

PEX_RX2_N

AN15

PEX_RX3

AM15

PEX_RX3_N

AN17

PEX_RX4

AM17

PEX_RX4_N

AP17

PEX_RX5

AP18

PEX_RX5_N

AN18

PEX_RX6

AM18

PEX_RX6_N

AN20

PEX_RX7

AM20

PEX_RX7_N

AP20

PEX_RX8

AP21

PEX_RX8_N

AN21

PEX_RX9

AM21

PEX_RX9_N

AN23

PEX_RX10

AM23

PEX_RX10_N

AP23

PEX_RX11

AP24

PEX_RX11_N

AN24

PEX_RX12

AM24

PEX_RX12_N

AN26

PEX_RX13

AM26

PEX_RX13_N

AP26

PEX_RX14

AP27

PEX_RX14_N

AN27

PEX_RX15

AM27

PEX_RX15_N

AK14

PEX_TX0

AJ14

PEX_TX0_N

AH14

PEX_TX1

AG14

PEX_TX1_N

AK15

PEX_TX2

AJ15

PEX_TX2_N

AL16

PEX_TX3

AK16

PEX_TX3_N

AK17

PEX_TX4

AJ17

PEX_TX4_N

AH17

PEX_TX5

AG17

PEX_TX5_N

AK18

PEX_TX6

AJ18

PEX_TX6_N

AL19

PEX_TX7

AK19

PEX_TX7_N

AK20

PEX_TX8

AJ20

PEX_TX8_N

AH20

PEX_TX9

AG20

PEX_TX9_N

AK21

PEX_TX10

AJ21

PEX_TX10_N

AL22

PEX_TX11

AK22

PEX_TX11_N

AK23

PEX_TX12

AJ23

PEX_TX12_N

AH23

PEX_TX13

AG23

PEX_TX13_N

AK24

PEX_TX14

AJ24

PEX_TX14_N

AL25

PEX_TX15

AK25

PEX_TX15_N

AJ11

PEX_WAKE_N

AL13

PEX_REFCLK

AK13

PEX_REFCLK_N

AK12

PEX_CLKREQ_N

AJ26

PEX_TSTCLK_OUT

AK26

PEX_TSTCLK_OUT_N

AJ12

PEX_RST_N

AP29

PEX_TERMP

N13P-PES-A2_FCBGA908 N13PGLR1@

Part 1 of 7

GPIO

DACs

120mA

PCI EXPRESS

60mA 45mA 45mA

CLK

1

CV48

CV48 18P_0402_50V8J

18P_0402_50V8J NOGCLK@

NOGCLK@

2

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC DACA_VSYNC

DACA_VDD DACA_VREF DACA_RSET

I2CA_SCL I2CA_SDA

I2CB_SCL I2CB_SDA

I2CC_SCL

I2C

I2CC_SDA

I2CS_SCL I2CS_SDA

PLLVDD

SP_PLLVDD

VID_PLLVDD

XTAL_IN

XTAL_OUT

XTAL_OUTBUFF

XTAL_SSIN

1

VGA_VID_4

P6

VGA_VID_3

M3 L6 P5 P7

VGA_VID_1

L7

VGA_VID_2

M7 N8

OVERT#_VGA

M1

GPU_EVENT

M2 L1

VGA_VID_0

M5

GPS_DOWN#

N3

VGA_VID_5

M4 N4 P2 R8 M6

HDMI_HPD_VGA

R1 P3 P4 P1

AK9 AL10 AL9

AM9 AN9

AG10 AP9 AP8

VGA_CRT_CLK

R4

VGA_CRT_DATA

R5

HDCP_SCL

R7

HDCP_SDA

R6

VGA_EDID_CLK

R2

VGA_EDID_DATA

R3 T4

T3

Internal Thermal Sensor

+PLLVDD

AD8 AE8 AD7

XTAL_OUTBUFF

XTAL_SSIN

NOGCLK@

GND

3

4

XTALIN

XTAL_OUT

RV52

OPT@ RV52

OPT@

3

18P_0402_50V8J

H3 H2

J4 H1

YV3

1

GND

2

27MHZ_16PF_7V27000011

C

VGA_VID_4 <51> VGA_VID_3 <51>

VGA_VID_1 <51> VGA_VID_2 <51>

VGA_VID_0 <51> VGA_VID_5 <51>

12

CV225

CV225 10K_0402_5%

10K_0402_5% OPT@

OPT@

110804 check with NV pull down 10k if DAC unused

SMB_CLK_GPU SMB_DATA_GPU

+GPU_PLLVDD

12

RV45

CV38,CV40, CV41 under GPU close to ball : AE8,AD7

10K_0402_5%

OPT@

GPS_DOWN# <40>

EC GPS_DOWN# must be OD\Low to avoid leakage on OPT SKU.

LVDS

CV1971 under GPU close to ball : ADB

1

CV38

2

OPT@ CV38

OPT@

VGA_X1<34>

CV40

2

OPT@ CV40

OPT@

0.1U_0402_10V7K

1

CV41

2

0.1U_0402_10V7K

OPT@ CV41

OPT@

1 2

RV5 0_0402_5%

OPT@

Close to VGA side

XTAL_OUTXTALIN

1

CV49

NOGCLK@

2

1

2

0.1U_0402_10V7K

BLM18PG181SN1D_2P

1 2

OPT@

1

CV43

CV42

2

OPT@ CV43

OPT@

OPT@ CV42

OPT@

22U_0805_6.3V6M

4.7U_0402_6.3V6M

XTALIN

+PLLVDD

LV15

PCIE_GTX_C_CRX_P[0..15]<6>

PCIE_GTX_C_CRX_N[0..15]<6>

PCIE_CTX_C_GRX_P[0..15]<6>

PCIE_CTX_C_GRX_N[0..15]<6>

1

2

+1.05VS_DGPU

1

CV197

2

0.1U_0402_10V7K

OPT@ CV197

0.1U_0402_10V7K

OPT@

1

CV44

2

OPT@ CV44

OPT@

SMB_CLK_GPU

SMB_DATA_GPU

D

1

CV109

2

OPT@ CV109

OPT@

4.7U_0402_6.3V6M

10U_0603_6.3V6M

2.2K_0402_5%

PCIE_GTX_C_CRX_P[0..15]

PCIE_CTX_C_GRX_P[0..15]

PCIE_CTX_C_GRX_N[0..15]

1 2

BLM18PG330SN1D_0603

CV47

OPT@ CV47

OPT@

22U_0805_6.3V6M

+3VS_DGPU

RV22

OPT@

1 2

PCIE_GTX_C_CRX_N[0..15]

+1.05VS_DGPU

LV10

OPT@

RV24

2.2K_0402_5%

2.2K_0402_5% OPT@

OPT@

1 2

OPT@

QV1A

2N7002DW-T/R7_SOT363-6

1

2

+3VS_DGPU

4

2

2N7002DW-T/R7_SOT363-6

61

E

+3VS_DGPU

OPT@

VGA_EDID_CLK

VGA_EDID_DATA GPS_DOWN# GPU_EVENT OVERT#_VGA HDCP_SCL HDCP_SDA

VGA_CRT_DATA VGA_CRT_CLK

HDMI_HPD_VGA

CV53

OPT@ CV53

OPT@

10U_0603_6.3V6M

5

OPT@

OPT@ QV1B

QV1B

3

EC_SMB_CK2 <25,40>

EC_SMB_DA2 <25,40>

OPT@

1 2

RV6 2.2K_0402_5%

OPT@

1 2

RV7 2.2K_0402_5%

OPT@

1 2

RV32 10K_0402_5%

OPT@

1 2

RV10 10K_0402_5%

OPT@

1 2

RV37 10K_0402_5%

OPT@

1 2

RV11 2.2K_0402_5%

OPT@

1 2

RV12 2.2K_0402_5%

OPT@

1 2

RV13 2.2K_0402_5%

OPT@

1 2

RV14 2.2K_0402_5%

OPT@

RV608 100K_0402_5%

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

VGA_N13P PEG & DAC

13 53Tuesday, October 16, 2012

E

13 53Tuesday, October 16, 2012

1.0

of

A

VRAM Interface

UV4B

MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43

1 1

DQMA[3..0]<19>

DQMA[7..4]<18>

DQSA[3..0]<19>

DQSA[7..4]<18>

DQSA#[3..0]<19>

DQSA#[7..4]<18>

MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63

DQMA0 DQMA1 DQMA2DQMA2 DQMA3 DQMA4DQMA4 DQMA5 DQMA6 DQMA7

DQSA0 DQSA1 DQSA2 DQSA3 DQSA4 DQSA5 DQSA6 DQSA7

DQSA#0 DQSA#1 DQSA#2 DQSA#3 DQSA#4 DQSA#5 DQSA#6 DQSA#7

L28

FBA_D0

M29

FBA_D1

L29

FBA_D2

M28

FBA_D3

N31

FBA_D4

P29

FBA_D5

R29

FBA_D6

P28

FBA_D7

J28

FBA_D8

H29

FBA_D9

J29

FBA_D10

H28

FBA_D11

G29

FBA_D12

E31

FBA_D13

E32

FBA_D14

F30

FBA_D15

C34

FBA_D16

D32

FBA_D17

B33

FBA_D18

C33

FBA_D19

F33

FBA_D20

F32

FBA_D21

H33

FBA_D22

H32

FBA_D23

P34

FBA_D24

P32

FBA_D25

P31

FBA_D26

P33

FBA_D27

L31

FBA_D28

L34

FBA_D29

L32

FBA_D30

L33

FBA_D31

AG28

FBA_D32

AF29

FBA_D33

AG29

FBA_D34

AF28

FBA_D35

AD30

FBA_D36

AD29

FBA_D37

AC29

FBA_D38

AD28

FBA_D39

AJ29

FBA_D40

AK29

FBA_D41

AJ30

FBA_D42

AK28

FBA_D43

AM29

FBA_D44

AM31

FBA_D45

AN29

FBA_D46

AM30

FBA_D47

AN31

FBA_D48

AN32

FBA_D49

AP30

FBA_D50

AP32

FBA_D51

AM33

FBA_D52

AL31

FBA_D53

AK33

FBA_D54

AK32

FBA_D55

AD34

FBA_D56

AD32

FBA_D57

AC30

FBA_D58

AD33

FBA_D59

AF31

FBA_D60

AG34

FBA_D61

AG32

FBA_D62

AG33

FBA_D63

P30

FBA_DQM0

F31

FBA_DQM1

F34

FBA_DQM2

M32

FBA_DQM3

AD31

FBA_DQM4

AL29

FBA_DQM5

AM32

FBA_DQM6

AF34

FBA_DQM7

M31

FBA_DQS_WP0

G31

FBA_DQS_WP1

E33

FBA_DQS_WP2

M33

FBA_DQS_WP3

AE31

FBA_DQS_WP4

AK30

FBA_DQS_WP5

AN33

FBA_DQS_WP6

AF33

FBA_DQS_WP7

M30

FBA_DQS_RN0

H30

FBA_DQS_RN1

E34

FBA_DQS_RN2

M34

FBA_DQS_RN3

AF30

FBA_DQS_RN4

AK31

FBA_DQS_RN5

AM34

FBA_DQS_RN6

AF32

FBA_DQS_RN7

N13P-PES-A2_FCBGA908 N13PGLR1@

MDA[15..0]<19> MDA[31..16]<19> MDA[47..32]<18> MDA[63..48]<18>

Part 2 of 7

FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31

FBA_CMD_RFU0 FBA_CMD_RFU1

MEMORY INTERFACE

A

MEMORY INTERFACE

A

FBA_DEBUG0 FBA_DEBUG1

FBA_CLK0_N FBA_CLK1_N

FBA_WCK01

FBA_WCK01_N

FBA_WCK23

FBA_WCK23_N

FBA_WCK45

FBA_WCK45_N

FBA_WCK67

FBA_WCK67_N

FBA_WCKB01

FBA_WCKB01_N

FBA_WCKB23

FBA_WCKB23_N

FBA_WCKB45

FBA_WCKB45_N

FBA_WCKB67

FBA_WCKB67_N

35mA

FB_DLL_AVDD

66mA

FBA_PLL_AVDD

FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9

FBA_CLK0 FBA_CLK1

FB_CLAMP

FB_VREF

MDA[15..0] MDA[31..16] MDA[47..32] MDA[63..48]

CMDA0

U30

CMDA1

T31

CMDA2

U29

CMDA3

R34

CMDA4

R33

CMDA5

U32

CMDA6

U33

CMDA7

U28

CMDA8

V28

CMDA9

V29

CMDA10

V30

CMDA11

U34

CMDA12

U31

CMDA13

V34

CMDA14

V33

CMDA15

Y32

CMDA16

AA31

CMDA17

AA29

CMDA18

AA28

CMDA19

AC34

CMDA20

AC33

CMDA21

AA32

CMDA22

AA33

CMDA23

Y28

CMDA24

Y29

CMDA25

W31

CMDA26

Y30

CMDA27

AA34

CMDA28

Y31

CMDA29

Y34

CMDA30

Y33 V31

R32 AC32

FBA_DEBUG0 FBB_DEBUG0

R28 AC28

R30 R31 AB31 AC31

K31 L30 H34 J34 AG30 AG31 AJ34 AK34

J30 J31 J32 J33 AH31 AJ31 AJ32 AJ33

FB_CLAMP

E1

K27

+FB_AVDD

U27

H26

CMDA[30..0] <18,19>

RV57 60.4_0402_1%

@

12

@

12

RV59 60.4_0402_1%

CLKA0 <19> CLKA0# <19> CLKA1 <18> CLKA1# <18>

OPT@

1 2

RV7410K_0402_1%

CV51

1

2

0.1U_0402_10V7K

OPT@ CV51

0.1U_0402_10V7K

OPT@

+VRAM_1.5VS

1

CV50

2

OPT@

0.1U_0402_10V7K

MDC0 MDC1 MDC2 MDC3 MDC4 MDC5 MDC6 MDC7 MDC8 MDC9 MDC10 MDC11 MDC12 MDC13 MDC14 MDC15 MDC16 MDC17 MDC18 MDC19 MDC20 MDC21 MDC22 MDC23 MDC24 MDC25 MDC26 MDC27 MDC28 MDC29 MDC30 MDC31 MDC32 MDC33 MDC34 MDC35 MDC36 MDC37 MDC38 MDC39 MDC40 MDC41 MDC42 MDC43 MDC44 MDC45 MDC46 MDC47 MDC48 MDC49 MDC50 MDC51 MDC52 MDC53 MDC54 MDC55 MDC56 MDC57 MDC58 MDC59 MDC60 MDC61 MDC62

DQMC[3..0]<20>

DQMC[7..4]<21>

DQSC[3..0]<20>

DQSC[7..4]<21>

DQSC#[3..0]<20>

DQSC#[7..4]<21>

MDC63

DQMC0 DQMC1 DQMC2 DQMC3 DQMC4 DQMC5 DQMC6 DQMC7

DQSC0 DQSC1 DQSC2 DQSC3 DQSC4 DQSC5 DQSC6 DQSC7

DQSC#0 DQSC#1 DQSC#2 DQSC#3 DQSC#4 DQSC#5 DQSC#6 DQSC#7

MDC[15..0]<20> MDC[31..16]<20> MDC[47..32]<21> MDC[63..48]<21>

UV4C

G9

FBB_D0

E9

FBB_D1

G8

FBB_D2

F9

FBB_D3

F11

FBB_D4

G11

FBB_D5

F12

FBB_D6

G12

FBB_D7

G6

FBB_D8

F5

FBB_D9

E6

FBB_D10

F6

FBB_D11

F4

FBB_D12

G4

FBB_D13

E2

FBB_D14

F3

FBB_D15

C2

FBB_D16

D4

FBB_D17

D3

FBB_D18

C1

FBB_D19

B3

FBB_D20

C4

FBB_D21

B5

FBB_D22

C5

FBB_D23

A11

FBB_D24

C11

FBB_D25

D11

FBB_D26

B11

FBB_D27

D8

FBB_D28

A8

FBB_D29

C8

FBB_D30

B8

FBB_D31

F24

FBB_D32

G23

FBB_D33

E24

FBB_D34

G24

FBB_D35

D21

FBB_D36

E21

FBB_D37

G21

FBB_D38

F21

FBB_D39

G27

FBB_D40

D27

FBB_D41

G26

FBB_D42

E27

FBB_D43

E29

FBB_D44

F29

FBB_D45

E30

FBB_D46

D30

FBB_D47

A32

FBB_D48

C31

FBB_D49

C32

FBB_D50

B32

FBB_D51

D29

FBB_D52

A29

FBB_D53

C29

FBB_D54

B29

FBB_D55

B21

FBB_D56

C23

FBB_D57

A21

FBB_D58

C21

FBB_D59

B24

FBB_D60

C24

FBB_D61

B26

FBB_D62

C26

FBB_D63

E11

FBB_DQM0

E3

FBB_DQM1

A3

FBB_DQM2

C9

FBB_DQM3

F23

FBB_DQM4

F27

FBB_DQM5

C30

FBB_DQM6

A24

FBB_DQM7

D10

FBB_DQS_WP0

D5

FBB_DQS_WP1

C3

FBB_DQS_WP2

B9

FBB_DQS_WP3

E23

FBB_DQS_WP4

E28

FBB_DQS_WP5

B30

FBB_DQS_WP6

A23

FBB_DQS_WP7

D9

FBB_DQS_RN0

E4

FBB_DQS_RN1

B2

FBB_DQS_RN2

A9

FBB_DQS_RN3

D22

FBB_DQS_RN4

D28

FBB_DQS_RN5

A30

FBB_DQS_RN6

B23

FBB_DQS_RN7

N13P-PES-A2_FCBGA908 N13PGLR1@

MDC[15..0] MDC[31..16] MDC[47..32] MDC[63..48]

Part 3 of 7

FBB_CMD0 FBB_CMD1 FBB_CMD2 FBB_CMD3 FBB_CMD4 FBB_CMD5 FBB_CMD6 FBB_CMD7 FBB_CMD8

FBB_CMD9 FBB_CMD10 FBB_CMD11 FBB_CMD12 FBB_CMD13 FBB_CMD14 FBB_CMD15 FBB_CMD16 FBB_CMD17 FBB_CMD18 FBB_CMD19 FBB_CMD20 FBB_CMD21 FBB_CMD22 FBB_CMD23 FBB_CMD24 FBB_CMD25 FBB_CMD26 FBB_CMD27 FBB_CMD28 FBB_CMD29 FBB_CMD30 FBB_CMD31

FBB_CMD_RFU0 FBB_CMD_RFU1

FBB_DEBUG0

FBB_DEBUG1

MEMORY INTERFACE B

FBB_CLK0

FBB_CLK0_N

FBB_CLK1

FBB_CLK1_N

FBB_WCK01

FBB_WCK01_N

FBB_WCK23

FBB_WCK23_N

FBB_WCK45

FBB_WCK45_N

FBB_WCK67

FBB_WCK67_N

FBB_WCKB01

FBB_WCKB01_N

FBB_WCKB23

FBB_WCKB23_N

FBB_WCKB45

FBB_WCKB45_N

FBB_WCKB67

FBB_WCKB67_N

66mA

FBB_PLL_AVDD

D13 E14 F14 A12 B12 C14 B14 G15 F15 E15 D15 A14 D14 A15 B15 C17 D18 E18 F18 A20 B20 C18 B18 G18 G17 F17 D16 A18 D17 A17 B17 E17

C12 C20

G14 G20

D12 E12 E20 F20

F8 E8 A5 A6 D24 D25 B27 C27

D6 D7 C6 B6 F26 E26 A26 A27

H17

12mil

FBB_DEBUG1FBA_DEBUG1

CMDC0 CMDC1 CMDC2 CMDC3 CMDC4 CMDC5 CMDC6 CMDC7 CMDC8 CMDC9 CMDC10

CMDC11

CMDC12 CMDC13 CMDC14 CMDC15 CMDC16 CMDC17 CMDC18 CMDC19 CMDC20 CMDC21 CMDC22 CMDC23 CMDC24 CMDC25 CMDC26 CMDC27 CMDC28 CMDC29 CMDC30

1

2

OPT@

+FB_AVDD

CV52

0.1U_0402_10V7K

CMDC[30..0] <20,21>

RV58 60.4_0402_1%

@

12

@

12

RV60 60.4_0402_1%

CLKC0 <20> CLKC0# <20> CLKC1 <21> CLKC1# <21>

+1.05VS_DGPU

1

2

+VRAM_1.5VS

BLM18PG330SN1D_0603

LV5

1 2

OPT@

CV86

OPT@ CV86

OPT@

1U_0402_6.3V6K

+FB_AVDD

100mA

+FB_AVDD

1

CV233

2

OPT@CV233

OPT@

22U_0805_6.3V6M

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

N13P VRAM Interface

of

14 53Tuesday, October 16, 2012

1.0

5

D D

C C

B B

A A

UV4D

AM6

IFPA_TXC

AN6

IFPA_TXC_N

AP3

IFPA_TXD0

AN3

IFPA_TXD0_N

AN5

IFPA_TXD1

AM5

IFPA_TXD1_N

AL6

IFPA_TXD2

AK6

IFPA_TXD2_N

AJ6

IFPA_TXD3

AH6

IFPA_TXD3_N

AJ9

IFPB_TXC

AH9

IFPB_TXC_N

AP6

IFPB_TXD4

AP5

IFPB_TXD4_N

AM7

IFPB_TXD5

AL7

IFPB_TXD5_N

AN8

IFPB_TXD6

AM8

IFPB_TXD6_N

AK8

IFPB_TXD7

AL8

IFPB_TXD7_N

AK1

IFPC_L0

AJ1

IFPC_L0_N

AJ3

IFPC_L1

AJ2

IFPC_L1_N

AH3

IFPC_L2

AH4

IFPC_L2_N

AG5

IFPC_L3

AG4

IFPC_L3_N

AM1

IFPD_L0

AM2

IFPD_L0_N

AM3

IFPD_L1

AM4

IFPD_L1_N

AL3

IFPD_L2

AL4

IFPD_L2_N

AK4

IFPD_L3

AK5

IFPD_L3_N

AD2

IFPE_L0

AD3

IFPE_L0_N

AD1

IFPE_L1

AC1

IFPE_L1_N

AC2

IFPE_L2

AC3

IFPE_L2_N

AC4

IFPE_L3

AC5

IFPE_L3_N

AE3

IFPF_L0

AE4

IFPF_L0_N

AF4

IFPF_L1

AF5

IFPF_L1_N

AD4

IFPF_L2

AD5

IFPF_L2_N

AG1

IFPF_L3

AF1

IFPF_L3_N

AG3

IFPC_AUX_I2CW_SCL

AG2

IFPC_AUX_I2CW_SDA_N

AK3

IFPD_AUX_I2CX_SCL

AK2

IFPD_AUX_I2CX_SDA_N

AB3

IFPE_AUX_I2CY_SCL

AB4

IFPE_AUX_I2CY_SDA_N

AF3

IFPF_AUX_I2CZ_SCL

AF2

IFPF_AUX_I2CZ_SDA_N

N13P-PES-A2_FCBGA908 N13PGLR1@

Part 4 of 7

TEST

SERIAL

LVDS/TMDS

GENERAL

MULTI_STRAP_REF0_GND

NC

VDD_SENSE

GND_SENSE

TESTMODE

JTAG_TCK

JTAG_TDI JTAG_TDO JTAG_TMS

JTAG_TRST_N

ROM_CS_N ROM_SCLK

ROM_SI

ROM_SO

BUFRST_N

CEC

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

THERMDP THERMDN

4

P8

NC

AC6

NC

AJ28

NC

AJ4

NC

AJ5

NC

AL11

NC

C15

NC

D19

NC

D20

NC

D23

NC

D26

NC

H31

NC

T8

NC

V32

NC

L4

L5

AK11 AM10

AM11 AP12 AP11 AN11

H6 H4 H5 H7

L2 L3 J1

J2 J7 J6 J5 J3

K3 K4

GCORE_SEN_R

FB_GND_R

ROM_CS# ROM_SCLK ROM_SI ROM_SO

MULTI_STRAP_REF0_GND

RV80 0_0402_5%

RV81 0_0402_5%

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST

RV84 10K_0402_5%

@

1 2

RV85 10K_0402_5%

STRAP0 STRAP1 STRAP2 STRAP3 STRAP4

@

1 2

@

1 2

RV82 10K_0402_5%OPT@RV82 10K_0402_5%OPT@

1 2

OPT@

1 2

RV153 10K_0402_5%OPT@RV153 10K_0402_5%OPT@

1 2

RV86 10K_0402_5%N13PGL@RV86 10K_0402_5%N13PGL@

1 2

OPT@

1 2

RV87 40.2K_0402_1%

+VGA_CORE

RV15

RV15 100_0402_1%

100_0402_1% OPT@

OPT@

1 2

100_0402_1%

+3VS_DGPU

OPT@

12

RV17

PAD

TV4

PAD

TV1

PAD @

TV2

PAD

TV3

3

VGA_VCC_SENSE <51>

VGA_VSS_SENSE <51>

@

@ @

@ @TV3

@

+3VS_DGPU

Physical Strapping pin

ROM_SO

ROM_SCLK

ROM_SI

STRAP0

STRAP1

STRAP2

STRAP3 STRAP4

N13P-GL ES2

N13P-GS ES1

N13P-GS QS

N13P-GL

ROM_SI

2

Power Rail

+3VS_DGPU

Logical Strapping Bit3

XCLK_417 for GL , FB[1]

PCI_DEVID[4]

+3VS_DGPU

+3VS_DGPU +3VS_DGPU 3GIO_PADCFG[0]3GIO_PADCFG[1]3GIO_PADCFG[2]

+3VS_DGPU +3VS_DGPU SOR0_EXPOSEDSOR2_EXPOSED SOR1_EXPOSED +3VS_DGPU DP_PLL_VDD33V

SKU

Device ID

MULTI LEVEL STRAPS

Straps

STRAP0 STRAP1 STRAP2

RV73

4.99K_0402_1%

4.99K_0402_1% N13PGS@

N13PGS@

0x0DE9

0x0FDB

0x0FD2

12

OPT@

RV64

12

@

RV72

USER[3] 3GIO_PADCFG[3]

PCI_DEVID[3]

SOR3_EXPOSED RESERVED

biit5 to bit0

+3VS_DGPU

12 @

@

N13PGL@

RV65

45.3K_0402_1%

4.99K_0402_1%

12

N13PGL@

RV73

45.3K_0402_1%

4.99K_0402_1%

101001

011011

010010

12

RV79

15K_0402_1%

N13PGS@

1 2

10K_0402_1%

RV54

Hynix (900MHZ) 64MX16 H5TQ1G63DFR-11C SA000041S20

Hynix (900MHZ) 128MX16 H5TQ2G63BFR-11C SA00003YO00

Hynix (900MHZ) 128MX16 H5TQ2G63DFR-11C SA00003YO70

Samsung (900MHZ) 64MX16 K4W1G1646G-BC11 SA00004GS00

Samsung (900MHZ) 128M16 K4W2G1646C-HC11 SA000047Q00

Samsung (900MHZ) 128M16 K4W2G1646E-BC11

Logical Strapping Bit2

FB_0_BAR_SIZE for GL , FB[0]

SUB_VENDOR

PCIE_SPEED_CHANGE_GEN3

12

@

RV98

GSDIS@

10K_0402_1%

RV68

4.99K_0402_1%

4.99K_0402_1% STRAP3

STRAP4

12

RV75

RV76

GSOPT@

N13PGS@

45.3K_0402_1%

4.99K_0402_1%

1GB

2GB

1GB

2GB

Resistor Values

5K 10K 15K 20K 25K 30K 35K 45K

ROM_SI ROM_SO ROM_SCLK

For X76

RV77 PD 15K

0010

01102GB

0101

0011

0111

0001

(SD034150280)

RV77 PD 34.8k (SD034348280)

RV77 PD 30k (SD034300280)

RV77 PD 20K (SD034200280)

RV77 PD 45.3K (SD034453280)

RV77 PD 10K (SD028100280)

Logical Strapping Bit1

SMB_ALT_ADDR

SLOT_CLK_CFG for GL PCI_DEVID[5]

RAMCFG[1]RAMCFG[3] RAMCFG[2]

PCIE_MAX_SPEED

Pull-up to +3VS _DGPU

1000 1001 1010 1011 1100 1101 1110 1111

+3VS_DGPU

12

N13PGS@

4.99K_0402_1%

12

N13PGL@

34.8K_0402_1%

10K_0402_1%

RV78

10K_0402_1%

RV89

12

1 2

@

RV69

12

@

RV77

1

Logical Strapping Bit0

VGA_DEVICE

PEX_PLLEN_TERM

RAMCFG[0]

USER[0]USER[1]USER[2]

PCI_DEVID[0]PCI_DEVID[1]PCI_DEVID[2]

N13PGS@

RV70

4.99K_0402_1%

RV53

N13PGL@

15K_0402_1%

Pull-down to Gnd

0000 0001 0010 0011 0100 0101 0110 0111

SA00005SH00

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA_N13P LVDS&TMDS

15 53Tuesday, October 16, 2012

1

15 53Tuesday, October 16, 2012

1.0

of

5

4

3

2

1

+1.05VS_DGPU

1

CV58

CV59

2

OPT@ CV58

OPT@

OPT@ CV59

OPT@

10U_0603_6.3V6M

22U_0805_6.3V6M

+1.05VS_DGPU

1

CV78

CV67

2

OPT@ CV78

OPT@

OPT@ CV67

OPT@

22U_0805_6.3V6M

10U_0603_6.3V6M

+3VS_DGPU

CV82

N13PGS@

OPT@ CV82

OPT@

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M RV101

RV101

0_0603_5%

LV7

BLM18PG121SN1D_0603

N13PGL@

CV89

OPT@ CV89

OPT@

4.7U_0402_6.3V6M

1

CV95

CV92

2

0.1U_0402_10V7K

OPT@ CV95

0.1U_0402_10V7K

OPT@

0.1U_0402_10V7K

OPT@ CV92

0.1U_0402_10V7K

OPT@

1

CV60

2

OPT@ CV60

OPT@

22U_0805_6.3V6M

1

CV68

2

OPT@ CV68

OPT@

22U_0805_6.3V6M

12

+1.05VS_DGPU

12

PCIE2.0 N13P-GL N13M-GS PCIE3.0 N13P-GS/GT N13E-GE

+3VS_DGPU

Near GPU

1

2

CV96

OPT@ CV96

OPT@

CV97

2

OPT@ CV97

OPT@

1U_0402_6.3V6K

4.7U_0402_6.3V6M

1

CV56

2

OPT@ CV56

OPT@

1

CV76

2

OPT@ CV76

OPT@

1

CV87

2

OPT@ CV87

OPT@

1

CV90

2

OPT@ CV90

OPT@

midway between GPU and Power supply

1

CV57

2

OPT@ CV57

OPT@

10U_0603_6.3V6M

4.7U_0402_6.3V6M

midway between GPU and Power supply

1

CV77

2

OPT@ CV77

OPT@

10U_0603_6.3V6M

4.7U_0402_6.3V6M

Near GPU

1

CV81

2

OPT@ CV81

OPT@

4.7U_0402_6.3V6M

Near GPU

1

CV88

2

1U_0402_6.3V6K

OPT@ CV88

OPT@

0.1U_0402_10V7K

1

CV91

2

0.1U_0402_10V7K

OPT@ CV91

0.1U_0402_10V7K

OPT@

0.1U_0402_10V7K

1

2

1

2

1

2

1

2

1

2

Under GPU

1

CV54

2

OPT@ CV54

UV4E

AA27 AA30 AB27 AB33 AC27 AD27 AE27

AF27

AG27

M27 N27

R27

W27 W30 W33

H27

H25

UV4E

B13 B16 B19 E13 E16 E19 H10 H11 H12 H13 H14 H15 H16 H18 H19 H20 H21 H22 H23 H24

H8 H9

L27

P27 T27

T30 T33 V27

Y27

F1

F2

J27

Part 5 of 7

7200 mA 3300 mA

FBVDDQ_0 FBVDDQ_1 FBVDDQ_2 FBVDDQ_3 FBVDDQ_4 FBVDDQ_5 FBVDDQ_6 FBVDDQ_7 FBVDDQ_8 FBVDDQ_9 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_15 FBVDDQ_16 FBVDDQ_17 FBVDDQ_18 FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 FBVDDQ_28 FBVDDQ_29 FBVDDQ_30 FBVDDQ_31 FBVDDQ_32 FBVDDQ_33 FBVDDQ_34 FBVDDQ_35 FBVDDQ_36 FBVDDQ_37 FBVDDQ_38 FBVDDQ_39 FBVDDQ_40 FBVDDQ_41 FBVDDQ_42 FBVDDQ_43

FB_VDDQ_SENSE

FB_GND_SENSE

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

PEX_IOVDD_0 PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5

3300mA

PEX_IOVDDQ_0 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13

210mA

PEX_PLL_HVDD

210mA

PEX_SVDD_3V3

150mA

POWER

PEX_PLLVDD

85mA

VDD33_0 VDD33_1 VDD33_2 VDD33_3

125mA

IFPAB_PLLVDD

IFPAB_RSET

115mA

IFPA_IOVDD IFPB_IOVDD

100mA

IFPC_PLLVDD

IFPC_RSET

72mA

IFPC_IOVDD

IFPD_PLLVDD

IFPD_RSET

IFPD_IOVDD

200mA

IFPEF_PLVDD

IFPEF_RSET

IFPE_IOVDD

144mA

IFPF_IOVDD

AG19 AG21 AG22 AG24 AH21 AH25

AG13 AG15 AG16 AG18 AG25 AH15 AH18 AH26 AH27 AJ27 AK27 AL27 AM28 AN28

AH12

AG12

AG26

J8 K8 L8 M8

AH8 AJ8

AG8 AG9

AF7 AF8

AF6

AG7 AN2

AG6

AB8 AD6

AC7 AC8

total 6600mA Design guide page.74

+3VS_DGPU

OPT@

1 2

CV80 0.1U_0402_10V7K

OPT@

1 2

CV198 0.1U_0402_10V7K

+PEX_PLLVDD

+3VS_DGPU

+IFPAB_PLLVDD

+IFPAB_IOVDD

+IFPC_PLLVDD

+IFPC_IOVDD

+IFPD_PLLVDD

+IFPD_IOVDD

+IFPEF_PLLVDD

+IFPEF_IOVDD

CV101 OPT@ 10K_0402_5%CV101 OPT@ 10K_0402_5% RV90 1K_0402_5%@RV90 1K_0402_5%@

CV104 OPT@ 10K_0402_5%CV104 OPT@ 10K_0402_5%

RV298 10K_0402_5%OPT@RV298 10K_0402_5%OPT@

RV295 10K_0402_5%OPT@RV295 10K_0402_5%OPT@

RV297 10K_0402_5%OPT@RV297 10K_0402_5%OPT@

RV296 10K_0402_5%OPT@RV296 10K_0402_5%OPT@

CV286 OPT@ 10K_0402_5%CV286 OPT@ 10K_0402_5% RV103 1K_0402_5%@RV103 1K_0402_5%@

CV234 OPT@ 10K_0402_5%CV234 OPT@ 10K_0402_5%

1 2 1 2

1 2

1 2 1 2

1 2

420mA

CV80,CV198 Under GPU close to ball

85mA

D D

C C

B B

+VRAM_1.5VS

1

2

CV83

OPT@ CV83

OPT@

1

CV61

2

OPT@ CV61

OPT@

1

CV69

2

OPT@ CV69

OPT@

1

CV84

2

OPT@ CV84

OPT@

10U_0603_6.3V6M

1

2

4.7U_0402_6.3V6M

1

2

4.7U_0402_6.3V6M

Near GPU

1

2

10U_0603_6.3V6M

+VRAM_1.5VS

CV62

OPT@

CV70

OPT@ CV70

OPT@

CV244

OPT@CV244

OPT@

1

2

1U_0402_6.3V6K

1

2

1U_0402_6.3V6K

1

2

10U_0603_6.3V6M

Under GPU

1

CV63

2

OPT@ CV63

OPT@

0.1U_0402_10V7K

Under GPU

1

CV79

2

OPT@

0.1U_0402_10V7K

1

CV243

2

OPT@CV243

OPT@

10U_0603_6.3V6M

RV96 40.2_0402_1%

RV605 42.2_0402_1%

RV609 51.1_0402_1%

1

CV64

2

OPT@ CV64

OPT@

0.1U_0402_10V7K

1

CV71

2

OPT@

0.1U_0402_10V7K

CV231 @CV231

@

22U_0805_6.3V6M

OPT@

1 2

OPT@

1 2

1

2

CV65

OPT@ CV65

OPT@

CV72

OPT@

12

0.1U_0402_10V7K

CV85 @ CV85

@

1

2

1

2

22U_0805_6.3V6M

CV66

OPT@ CV66

OPT@

0.1U_0402_10V7K

CV73

OPT@

0.1U_0402_10V7K

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

OPT@

Under GPU

1

CV74

2

OPT@ CV74

OPT@

Near GPU

1

CV55

2

OPT@ CV55

OPT@

1U_0402_6.3V6K

Near GPU

1

CV75

2

OPT@ CV75

OPT@

1U_0402_6.3V6K

Under GPU

N13P-PES-A2_FCBGA908 N13PGLR1@

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA_N13P POWER

1

1.0

of

16 53Tuesday, October 16, 2012

5

4

3

2

1

UV4F

D D

C C

B B

A A

5

A2 AA17 AA18 AA20 AA22 AB12 AB14 AB16 AB19

AB2

AB21

A33 AB23 AB28 AB30 AB32

AB5

AB7 AC13 AC15 AC17 AC18 AA13 AC20 AC22

AE2 AE28 AE30 AE32 AE33

AE5

AE7 AH10 AA15 AH13 AH16 AH19

AH2 AH22 AH24 AH28 AH29 AH30 AH32 AH33

AH5

AH7

AJ7

AK10

AK7

AL12 AL14 AL15 AL17 AL18

AL2 AL20 AL21 AL23 AL24 AL26 AL28 AL30 AL32 AL33

AL5

AM13 AM16 AM19 AM22 AM25

AN1 AN10 AN13 AN16 AN19 AN22 AN25 AN30 AN34

AN4

AN7

AP2 AP33

B1 B10 B22 B25 B28 B31 B34

B4

B7

C10 C13 C19 C22 C25 C28

C7

N13P-PES-A2_FCBGA908 N13PGLR1@

GND_0 GND_1 GND_2 GND_3 GND_4 GND_5 GND_6 GND_7 GND_8 GND_9 GND_10 GND_11 GND_12 GND_13 GND_14 GND_15 GND_16 GND_17 GND_18 GND_19 GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26 GND_27 GND_28 GND_29 GND_30 GND_31 GND_32 GND_33 GND_34 GND_35 GND_36 GND_37 GND_38 GND_39 GND_40 GND_41 GND_42 GND_43 GND_44 GND_45 GND_46 GND_47 GND_48 GND_49 GND_50 GND_51 GND_52 GND_53 GND_54 GND_55 GND_56 GND_57 GND_58 GND_59 GND_60 GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67 GND_68 GND_69 GND_70 GND_71 GND_72 GND_73 GND_74 GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82 GND_83 GND_84 GND_85 GND_86 GND_87 GND_88 GND_89 GND_90 GND_91 GND_92 GND_93 GND_94 GND_95 GND_96 GND_97 GND_98 GND_99

Part 6 of 7

D2

GND_100

D31

GND_101

D33

GND_102

E10

GND_103

E22

GND_104

E25

GND_105

E5

GND_106

E7

GND_107

F28

GND_108

F7

GND_109

G10

GND_110

G13

GND_111

G16

GND_112

G19

GND_113

G2

GND_114

G22

GND_115

G25

GND_116

G28

GND_117

G3

GND_118

G30

GND_119

G32

GND_120

G33

GND_121

G5

GND_122

G7

GND_123

K2

GND_124

K28

GND_125

K30

GND_126

K32

GND_127

K33

GND_128

K5

GND_129

K7

GND_130

M13

GND_131

M15

GND_132

M17

GND_133

M18

GND_134

M20

GND_135

M22

GND_136

N12

GND_137

N14

GND_138

N16

GND_139

N19

GND_140

N2

GND_141

N21

GND_142

N23

GND_143

N28

GND_144

N30

GND_145

N32

GND_146

N33

GND_147

N5

GND_148

N7

GND_149

P13

GND_150

P15

GND_151

P17

GND_152

GND

GND_153 GND_154 GND_155 GND_156 GND_157 GND_158 GND_159 GND_160 GND_161 GND_162 GND_163 GND_164 GND_165 GND_166 GND_167 GND_168 GND_169 GND_170 GND_171 GND_172 GND_173 GND_174 GND_175 GND_176 GND_177 GND_178 GND_179 GND_180 GND_181 GND_182 GND_183 GND_184 GND_185 GND_186 GND_187 GND_188 GND_189 GND_190 GND_191 GND_192 GND_193 GND_194 GND_195 GND_196 GND_197 GND_198

GND_199 GND_OPT GND_OPT

P18 P20 P22 R12 R14 R16 R19 R21 R23 T13 T15 T17 T18 T2 T20 T22 AG11 T28 T32 T5 T7 U12 U14 U16 U19 U21 U23 V12 V14 V16 V19 V21 V23 W13 W15 W17 W18 W20 W22 W28 Y12 Y14 Y16 Y19 Y21 Y23 AH11 C16 W32

50A

VGA_CORE cap. ought to power pate

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

2

UV4G

Part 7 of 7

VDD_0 VDD_1 VDD_2 VDD_3 VDD_4 VDD_5 VDD_6 VDD_7 VDD_8 VDD_9 VDD_10 VDD_11 VDD_12 VDD_13 VDD_14 VDD_15 VDD_16 VDD_17 VDD_18 VDD_19 VDD_20 VDD_21 VDD_22 VDD_23 VDD_24 VDD_25 VDD_26 VDD_27 VDD_28 VDD_29 VDD_30 VDD_31 VDD_32 VDD_33 VDD_34 VDD_35 VDD_36 VDD_37 VDD_38 VDD_39 VDD_40 VDD_41 VDD_42 VDD_43 VDD_44 VDD_45 VDD_46 VDD_47 VDD_48 VDD_49 VDD_50 VDD_51 VDD_52 VDD_53 VDD_54 VDD_55

Part 7 of 7

POWER

Title

Size Document Number Rev

Custom

Date: Sheet

AA12 AA14 AA16 AA19 AA21 AA23 AB13 AB15 AB17 AB18 AB20 AB22 AC12 AC14 AC16 AC19 AC21 AC23

M12 M14 M16 M19 M21 M23 N13 N15 N17 N18 N20 N22

P12 P14 P16 P19 P21

P23 R13 R15 R17 R18 R20 R22

T12

T14

T16

T19

T21

T23 U13 U15 U17 U18 U20 U22

V13

V15

N13P-PES-A2_FCBGA908 N13PGLR1@

VDD_56 VDD_57 VDD_58 VDD_59 VDD_60 VDD_61 VDD_62 VDD_63 VDD_64 VDD_65 VDD_66 VDD_67 VDD_68 VDD_69 VDD_70 VDD_71

XVDD_1 XVDD_2 XVDD_3 XVDD_4 XVDD_5 XVDD_6 XVDD_7 XVDD_8

XVDD_9 XVDD_10 XVDD_11 XVDD_12 XVDD_13 XVDD_14 XVDD_15 XVDD_16

XVDD_17 XVDD_18 XVDD_19 XVDD_20 XVDD_21 XVDD_22

XVDD_23 XVDD_24 XVDD_25 XVDD_26 XVDD_27 XVDD_28 XVDD_29 XVDD_30

XVDD_31 XVDD_32 XVDD_33 XVDD_34 XVDD_35 XVDD_36 XVDD_37 XVDD_38

VGA_N13P POWER & GND

+VGA_CORE+VGA_CORE

V17 V18 V20 V22 W12 W14 W16 W19 W21 W23 Y13 Y15 Y17 Y18 Y20 Y22

U1 U2 U3 U4 U5 U6 U7 U8

V1 V2 V3 V4 V5 V6 V7 V8

W2 W3 W4 W5 W7 W8

Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8

AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8

Compal Electronics, Inc.

1

1.0

of

17 53Tuesday, October 16, 2012

5

4

3

2

1

VRAM DDR3 chips (1GB)

64Mx16 DDR3 *8==>1GB

D D

+MEM_VREF_CA1

DQMA[7..0]<14,19> CMDA[30..0]<14,19>

DQSA#[7..0]<14,19> DQSA[7..0]<14,19>

MDA[63..0]<14,19>

+VRAM_1.5VS

12

RV107

1K_0402_1%

OPT@

12

1

CV230

12

CV230

0.01U_0402_25V7K

0.01U_0402_25V7K OPT@

OPT@

2

+MEM_VREF_DQ1

1

CV301

0.01U_0402_25V7K

0.01U_0402_25V7K OPT@

OPT@

2

RV106

1K_0402_1%

C C

B B

1K_0402_1%

OPT@

RV119

1K_0402_1%

OPT@

RV108

1K_0402_1%

OPT@

CLKA1<14>

CLKA1#<14>

+VRAM_1.5VS

DQMA[7..0]

CMDA[30..0] DQSA#[7..0]

DQSA[7..0]

MDA[63..0]

+MEM_VREF_CA1

12

OPT@

OPT@ RV126

RV126 160_0402_1%

160_0402_1%

+MEM_VREF_DQ1

CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14

CMDA12 CMDA27 CMDA26

CLKA1 CLKA1# CMDA19

CMDA18 CMDA16 CMDA30 CMDA15 CMDA13

DQSA4 DQSA7

DQMA4 DQMA7

DQSA#4 DQSA#7

CMDA5

OPT@

OPT@ RV123

RV123

243_0402_1%

M8 H1

N3

N2

R8 R2

R3 R7

N7

M7

M2 N8 M3

C7

D3

G3

ZQ2

12

UV10

@

UV10

@

VREFCA VREFDQ

A0

P7

A1

P3

A2 A3

P8

A4

P2

A5 A6 A7

T8

A8 A9

L7

A10/AP A11 A12

T3

A13

T7

A14 A15/BA3

BA0 BA1 BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

F3

DQSL DQSU

E7

DML DMU

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

K4B1G1646E-HC12_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ

310mA 310mA

VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDA39 MDA35 MDA37 MDA33 MDA38 MDA32 MDA36 MDA34

MDA61 MDA59 MDA60 MDA57 MDA63 MDA56 MDA62 MDA58

+VRAM_1.5VS

Group4

+MEM_VREF_CA1 +MEM_VREF_DQ1

CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14

CMDA12 CMDA27 CMDA26

CLKA1 CLKA1# CMDA19

CMDA18 CMDA16 CMDA30 CMDA15 CMDA13

DQSA5 DQSA6

DQMA5 DQMA6

DQSA#5 DQSA#6

CMDA5

OPT@

OPT@ RV124

RV124

243_0402_1%

M8 H1

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7

K7

K9

K1

L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2

ZQ3

L8

12

J1

L1

J9

L9

UV11

@

UV11

@

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

K4B1G1646E-HC12_FBGA96

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDA45 MDA40 MDA46 MDA41 MDA47 MDA43 MDA44 MDA42

MDA53 MDA49 MDA55 MDA50 MDA52 MDA48 MDA54 MDA51

+VRAM_1.5VS

Group5

Group6Group7

Mode D Address

CMD0

0..31

CS0_L# CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15

ODT_L

CKE A14 RST A9 A7 A2 A0 A4 A1 BA0 WE* A15

CAS* CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 A8 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30

Not Available

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS*

LOW HIGH

32..63

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE* A15 CAS*

CS0_H#

ODT_H CKE_H

A13

A6 A11 A5 A3 BA2 BA1 A12 A10 RAS*

+VRAM_1.5VS

1

CV257

CV238

2

OPT@

10U_0603_6.3V6M

A A

5

4

1

CV256

2

1U_0402_6.3V6K

OPT@

1

CV255

2

1U_0402_6.3V6K

OPT@

1

CV137

CV138

0.1U_0402_10V7K

CV139

CV141

2

0.1U_0402_10V7K

OPT@

CV141

2

0.1U_0402_10V7K

OPT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

+VRAM_1.5VS

1

2

1U_0402_6.3V6K

OPT@

1

CV260

CV258

2

1U_0402_6.3V6K

OPT@

Compal Secret Data

Deciphered Date

1

CV259

2

1U_0402_6.3V6K

OPT@

1

CV288

2

OPT@

2012/04/19 2015/04/19

1

CV144

CV143

2

0.1U_0402_10V7K

OPT@

2

1

CV140

CV142

2

0.1U_0402_10V7K

0.1U_0402_10V7K OPT@

OPT@

1

CV275

CV276

2

1U_0402_6.3V6K

OPT@

Title

Size Document Number Rev

Custom

Date: Sheet

1

CV278

CV279

CV277

1U_0402_6.3V6K

CV279

CV280

2

1U_0402_6.3V6K

OPT@

VGA_N13P VRAM Channel AH

CV280

2

1U_0402_6.3V6K

OPT@

Compal Electronics, Inc.

1

1.0

of

18 53Tuesday, October 16, 2012

5

4

3

2

1

VRAM DDR3 chips (1GB)

D D

C C

B B

64Mx16 DDR3 *8==>1GB

DQSA[7..0]<14,18>

DQSA#[7..0]<14,18>

DQMA[7..0]<14,18>

MDA[63..0]<14,18>

CMDA[30..0]<14,18>

+VRAM_1.5VS

12

RV62

1K_0402_1%

OPT@

12

RV63

1K_0402_1%

OPT@

+VRAM_1.5VS

12

RV105

1K_0402_1%

OPT@

12

RV88

1K_0402_1%

OPT@

CLKA0<14>

CLKA0#<14>

12

OPT@

OPT@ RV114

RV114 160_0402_1%

160_0402_1%

DQSA[7..0] DQSA#[7..0]

DQMA[7..0]

MDA[63..0]

CMDA[30..0]

+MEM_VREF_CA0

1

CV228

0.01U_0402_25V7K

0.01U_0402_25V7K OPT@

OPT@

2

+MEM_VREF_DQ0

1

CV229

0.01U_0402_25V7K

0.01U_0402_25V7K OPT@

OPT@

2

+MEM_VREF_CA0 +MEM_VREF_DQ0

OPT@

OPT@ RV110

RV110

243_0402_1%

+VRAM_1.5VS

CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14

CMDA12 CMDA27 CMDA26

CLKA0 CLKA0# CMDA3

CMDA2 CMDA0 CMDA30 CMDA15 CMDA13

DQSA1 DQSA2

DQMA1 DQMA2

DQSA#1 DQSA#2

CMDA5

12

UV8

@

UV8

@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

310mA

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDA12 MDA14 MDA8 MDA15 MDA9 MDA13 MDA10 MDA11

MDA17 MDA21 MDA18 MDA23 MDA19 MDA22 MDA16 MDA20

+VRAM_1.5VS

swap 0329

Group1

Group2

OPT@

OPT@ RV111

RV111

243_0402_1%

+MEM_VREF_CA0 +MEM_VREF_DQ0

CMDA9 CMDA11 CMDA8 CMDA25 CMDA10 CMDA24 CMDA22 CMDA7 CMDA21 CMDA6 CMDA29 CMDA23 CMDA28 CMDA20 CMDA4 CMDA14

CMDA12 CMDA27 CMDA26

CLKA0 CLKA0# CMDA3

CMDA2 CMDA0 CMDA30 CMDA15 CMDA13

DQSA0 DQSA3

DQMA0 DQMA3

DQSA#0 DQSA#3

CMDA5

ZQ1ZQ0

12

+VRAM_1.5VS

UV9

@

UV9

M8

H1 N3

P7 P3 N2 P8 P2 R8 R2 T8 R3

L7 R7 N7 T3 T7

M7

M2

N8

M3

J7 K7 K9

K1

L2

J3 K3

L3

F3 C7

E7 D3

G3 B7

T2

L8

J1

L1

J9

L9

@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

310mA

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDA3 MDA4 MDA2 MDA7 MDA0 MDA5 MDA1 MDA6

MDA27 MDA29 MDA25 MDA30 MDA24 MDA28 MDA26 MDA31

+VRAM_1.5VS

CMDA2 CMDA3 CMDA5 CMDA18 CMDA19

Group0

Group3

RV112 10K_0402_5%OPT@RV112 10K_0402_5%OPT@

1 2

RV113 10K_0402_5%OPT@RV113 10K_0402_5%OPT@

1 2

OPT@

RV115 10K_0402_5%

1 2

RV116 10K_0402_5%

OPT@

1 2

RV117 10K_0402_5%OPT@RV117 10K_0402_5%OPT@

1 2

Mode D Address

CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 A8 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30

Not Available

Command Bit Default Pull-down

ODTx 10k

CKEx

DDR3

RST 10k

CS* No Termination

0..31

32..63

CS0_L#

ODT_L

CKE A14 RST A9 A7 A2 A0 A4 A1 BA0 WE* A15 CAS*

CS0_H#

ODT_H

CKE_H A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS*

LOW HIGH

10k

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE* A15 CAS*

A13

A6 A11 A5 A3 BA2 BA1 A12 A10 RAS*

1

CV261

CV240

2

A A

5

10U_0603_6.3V6M

OPT@

4

1

CV310

2

1U_0402_6.3V6K

OPT@

1

CV262

2

1U_0402_6.3V6K

OPT@

1

CV147

CV148

0.1U_0402_10V7K

CV145

CV146

2

0.1U_0402_10V7K

OPT@

CV146

2

0.1U_0402_10V7K

OPT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2

OPT@

3

1

CV311

CV313

CV241

CV313

2

1U_0402_6.3V6K

10U_0603_6.3V6M

OPT@

2012/04/19 2015/04/19

1

CV312

2

1U_0402_6.3V6K

OPT@

1

CV152

2

0.1U_0402_10V7K

1U_0402_6.3V6K

OPT@

Compal Secret Data

Deciphered Date

1

CV150

CV149

CV151

2

0.1U_0402_10V7K

0.1U_0402_10V7K OPT@

OPT@

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA_N13P VRAM Channel AL

19 53Tuesday, October 16, 2012

1

19 53Tuesday, October 16, 2012

1.0

of

5

VRAM DDR3 chips (1GB)

4

3

2

Mode D Address

CMD0

0..31 CS0_L#

1

32..63

CMD1

D D

64Mx16 DDR3 *8==>1GB

CMD2 CMD3 CMD4

DQSC[7..0]<14,21>

DQSC#[7..0]<14,21>

DQMC[7..0]<14,21>

MDC[63..0]<14,21>

CMDC[30..0]<14,21>

+VRAM_1.5VS

12

RV121

1K_0402_1%

OPT@

C C

B B

CLKC0<14>

CLKC0#<14>

A A

1K_0402_1%

RV120

RV120 OPT@

OPT@

+VRAM_1.5VS

RV128

RV128 OPT@

OPT@

RV122

RV122 OPT@

OPT@

12

RV140

RV140 160_0402_1%

160_0402_1% OPT@

OPT@

12

DQSC[7..0] DQSC#[7..0]

DQMC[7..0]

MDC[63..0]

CMDC[30..0]

+MEM_VREF_CA2

1

CV302

0.01U_0402_25V7K

0.01U_0402_25V7K OPT@

OPT@

2

+MEM_VREF_DQ2

1

CV303

0.01U_0402_25V7K

0.01U_0402_25V7K OPT@

OPT@

2

RV132

243_0402_1%

OPT@

UV12

@

UV12

+MEM_VREF_CA2 +MEM_VREF_DQ2

CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14

CMDC12 CMDC27 CMDC26

CLKC0 CLKC0# CMDC3

CMDC2 CMDC0 CMDC30 CMDC15 CMDC13

DQSC1 DQSC2

DQMC1 DQMC2

DQSC#1 DQSC#2

CMDC5

ZQ4 ZQ5

12

+VRAM_1.5VS

1

CV245

2

OPT@

@

M8

VREFCA

H1

VREFDQ

N3

A0

P7

A1

P3

A2

N2

A3

P8

A4

P2

A5

R8

A6

R2

A7

T8

A8

R3

A9

L7

A10/AP

R7

A11

N7

A12

T3

A13

T7

A14

M7

A15/BA3

M2

BA0

N8

BA1

M3

BA2

J7

CK

K7

CK

K9

CKE/CKE0

K1

ODT/ODT0

L2

CS/CS0

J3

RAS

K3

CAS

L3

WE

310mA

F3

DQSL

C7

DQSU

E7

DML

D3

DMU

G3

DQSL

B7

DQSU

T2

RESET

L8

ZQ/ZQ0

J1

NC/ODT1

L1

NC/CS1

J9

NC/CE1

L9

NCZQ1

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

K4B1G1646E-HC12_FBGA96

1

CV263

CV265

2

1U_0402_6.3V6K

OPT@

10U_0603_6.3V6M

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

2

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

OPT@

CV264

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

1U_0402_6.3V6K

MDC8 MDC12 MDC11 MDC13 MDC9 MDC14 MDC10 MDC15

MDC18 MDC20 MDC17 MDC22 MDC16 MDC23 MDC19 MDC21

+VRAM_1.5VS

1

CV156

2

0.1U_0402_10V7K

OPT@

swap 0329

Group1

Group2

1

2

OPT@

1

CV155

0.1U_0402_10V7K

CV154

CV153

2

0.1U_0402_10V7K

0.1U_0402_10V7K OPT@

OPT@

+MEM_VREF_CA2 +MEM_VREF_DQ2

RV133

243_0402_1%

OPT@

0.1U_0402_10V7K

CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14

CMDC12 CMDC27 CMDC26

CLKC0 CLKC0# CMDC3

CMDC2 CMDC0 CMDC30 CMDC15 CMDC13

DQSC0 DQSC3

DQMC0 DQMC3

DQSC#0 DQSC#3

CMDC5

12

M8 H1

N3

P7 P3

N2

P8

P2 R8 R2

T8 R3

L7 R7 N7

T3

T7 M7

M2 N8 M3

J7

K7

K9

K1

L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2

L8

J1

L1

J9

L9

+VRAM_1.5VS

1

CV246

2

OPT@

UV13

@

UV13

@

310mA

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

1

CV266

2

1U_0402_6.3V6K

OPT@

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

1

CV268

2

1U_0402_6.3V6K

OPT@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

K4B1G1646E-HC12_FBGA96

10U_0603_6.3V6M

1

2

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

CV267

1U_0402_6.3V6K

OPT@

MDC3 MDC7 MDC1 MDC4 MDC2 MDC6 MDC0 MDC5

MDC26 MDC31 MDC25 MDC30 MDC27 MDC28 MDC24 MDC29

+VRAM_1.5VS

1

CV160

2

0.1U_0402_10V7K

OPT@

Group0

Group3

CMDC2 CMDC3 CMDC5 CMDC18 CMDC19

1

CV159

2

OPT@

RV134 10K_0402_5%

RV134 10K_0402_5% RV135 10K_0402_5%

RV135 10K_0402_5% RV136 10K_0402_5%

RV136 10K_0402_5% RV137 10K_0402_5%

RV137 10K_0402_5% RV138 10K_0402_5%

RV138 10K_0402_5%

1

CV157

2

0.1U_0402_10V7K

0.1U_0402_10V7K OPT@

OPT@

CV158

0.1U_0402_10V7K

1 2

OPT@

1 2

OPT@

1 2

OPT@

1 2

OPT@

1 2

OPT@

CV131

330U_2.5V_M

+VRAM_1.5VS

1

2

@

CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 A8 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30

Not Available

DDR3

+

1

+

2

ODT_L

CKE A14 RST A9 A7 A2 A0 A4 A1 BA0 WE* A15 CAS*

A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS*

LOW HIGH

Command Bit Default Pull-down

ODTx

CKEx RST

CS* No Termination

CV344

CV344 330U_B2_2.5VM_R15M

330U_B2_2.5VM_R15M @

@

CS0_H#

ODT_H CKE_H

10k 10k 10k

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE* A15 CAS*

A13

A6 A11 A5 A3 BA2 BA1 A12 A10 RAS*

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

2

Date: Sheet

Compal Electronics, Inc.

VGA_N13P VRAM Channel CL

20 53Tuesday, October 16, 2012

1

20 53Tuesday, October 16, 2012

1.0

of

5

4

3

2

1

VRAM DDR3 chips (1GB)

64Mx16 DDR3 *8==>1GB

D D

+MEM_VREF_CA3

1

CV304

0.01U_0402_25V7K

0.01U_0402_25V7K OPT@

OPT@

2

+MEM_VREF_DQ3

1

CV305

0.01U_0402_25V7K

0.01U_0402_25V7K OPT@

OPT@

2

DQMC[7..0]

CMDC[30..0] DQSC#[7..0]

DQSC[7..0]

MDC[63..0]

+MEM_VREF_CA3 +MEM_VREF_DQ3

RV146

243_0402_1%

OPT@

+VRAM_1.5VS

CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14

CMDC12 CMDC27 CMDC26

CLKC1 CLKC1# CMDC19

CMDC18 CMDC16 CMDC30 CMDC15 CMDC13

DQSC4 DQSC5

DQMC4 DQMC5

DQSC#4 DQSC#5

12

M8

H1 N3

P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M7

M2

N8

M3

J7 K7 K9

K1 L2

J3 K3 L3

F3 C7

E7 D3

G3

B7

T2

ZQ6

L8

J1 L1

J9 L9

UV15

@

UV15

@

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

K4B1G1646E-HC12_FBGA96

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ

310mA 310mA

VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDC39 MDC33 MDC38 MDC32 MDC36 MDC34 MDC37 MDC35

MDC44 MDC43 MDC47 MDC40 MDC45 MDC42 MDC46 MDC41

+VRAM_1.5VS

Group4

Group5

+MEM_VREF_CA3 +MEM_VREF_DQ3

CMDC9 CMDC11 CMDC8 CMDC25 CMDC10 CMDC24 CMDC22 CMDC7 CMDC21 CMDC6 CMDC29 CMDC23 CMDC28 CMDC20 CMDC4 CMDC14

CMDC12 CMDC27 CMDC26

CLKC1 CLKC1# CMDC19

CMDC18 CMDC16 CMDC30 CMDC15 CMDC13

DQSC7 DQSC6

DQMC7 DQMC6

DQSC#7 DQSC#6

CMDC5CMDC5

RV147

243_0402_1%

OPT@

ZQ7

12

+VRAM_1.5VS

M8

H1 N3

P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7

M7

M2

N8

M3

J7 K7 K9

K1 L2

J3

K3

L3

F3 C7

E7 D3

G3

B7

T2 L8

J1 L1 J9 L9

UV14

@

UV14

@

96-BALL

96-BALL SDRAM DDR3

SDRAM DDR3

DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7

DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7

VDD VDD VDD VDD VDD VDD VDD VDD VDD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ

VREFCA VREFDQ

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12 A13 A14 A15/BA3

BA0 BA1 BA2

CK CK CKE/CKE0

ODT/ODT0 CS/CS0 RAS CAS WE

DQSL DQSU

DML DMU

DQSL DQSU

RESET ZQ/ZQ0

NC/ODT1 NC/CS1 NC/CE1 NCZQ1

K4B1G1646E-HC12_FBGA96

E3 F7 F2 F8 H3 H8 G2 H7

D7 C3 C8 C2 A7 A2 B8 A3

B2 D9 G7 K2 K8 N1 N9 R1 R9

A1 A8 C1 C9 D2 E9 F1 H2 H9

A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9

B1 B9 D1 D8 E2 E8 F9 G1 G9

MDC63 MDC58 MDC62 MDC59 MDC60 MDC61 MDC57 MDC56

MDC54 MDC48 MDC52 MDC50 MDC53 MDC51 MDC55 MDC49

+VRAM_1.5VS

Group7

Group6

Mode D Address

CMD0

0..31

CS0_L# CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15

ODT_L

CKE A14 RST A9 A7 A2 A0 A4 A1 BA0 WE* A15

CAS* CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 A8 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30

Not Available

A13

A8

A6

A11

A5

A3

BA2

BA1

A12

A10

RAS*

LOW HIGH

32..63

A14 RST A9 A7 A2 A0 A4 A1 BA0 WE* A15 CAS*

CS0_H#

ODT_H CKE_H

A13

A6 A11 A5 A3 BA2 BA1 A12 A10 RAS*

DQMC[7..0]<14,20> CMDC[30..0]<14,20>

DQSC#[7..0]<14,20> DQSC[7..0]<14,20>

MDC[63..0]<14,20>

+VRAM_1.5VS

12

RV130

1K_0402_1%

OPT@

12

RV129

1K_0402_1%

C C

CLKC1<14>

B B

CLKC1#<14>

1K_0402_1%

OPT@

RV142

1K_0402_1%

OPT@

RV131

1K_0402_1%

OPT@

12

RV149

RV149 160_0402_1%

160_0402_1%

OPT@

+VRAM_1.5VS

12

1

CV269

CV247

A A

5

CV269

2

10U_0603_6.3V6M

OPT@

4

1

CV271

2

1U_0402_6.3V6K

OPT@

1

CV270

2

1U_0402_6.3V6K

OPT@

1

CV164

2

0.1U_0402_10V7K

OPT@

1

CV161

CV163

0.1U_0402_10V7K

OPT@

CV162

2

0.1U_0402_10V7K

OPT@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

CV272

CV248

2012/04/19 2015/04/19

CV272

2

OPT@

10U_0603_6.3V6M

1

CV274

2

1U_0402_6.3V6K

OPT@

Compal Secret Data

Deciphered Date

1

CV168

CV273

2

0.1U_0402_10V7K

1U_0402_6.3V6K

OPT@

2

1

CV166

CV167

0.1U_0402_10V7K

OPT@

CV166

CV165

2

0.1U_0402_10V7K

0.1U_0402_10V7K OPT@

OPT@

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

VGA_N13P VRAM Channel CH

21 53Tuesday, October 16, 2012

1

21 53Tuesday, October 16, 2012

1.0

of

A

B

C

D

E

12

100K_0402_5%

61

2

R112

R112 100K_0402_5%

100K_0402_5%

1 2

+3VS

12

R108

34

5

Q1B

Q1B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

0.047U_0402_25V7K

R110

1 2

68K_0402_5%

4700P_0402_25V7K

C228

LCDPWR_GATE

C230

+3VS

1

W=80mils

S

G

2 1

2

Q17

2

AO3413_SOT23

D

1 3

+LCD_VDD

W=80mils

1

C233

0.1U_0402_10V7K

2

+LCD_VDD

R109

100_0805_5%

1 1

2N7002KDWH_SOT363-6

1 2

R78 0_0402_5%CAM@R78 0_0402_5%CAM@

@

USB20_P11_R

USB20_N11_R

@

1

4

WCM-2012-900T_0805

L55

1 2

R96 0_0402_5%CAM@R96 0_0402_5%CAM@

2

3

USB20_P11 <28>

USB20_N11 <28>

LCD_ENVDD<27>

Q1A

LCD_ENVDD

Reserve for EMI request

@

For RF

C256 47P_0402_50V8J

EMI request

R388

301LMA20T_0603

USB20_N11_R USB20_P11_R

INT_MIC_CLK INT_MIC_DATA

+LCD_VDD +3VS LCD_EDID_CLK

LCD_EDID_DATA LCD_TXOUT0LCD_TXOUT0+

LCD_TXOUT1LCD_TXOUT1+ LCD_TXOUT2LCD_TXOUT2+ LCD_TXCLKLCD_TXCLK+

LED_PWM BKOFF#_R

2 2

3 3

STARC_111H30-000000-G4-R

4 4

JLVDS

GND GND GND GND GND

+3VS

@JLVDS

@

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31 32 33 34 35

W=20mils

+3VS_LVDS_CAM

12

LCD_EDID_CLK <27>

LCD_EDID_DATA <27>

LCD_TXOUT0- <27>

LCD_TXOUT0+ <27>

LCD_TXOUT1- <27>

LCD_TXOUT1+ <27>

LCD_TXOUT2- <27>

LCD_TXOUT2+ <27>

LCD_TXCLK+ <27>

1.5A

+LCD_INV

1 2

@

C257 47P_0402_50V8J

1.5A

+LCD_INV

C234

68P_0402_50V8J

LCD_TXCLK- <27>

For RF

1

2

C256 47P_0402_50V8J

1 2

CAM@

0.1U_0402_10V7K

0.1U_0402_10V7K 1 2

C225

2 3

D84 AZ5125-02S.R7G_SOT23-3

@

1 C226

C226

2

0.1U_0402_10V7K

4.7U_0805_10V4Z

L2

FBMA-L11-201209-221LMA30T_0805

1

C235

0.1U_0402_25V6

0.1U_0402_25V6 2

B+

12

1

INT_MIC_CLK <38>

INT_MIC_DATA <38>

+LCD_VDD

2A

1 C227

C227

2

+3VS

1

C232

0.1U_0402_10V7K

2

+LCD_VDD

For RF

1 2

@

C258 47P_0402_50V8J

LED_PWM

R131

47K_0402_5%

BKOFF#_R

12

1 2

D15 RB751V40_SC76-2D15 RB751V40_SC76-2

12

R113

R113 10K_0402_5%

10K_0402_5%

D17RB751V40_SC76-2 D17RB751V40_SC76-2

PCH_PWM <27>

BKOFF# <40>

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

LVDS

VCUAA

22 53Tuesday, October 16, 2012

E

1.0

of

A

B

C

D

+3VS+3VS

E

+HDMI_5V_OUT

CV336 0.1U_0402_10V7KCV336 0.1U_0402_10V7K

UMA_HDMI_TXC+<27> UMA_HDMI_TXC-<27> UMA_HDMI_TX0+<27>

UMA_HDMI_TX0-<27>

1 1

2 2

3 3

UMA_HDMI_TX1+<27>

UMA_HDMI_TX1-<27>

UMA_HDMI_TX2+<27>

UMA_HDMI_TX2-<27>

UMA_DVI_TXC+

UMA_DVI_TXC-

UMA_DVI_TXD0-

UMA_DVI_TXD0+

UMA_DVI_TXD1+

UMA_DVI_TXD1-

UMA_DVI_TXD2-

UMA_DVI_TXD2+

1 2

CV337 0.1U_0402_10V7KCV337 0.1U_0402_10V7K

1 2

CV338 0.1U_0402_10V7KCV338 0.1U_0402_10V7K

1 2

CV339 0.1U_0402_10V7KCV339 0.1U_0402_10V7K

1 2

CV340 0.1U_0402_10V7KCV340 0.1U_0402_10V7K

1 2

CV341 0.1U_0402_10V7KCV341 0.1U_0402_10V7K

1 2

CV342 0.1U_0402_10V7KCV342 0.1U_0402_10V7K

1 2

CV343 0.1U_0402_10V7KCV343 0.1U_0402_10V7K

1 2

@

1 2

R160 0_0402_5%

R160 0_0402_5% WCM-2012HS-900T_4P

WCM-2012HS-900T_4P

4

1

L8

1 2

R199 0_0402_5%

1 2

R208 0_0402_5%

R208 0_0402_5% L9

L9

1

4

WCM-2012HS-900T_4P

1 2

R210 0_0402_5%

1 2

R207 0_0402_5%

R207 0_0402_5% WCM-2012HS-900T_4P

WCM-2012HS-900T_4P

4

1

L10

1 2

R196 0_0402_5%

1 2

R192 0_0402_5%

R192 0_0402_5% L11

L11

1

4

WCM-2012HS-900T_4P

1 2

R209 0_0402_5%

3

2

@

2

3

@

3

2

@

2

3

@

HDMI_R_CK+

HDMI_R_CK-

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1+

HDMI_R_D1-

HDMI_R_D2-

HDMI_R_D2+

UMA_DVI_TXC+

UMA_DVI_TXCUMA_DVI_TXD0+

UMA_DVI_TXD0-

UMA_DVI_TXD1+

UMA_DVI_TXD1-

UMA_DVI_TXD2+

UMA_DVI_TXD2-

HDMI Royalty

JHDMI1

RO0000003HM

HDMI W/Logo + HDCP

HDMIW/OLogo:RO0000001HM HDMIW/Logo:RO0000002HM HDMIW/Logo+HDCP:RO0000003HM

0.1U_0402_10V7K

C264

45@JHDMI1

45@

2

1

+HDMI_5V_OUT

A2Y

1 2

1K_0402_5%

1

5

U9

P

G

3

HDMI_HPD

4

OE#

74AHCT1G125GW_SOT353-5

R145

100K_0402_5%

HDMI_R_CK+ HDMI_R_CKHDMI_R_D1HDMI_R_D1+ HDMI_R_D0+

HDMI_R_D0HDMI_R_D2-

HDMI_R_D2+

R186

UMA_HDMI_CLK<27>

UMA_HDMI_DATA<27>

HDMI_HPD_CHDMI_HPD_U

2

C265

0.1U_0402_10V7K

1

1 2

R195

1 2

680_0402_5%

R197

1 2

680_0402_5%

R198

1 2

680_0402_5%

R202

1 2

680_0402_5%

R201

1 2

680_0402_5%

R203

1 2

680_0402_5%

R205

1 2

680_0402_5%

R206

1 2

680_0402_5%

+5VS

Q24

2

G

PMEG2010AEH_SOD123

13

D

S

2N7002KW_SOT323-3

D53

2 1

+HDMI_5V_OUT

R184

2.2K_0402_5%

2

3 1

2

SGD

Q18

BSH111_SOT23-3

SGD

Q19

HDMI_HPD

0.5A_8V_KMC3S050RY

BSH111_SOT23-3

R571

2.2K_0402_5%

F2

21

3 1

BSH111_SOT23-3

+HDMI_5V_OUT_F

HDMI Connector

HDMI_HPD_C

HDMI_SDATA HDMI_SCLK

HDMI_R_CKHDMI_R_CK+

HDMI_R_D0-

HDMI_R_D0+

HDMI_R_D1-

HDMI_R_D1+

HDMI_R_D2-

HDMI_R_D2+

JHDMI 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

TYCO_2041343-1~D

12

+3VS

1

C259

0.1U_0402_10V7K

2

HP_DET +5V DDC/CEC_GND SDA SCL Reserved CEC CKCK_shield CK+ D0D0_shield D0+ D1D1_shield D1+ D2D2_shield D2+

12

R185

2.2K_0402_5%

HDMI_SCLK

HDMI_SDATA

HDMI_HPD <27,29>

+HDMI_5V_OUT+5VS

@JHDMI

@

23

GND

22

GND

21

GND

20

GND

common CHOKE use 67ohm 5/30 change to 90ohm EMI request

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

HDMI Conn.

VCUAA

23 53Tuesday, October 16, 2012

E

1.0

of

A

CMOS Setting, near DDR Door

RH23

+RTCVCC

1 1

RH23 20K_0402_5%

20K_0402_5%

iME Setting.

RH24

RH24 20K_0402_5%

20K_0402_5%

1 2

PCH_RTCRST#

PCH_SRTCRST#

CH4

1U_0402_6.3V6K

CH5

1U_0402_6.3V6K

JCMOS @JCMOS @

1 2 1 2

JME @JME @

1 2 1 2

Integrated SUS 1.05V VRM Enable

PCH_INTVRMEN

+RTCVCC

+3VS

HDA_SDO

ME debug mode, this signal has a weak internal pull down

2 2

Low = Disable (default)

*

High = Enable (flash descriptor security overide)

HDA_SYNC

This signal has a weak internal pull down

*

H=>On Die PLL is supplied by 1.5V L=>On Die PLL is supplied by 1.8V Need to pull high for Chief River Mobile platform

AZ_SYNC_HD<38>

3 3

12

47P_0402_50V8J

47P_0402_50V8J @

@

For RF

PCH_SPICLK PCH_SPIDI

High - Enable Internal VRs (must be always pulled high)

RH12

1 2

1M_0402_5%

RH33

RH36 1K_0402_5%

CH19

1M_0402_5%

1 2

330K_0402_5%

@

1 2

+3VALW_PCH

CH6

0.1U_0402_10V7K

1 2

RH66 33_0402_5%RH66 33_0402_5%

1 2

RH67 33_0402_5%RH67 33_0402_5%

1 2

RH54 33_0402_5%RH54 33_0402_5%

1 2

RH56 1M_0402_5%RH56 1M_0402_5%

+3VS

1

2

PCH_SPICS0# PCH_SPI0_CLK

SM_INTRUDER# PCH_INTVRMEN

PCH_SPKR

AZ_SYNC_R

PCH_SPKR High = Enabled "No Reboot Mode" Low = Disabled (Default)

*

12

RH55 1K_0402_5%RH55 1K_0402_5%

+5VS

G

S

BSS138_NL_SOT23-3

1 2

RH274 0_0402_5%

SPI ROM for BIOS & ME (4MByte )

UH3

8

VCC

VSS

3

W

7

HOLD

1

S

6

C

5

MX25L3205DM2I-12G SO8

Q

D

Placement near to YH1

PCH_RTCX1_R<34>

AZ_BITCLK_HD

1

@ CH101

@

2

AZ_SYNC

2

QH1

13

D

@

4MB ROM P/N:

4

SA00003K800 SA00004LI00

PCH_SPI0_DOPCH_SPI0_DI

2

CH101 10P_0402_50V8J

10P_0402_50V8J

1 2

RH68 33_0402_5%RH68 33_0402_5%

Socket: SP07000F500/SP07000H900 Please place U13 & U4 close to U2 PCH, please place RH66, RH67, RH68 near UH3 Please place RH267 near RH66, Please place RH271 near RH67, Please place RH269 near RH68.

4 4

B

CH2 15P_0402_50V8J

RH26 0_0402_5%

Change Net name due to this function is high active

32.768KHZ_12.5P_1TJF125DP1A000D

AZ_BITCLK_HD<38>

PCH_SPKR<38>

AZ_RST_HD#<38>

AZ_SDIN0_HD<38>

AZ_SDOUT_HD<38>

PWRME_CTRL<40>

PCH_SPIDO

PCH_RTCX1

GCLK@

1 2

RH26 0_0402_5%

CH2 15P_0402_50V8J

NOGCLK@

CH3 15P_0402_50V8J

RH27 33_0402_5%RH27 33_0402_5%

RH30 33_0402_5%RH30 33_0402_5%

+3VALW_PCH

RH272 1K_0402_5%

RH272 1K_0402_5% RH32 33_0402_5%RH32 33_0402_5%

PCH_SPIDO PCH_SPI1_DO

NOGCLK@

12

YH1

RH2

1 2

NOGCLK@

12

1 2

RH25 0_0402_5%

10M_0402_5%

@

12

@

T74 PADT74 PAD T75 PADT75 PAD T88 PADT88 PAD

SPI ROM for Win8 (2MByte )

PCH_SPICS1#

1 2

RH269 33_0402_5%RH269 33_0402_5%

for EMI

RH65

10_0402_5%

CH7

10P_0402_50V8J

12

NOGCLK@

+3VS

PCH_SPI0_CLK

12

1

2

C

PCH_RTCX1

PCH_RTCX2 PCH_RTCRST# PCH_SRTCRST# SM_INTRUDER# PCH_INTVRMEN

AZ_BITCLK AZ_SYNC PCH_SPKR AZ_RST#

AZ_SDIN0_HD

AZ_SDOUT

PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI PCH_JTAG_TDO

PCH_SPICLK PCH_SPICS0# PCH_SPICS1#

PCH_SPIDI PCH_SPIDO

UH4

1

CS#

2

SO

3

WP#

4

GND

MX25L1606EM2I-12G_SO8

UH1A

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

N34

HDA_BCLK

L34

HDA_SYNC

T10

SPKR

K34

HDA_RST#

E34

HDA_SDIN0

G34

HDA_SDIN1

C34

HDA_SDIN2

A34

HDA_SDIN3

A36

HDA_SDO

C36

HDA_DOCK_EN# / GPIO33

N32

HDA_DOCK_RST# / GPIO13

J3

JTAG_TCK

H7

JTAG_TMS

K5

JTAG_TDI

H1

JTAG_TDO

T3

SPI_CLK

Y14

SPI_CS0#

T1

SPI_CS1#

V4

SPI_MOSI

U3

SPI_MISO

PANTHER-POINT_FCBGA989 HM77R1@

8

VCC

7

HOLD#

6

SCLK

5

SI

+3VS

RTCIHDA

JTAG

SPI

47P_0402_50V8J

1 2

CH20

@ CH20

@

0.1U_0402_10V7K

1 2

CH100

RH267 33_0402_5%RH267 33_0402_5%

1 2 1 2

RH271 33_0402_5%RH271 33_0402_5%

2MB ROM P/N: SA000041N00 SA00003FO10

for EMI

10_0402_5%

10P_0402_50V8J

RH69

CH21

FWH0 / LAD0 FWH1 / LAD1 FWH2 / LAD2 FWH3 / LAD3

LPC

FWH4 / LFRAME#

LDRQ0#

LDRQ1# / GPIO23

SERIRQ

SATA0RXN

SATA0RXP SATA0TXN SATA0TXP

SATA1RXN

SATA1RXP

SATA 6G

SATA1TXN SATA1TXP

SATA2RXN

SATA2RXP SATA2TXN SATA2TXP

SATA3RXN

SATA3RXP SATA3TXN SATA3TXP

SATA4RXN

SATA4RXP SATA4TXN

SATA

SATA4TXP

SATA5RXN

SATA5RXP SATA5TXN SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3RCOMPO

SATA3COMPI

SATA3RBIAS

SATALED# SATA0GP / GPIO21 SATA1GP / GPIO19

For RF

PCH_SPICLKPCH_SPI1_CLK PCH_SPIDIPCH_SPI1_DI

PCH_SPI1_CLK

12

1

2

D

C38 A38 B37 C37

D36 E36

K36 V5

SATA_PRX_C_DTX_N0

AM3

SATA_PRX_C_DTX_P0

AM1

SATA_PTX_DRX_N0

AP7

SATA_PTX_DRX_P0

AP5

SATA_PRX_C_DTX_N1

AM10

SATA_PRX_C_DTX_P1

AM8

SATA_PTX_DRX_N1

AP11

SATA_PTX_DRX_P1

AP10 AD7

AD5 AH5 AH4

AB8 AB10 AF3 AF1

Y7 Y5 AD3 AD1

Y3 Y1 AB3 AB1

Y11 Y10

AB12 AB13

AH1

P3 V14 P1

LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3

LPC_FRAME#

SERIRQ

SATAICOMP

SATA3_COMP

RBIAS_SATA3

SATA_LED# PCH_GPIO21 PCH_GPIO19

E

LPC_AD0 <40,41> LPC_AD1 <40,41> LPC_AD2 <40,41> LPC_AD3 <40,41>

LPC_FRAME# <40,41>

SERIRQ <40>

SATA_PRX_C_DTX_N0 <33> SATA_PRX_C_DTX_P0 <33> SATA_PTX_DRX_N0 <33> SATA_PTX_DRX_P0 <33>

SATA_PRX_C_DTX_N1 <34> SATA_PRX_C_DTX_P1 <34> SATA_PTX_DRX_N1 <34> SATA_PTX_DRX_P1 <34>

1 2

RH43 37.4_0402_1%RH43 37.4_0402_1%

1 2

RH48 49.9_0402_1%RH48 49.9_0402_1%

1 2

RH41 750_0402_1%RH41 750_0402_1%

SERIRQ

PCH_GPIO21

PCH_GPIO19

SATA_LED#

+1.05VS_VCC_SATA

+1.05VS_SATA3

RH31 10K_0402_5%RH31 10K_0402_5%

12

HDD

mSATA

RH34 10K_0402_5%RH34 10K_0402_5%

RH28 10K_0402_5%RH28 10K_0402_5%

RH29 10K_0402_5%RH29 10K_0402_5%

12

1 2

12

BOOT BIOS Strap Bit 0

PCH_GPIO19 <28>

+RTCVCC +RTCBATT

+RTCBATT

Un-mount for reduce power consumption at S0, S3 state

12

RH46

RH46 200_0402_5%

200_0402_5% @

@

PCH_JTAG_TMS PCH_JTAG_TDO PCH_JTAG_TDI

12

RH44

RH44 100_0402_1%

100_0402_1% @

@

1 2

RH50 51_0402_1%

If use GCLK, please delete DH1

1

CH8

2

0.1U_0402_10V7K

+3VALW_PCH +3VALW_PCH+3VALW_PCH

12

PCH_JTAG_TCK

RH45

RH45 200_0402_5%

200_0402_5% @

@

RH39

RH39 100_0402_1%

100_0402_1% @

@

DH1

12

RB751V-40_SOD323-2

12

DH7

DH7 RB751V-40_SOD323-2

RB751V-40_SOD323-2

+3VL

RH38

RH38 200_0402_5%

200_0402_5% @

@

1 2

RH40

RH40 100_0402_1%

100_0402_1% @

@

1 2

+3VS

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

PCH_HDA/JTAG/SATA/SPI/LPC

VCUAA

E

of

24 53Tuesday, October 16, 2012

1.0

A

PCIE_PRX_C_LANTX_N1<35>

PCIE_PRX_C_LANTX_P1<35>

LAN

WLAN

1 1

+3VS

Intel Spec: PCIECLK_RQ0# is suspend well,

2 2

but we pull high to +3VS for LAN en/disable function

+3VALW_PCH

3 3

PCIE_PTX_C_LANRX_N1<35> PCIE_PTX_C_LANRX_P1<35>

PCIE_PRX_WLANTX_N2<34>

PCIE_PRX_WLANTX_P2<34> PCIE_PTX_C_WLANRX_N2<34> PCIE_PTX_C_WLANRX_P2<34>

1 2

RH99 10K_0402_5%RH99 10K_0402_5%

1 2

RH104 10K_0402_5%RH104 10K_0402_5%

1 2

RH95 10K_0402_5%RH95 10K_0402_5%

1 2

RH116 10K_0402_5%RH116 10K_0402_5%

1 2

RH107 10K_0402_5%RH107 10K_0402_5%

1 2

RH110 10K_0402_5%RH110 10K_0402_5%

1 2

RH112 10K_0402_5%RH112 10K_0402_5%

1 2

RH119 10K_0402_5%RH119 10K_0402_5%

1 2

RH114 10K_0402_5%RH114 10K_0402_5%

PCH_GPIO20

CLKREQ_WLAN#

CLKREQ_LAN#

CH13 0.1U_0402_10V7KCH13 0.1U_0402_10V7K CH11 0.1U_0402_10V7KCH11 0.1U_0402_10V7K

CH14 0.1U_0402_10V7KCH14 0.1U_0402_10V7K CH17 0.1U_0402_10V7KCH17 0.1U_0402_10V7K

LAN

WLAN

LVDS_SEL

PCH_GPIO26

PCH_GPIO44

PANEL_SEL

PASSWORD_CLEAR#

12 12

CLK_LAN#<35> CLK_LAN<35>

CLKREQ_LAN#<35>

CLK_WLAN#<34> CLK_WLAN<34>

CLKREQ_WLAN#<34>

12

JPW@JPW

@

PCIE_PRX_C_LANTX_N1 PCIE_PRX_C_LANTX_P1 PCIE_PTX_LANRX_N1 PCIE_PTX_LANRX_P1

PCIE_PRX_WLANTX_N2 PCIE_PRX_WLANTX_P2 PCIE_PTX_WLANRX_N2 PCIE_PTX_WLANRX_P2

CLK_LAN# CLK_LAN

CLKREQ_LAN#

CLK_WLAN# CLK_WLAN

CLKREQ_WLAN#

PCH_GPIO20

PCH_GPIO25

PCH_GPIO26

PCH_GPIO44PCH_GPIO25

PASSWORD_CLEAR#

LVDS_SEL

PANEL_SEL

LVDS_SEL

4 4

Channel

HL

Single (Default)

Dual

B

UH1B

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

PETN4

BB34

PETP4

BG37

PERN5

BH37

PERP5

AY36

PETN5

BB36

PETP5

BJ38

PERN6

BG38

PERP6

AU36

PETN6

AV36

PETP6

BG40

PERN7

BJ40

PERP7

AY40

PETN7

BB40

PETP7

BE38

PERN8

BC38

PERP8

AW38

PETN8

AY38

PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0# / GPIO73

AB49

CLKOUT_PCIE1N

AB47

CLKOUT_PCIE1P

M1

PCIECLKRQ1# / GPIO18

AA48

CLKOUT_PCIE2N

AA47

CLKOUT_PCIE2P

V10

PCIECLKRQ2# / GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3# / GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4# / GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5# / GPIO44

AB42

CLKOUT_PEG_B_N

AB40

CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ# / GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6# / GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7# / GPIO46

AK14

CLKOUT_ITPXDP_N

AK13

CLKOUT_ITPXDP_P

PANTHER-POINT_FCBGA989 HM77R1@

SMBUSController

SML1ALERT# / PCHHOT# / GPIO74

PCI-E*

CLOCKS

PANEL_SEL

HL

Channel LVDS

SMBALERT# / GPIO11

SML0ALERT# / GPIO60

SML1CLK / GPIO58

SML1DATA / GPIO75

Link

PEG_A_CLKRQ# / GPIO47

CLKOUT_PEG_A_N CLKOUT_PEG_A_P

CLKOUT_DMI_N CLKOUT_DMI_P

CLKOUT_DP_N

CLKOUT_DP_P

CLKIN_DMI_N CLKIN_DMI_P

CLKIN_GND1_N CLKIN_GND1_P

CLKIN_DOT_96N CLKIN_DOT_96P

CLKIN_SATA_N CLKIN_SATA_P

REFCLK14IN

CLKIN_PCILOOPBACK

XTAL25_OUT

XCLK_RCOMP

CLKOUTFLEX0 / GPIO64 CLKOUTFLEX1 / GPIO65 CLKOUTFLEX2 / GPIO66 CLKOUTFLEX3 / GPIO67

FLEX CLOCKS

EDP

C

PCH_SMBALERT#

E12

PCH_SMBCLK

H14

SMBCLK

SMBDATA

SML0CLK

SML0DATA

CL_CLK1

CL_DATA1

CL_RST1#

XTAL25_IN

PCH_SMBDATA

C9

DRAMRST_CNTRL_PCH

A12

PCH_SMLCLK0

C8

PCH_SMLDATA0

G12

LAN_EN

C13

PCH_SMLCLK1

E14

PCH_SMLDATA1

M16

M7

Control Link only for support Intel IAMT.

T11

P10

CLK_REQ_VGA#

M10

CLK_PCIE_VGA#

AB37

CLK_PCIE_VGA

AB38

CLK_CPU_DMI#

AV22

CLK_CPU_DMI

AU22

AM12 AM13

PCH_CLK_DMI#

BF18

PCH_CLK_DMI

BE18

CLKIN_GND1#

BJ30

CLKIN_GND1

BG30

CLK_DOT#

G24

CLK_DOT

E24

CLK_SATA#

AK7

CLK_SATA

AK5

CLK_14M_PCH

K45

CLK_PCILOOP

H45

PCH_X1

V47

PCH_X2

V49

XCLK_RCOMP

Y47

K43 F47 H47 K49

Compal common design SW request to add DGPU_Present on this GPIO67

CLK_FLEX0 PCH_48MCLK CLK_FLEX2 DGPU_PRSNT#

RH115 90.9_0402_1%RH115 90.9_0402_1%

RH1 22_0402_5%RH1 22_0402_5%

DGPU_PRSNT#

M/B SKU UMA

DRAMRST_CNTRL_PCH <11,7>

LAN_EN <35>

CLK_REQ_VGA# <13>

CLK_PCIE_VGA# <13> CLK_PCIE_VGA <13>

CLK_CPU_DMI# <5> CLK_CPU_DMI <5>

CLK_PCILOOP <28>

1 2

T72

1 2

T73 PADT73 PAD

PAD

+1.05VS_VCCDIFFCLKN

HL

DIS/OPT

D

RH72 2.2K_0402_5%RH72 2.2K_0402_5%

+3VALW_PCH +3VS

VGA

From Clock Gen.

12

RH70 2.2K_0402_5%RH70 2.2K_0402_5%

12

PCH_SMBDATA

PCH_SMBCLK

RH78 2.2K_0402_5%RH78 2.2K_0402_5%

12

RH74 2.2K_0402_5%RH74 2.2K_0402_5%

12

PCH_SMLDATA1

PCH_SMLCLK1

PCH_SMBALERT# DRAMRST_CNTRL_PCH LAN_EN PCH_SMLCLK0 PCH_SMLDATA0

PCH_CLK_DMI# PCH_CLK_DMI

CLKIN_GND1# CLKIN_GND1

CLK_DOT# CLK_DOT

CLK_SATA# CLK_SATA

CLK_14M_PCH

5

3 4

2

QH3B

QH3B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

6 1

QH3A

QH3A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

3 4

2

QH4B

QH4B 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

6 1

QH4A

QH4A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

@

CLK_REQ_VGA#

12

RH275 10K_0402_5%

RH79 10K_0402_5%RH79 10K_0402_5% RH82 10K_0402_5%RH82 10K_0402_5%

RH85 10K_0402_5%RH85 10K_0402_5% RH86 10K_0402_5%RH86 10K_0402_5%

RH80 10K_0402_5%RH80 10K_0402_5% RH81 10K_0402_5%RH81 10K_0402_5%

RH83 10K_0402_5%RH83 10K_0402_5% RH84 10K_0402_5%RH84 10K_0402_5%

RH87 10K_0402_5%RH87 10K_0402_5%

RH102 4.7K_0402_5%RH102 4.7K_0402_5%

RH103 4.7K_0402_5%RH103 4.7K_0402_5%

5

RH262 10K_0402_5%RH262 10K_0402_5%

1 2

RH76 1K_0402_5%RH76 1K_0402_5%

1 2

RH75 10K_0402_5%RH75 10K_0402_5%

1 2 RH73 2.2K_0402_5%RH73 2.2K_0402_5% RH77 2.2K_0402_5%RH77 2.2K_0402_5%

RH89 10K_0402_5%RH89 10K_0402_5%

1 2 1 2

1 2

For EMI

CLK_48M_CR <36>

CH26

27P_0402_50V8J

NOGCLK@

CLK_PCILOOP

PCH_X1_R<34>

PCH_X1 PCH_X2

1

2

DGPU_PRSNT#

@

12

RH124 10_0402_5%

RH37

1 2

0_0402_5%

GCLK@

Placement near to YH2

NOGCLK@

RH117 1M_0402_5%

YH2

1

RH227 10K_0402_5%

RH261 10K_0402_5%

25MHZ_20PF_7V25000016NOGCLK@

GND

2

UMA@

1 2

OPT@

GND

12

3

4

E

PM_SMBDATA <11,12,34,41>

PM_SMBCLK <11,12,34,41>

+3VS+3VALW_PCH

EC_SMB_DA2 <13,40>

EC_SMB_CK2 <13,40>

12 12

12

@

12

CH28 22P_0402_50V8J

PCH_X1

1

CH27

CH27 27P_0402_50V8J

27P_0402_50V8J

2

NOGCLK@

+3VS

+3VALW_PCH

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

PCH_PCI-E/SMBUS/CLK

VCUAA

25 53Tuesday, October 16, 2012

E

1.0

of

A

+3VALW_PCH

PCH_SUSPWRDN#_R

1 1

2 2

Stuff R137 if EC does not want to involve in the handshake mechanism for the DeepSX state entry and exit

3 3

RH234 10K_0402_5%RH234 10K_0402_5%

RH157 10K_0402_5%RH157 10K_0402_5%

RH155 10K_0402_5%RH155 10K_0402_5%

RH163 10K_0402_5%RH163 10K_0402_5%

RH279 10K_0402_5%RH279 10K_0402_5%

RH280 10K_0402_5%

Reserve 0 ohm for cost down plan 2010/08/25

VGATE<40,49>

PM_PWROK<40,5>

12

@

12

0.1U_0402_10V7K

0.1U_0402_10V7K 1 2

CH103

PM_PWROK

@

PCH_SUSPWRDN#_RSUSACK#_R

12

RH282 0_0402_5%

RI#

PCH_LOW_BAT#

PCH_RSMRST#

PM_PWROK

SYS_PWROK

0_0402_5%

RH281

1 2

@CH103

@

1 2

+3VS

IN1 IN2

5

UH5

P

4

O

G

SN74AHC1G08DCKR_SC70-5

3

@

+3VALW_PCH

+1.05VS_PCH

Reserve this signal to EC by SW demand 2011/10/18a

SUSACK#<40>

DRAMPWROK<5>

PCH_RSMRST#<40>

PCH_SUSPWRDN#<40>

PBTN_OUT#<40>

1 2

RH161 330K_0402_5%RH161 330K_0402_5%

ACIN<40,44>

CH751H-40PT_SOD323-2

Reserve this signal to EC by SW demand 2011/10/18a

DMI_CTX_PRX_N0<6> DMI_CTX_PRX_N1<6> DMI_CTX_PRX_N2<6> DMI_CTX_PRX_N3<6>

DMI_CTX_PRX_P0<6> DMI_CTX_PRX_P1<6> DMI_CTX_PRX_P2<6> DMI_CTX_PRX_P3<6>

DMI_PTX_CRX_N0<6> DMI_PTX_CRX_N1<6> DMI_PTX_CRX_N2<6> DMI_PTX_CRX_N3<6>

DMI_PTX_CRX_P0<6> DMI_PTX_CRX_P1<6> DMI_PTX_CRX_P2<6> DMI_PTX_CRX_P3<6>

1 2

RH126 49.9_0402_1%RH126 49.9_0402_1%

1 2

RH127 750_0402_1%RH127 750_0402_1%

+3VS

DH2

21

B

DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3

DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3

DMI_PTX_CRX_N0 DMI_PTX_CRX_N1 DMI_PTX_CRX_N2 DMI_PTX_CRX_N3

DMI_PTX_CRX_P0 DMI_PTX_CRX_P1 DMI_PTX_CRX_P2 DMI_PTX_CRX_P3

DMI_COMP

RBIAS_CPY

SUSACK#_R

@

1 2

RH133 0_0402_5%

1 2

RH47 1K_0402_5%RH47 1K_0402_5%

@

1 2

RH132 0_0402_5%

XDP_DBRESET#

SYS_PWROK

PM_PWROK

DRAMPWROK

PCH_RSMRST#

PCH_SUSPWRDN#_R

PBTN_OUT#

PCH_ACIN

PCH_LOW_BAT#

RI#

C

UH1C

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

K3

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT / GPIO31

E10

BATLOW# / GPIO72

A10

RI#

PANTHER-POINT_FCBGA989 HM77R1@

DMI

FDI

DMI

FDI

CLKRUN# / GPIO32

SUS_STAT# / GPIO61

SUSCLK / GPIO62

SLP_S5# / GPIO63

System Power Management

SLP_LAN# / GPIO29

FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7

FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7

FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1

DSWVRMEN

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

D

FDI_CTX_PRX_N0

BJ14

FDI_CTX_PRX_N1

AY14

FDI_CTX_PRX_N2

BE14

FDI_CTX_PRX_N3

BH13

FDI_CTX_PRX_N4

BC12

FDI_CTX_PRX_N5

BJ12

FDI_CTX_PRX_N6

BG10

FDI_CTX_PRX_N7

BG9

FDI_CTX_PRX_P0

BG14

FDI_CTX_PRX_P1

BB14

FDI_CTX_PRX_P2

BF14

FDI_CTX_PRX_P3

BG13

FDI_CTX_PRX_P4

BE12

FDI_CTX_PRX_P5

BG12

FDI_CTX_PRX_P6

BJ10

FDI_CTX_PRX_P7

BH9

FDI_INT

AW16

FDI_FSYNC0

AV12

FDI_FSYNC1

BC10

FDI_LSYNC0

AV14

FDI_LSYNC1

BB10

DSWVREN

A18

PCH_DPWROK

E22

EC_SWI#

B9

PCH_GPIO32

N3

SUS_STAT#

G8

N14

PM_SLP_S5#

D10

PM_SLP_S4#

H4

PM_SLP_S3#

F4

PM_SLP_A#

G10

PM_SLP_SUS#

G16

H_PM_SYNC

AP14

PCH_GPIO29 PCH_GPIO29

K14

FDI_CTX_PRX_N0 <6> FDI_CTX_PRX_N1 <6> FDI_CTX_PRX_N2 <6> FDI_CTX_PRX_N3 <6> FDI_CTX_PRX_N4 <6> FDI_CTX_PRX_N5 <6> FDI_CTX_PRX_N6 <6> FDI_CTX_PRX_N7 <6>

FDI_CTX_PRX_P0 <6> FDI_CTX_PRX_P1 <6> FDI_CTX_PRX_P2 <6> FDI_CTX_PRX_P3 <6> FDI_CTX_PRX_P4 <6> FDI_CTX_PRX_P5 <6> FDI_CTX_PRX_P6 <6> FDI_CTX_PRX_P7 <6>

FDI_INT <6> FDI_FSYNC0 <6> FDI_FSYNC1 <6> FDI_LSYNC0 <6> FDI_LSYNC1 <6>

EC_SWI# <35>

T76 PADT76 PAD

32.768 KHz

CLK_EC <40>

PM_SLP_S5# <40>

PM_SLP_S4# <40>

PM_SLP_S3# <40>

T77 PADT77 PAD

T78 PADT78 PAD

H_PM_SYNC <5>

E

PCH_RSMRST#PCH_DPWROK

@

1 2

RH128 0_0402_5%

Stuff R222 if do not support DeepSX state

+RTCVCC

DSWVREN

RH150 330K_0402_5%RH150 330K_0402_5% RH151 330K_0402_5%@RH151 330K_0402_5%@

12 12

DSWVREN must be always pulled high to +RTCVCC DSWVREN - Internal Deep Sleep 1.05V regulator

：

H Enable

*

L Disable

：

Follow EC check list demand, but don't implement CLKRUN# this fuction

+3VS

PCH_GPIO32

EC_SWI#

RH256 8.2K_0402_5%@RH256 8.2K_0402_5%@

1 2

RH160 10K_0402_5%RH160 10K_0402_5%

RH159 10K_0402_5%RH159 10K_0402_5%

1 2

RH162 10K_0402_5%@RH162 10K_0402_5%@

1 2

+3VALW_PCH

DH5

2 1

CH751H-40PT_SOD323-2

DH6

POK<43,45>

4 4

A

DH6

CH751H-40PT_SOD323-2

21

PCH_RSMRST#PM_PWROK PCH_RSMRST#

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_DMI/FDI/PM

VCUAA

26 53Tuesday, October 16, 2012

E

of

1.0

A

1 2

RH125 100K_0402_5%RH125 100K_0402_5%

1 1

+3VS

RH145 2.2K_0402_5%RH145 2.2K_0402_5%

RH146 2.2K_0402_5%RH146 2.2K_0402_5%

RH149 2.2K_0402_5%RH149 2.2K_0402_5%

RH148 2.2K_0402_5%RH148 2.2K_0402_5%

RH142 2.2K_0402_5%

RH144 2.2K_0402_5%

2 2

RH144 2.2K_0402_5%

EC_ENBKL

LCTL_CLK

12

LCTL_DATA

12

LCD_EDID_CLK

12

LCD_EDID_DATA

12

@

UMA_CRT_DATA

12

@

UMA_CRT_CLK

12

EC_ENBKL<40> LCD_ENVDD<22>

PCH_PWM<22>

LCD_EDID_CLK<22>

LCD_EDID_DATA<22>

1 2

RH143 2.37K_0402_1%RH143 2.37K_0402_1%

LCD_TXCLK-<22> LCD_TXCLK+<22>

LCD_TXOUT0-<22> LCD_TXOUT1-<22> LCD_TXOUT2-<22>

LCD_TXOUT0+<22> LCD_TXOUT1+<22> LCD_TXOUT2+<22>

Disable CRT, use 5%

B

EC_ENBKL LCD_ENVDD

PCH_PWM LCD_EDID_CLK

LCD_EDID_DATA LCTL_CLK

LCTL_DATA LVDS_IBG

T79 PADT79 PAD

LCD_TXCLKLCD_TXCLK+

LCD_TXOUT0LCD_TXOUT1LCD_TXOUT2-

LCD_TXOUT0+ LCD_TXOUT1+ LCD_TXOUT2+

UMA_CRT_CLK UMA_CRT_DATA

1 2

RH138 1K_0402_5%RH138 1K_0402_5%

CRT_IREF

UH1D

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

AF37

LVD_IBG

AF36

LVD_VBG

AE48

LVD_VREFH

AE47

LVD_VREFL

AK39

LVDSA_CLK#

AK40

LVDSA_CLK

AN48

LVDSA_DATA#0

AM47

LVDSA_DATA#1

AK47

LVDSA_DATA#2

AJ48

LVDSA_DATA#3

AN47

LVDSA_DATA0

AM49

LVDSA_DATA1

AK49

LVDSA_DATA2

AJ47

LVDSA_DATA3

AF40

LVDSB_CLK#

AF39

LVDSB_CLK

AH45

LVDSB_DATA#0

AH47

LVDSB_DATA#1

AF49

LVDSB_DATA#2

AF45

LVDSB_DATA#3

AH43

LVDSB_DATA0

AH49

LVDSB_DATA1

AF47

LVDSB_DATA2

AF43

LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

PANTHER-POINT_FCBGA989 HM77R1@

LVDS

CRT

SDVO_TVCLKINN SDVO_TVCLKINP

SDVO_CTRLCLK

SDVO_CTRLDATA

DDPC_CTRLCLK

DDPC_CTRLDATA

Digital Display Interface

DDPD_CTRLCLK

DDPD_CTRLDATA

C

SDVO_STALLN SDVO_STALLP

SDVO_INTN

SDVO_INTP

DDPB_AUXN DDPB_AUXP

DDPB_HPD

DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P

DDPC_AUXN DDPC_AUXP

DDPC_HPD

DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P

DDPD_AUXN DDPD_AUXP

DDPD_HPD

DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P

D

AP43 AP45

AM42 AM40

AP39

2.2K_0402_5%

AP40

P38 M39

AT49 AT47 AT40

AV42 AV40 AV45 AV46 AU48 AU47 AV47 AV49

P46 P42

AP47 AP49

RH141 100K_0402_5%RH141 100K_0402_5%

AT38 AY47

AY49 AY43 AY45 BA47 BA48 BB47 BB49

M43 M36

AT45 AT43

RH255 100K_0402_5%RH255 100K_0402_5%

BH41 BB43

BB45 BF44 BE44 BF42 BE42 BJ42 BG42

+3VS

12

RH140

RH139

2.2K_0402_5%

UMA_HDMI_CLK <23> UMA_HDMI_DATA <23>

HDMI_HPD HDMI_HPD UMA_HDMI_TX2-

UMA_HDMI_TX2+ UMA_HDMI_TX1UMA_HDMI_TX1+ UMA_HDMI_TX0UMA_HDMI_TX0+ UMA_HDMI_TXCUMA_HDMI_TXC+

12

HDMI_HPD <23,29> UMA_HDMI_TX2- <23>

UMA_HDMI_TX2+ <23> UMA_HDMI_TX1- <23> UMA_HDMI_TX1+ <23> UMA_HDMI_TX0- <23> UMA_HDMI_TX0+ <23> UMA_HDMI_TXC- <23> UMA_HDMI_TXC+ <23>

HDMI

@

100K_0402_5%

100K_0402_5% RH254

RH254

E

12

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

PCH_CRT/LVDS/HDMI

VCUAA

E

1.0

of

27 53Tuesday, October 16, 2012

A

+3VS

1 1

2 2

3 3

4 4

1 2

@

RH3188.2K_0402_5% RH3188.2K_0402_5%

PCH_GPIO4

RH3198.2K_0402_5% RH3198.2K_0402_5%

PCH_GPIO52

RH3208.2K_0402_5% RH3208.2K_0402_5%

PCH_GPIO2

RH3218.2K_0402_5% RH3218.2K_0402_5%

PCH_GPIO53

RH3248.2K_0402_5% RH3248.2K_0402_5%

PCH_GPIO51

RH3238.2K_0402_5% RH3238.2K_0402_5%

PCI_PIRQA#

RH3258.2K_0402_5% RH3258.2K_0402_5%

PCI_PIRQB#

RH3228.2K_0402_5% RH3228.2K_0402_5%

PCI_PIRQC#

RH2998.2K_0402_5% RH2998.2K_0402_5%

PCH_GPIO55

12

RH3058.2K_0402_5% RH3058.2K_0402_5%

PCH_GPIO3

RH3268.2K_0402_5% RH3268.2K_0402_5%

PCH_GPIO5

12

RH2908.2K_0402_5% RH2908.2K_0402_5%

PCI_PIRQD#

RH17510K_0402_5% RH17510K_0402_5%

DGPU_RST#

RH17610K_0402_5% RH17610K_0402_5%

DGPU_PWR_EN

RH2911K_0402_5%@RH2911K_0402_5%

DGPU_PWR_EN

CLK_PCI_EC<40> CLK_PCILOOP<25> CLK_PCI_DDR<41>

@

CH104100P_0402_50V8J@CH104100P_0402_50V8J

PLT_RST#

12

PCH_GPIO51

RH2931K_0402_5% @ RH2931K_0402_5% @

12

PCH_GPIO19

RH2941K_0402_5% @ RH2941K_0402_5% @

12

PCH_GPIO55

RH2951K_0402_5% @ RH2951K_0402_5% @

12

U3RXDN1<37> U3RXDN2<37>

U3RXDP1<37> U3RXDP2<37>

U3TXDN1<37> U3TXDN2<37>

U3TXDP1<37> U3TXDP2<37>

DGPU_PWR_EN<42,51>

PCH_GPIO19 <24>

T80 PADT80 PAD

PLT_RST#<34,35,40,41,5>

1 2 1 2 1 2

@

12

CH22

CH22 47P_0402_50V8J

47P_0402_50V8J @

@

U3RXDN1 U3RXDN2

U3RXDP1 U3RXDP2

U3TXDN1 U3TXDN2

U3TXDP1 U3TXDP2

RH16722_0402_5% RH16722_0402_5% RH16622_0402_5% RH16622_0402_5% RH29222_0402_5%

RH29222_0402_5%

PCH_GPIO51

B

UH1E

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3Rn1

BC30

USB3Rn2

BE32

USB3Rn3

BJ32

USB3Rn4

BC28

USB3Rp1

BE30

USB3Rp2

BF32

USB3Rp3

BG32

USB3Rp4

AV26

USB3Tn1

BB26

USB3Tn2

AU28

USB3Tn3

AY30

USB3Tn4

AU26

USB3Tp1

AY26

USB3Tp2

AV28

USB3Tp3

AW30

USB3Tp4

PCI_PIRQA# PCI_PIRQB# PCI_PIRQC# PCI_PIRQD#

DGPU_RST# PCH_GPIO52 DGPU_PWR_EN

PCH_GPIO51 PCH_GPIO53 PCH_GPIO55

PCH_GPIO2 PCH_GPIO3 PCH_GPIO4 PCH_GPIO5

PCI_PME# PLT_RST#

CLK_EC_R CLK_PCH CLK_SIO

RF_OFF#

0 0 1

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1# / GPIO50

C44

REQ2# / GPIO52

E40

REQ3# / GPIO54

D47

GNT1# / GPIO51

E42

GNT2# / GPIO53

F46

GNT3# / GPIO55

G42

PIRQE# / GPIO2

G40

PIRQF# / GPIO3

C42

PIRQG# / GPIO4

D44

PIRQH# / GPIO5

K10

PME#

C6

PLTRST#

H49

CLKOUT_PCI0

H43

CLKOUT_PCI1

J48

CLKOUT_PCI2

K42

CLKOUT_PCI3

H40

CLKOUT_PCI4

PANTHER-POINT_FCBGA989 HM77R1@

Boot BIOS Strap

PCH_GPIO19 Boot BIOS Loaction

0 1 0

11

RSVD

LPC

Reserved

PCI SPI

PCI

*

EHCI 1

EHCI 2

USB

RSVD1 RSVD2 RSVD3 RSVD4

RSVD5 RSVD6

RSVD7 RSVD8

RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22

RSVD23 RSVD24

RSVD25 RSVD26

RSVD27 RSVD28

RSVD29

USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N

USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P

USBRBIAS#

USBRBIAS

OC0# / GPIO59 OC1# / GPIO40 OC2# / GPIO41 OC3# / GPIO42 OC4# / GPIO43

OC5# / GPIO9 OC6# / GPIO10 OC7# / GPIO14

AY7 AV7 AU3 BG4

AT10 BC8

AU2 AT4 AT3 AT1 AY3 AT5 AV3 AV1 BB1 BA3 BB5 BB3 BB7 BE8 BD4 BF6

AV5 AV10

AT8 AY5

BA2 AT12

BF3

C24 A24 C25 B25 C26 A26 K28 H28 E28 D28 C28 A28 C29 B29 N28 M28 L30 K30 G30 E30 C30 A30 L32 K32 G32 E32 C32 A32

C33

B33

A14 K20 B17 C16 L16 A16 D14 C14

C

NV_ALE

USB20_N0 USB20_P0 USB20_N1 USB20_P1 USB20_N2 USB20_P2 USB20_N3 USB20_P3

USB20_N8 USB20_P8 USB20_N9 USB20_P9

USB20_N11 USB20_P11

USBBIAS

Within 500 mils

USB_OC#0 USB_OC#1 USB_OC#2 SLP_CHG_M3 SLP_CHG_M4 USB_OC#5 USB_OC#6 USB_OC#7

For Optimus

USB20_N0 <37> USB20_P0 <37> USB20_N1 <37> USB20_P1 <37> USB20_N2 <37> USB20_P2 <37> USB20_N3 <36> USB20_P3 <36>

T18 PAD @T18 PAD @ T19 PAD @T19 PAD @

USB20_N9 <34> USB20_P9 <34>

USB20_N11 <22> USB20_P11 <22>

1 2

RH165 22.6_0402_1%RH165 22.6_0402_1%

USB_OC#0 <37,40> USB_OC#1 <37,40>

USB_OC#2 <37,40> SLP_CHG_M3 <37> SLP_CHG_M4 <37>

1K_0402_5%

USB-Right1 USB-Right2 USB-Left CardReader

BT

Int. Camera

USB-Right Front USB-Right Rear USB-Left

PLT_RST# DGPU_RST#

RH287

@

D

2

1

1 2

PLT_RST#

RH173

100K_0402_5%

+3VS

1

IN1

2

IN2

SN74AHC1G08DCKR_SC70-5

CH12

0.47U_0402_6.3V6K

0.47U_0402_6.3V6K OPT@

OPT@

1 2

OPT@

1 2

CH30 0.1U_0402_10V7K

5

UH6

P

O

G

3

OPT@

@

4

1 2

RH286 0_0402_5%

100K_0402_5%

Intel Anti-Theft Techonlogy

High=Endabled

NV_ALE

Low=Disable(floating)

NV_ALE

RH164 1K_0402_5%

USB_OC#7

RH215 10K_0402_5%RH215 10K_0402_5%

USB_OC#0

RH209 10K_0402_5%RH209 10K_0402_5%

SLP_CHG_M3

RH210 10K_0402_5%RH210 10K_0402_5%

SLP_CHG_M4

RH211 10K_0402_5%RH211 10K_0402_5%

USB_OC#6

RH212 10K_0402_5%RH212 10K_0402_5%

USB_OC#1

RH177 10K_0402_5%RH177 10K_0402_5%

USB_OC#2

RH183 10K_0402_5%RH183 10K_0402_5%

USB_OC#5

RH186 10K_0402_5%RH186 10K_0402_5%

RH288

OPT@

@

1 2

E

PLTRST_VGA# <13>

12

*

+1.8VS

+3VALW_PCH

A16 Swap Override Strap

WL_OFF#

A

Low= A16 swap override Enable High= A16 swap override Disable

*

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_PCI/USB/NAND

VCUAA

28 53Tuesday, October 16, 2012

E

of

1.0

@

UMA@

@

OPT@

A

EC_LID_OUT#

12

EC_SMI#

PCH_GPIO12

PCH_GPIO28

PCH_GPIO57

BT_ON#

PCH_GPIO1

PCH_GPIO22

PCH_GPIO36

PCH_GPIO6

PCH_GPIO16

EC_SCI#

PCH_GPIO39

PCH_GPIO48

PCH_GPIO49

HDMI_HPD

12

OPTIMUS_EN#

PCH_GPIO37

PCH_GPIO27

12

PCH_GPIO48

12

OPTIMUS_EN#

12

Follow Compal ORB and Intel Check list 460603 V1.5

For OPT

+3VALW_PCH

RH204 1K_0402_5%RH204 1K_0402_5%

1 2

RH205 10K_0402_5%RH205 10K_0402_5%

1 2

RH298 10K_0402_5%RH298 10K_0402_5%

1 2

1 1

2 2

RH202 10K_0402_5%RH202 10K_0402_5%

RH207 10K_0402_5%RH207 10K_0402_5%

+3VS

RH180 10K_0402_5%RH180 10K_0402_5%

RH190 10K_0402_5%RH190 10K_0402_5%

RH185 10K_0402_5%RH185 10K_0402_5%

RH178 200K_0402_5%RH178 200K_0402_5%

RH197 10K_0402_5%RH197 10K_0402_5%

RH179 10K_0402_5%RH179 10K_0402_5%

RH303 10K_0402_5%RH303 10K_0402_5%

RH194 10K_0402_5%RH194 10K_0402_5%

RH304 10K_0402_5%

RH195 10K_0402_5%RH195 10K_0402_5%

RH216 10K_0402_5%

RH196 10K_0402_5%

RH198 10K_0402_5%RH198 10K_0402_5%

RH199 10K_0402_5%

RH307 47K_0402_5%RH307 47K_0402_5%

RH201 10K_0402_5%

1 2

GPIO28 On-Die PLL Voltage Regulator

H: Enable

*

3 3

L: Disable

RH206 1K_0402_5%@RH206 1K_0402_5%@

1 2

PCH_GPIO28

B

UH1F

T81 PADT81 PAD

HDMI_HPD PCH_GPIO1 PCH_GPIO6 EC_SCI# EC_SMI# PCH_GPIO12 EC_LID_OUT#

PCH_GPIO16

VGA_PWROK PCH_GPIO22

PCH_GPIO27 PCH_GPIO28 BT_ON# PCH_GPIO35 PCH_GPIO36 PCH_GPIO37 OPTIMUS_EN# PCH_GPIO39 PCH_GPIO48 PCH_GPIO49 PCH_GPIO57

HDMI_HPD<23,27>

EC_SCI#<40> EC_SMI#<40>

EC_LID_OUT#<40>

VGA_PWROK<42,51>

BT_ON#<34>

T7

BMBUSY# / GPIO0

A42

TACH1 / GPIO1

H36

TACH2 / GPIO6

E38

TACH3 / GPIO7

C10

GPIO8

C4

LAN_PHY_PWR_CTRL / GPIO12

G2

GPIO15

U2

SATA4GP / GPIO16

D40

TACH0 / GPIO17

T5

SCLOCK / GPIO22

E8

GPIO24

E16

GPIO27

P8

GPIO28

K1

STP_PCI# / GPIO34

K4

GPIO35

V8

SATA2GP / GPIO36

M5

SATA3GP / GPIO37

N2

SLOAD / GPIO38

M3

SDATAOUT0 / GPIO39

V13

SDATAOUT1 / GPIO48

V3

SATA5GP / GPIO49 / TEMP_ALERT#

D6

GPIO57

A4

VSS_NCTF_1

A44

VSS_NCTF_2

A45

VSS_NCTF_3

A46

VSS_NCTF_4

A5

VSS_NCTF_5

A6

VSS_NCTF_6

B3

VSS_NCTF_7

B47

VSS_NCTF_8

BD1

VSS_NCTF_9

BD49

VSS_NCTF_10

BE1

VSS_NCTF_11

BE49

VSS_NCTF_12

BF1

VSS_NCTF_13

BF49

VSS_NCTF_14

PANTHER-POINT_FCBGA989 HM77R1@

C

GPIO

NCTF

TACH4 / GPIO68 TACH5 / GPIO69 TACH6 / GPIO70 TACH7 / GPIO71

A20GATE

PECI

RCIN#

PROCPWRGD

THRMTRIP#

INIT3_3V#

DF_TVS

CPU/MISC

TS_VSS1 TS_VSS2 TS_VSS3 TS_VSS4

NC_1

VSS_NCTF_15 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_18 VSS_NCTF_19 VSS_NCTF_20 VSS_NCTF_21 VSS_NCTF_22 VSS_NCTF_23 VSS_NCTF_24 VSS_NCTF_25 VSS_NCTF_26 VSS_NCTF_27 VSS_NCTF_28 VSS_NCTF_29 VSS_NCTF_30 VSS_NCTF_31 VSS_NCTF_32

C40 B41 C41 A40

P4 AU16 P5 AY11 AY10 T14 AY1

AH8 AK11 AH10 AK10

P37

BG2 BG48 BH3 BH47 BJ4 BJ44 BJ45 BJ46 BJ5 BJ6 C2 C48 D1 D49 E1 E49 F1 F49

PCH_GPIO68

PCH_GPIO71

GATEA20

KB_RST# H_PWRGOOD PCH_THRMTRIP#

NV_CLE

D

GATEA20 <40>

KB_RST# <40>

1 2

RH191 390_0402_5%RH191 390_0402_5%

This signal has weak internal pull-up, can't be pulled low

H_PWRGOOD <5> H_THERMTRIP# <5>

DMI & FDI Termination Voltage

NV_CLE

PCH_GPIO68 GATEA20 KB_RST# PCH_GPIO71

Set to VCC when HIGH Set to VSS when LOW

+1.8VS

12

RH189 1K_0402_5%RH189 1K_0402_5%

1 2

RH297 10K_0402_5%RH297 10K_0402_5%

1 2

RH182 10K_0402_5%RH182 10K_0402_5%

1 2

RH184 10K_0402_5%RH184 10K_0402_5%

1 2

RH203 10K_0402_5%RH203 10K_0402_5%

RH187

2.2K_0402_5%

H_SNB_IVB# <5>

E

+3VS

GPIO8 Integrated Clock Chip Enable (Removed)

H: Disable L: Enable

*

RH308 1K_0402_5%@RH308 1K_0402_5%@

1 2

Integrated clock enable functionality is achieved by soft-strap The current default is clock enable

4 4

A

EC_SMI#

OPTIMUS_EN#

SKU NonOPT

HL

Optimus

B

PCH_GPIO57

HDD2_DET#

SKU ONE HDD

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HL

TWO HDD

2012/04/19 2015/04/19

C

PCH_GPIO71

3D_DET#

SKU Non3D

Compal Secret Data

Deciphered Date

HL

D

3D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_CPU/GPIO

VCUAA

E

1.0

of

29 53Tuesday, October 16, 2012

A

B

C

D

E

POWER

3709mA

POWER

VCC CORE

VCCIO

FDI

1mA

CRTLVDS

1mA

VCCTX_LVDS[1] VCCTX_LVDS[2]

60mA

VCCTX_LVDS[3] VCCTX_LVDS[4]

DMI

75mA

VCCDFTERM

VCCDFTERM[1]

VCCDFTERM[2]

190mA

VCCDFTERM[3]

VCCDFTERM[4]

DFT / SPI HVCMOS

20mA

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCSPI

U48

U47

AK36 AK37

AM37 AM38 AP36

0.01U_0402_25V7K

AP37

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

0.01U_0402_25V7K

+VCCA_LVDS

+VCCTX_LVDS

CH38

1

CH42

0.1U_0402_10V7K

2

+VCCAFDI_VRM

+VCCP_VCCDMI

+1.05VS_VCC_DMI

1

CH51

0.1U_0402_10V7K

2

1

CH53

CH53 1U_0402_6.3V6K

1U_0402_6.3V6K

2

0.1U_0402_10V7K

1

CH36

CH35

2

1 2

RH208 0_0603_5%

0.01U_0402_25V7K

1

CH39

2

+3VS

+VCCP_VCCDMI

1 2

RH214 0_0603_5%

1

CH49

CH49 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.8VS

+3VS

1

2

@

1

CH40

CH40 22U_0805_6.3V6M

22U_0805_6.3V6M

2

+VCCAFDI_VRM

+1.05VS_PCH

@

RH309

+VCCA_DAC_R

1 2

1_0603_1%

1

CH37

CH37 10U_0603_6.3V6M

10U_0603_6.3V6M

2

+3VS

LH2

BLM18PG181SN1D_0603

@

1 2

RH221 0_0603_5%

RH213 0_0603_5%

1

CH48

CH48 1U_0402_6.3V6K

1U_0402_6.3V6K

2

BLM18PG181SN1D_0603

12

+1.5VS

@

1 2

+1.05VS_VCCP

1 1

2 2

3 3

PJ4

2

JUMP_43X118

10U_0603_6.3V6M

+1.05VS_PCH

10U_0603_6.3V6M

@PJ4

@

112

1

CH32

2

This pin can be left as NC if On-Die VR is enabled (Default)

1

CH43

CH45

2

1U_0402_6.3V6K

This pin can be left as NC if On-Die VR is enabled (Default)

1

CH33

2

1U_0402_6.3V6K

1

CH46

2

+3VS

1U_0402_6.3V6K

CH31

1U_0402_6.3V6K

1

CH34

2

1U_0402_6.3V6K

+1.05VS_PCH

1

CH47

2

1

CH50

0.1U_0402_10V7K

2

+1.05VS_PCH

+VCCP_VCCDMI

+1.05VS_PCH +VCCA_DAC

1

2

T82PAD T82PAD

1

CH44

CH44 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+VCCAFDI_VRM

T83PAD T83PAD

UH1G

1700mA

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

PANTHER-POINT_FCBGA989 HM77R1@

LH1

+1.8VS

+3VS

12

PCH Power Rail Table Refer to PCH EDS R1.0

Voltage Rail

V_PROC_IO

V5REF

V5REF_Sus

Vcc3_3

VccADAC

VccADPLLA

VccADPLLB

VccCore

VccDMI

Voltage

1.05

5

3.3

1.05

1.1

S0 Iccmax Current (A)

0.001

0.228

0.063

0.08

1.7

0.047

1.05VccIO 3.711

1.05VccASW 0.903

3.3VccSPI 0.01

3.3VccDSW 0.001

1.8 0.002VccDFTERM

3.3VccRTC N/A

3.3VccSus3_3

3.3VccSusHDA

0.095

0.01

VccVRM 1.5 0.167

1.05VccCLKDMI

0.07

VccSSC 1.05 0.095

VccDIFFCLKN 1.05 0.055

VccALVDS 3.3

0.001

1.8VccTX_LVDS 0.04

+3VALW to +3V_PCH

+3VALW

4 4

PCH_PWR_EN#<31,42>

PCH_PWR_EN#

A

12

RH3 47K_0402_5%RH3 47K_0402_5%

@

2

112

PJ2 JUMP_43X79

QH2

QH2 AO3413_SOT23

AO3413_SOT23

D

S

D

S

13

G

1

2

CH1110.1U_0402_25V6 CH1110.1U_0402_25V6

CH1120.01U_0402_25V7K CH1120.01U_0402_25V7K

2

1

CH1140.1U_0402_25V6@CH1140.1U_0402_25V6

@

2

1 CH1130.1U_0402_10V7K CH1130.1U_0402_10V7K

2

B

+3VALW_PCH

12

@

RH4 20K_0402_5%@RH4 20K_0402_5%

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

PCH_POWER-1

VCUAA

30 53Tuesday, October 16, 2012

E

of

1.0

A

B

C

D

E

+3VS

LH5

1 2

10UH_LB2012T100MR_20%

1 1

2 2

+1.05VS_PCH

BLM18PG181SN1D_0603

+1.05VS_PCH

3 3

+1.05VS_PCH

4 4

@

1 2

RH244 0_0603_5%

@

1 2

RH247 0_0603_5%

RH313

@RH313

@

12

0_0603_5%

1

2

unmount CH83 by follow Compal ORB abd Intel CRB

A

+3VS_VCC_CLKF33

1

CH73

CH73 10U_0603_6.3V6M

10U_0603_6.3V6M

2

LH7

1 2

LH8

1 2

10U_0603_6.3V6M

+VCCDIFFCLK

1

CH79

CH79 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS_VCCDIFFCLKN

1

CH81

CH81 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VM_VCCSUS

CH83

CH83 1U_0402_6.3V6K

1U_0402_6.3V6K @

@

1

CH74

CH74 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS_VCCADPLLB

1

CH94

CH93

1U_0402_6.3V6K

2

+1.05VS_VCCDIFFCLKN

"@" Avoid leakage

+1.05VS_VCCADPLLA

1

CH95

2

10U_0603_6.3V6M

+1.05VS_VCCP

RH249 0_0603_5%

4.7U_0402_6.3V6M

+3VALW_PCH

CH58

0.1U_0402_10V7K

This pin can be left as NC if On-Die VR is enabled (Default)

1U_0402_6.3V6K

1

2

0.1U_0402_10V7K

+1.05VS_PCH

1U_0402_6.3V6K

@

1 2

CH86

+1.05VS_PCH

CH67

CH96

CH96 1U_0402_6.3V6K

1U_0402_6.3V6K

1

CH84

2

0.1U_0402_10V7K

1

CH87

2

+1.05VS_PCH

1

2

CH78

1

CH88

0.1U_0402_10V7K

2

This pin can be left as NC if On-Die VR is enabled (Default)

1

CH55

0.1U_0402_10V7K

2

@

12

1

CH54

CH54 1U_0402_6.3V6K

1U_0402_6.3V6K @

@

2

1

CH64

CH65

CH65 22U_0805_6.3V6M

22U_0805_6.3V6M

2

22U_0805_6.3V6M

1U_0402_6.3V6K

1

CH68

CH69

1U_0402_6.3V6K

2

+VCCRTCEXT

1

+VCCAFDI_VRM

2

+1.05VS_VCCADPLLA +1.05VS_VCCADPLLB

+VCCDIFFCLK

+1.05VS_VCCDIFFCLKN

+VCCSST

1

0.1U_0402_10V7K

0.1U_0402_10V7K +1.05VM_VCCSUS

CH85

2

1

+RTCVCC

2

CH89

1U_0402_6.3V6K

B

PAD

T84

+PCH_VCCDSW

+3VS_VCC_CLKF33

T85PAD T85PAD

+VCCSUS

1

2

1

2

+V_CPU_IO

0.1U_0402_10V7K

1

CH90

2

1

2

POWER

UH1J

AD49

VCCACLK

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

PANTHER-POINT_FCBGA989 HM77R1@

CH91

0.1U_0402_10V7K

POWER

3mA

1010mA

Clock and Miscellaneous

80mA 80mA

55mA

95mA

1mA

CPURTC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

119mA

1mA

PCI/GPIO/LPCMISC

SATA USB

10mA

HDA

+1.05VS_PCH

N26

VCCIO[29]

P26

VCCIO[30]

P28

VCCIO[31]

T27

VCCIO[32]

T29

VCCIO[33]

VCCSUS3_3[7] VCCSUS3_3[8] VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCSUS3_3[1]

1mA

VCCSUS3_3[2] VCCSUS3_3[3] VCCSUS3_3[4] VCCSUS3_3[5]

VCCAPLLSATA

VCCSUSHDA

T23 T24 V23 V24 P24

T26

VCCIO[34]

M26

V5REF_SUS

AN23

DCPSUS[4]

AN24

P34

V5REF

N20 N22 P20 P22

AA16

VCC3_3[1]

W16

VCC3_3[8]

T34

VCC3_3[4]

AJ2

VCC3_3[2]

AF13

VCCIO[5]

AH13

VCCIO[12]

AH14

VCCIO[13]

AF14

VCCIO[6]

AK1

AF11

VCCVRM[1]

AC16

VCCIO[2]

AC17

VCCIO[3]

AD17

VCCIO[4]

T21

VCCASW[22]

V21

VCCASW[23]

T19

VCCASW[21]

P32

2012/04/19 2015/04/19

1

CH56

CH56 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+3VALW_PCH

1

CH60

0.1U_0402_10V7K

2

+1.05VS_PCH

+PCH_V5REF_SUS

+VCCA_USBSUS

1 2

CH66 0.1U_0402_10V7KCH66 0.1U_0402_10V7K

+PCH_V5REF_RUN

1 2

CH75

0.1U_0402_10V7K

1

CH76

0.1U_0402_10V7K

2

+1.05VS_SATA3

This pin can be left as NC if On-Die VR is enabled (Default)

T86 PADT86 PAD

+VCCAFDI_VRM

+1.05VS_VCC_SATA

+VCCME_22

+VCCME_23

+VCCME_21

+VCCAFDI_VRM

+3VALW_PCH

1

CH92

0.1U_0402_10V7K

2

Compal Secret Data

Deciphered Date

+3VALW_PCH

1

CH61

0.1U_0402_10V7K

2

CH62 1U_0402_6.3V6K

+3VALW_PCH

1

CH70

CH70 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+3VS

+1.05VS_SATA3

+1.05VS_VCC_SATA

1

CH82

CH82 1U_0402_6.3V6K

1U_0402_6.3V6K

2

@

1 2

RH311 0_0402_5%

@

1 2

RH312 0_0402_5%

@

1 2

RH314 0_0402_5%

1 2

1

2

RH246 0_0805_5%

PCH_PWR_EN#<30,42>

RH5 47K_0402_5%RH5 47K_0402_5%

Change RH232, RH237 to 10 ohm by follow Compal ORB abd Intel CRB

@

+3VS

CH72

0.1U_0402_10V7K

+1.05VS_PCH

@

1 2

RH242 0_0805_5%

1

CH77

CH77 1U_0402_6.3V6K

1U_0402_6.3V6K

2

+1.05VS_PCH

@

1 2

+1.05VS_PCH

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

@

2

112

PJ5 JUMP_43X39

QH6

AO3413_SOT23

D

S

D

S

13

1

CH1150.1U_0402_25V6 CH1150.1U_0402_25V6

G

2

12

+5VALW_PCH +3VALW_PCH

12

RH232

10_0402_5%

+5VS +3VS

12

RH237

10_0402_5%

Compal Electronics, Inc.

PCH_POWER-2

VCUAA

+5VALW_PCH+5VALW

1

12

CH590.1U_0402_10V7K CH590.1U_0402_10V7K

2

@

RH228 20K_0402_5%@RH228 20K_0402_5%

21

DH3

DH3 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

+PCH_V5REF_SUS

1

CH63

0.1U_0402_10V7K

2

CH63 & CH71 are different by Intel CRB.

21

DH4

DH4 CH751H-40PT_SOD323-2

CH751H-40PT_SOD323-2

+PCH_V5REF_RUN

1

CH71

CH71 1U_0402_6.3V6K

1U_0402_6.3V6K

2

31 53Tuesday, October 16, 2012

E

1.0

of

A

UH1H

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

1 1

2 2

3 3

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

AB5

VSS[11]

AB7

VSS[12]

AC19

VSS[13]

AC2

VSS[14]

AC21

VSS[15]

AC24

VSS[16]

AC33

VSS[17]

AC34

VSS[18]

AC48

VSS[19]

AD10

VSS[20]

AD11

VSS[21]

AD12

VSS[22]

AD13

VSS[23]

AD19

VSS[24]

AD24

VSS[25]

AD26

VSS[26]

AD27

VSS[27]

AD33

VSS[28]

AD34

VSS[29]

AD36

VSS[30]

AD37

VSS[31]

AD38

VSS[32]

AD39

VSS[33]

AD4

VSS[34]

AD40

VSS[35]

AD42

VSS[36]

AD43

VSS[37]

AD45

VSS[38]

AD46

VSS[39]

AD8

VSS[40]

AE2

VSS[41]

AE3

VSS[42]

AF10

VSS[43]

AF12

VSS[44]

AD14

VSS[45]

AD16

VSS[46]

AF16

VSS[47]

AF19

VSS[48]

AF24

VSS[49]

AF26

VSS[50]

AF27

VSS[51]

AF29

VSS[52]

AF31

VSS[53]

AF38

VSS[54]

AF4

VSS[55]

AF42

VSS[56]

AF46

VSS[57]

AF5

VSS[58]

AF7

VSS[59]

AF8

VSS[60]

AG19

VSS[61]

AG2

VSS[62]

AG31

VSS[63]

AG48

VSS[64]

AH11

VSS[65]

AH3

VSS[66]

AH36

VSS[67]

AH39

VSS[68]

AH40

VSS[69]

AH42

VSS[70]

AH46

VSS[71]

AH7

VSS[72]

AJ19

VSS[73]

AJ21

VSS[74]

AJ24

VSS[75]

AJ33

VSS[76]

AJ34

VSS[77]

AK12

VSS[78]

AK3

VSS[79]

PANTHER-POINT_FCBGA989 HM77R1@

VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98]

VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158]

AK38 AK4 AK42 AK46 AK8 AL16 AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34 AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2 AN29 AN3 AN31 AP12 AP19 AP28 AP30 AP32 AP38 AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22 AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24 AU30 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8 AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40 AW48 AV11 AY12 AY22 AY28

B

C

UH1I

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

PANTHER-POINT_FCBGA989 HM77R1@

VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS[302] VSS[303] VSS[304] VSS[305] VSS[306] VSS[307] VSS[308] VSS[309] VSS[310] VSS[311] VSS[312] VSS[313] VSS[314] VSS[315] VSS[316] VSS[317] VSS[318] VSS[319] VSS[320] VSS[321] VSS[322] VSS[323] VSS[324] VSS[325] VSS[328] VSS[329] VSS[330] VSS[331] VSS[333] VSS[334] VSS[335] VSS[337] VSS[338] VSS[340] VSS[342] VSS[343] VSS[344] VSS[345] VSS[346] VSS[347] VSS[348] VSS[349] VSS[350] VSS[351] VSS[352]

H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 P16 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 P30 N47 P11 P18 T33 P40 P43 P47 P7 R2 R48 T12 T31 T37 T4 W34 T46 T47 T8 V11 V17 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W48 Y12 Y38 Y4 Y42 Y46 Y8 BG29 N24 AJ3 AD47 B43 BE10 BG41 G14 H16 T36 BG22 BG24 C22 AP13 M14 AP3 AP1 BE16 BC16 BG28 BJ28

D

E

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

PCH_GND

VCUAA

32 53Tuesday, October 16, 2012

E

1.0

of

A

B

C

D

E

SATA HDD Conn.

JHDD @JHDD @

1 1

26

boss

25

boss

24

GND

23

GND

2 2

GND

GND GND GND

GND GND

RX+

3.3V

1

SATA_PTX_C_DRX_P0

2

SATA_PTX_C_DRX_N0

3

RX-

4

SATA_PRX_DTX_N0

5

TX-

TX+

5V 5V

5V Rsv 12V

12V 12V

6 7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

SATA_PRX_DTX_P0

+5VS

12

10U_0805_6.3V6M

Close to JHDD

C369 0.01U_0402_25V7KC369 0.01U_0402_25V7K

1 2

C367 0.01U_0402_25V7KC367 0.01U_0402_25V7K

1 2

C368 0.01U_0402_25V7KC368 0.01U_0402_25V7K

1 2

C370 0.01U_0402_25V7KC370 0.01U_0402_25V7K

1 2

+5VS

Place closely JHDD SATA CONN.

1.2A

C356

reserve for HDD noise, place close to HDD connector

1

C357

0.1U_0402_10V7K

2

1

C371

0.1U_0402_10V7K

0.1U_0402_10V7K @

@

2

1

C358

0.1U_0402_10V7K

2

SATA_PTX_DRX_P0 <24>

SATA_PTX_DRX_N0 <24>

SATA_PRX_C_DTX_N0 <24> SATA_PRX_C_DTX_P0 <24>

1

C360

0.1U_0402_10V7K

0.1U_0402_10V7K @

@

2

1

C359

0.1U_0402_10V7K

2

3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

HDD

VCUAA

E

1.0

of

33 53Tuesday, October 16, 2012

of

33 53Tuesday, October 16, 2012

of

33 53Tuesday, October 16, 2012

A

JWLAN

1 3 5 7 9910 111112 131314 151516

171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

G153G254G355G4

+3V_WLAN

CM1

0.01U_0402_25V7K

CM7

0.01U_0402_25V7K

@JWLAN

@

2 4 6 8

BELLW_80060-1021

56

Slot 1 Half PCIe Mini Card-WLAN

+3V_WLAN+3VS

2

112

PJ6 JUMP_43X79@PJ6 JUMP_43X79@

Short for WIFI

1 1

PJ9 JUMP_43X79@PJ9 JUMP_43X79@

reserve for BT issue

+3V_WLAN

47P_0402_50V8J

2 2

+1.5VS

47P_0402_50V8J

+3V_WLAN+3VALW

2

112

1

BT_CTRL_RBT_CTRL

0_0402_5%

1 2

R1443

@ R1443

CLKREQ_WLAN#<25>

CLK_WLAN#<25> CLK_WLAN<25>

12

C266

C266 @

@

12

C260

C260 @

@

PCIE_PRX_WLANTX_N2<25> PCIE_PRX_WLANTX_P2<25>

PCIE_PTX_C_WLANRX_N2<25> PCIE_PTX_C_WLANRX_P2<25>

E51_TXD<40> E51_RXD<40>

WLAN/ WiFi

@

+3V_WLAN

R16 0_0402_5%

@

1 2 1 2

R17 0_0402_5%

E51_RXD_R

@

3 5 7

Debug card using

0.1U_0402_10V7K

1

CM2

2

+1.5VS

0.1U_0402_10V7K

1

CM8

2

2 4 6 8 10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

B

40 mils

1

CM3

2

4.7U_0805_10V4Z

1

CM9

2

4.7U_0805_10V4Z

+1.5VS

For SED

1

47P_0402_50V8J

2

1

2

+3V_WLAN

WLAN_OFF# PLT_RST#

12

C253

C253 @

@

For SED

12

C254

47P_0402_50V8J

@

BT_ON#<29>

EC_BT_ON#<40>

+3V_WLAN

RM17

8.2K_0402_5%

1 2

WLAN&BT Combo module circuits

BT_ON#

QM1A

0_0402_5%

1 2

R1444

0_0402_5%

1 2

R1445

For isolate Intel Rainbow Peak and Compal Debug Card.

WL_OFF# <40>

PLT_RST# <28,35,40,41,5>

PM_SMBCLK <11,12,25,41> PM_SMBDATA <11,12,25,41>

USB20_N9 <28> USB20_P9 <28>

QM1A

2

2N7002DW-T/R7_SOT363-6

@R1445

@

BT_CTRL

R327

1 2

1K_0402_5%

BT

61

SUSP<42,5,9>

E51_RXD_R

C

BT on module

Enable Disable

HLBT_CTRL

LH

BT_CTRL

2N7002DW-T/R7_SOT363-6

QM1B

3

5

4

D

Slot 2 Full PCIe Mini Card- mSATA

JMSATA

@JMSATA

1 3 5 7 9910 111112 131314 151516

171718 191920 212122 232324 252526 272728 292930 313132 333334 353536 373738 393940 414142 434344 454546 474748 494950 515152

G153G254G355G4

@

2

4

6

8

10 12 14 16

18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52

BELLW_80060-1021

56

SATA_PRX_DTX_P1 SATA_PRX_DTX_N1

SATA_PTX_C_DRX_N1 SATA_PTX_C_DRX_P1

+3VS

1 3 5 7

+3VS

SATA_PRX_DTX_P1

SATA_PTX_C_DRX_N1 SATA_PTX_C_DRX_P1

For RF

47P_0402_50V8J

12

CM18

680P_0402_50V7K

EMI request 8/7

CM21 0.01U_0402_25V7KCM21 0.01U_0402_25V7K

SATA_PRX_C_DTX_N1SATA_PRX_DTX_N1

1 2

SATA_PRX_C_DTX_P1

1 2

CM22 0.01U_0402_25V7KCM22 0.01U_0402_25V7K CM23 0.01U_0402_25V7KCM23 0.01U_0402_25V7K

SATA_PTX_DRX_N1

1 2

SATA_PTX_DRX_P1

1 2

CM24 0.01U_0402_25V7KCM24 0.01U_0402_25V7K

E

+3VS

0.1U_0402_10V7K

1

12

CM19

CM4

@

2

0.01U_0402_25V7K

120 mils

1

CM6

CM5

2

4.7U_0805_10V4Z

SATA_PRX_C_DTX_N1 <24> SATA_PRX_C_DTX_P1 <24>

SATA_PTX_DRX_N1 <24> SATA_PTX_DRX_P1 <24>

For SED

12

CM20

CM20 47P_0402_50V8J

47P_0402_50V8J @

@

+3VL

1

GCLK@

2

3 3

0.1U_0402_10V7K

+1.05VS_VCCP

1

GCLK@

2

0.1U_0402_10V7K

4 4

1

CCL4

CCL4 18P_0402_50V8J

18P_0402_50V8J GCLK@

GCLK@

2

+3V_LAN

CCL1

CCL3

1

CCL2

GCLK@

2

0.1U_0402_10V7K

+3VS_VDDIO

1

CCL6

GCLK@

2

0.1U_0402_10V7K

GCLK@

YCL1 25MHZ 12PF X3G025000DK1H-X

1

GND

2

+3VALW

+3VS_DGPU

VGA_PWROK#<42>

3

GND

4

A

1

CCL8

GCLK@

2

0.1U_0402_10V7K

CLK_X2CLK_X1

3

G304@

1 2

RCL4 0_0603_5%

AO3413_SOT23

D

S

D

S

13

G300@

QCL1

G

2

+1.05VS_VCCP

1

CCL5

CCL5 15P_0402_50V8J

15P_0402_50V8J

2

GCLK@

1

CCL7

2.2U_0402_6.3V6M

+RTCVCC_GCLK

14

9

12 6 5

2.2U_0402_6.3V6M GCLK@

GCLK@

2

PCH_RTCX1_R

VGA_X1_R

RCL3 22_0402_5%

LAN_X1_R_R

PCH_X1_R_R

PJ8

@

2 1

PAD-OPEN 2x2m

OPT@

1 2

22 ohm for NV chip

UCL1

UCL1 SLG3NB244VTR_TQFN16_2X3

SLG3NB244VTR_TQFN16_2X3 UMA@

UMA@ UCL1

UCL1 SLG3NB304VTR_TQFN16_2X3

SLG3NB304VTR_TQFN16_2X3 G304@

G304@

1

C16

22U_0805_6.3V6M

GCLK@

+RTCBATT +RTCVCC

+3VL

+3VALW

+3VS_VDDIO

+3V_LAN

CLK_X1 CLK_X2

SLG3NB300VTR_TQFN16_2X3

2

UCL1

10

VBAT

15

2

8 3 1

16

VDD_RTC_OUT +V3.3A VDD

VDDIO_27M1127MHz VDDIO_25M_A VDDIO_25M_B XTAL_IN

XTAL_OUT

4

GND1

7

G300@UCL1

G300@

32kHz

25MHz_A 25MHz_B

GND2

GND3

13

GND4

17

OPT UMA

300(default)

GCLK

B

SA00005RS00

304(low power)

244

SA000057I00

PCH_X1_RPCH_X1_R_R

GCLK@

1 2

RCL1 0_0402_5%

LAN_X1_R_R

RCL2 33_0402_5%

PCH_RTCX1_R <24>

VGA_X1 <13>

LAN_X1_R_R

RCL5 0_0402_5%

Reserved for Swing Level adjustment ( Close GCLK side )

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

GCLK@

1 2

@

1 2

LAN_X1_R

Compal Secret Data

PCH_X1_R <25>

1

2

Deciphered Date

LAN_X1_R <35>

CCL10

5P_0402_50V8C

GCLK@

EMI request 11/06

D

Title

Size Document Number Rev

Date: Sheet of

Date: Sheet

Compal Electronics, Inc.

PCIe-WLAN/mSATA/GCLK

VCUAA

Tuesday, October 16, 2012

E

of

34 53

1.0

A

CL1 0.1U_0402_10V7KCL1 0.1U_0402_10V7K

PCIE_PRX_C_LANTX_P1<25>

PCIE_PRX_C_LANTX_N1<25>

12

1K_0402_5%

1K_0402_5% RL6

RL6 @

@

RL7

15K_0402_5%

LAN_EN

CLKREQ_LAN#

2N7002KW_SOT323-3

12

@

1 2

RL433 0_0402_5%

LAN_EN<25>

CLKREQ_LAN#<25>

1 1

+3VS

RL24 10K_0402_5%RL24 10K_0402_5%

+3V_LAN

RL25 10K_0402_5%@RL25 10K_0402_5%@

+3VS

2 2

WOL_EN#

2

G

1 3

D

QL53

LANCLK_REQ#

EC_SWI#

Sx Enable Wake up

LOW

WOL_EN#ISOLATE#

+3VALW TO +3V_LAN

Vgs=-4.5V,Id=3A,Rds<97mohm

+3VALW

12

RL147

RL147 100K_0402_5%

100K_0402_5% @

@

RL432

@RL432

@

WOL_EN#<40>

3 3

1 2

47K_0402_5%

2

CL483

CL483 @

@

0.1U_0402_10V7K

1

2

@

@ CL482

CL482

0.01U_0402_25V7K

1

4.7U_0805_10V4Z

1 2

CL2 0.1U_0402_10V7KCL2 0.1U_0402_10V7K

1 2

PCIE_PTX_C_LANRX_P1<25> PCIE_PTX_C_LANRX_N1<25>

@

CL681

QL51

2

+3VALW

G

@

LANCLK_REQ#

PLT_RST#<28,34,40,41,5>

CLK_LAN<25> CLK_LAN#<25>

EC_SWI#<26>

S0

HIGH

S

D

1 3

1

2

S

Sx Disable Wake up

HIGH

AO3413_SOT23

1 2

RL5 2.49K_0402_1%RL5 2.49K_0402_1%

RTL8105ENCRTL8111E/F Pin14 Pin15 Pin38

Reserve +3VALW_PCH to +3V_LAN for saving power consumption on DVT

21

PJ29

@

PAD-OPEN 2x2m

2

1

+3V_LAN rising time (10%~90%) need > 1ms and <100ms.

LAN WOL LAN_EN ISOLATEB S0 Sx S0 Sx

--------------------------------------------- 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0*

4 4

* S3: after SUSP# assert low over 100ms

B

PCIE_PRX_LANTX_P1 PCIE_PRX_LANTX_N1 PCIE_PTX_C_LANRX_P1

PCIE_PTX_C_LANRX_N1

PLT_RST# CLK_LAN

CLK_LAN#

LAN_X1 LAN_X2

EC_SWI# ISOLATE#

NC 10K ohm PD NC 1K ohm PH

+3VALW_PCH

21

PJ7

@

+3V_LAN

PAD-OPEN 2x2m

CL682

CL682 1U_0402_6.3V6K

1U_0402_6.3V6K

UL1

22

HSOP

23

HSON

17

HSIP

18

HSIN

16

CLKREQB

25

PERSTB

19

REFCLK_P

20

REFCLK_N

43

CKXTAL1

44

CKXTAL2

28

LANWAKEB

26

ISOLATEB

14

SMBCLK(NC)

15

SMBDATA(NC)

38

GPO/SMBALERT

33

ENSWREG

34

VDDREG

35

VDDREG

46

RSET

24

GND

49

GND

RTL8105E-GR_QFN48_6X6

NC

RTL8105E/8111E

1

CL26

CL26 27P_0402_50V8J

27P_0402_50V8J NOGCLK@

NOGCLK@

2

1

CL34

0.1U_0402_25V6

2

Place CL34 colse to LAN chip

LED3/EEDO LED1/EESK

LED0

EECS/SCL

EEDI/SDA

MDIP0 MDIN0 MDIP1

MDIN1 MDIP2(NC) MDIN2(NC) MDIP3(NC) MDIN3(NC)

DVDD10 DVDD10 DVDD10

DVDD33 DVDD33

AVDD33 AVDD33 AVDD33 AVDD33

EVDD10 AVDD10

AVDD10 AVDD10 AVDD10

REGOUT

1

LAN_MDI0+ LAN_MDI0-

LAN_MDI1+ LAN_MDI1-

31 37 40

RL2 10K_0402_5%

30

RL1 10K_0402_5%

32

LAN_MDI0+

1

LAN_MDI0-

2

LAN_MDI1+

4

LAN_MDI1-

5 7 8 10 11

13

+LAN_VDD10

29 41

27

+3V_LAN

39 12

+3V_LAN

42 47 48

21

+LAN_EVDD10

3

+LAN_VDD10

6 9 45

36

C

TL1PAD TL1PAD TL2PAD TL2PAD

@

TL3PAD TL3PAD

12 12

@

1 2

LL2 0_0603_5%

1U_0402_6.3V6K

CL18

1

2

Close to Pin 21

Placement near to YL1

GCLK@

1 2

0_0402_5%

LAN_X1_R<34>

CL43 10P_0402_50V8J

1 2

RL29 22_0402_5%

GCLK@

RL8

+LAN_EVDD10+LAN_VDD10

GCLK@RL8

GCLK@

D

1

CL17

0.1U_0402_10V7K

2

LAN_X2

+3V_LAN

+LAN_VDD10

E

CL3 to CL6 close to Pin 27,39,47,48 CL7 to CL8 close to Pin 12,42

1 2

CL3 0.1U_0402_10V7KCL3 0.1U_0402_10V7K

1 2

CL4 0.1U_0402_10V7KCL4 0.1U_0402_10V7K

1 2

CL5 0.1U_0402_10V7KCL5 0.1U_0402_10V7K

1 2

CL6 0.1U_0402_10V7KCL6 0.1U_0402_10V7K

CL19, CL20,CL21 close to pin 13,29,45, respectively CL22 close to pin 3, respectively CL23,CL24,CL25 close to pin 6,9,41, respectively

1 2

CL19 0.1U_0402_10V7KCL19 0.1U_0402_10V7K

1 2

CL20 0.1U_0402_10V7KCL20 0.1U_0402_10V7K

1 2

CL21 0.1U_0402_10V7KCL21 0.1U_0402_10V7K

EMI request 11/06

8105E-VL/VD 8111F/F-VB

YL1 25MHZ_20PF_7V25000016NOGCLK@ YL1 25MHZ_20PF_7V25000016NOGCLK@

GND

2

3

4

27P_0402_50V8J

LAN_X2LAN_X1

3

NOGCLK@

CL27

1

2

PWM Mode

RL4

0 ohm (Pull High)

NC 0 ohm

RL23

8105E-VL/VD

LDO Mode

NC

(Pull Down)

LAN Conn.

JLAN

8

UL3

1

TD+

2

TD-

3

CT

4

NC

5

NC

6

CT

7

RD+ RD-8RX-

10/100M transformer_NS681695

SP050006N00

TX+

RX+

16 15

TX-

14

CT

13

NC

12

NC

11

CT

10 9

RJ45_MIDI0+ RJ45_MIDI0-

RJ45_MIDI1+ RJ45_MIDI1-

CL39 1000P_0402_50V7KCL39 1000P_0402_50V7K

12

1 2

CL40 1000P_0402_50V7KCL40 1000P_0402_50V7K

RL11 75_0402_1%RL11 75_0402_1%

12

1 2

RL12 75_0402_1%RL12 75_0402_1%

RJ45_MIDI1-

RJ45_MIDI1+ RJ45_MIDI0RJ45_MIDI0+

RJ45_GND

1 2

CL36 1000P_1808_3KV7KCL36 1000P_1808_3KV7K

PR4-

7

PR4+

6

PR2-

5

PR3-

4

PR3+

3

PR2+

2

PR1-

1

PR1+

SANTA_130456-031

1

CL37

CL37 220P_0402_50V6K

220P_0402_50V6K

2

10

GND

9

GND

@

LANGND

1

CL38

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M @

@

2

3

D93

223

AZC199-02SPR7G_SOT23-3

1

For ESD

S4/S5: after SYSON assert low over 100ms

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

PCIe-LAN-RTL8105E

VCUAA

E

1.0

of

35 53Tuesday, October 16, 2012

5

4

3

2

1

Close to IC

D D

C C

USB20_P3<28>

USB20_N3<28>

RW1 0_0402_5%RW1 0_0402_5% @ LR4

@

2

3

WCM-2012-900T_0805

RW3 0_0402_5%RW3 0_0402_5%

12

LR4

1

4

12

USB20_P3_R

1

4

USB20_N3_R

+3VS

FAE recommand

4.7U_0402_6.3V6M

1

CW3

CW3 @

@

2

1

CW1

2

0.1U_0402_10V7K

1 2

CW2 100P_0402_50V8J@CW2 100P_0402_50V8J@

RW2

6.19K_0402_1%

+VCC_3IN1

1

2

12

USB20_N3_R USB20_P3_R

CW7

CW7 1U_0402_6.3V6K

1U_0402_6.3V6K

SDWP_MSCLK

SD_DATA0

+V1_8

1 2

3 4

5 6

7 8

9 10 11 12

UW1

REFE DM

DP 3V3_IN

CARD_3V3 V18

XD_CD# SP1

SP2 SP3 SP4 SP5

GPIO0

CLK_IN

XD_D7

SP14 SP13 SP12 SP11 SP10

SP9 SP8 SP7 SP6

EPAD

RTS5137-GR_QFN24_4X4

25

For EMI request

CLK_48M_CR

17

CLK_48M_CR

24 23 22

SD_DATA2_MS_DATA5

21

MS_DATA1_SD_DATA3

20 19

SDCMD

18 16

MS_DATA2_SDCLKSD_DATA1

15 14

SDCD#

13

RW6 10_0402_5%@RW6 10_0402_5%@

1 2

CLK_48M_CR <25>

CW10 10P_0402_50V8J@CW10 10P_0402_50V8J@

1 2

< 48MHz >

< 2 in 1 Card Reader >

JCARD

12

G1

13

B B

G2

TAITW_PSDAT0-09GLBS1ZZ4H1

DAT3

CMD

VSS1

VDD

CLK VSS2 DAT0 DAT1 DAT2

@JCARD

@

CD

WP

MS_DATA1_SD_DATA3

1

SDCMD

2 3 4

MS_DATA2_SDCLK

5 6

SD_DATA0

7

SD_DATA1

8

SD_DATA2_MS_DATA5

9

SDCD#

10

SDWP_MSCLK

11

1

CW6

0.1U_0402_16V4Z

2

+VCC_3IN1

1

CW5

CW5 1U_0402_6.3V6K

1U_0402_6.3V6K

2

For EMI request

MS_DATA2_SDCLK

SDWP_MSCLK

A A

5

4

RW4 10_0402_5%@RW4 10_0402_5%@

RW5 10_0402_5%@RW5 10_0402_5%@

1 2

CW8 6.8P_0402_50V8C@CW8 6.8P_0402_50V8C@

1 2

CW9 6.8P_0402_50V8C@CW9 6.8P_0402_50V8C@

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

3

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

USB-CardReader RTS5137

VCUAA

36 53Tuesday, October 16, 2012

1

of

1.0

5

4

3

2

1

Left USB 2.0 x 1 Right side USB 3.0 x 2/ Sleep&Charge

OUT OUT OUT OCB

1

CR1

CR2

2

22U_0805_6.3V6M

SLP_CHG_M4 <28> USB20_N1 <28> USB20_P1 <28>

W=60mils

+USB_VCCC

6

CR38 1000P_0402_50V7KCR38 1000P_0402_50V7K

7 8 5

1

CR39

4.7U_0805_10V4Z

2

+USB_VCCC

1

2

220U_6.3V_M

Co-lay OSCON

1

+

CR40

@+CR40

@

2

12

For EMI

USB_OC#2 <28,40>

W=80mils

4.7U_0805_10V4Z

1

CR46

@

2

1000P_0402_50V7K

USB20_P0_R USB20_N0_R

USB20_P1_R USB20_N1_R

0.1U_0402_10V7K

1

CR45

2

@D85

@ 2

3

@D86

@ 2

3

1

CR44

2

USB_CHG_EN#<40>

USB20_P0<28>

USB20_N0<28>

D85

2

1

3

AZC199-02SPR7G_SOT23-3

D86

2

1

3

AZC199-02SPR7G_SOT23-3

2.0A

U15

2

U14

IN

OUT

IN

OUT

EN/ENB

OUT

GND

OCB

SY6288DCAC_MSOP8

SA00004KB00 SA00003TV00

@ RR31

@

1 2

LR7

2

3

WCM-2012-900T_0805

1 2

@ RR48

@

1 2

LR8

2

3

WCM-2012-900T_0805

1 2

U3TXDP1_C_L U3TXDN1_C_L U3RXDP1_L U3RXDN1_L

3 4 1

SY6288DCAC_MSOP8

SA00004KB00 SA00003TV00

6 7 8 5

0_0402_5%

0_0402_5%@

USB_EN#0<40>

USB_EN#0

2.0A

2

USB_CHG_EN#

3 4 1

USB20_P0 USB20_P0_R

USB20_N0

USB20_P1_S USB20_P1_R

USB20_N1_S

USB Sleep & Charge Auto-Mode/Mode3

MAX14600 & MAX14617 CB0

SLP_CHG_M4

0

1

11

XX1

IN

OUT

IN

OUT

EN/ENB

OUT

GND

OCB

W=80mils

+USB_VCCA+5VALW

C361 1000P_0402_50V7KC361 1000P_0402_50V7K

1

C362

4.7U_0805_10V4Z

2

@

RR31

1

4

RR30

RR48

0_0402_5%

1

4

RR47

D87

1

2

4

4 5

3

8

YSCLAMP0524P_SLP2510P8-10-9

W=80mils

+USB_VCCB+5VALW

6 7 8 5

12

USB_OC#1 <28,40>

USB20_N0_R

USB20_N1_R

1

2

For EMI

@

CB1 SLP_CHG_M3

0

1

0

For EMI

12

C363 1000P_0402_50V7KC363 1000P_0402_50V7K

USB_OC#0 <28,40>

C364

4.7U_0805_10V4Z

4.7U_0805_10V4Z @

@

U3TXDP1_C_L

10

9

U3TXDN1_C_L

9

8

U3RXDP1_L

7

U3RXDN1_L

65

6

CB2 (14617 only)

0

STATUS

AUTO MODE Force Dedicated charger mode

(MODE3) Pass-Through (USB) Mode:

Connect DP/DM to TDP/TDM Pass-Through (USB) Mode with CDP Emulation:

Auto Connect DP/DM to TDP/TDM depending on CDP status

Force Apple 2A Charger Mode: Apple 2A resistor dividers

+USB_VCCB

USB20_N0_R USB20_P0_R

U3RXDN1_L U3RXDP1_L

U3TXDN1_C_L U3TXDP1_C_L

+USB_VCCA

USB20_N1_R USB20_P1_R

U3RXDN2_L U3RXDP2_L

U3TXDN2_C_L U3TXDP2_C_L

D88

U3TXDP2_C_L U3TXDN2_C_L U3RXDP2_L U3RXDN2_L

D88 1

1

2

4

4 5

3

8

YSCLAMP0524P_SLP2510P8-10-9

+USB_VCCB

1

+

2

220U_6.3V_M

+USB_VCCA

1

+

2

220U_6.3V_M

@

10

10 9

9 7

7 65

65

W=80mils

0.1U_0402_10V7K

C900

W=80mils

0.1U_0402_10V7K

C897

1 2 3 4 5 6 7 8 9

U3TXDP2_C_L

9

U3TXDN2_C_L

8

U3RXDP2_L

7

U3RXDN2_L

6

4.7U_0805_10V4Z

1

C901

C902

2

1000P_0402_50V7K

4.7U_0805_10V4Z

1

C899

C898

2

1000P_0402_50V7K

JUSBRF

VBUS DD+ GND StdA-SSRXStdA-SSRX+

GND

GND-DRAIN

GND

StdA-SSTX-

GND

StdA-SSTX+

GND

LOTES_AUSB0015-P001A

JUSBRR

VBUS DD+ GND StdA-SSRXStdA-SSRX+

GND

GND-DRAIN

GND

StdA-SSTX-

GND

StdA-SSTX+

GND

LOTES_AUSB0015-P001A

1

C366

C366 @

@

2

1

C365

C365 @

@

2

@JUSBRF

@

10 11 12 13

@JUSBRR

@

10 11 12 13

+5VALW

1

CR4

CR5

2

22U_0805_6.3V6M

U3RXDP1_L

U3RXDN1_L

U3TXDP1_C_LU3TXDP1_C

U3TXDN1_C_L

U3RXDP2_L

U3RXDN2_L

U3TXDP2_C_LU3TXDP2_C

U3TXDN2_C_L

1

C892

0.1U_0402_10V7K

0.1U_0402_10V7K 2

2.0A

U13

2

IN

3

IN

4

EN/ENB

1

GND

SY6288DCAC_MSOP8

SA00004KB00 SA00003TV00

1

CR3

2

22U_0805_6.3V6M

+5VALW

USB20_P2<28>

USB20_N2<28>

D D

C C

B B

A A

USB20_P2

USB20_P2_L USB20_N2_L

RR26

1 2

0_0402_5%

2

3

WCM-2012-900T_0805

RR25

1 2

0_0402_5% @

DR1

@

2

1

3

AZC199-02SPR7G_SOT23-3

U3TXDP1<28>

U3TXDN1<28>

U3TXDP2<28>

U3TXDN2<28>

@RR26

@

LR3

1

4

+USB_VCCC

U5

1

4

USB20_P2_L

USB20_N2_LUSB20_N2

USB20_N2_L USB20_P2_L

U3TXDP1

U3TXDN1

U3TXDP2

U3TXDN2

SLP_CHG_M3<28>

14617@U5

14617@

U3RXDP1<28>

U3RXDN1<28>

1 2

C903 0.1U_0402_10V7KC903 0.1U_0402_10V7K

1 2

C904 0.1U_0402_10V7KC904 0.1U_0402_10V7K

U3RXDP2<28>

U3RXDN2<28>

1 2

C905 0.1U_0402_10V7KC905 0.1U_0402_10V7K

1 2

C906 0.1U_0402_10V7KC906 0.1U_0402_10V7K

14617@

1 2

R1470

0_0402_5%

JUSBL

1

VBUS

G1

2

D-

G2

3

D+

G3

4

GND

G4

ACON_UARC9-4K1986

U3TXDN1_C

U3TXDN2_C

SLP_CHG_CB2 USB20_N1_S USB20_P1_S SLP_CHG_M3

USB_EN#2<40>

5 6 7 8

KINGCORE WCM-2012HS-670T

1

4

L56

KINGCORE WCM-2012HS-670T

1

4

L60

KINGCORE WCM-2012HS-670T

1

4

L58

KINGCORE WCM-2012HS-670T

1

4

L59

U5

1

CEN

2

DM

3

DP

4

CB1

9

PGND

MAX14600ETA+T_TDFN-EP8_2X2

MAX14600ETA+T_TDFN-EP8_2X2 14600@

14600@

1

CR7

CR8

2

22U_0805_6.3V6M

@ R1448

@

1 2

1

4

1 2

@ R1450

@

1 2

1

4

1 2

@ R1452

@

1 2

1

4

1 2

@ R1454

@

1 2

1

4

1 2

CB0

TDM

TDP

VCC

USB_EN#2

1

CR6

2

22U_0805_6.3V6M

R1448

0_0402_5%

2

3

R1449

0_0402_5%@

R1450

0_0402_5%

2

3

R1451

0_0402_5%@

R1452

0_0402_5%

2

3

R1453

0_0402_5%@

R1454

0_0402_5%

2

3

R1455

0_0402_5%@

8 7 6 5

1

2

22U_0805_6.3V6M

2

3

2

3

2

3

2

3

SLP_CHG_M4 USB20_N1 USB20_P1

MAX14617ETA+T

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

2

Compal Electronics, Inc.

Title

LUSB/RUSB/S&C

Size Document Number Rev

Custom

Date: Sheet

VCUAA

1

37 53Tuesday, October 16, 2012

of

1.0

A

MIC1_R_R MIC1_R_L

1 1

0.01U_0402_25V7K

0.01U_0402_25V7K CA65

@CA65

@

AZ_RST_HD#<24>

1 2

1 2 1 2

+MIC1_VREFO_L +MIC1_VREFO_R

1 2

CA59 100P_0402_50V8JCA59 100P_0402_50V8J

AZ_SYNC_HD<24>

close to pin 28

CA6010U_0603_6.3V6M CA6010U_0603_6.3V6M

1 2

AC_VREF

1

CA56

2

INT_MIC_CLK<22>

CA56

2.2U_0402_6.3V6M

2.2U_0402_6.3V6M @

@

2

RA34 20K_0402_1%

INT_MIC_DATA<22>

@

12

EC_MUTE#<40>

For EMI

RA42

FBMA-10-100505-301T

1

2

INT_MIC_CLK_R

CAM@

CA52

CAM@CA52

CAM@

220P_0402_50V7K

change to SM010027780

CA55

0.1U_0402_10V7K

2 2

3 3

MIC1_R_C_R

CA584.7U_0402_6.3V6M CA584.7U_0402_6.3V6M

MIC1_R_C_L

CA574.7U_0402_6.3V6M CA574.7U_0402_6.3V6M

MONO_IN

close to pin19

AC_JDREF

RA30

12

20K_0402_1%

CPVEE

1 2

CA54 2.2U_0402_6.3V6MCA54 2.2U_0402_6.3V6M

1 2

CA53 2.2U_0402_6.3V6MCA53 2.2U_0402_6.3V6M

INT_MIC_CLK_R

SENSE_A SENSE_B

22 21

17 16

31 30 29

15 14

20 12 10 11

19 28 27 34 35 36

2 3

13 18

47

4

B

UA1

MIC1_R MIC1_L

MIC2_R MIC2_L

MIC1_VREFO_L MIC1_VREFO_R MIC2_VREFO

LINE2_R LINE2_L

MONO_OUT PCBEEP SYNC RESET#

JDREF LDO_CAP VREF CPVEE CBN CBP

GPIO0/DMIC_DATA GPIO1/DMIC_CLK

SENSE_A SENSE_B

EAPD PD#

ALC259-VC2-CG_MQFN48_6X6

DVDD_IO

AVDD1 AVDD2

PVDD1 PVDD2

SPK_OUT_R+

SPK_OUT_R-

SPK_OUT_L+

SPK_OUT_L-

HPOUT_R HPOUT_L

SDATA_OUT

SDATA_IN

Thermal Pad

DVDD

BCLK

AVSS1 AVSS2 PVSS1 PVSS2

DVSS

NC NC NC

1 9

25 38

39 46

45 44

40 41

RA19

33

RA20

32

5

AZ_SDIN0_HD_R

8 6

23 24 48

26 37 42 43 7

49

+DVDD_IO +3VS_DVDD

+AVDD +AVDD

+PVDD +PVDD

SPKR+ SPKR-

SPKL+ SPKL-

75_0402_1%

AZ_BITCLK_HD

DGND

HP_R <39> HP_L <39>

RA23 33_0402_5%RA23 33_0402_5%

AZ_BITCLK_HD

@

AGND

2W 4ohm =40mil 1W 8ohm =20mil

SPKL+

SPKL-

SPKR+

SPKR-

C

35mA for 3.3V level

@

1 2

+3VS

RA28 0_0603_5%

@

1 2

+3VS

RA17 0_0603_5%

place close to chip

12

RA2910_0402_5%@RA2910_0402_5%

10P_0402_50V8J

0_0603_5%

AZ_SDOUT_HD <24>

AZ_SDIN0_HD <24> AZ_BITCLK_HD <24>

CA51

@

1 2

placement near Audio Codec

LA7

12

2 CA71

CA71

1000P_0603_50V7K

1 2

CA72

LA8

1000P_0603_50V7K

1

12

LA9

12

2 CA76

CA76

1000P_0603_50V7K

1 2

CA75

LA10

1000P_0603_50V7K

1

12

0.1U_0402_16V4Z

CA4

CA3

CA3 10U_0805_6.3V6M

10U_0805_6.3V6M

0.1U_0402_16V4Z

CA45

CA46

CA46 10U_0805_6.3V6M

10U_0805_6.3V6M

1

2

1

2

SPK_L1 <39>

SPK_L2 <39>

SPK_R1 <39>

SPK_R2 <39>

12

For EMI please place near codec

SPK_L1

2

CA74

CA74 1U_0402_6.3V4Z

1U_0402_6.3V4Z @

@

1

SPK_L2

SPK_R1

2

CA73

CA73 1U_0402_6.3V4Z

1U_0402_6.3V4Z @

@

1

SPK_R2

+DVDD_IO

+3VS_DVDD

D

+AVDD

1

CA33 0.1U_0402_10V7KCA33 0.1U_0402_10V7K

close to pin39

2

1

CA32 0.1U_0402_10V7KCA32 0.1U_0402_10V7K

2

PCI Beep

PCH_SPKR<24>

EC_MUTE#

To solve noise issue

close to pin 25 close to pin 38

0.1U_0402_10V7K

2

CA42

CA47

1

10U_0603_6.3V6M

+PVDD

EC_MUTE#

Hight LOW

CA48

Internal AMP

Enable Disable

RA50

4.7K_0402_5%

1 2

2

1 10U_0603_6.3V6M

10U_0603_6.3V6M

Ext.MIC/LINE IN JACK

MIC1_R_R

MIC1_R_L

1

2

CA50

CA37

2

1

10U_0603_6.3V6M

LA11

1 2

PBY160808T-601Y-N_2P

RA52

1 2 47K_0402_5%

47K_0402_5%

RA49

4.7K_0402_5%

RA47

RA48 2.2K_0402_5%RA48 2.2K_0402_5%

1K_0402_5%

12

1K_0402_5%

RA45

RA46 2.2K_0402_5%RA46 2.2K_0402_5%

0.1U_0402_10V7K

0.1U_0402_10V7K 1

2

0.1U_0402_10V7K

0.1U_0402_10V7K 1

CA44

2

1 2

12

E

@

1 2

RA18 0_0603_5%

1

CA39

@

10U_0603_6.3V6M

2

650mA

+5VS

12

CA36

CA36 10U_0805_6.3V6M

10U_0805_6.3V6M

Beep sound

CA70

MONO_IN

1 2

0.1U_0402_10V7K

CA69

100P_0402_50V8J

+MIC1_VREFO_R

MIC1_R <39>

MIC1_L <39>

+MIC1_VREFO_L

+5VS

EMI request

Sense Pin

SENSE A

4 4

Impedance

39.2K 20K 10K

5.1K

39.2K 20K 10K

A

Codec Signals

PORT-I (PIN 32, 33) PORT-B (PIN 21, 22) PORT-C (PIN 23, 24) (PIN 48) PORT-E (PIN 14, 15) PORT-F (PIN 16, 17)SENSE B PORT-H (PIN 20)

Function

Headphone out Ext. MIC

B

place close to chip

MIC_SENSE<39>

NBA_PLUG<39>

RA32 20K_0402_1%RA32 20K_0402_1%

RA33 39.2K_0402_1%RA33 39.2K_0402_1%

CA63 0.1U_0603_50V7KCA63 0.1U_0603_50V7K

SENSE_A

12

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

1 2

CA61 0.1U_0603_50V7KCA61 0.1U_0603_50V7K

1 2

CA66 0.1U_0603_50V7KCA66 0.1U_0603_50V7K

1 2

CA62 0.1U_0603_50V7KCA62 0.1U_0603_50V7K

1 2

RA31 0_0603_5%RA31 0_0603_5%

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

HDA-ALC259-VC

38 53Tuesday, October 16, 2012

E

of

HeadPhone/LINE OUT JACK

LA12

HP_L<38>

HP_R<38>

NBA_PLUG<38>

1 2

CHILISIN PBY100505T-121Y-N 0402

LA6

1 2

CHILISIN PBY100505T-121Y-N 0402

1

DA3

@DA3

@

PJDLC05_SOT23-3

EXT.MIC/LINE IN JACK

LA14

MIC1_L<38>

MIC1_R<38>

MIC_SENSE<38>

1 2

CHILISIN PBY100505T-121Y-N 0402

LA13

1 2

CHILISIN PBY100505T-121Y-N 0402

1

DA4

@DA4

@

PJDLC05_SOT23-3

3 2

HP_L_L

HP_R_L

3 2

MIC1_L_L

MIC1_L_R

CA38

100P_0402_50V8J

CA35

100P_0402_50V8J

CA40

100P_0402_50V8J

For EMI

CA41

100P_0402_50V8J

For EMI

1

CA34

@CA34

@

2

0.1U_0402_10V7K

1

CA43

@CA43

@

2

0.1U_0402_10V7K

JLINE

8 7 3 1 4 2

5 6

SINGA_2SJ2285-001191

JEXMIC

8 7 3 1 4 2

5 6

SINGA_2SJ2285-001191

@JLINE

@

@JEXMIC

@

SPK CONN.

@

@ DA5 PJDLC05_SOT23-3

DA5 PJDLC05_SOT23-3

1

SPK_L1<38> SPK_L2<38> SPK_R1<38> SPK_R2<38>

PJDLC05_SOT23-3

1

DA6

DA6 @

@

3 2

JSPK

@JSPK

@

6

GND2

5

GND1

4

3

2

1

E-T_3806K-F04N-03R

Security Classification

2012/04/19 2015/04/19

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

AUDIO CONN

Tuesday, October 16, 2012

of

39 53

of

39 53

of

39 53

1.0

A

0.1U_0402_10V7K

1

CB1

0.1U_0402_10V7K

KSI[0..7]<41>

KSO[0..15]<41>

PM_PWROK_EC

0.1U_0402_10V7K

1 2

5

UB2

P

B

Y

A

G

TC7SH08FUF_SSOP5

3

@

1 2

0.1U_0402_10V7K

CB17

SLP_S5#SLP_S5#

4

2

KSI[0..7] KSO[0..15]

EC_ON_R

GATEA20<29>

KB_RST#<29>

SERIRQ<24>

LPC_FRAME#<24,41>

LPC_AD3<24,41> LPC_AD2<24,41> LPC_AD1<24,41> LPC_AD0<24,41>

CLK_PCI_EC<28>

PLT_RST#<28,34,35,41,5> EC_SCI#<29>

EC_SMB_CK1<43,44> EC_SMB_DA1<43,44> EC_SMB_CK2<13,25> EC_SMB_DA2<13,25>

PM_SLP_S3#<26>

USB_OC#2<28,37>

USB_OC#1<28,37> USB_CHG_EN#<37> USB_EN#2<37>

FAN_SPEED1<5>

WL_OFF#<34>

PWR_ON_LED#<41>

For EMI

CLK_PCI_EC

12

RB3

10_0402_5%

@

1 1

+3VL

2 2

+3VL

+3VS

PM_PWROK<26,5>

3 3

Close to EC

PM_SLP_S5#<26> PM_SLP_S4#<26>

@

1

CB11

22P_0402_50V8J

@

2

RB2

47K_0402_5%

1 2

CB12 0.1U_0402_10V7KCB12 0.1U_0402_10V7K

RB12 2.2K_0402_5%RB12 2.2K_0402_5%

RB13 2.2K_0402_5%RB13 2.2K_0402_5% RB15 2.2K_0402_5%RB15 2.2K_0402_5%

RB16 2.2K_0402_5%RB16 2.2K_0402_5%

@

1 2

CB14 180P_0402_50V8J

EC_SMB_CK1

1 2

EC_SMB_DA1

1 2

EC_SMB_CK2

1 2

EC_SMB_DA2

1 2

RB32 0_0402_5%

SUSP#

1 2

EC_RST#

@

+3VALW

RB25 0_0402_5%

1 CB2

CB2

CB4

2

0.1U_0402_10V7K

EC_SMI#<29>

KB_LED<41>

E51_TXD<34> E51_RXD<34>

CLK_EC<26>

RB36

1 2

2.2K_0402_5%

0.1U_0402_10V7K

1

2

EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2

100K_0402_5%

1 CB5

CB5

2

1000P_0402_50V7K

GATEA20 KB_RST# SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0

CLK_PCI_EC PLT_RST# EC_RST# EC_SCI#

KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6

KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9

KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

PM_SLP_S3# SLP_S5# EC_SMI# USB_OC#2 USB_OC#1 USB_CHG_EN# USB_EN#2 KB_LED FAN_SPEED1 WL_OFF# E51_TXD E51_RXD PM_PWROK_EC PWR_ON_LED#

CLK_EC

12

RB22

1

1U_0402_6.3V6K

1U_0402_6.3V6K CB50

CB50

2

B

1000P_0402_50V7K

1

CB6

CB6 2

UB1

1 2 3 4 5 7 8

10 12

13 37 20 38

55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82

77 78 79 80

6 14 15 16 17 18 19 25 28 29 30 31 32 34 36

122 123

1

CB16

CB16 20P_0402_50V8

20P_0402_50V8

2

EC_ON <45>

+3VL

1 CB7

CB7

2

GATEA20/GPIO00 KBRST#/GPIO01 SERIRQ LPC_FRAME# LPC_AD3 LPC_AD2 LPC_AD1

LPC & MISC

LPC_AD0 CLK_PCI_EC

PCIRST#/GPIO05 EC_RST# EC_SCII#/GPIO0E GPIO1D

KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24

Int. K/B

KSO5/GPIO25

Matrix

KSO6/GPIO26 KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49

EC_SMB_CK1/GPIO44 EC_SMB_DA1/GPIO45 EC_SMB_CK2/GPIO46 EC_SMB_DA2/GPIO47

PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 GPIO0A GPIO0B GPIO0C GPIO0D EC_INVT_PWM/GPIO11 FAN_SPEED1/GPIO14 EC_PME#/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 PCH_PWROK/GPIO18 SUSP_LED#/GPIO19 NUM_LED#/GPIO1A

XCLKI/GPIO5D XCLKO/GPIO5E

9

22

33

96

EC_VDD/VCC

PWM Output

DA Output

PS2 Interface

SPI Device Interface

SPI Flash ROM

SM Bus

GPIO

GND/GND

11

24

35

+3VL

CB3

0.1U_0402_10V7K

1 2

111

125

67

EC_VDD0

EC_VDD/VCC

BEEP#/GPIO10

EC_VDD/AVCC

ACOFF/GPIO13

BATT_TEMP/GPIO38

AD Input

CPU1.5V_S3_GATE/GPXIOA00

GPIO

GND/GND

GND0

94

113

ADP_I/GPIO3A

IMON/GPIO43

DAC_BRIG/GPIO3C EN_DFAN1/GPIO3D

CHGVADJ/GPIO3F

EC_MUTE#/GPIO4A

USB_EN#/GPIO4B

CAP_INT#/GPIO4C

EAPD/GPIO4D

TP_CLK/GPIO4E

TP_DATA/GPIO4F

WOL_EN/GPXIOA01

ME_EN/GPXIOA02

VCIN0_PH/GPXIOD00

SPIDI/GPIO5B

SPIDO/GPIO5C SPICLK/GPIO58 SPICS#/GPIO5A

ENBKL/GPIO40

PECI_KB930/GPIO41

FSTCHG/GPIO50

BATT_CHG_LED#/GPIO52

CAPS_LED#/GPIO53

PWR_LED#/GPIO54

BATT_LOW_LED#/GPIO55

SYSON/GPIO56 VR_ON/GPIO57

PM_SLP_S4#/GPIO59

EC_RSMRST#/GPXIOA03 EC_LID_OUT#/GPXIOA04

PROCHOT_IN/GPXIOA05

H_PROCHOT#_EC/GPXIOA06

VCOUT0_PH/GPXIOA07

GPO

BKOFF#/GPXIOA08

PBTN_OUT#/GPXIOA09

PCH_APWROK/GPXIOA10

SA_PGOOD/GPXIOA11

AC_IN/GPXIOD01

EC_ON/GPXIOD02

ON/OFF/GPXIOD03

GPI

LID_SW#/GPXIOD04

SUSP#/GPXIOD05

PECI_KB9012/GPXIOD07

AGND/AGND

KB9012QF-A3_LQFP128_14X14

69

GPIO0F GPIO12

GPIO39 GPIO3B

GPIO42

IREF/GPIO3E

GPXIOD06

V18R

C

WL_BT_LED#

21 23

FANPWM

26 27

BATT_TEMPA

63 64

ADP_I

65

ADP_V

66

MOS_TEMP

75

EC_ENBKL

76

WOL_EN#

68

3VALW_EN

70

PCH_SUSPWRDN#

71

SUSACK#

72

EC_MUTE#

83

USB_EN#0

84 85 86

TP_CLK

87

TP_DATA

88

VGATE

97

EC_DRAMRST_CNTRL_PCH

98

PWRME_CTRL

99

VCIN0_PH

109

119

EC_BT_ON#

120

GPS_DOWN#

126 128

73 74 89

BATT_FULL_LED#

90

CAPS_LED#

91

PWR_SUSP_LED#

92

BATT_CHG_LOW_LED#

93

SYSON

95

VR_ON

121

USB_OC#0

127

PCH_RSMRST#

100

EC_LID_OUT#

101

PROCHOT_IN

102

H_PROCHOT#_EC

103

VCOUT0_PH_L

104

BKOFF#

105

PBTN_OUT#

106

PCH_PWR_EN

107

SA_PGOOD

108

ACIN_D

110

EC_ON_R

112

ON/OFFBTN#

114

LID_SW#

115

SUSP#

116 117

EC_PECI H_PECI

118

+EC_V18R

124

1

CB15

4.7U_0805_10V4Z

2

WL_BT_LED# <41>

FANPWM <5>

BATT_TEMPA <43> ADP_I <43,44>

ADP_V <44> MOS_TEMP <51> EC_ENBKL <27>

WOL_EN# <35>

3VALW_EN <45>

PCH_SUSPWRDN# <26>

SUSACK# <26>

Reserve this signal to EC by SW demand

EC_MUTE# <38>

USB_EN#0 <37>

TP_CLK <41>

TP_DATA <41>

EC_BT_ON# <34> GPS_DOWN# <13>

SYSON <46> VR_ON <49>

USB_OC#0 <28,37>

ON/OFFBTN# <41> LID_SW# <41>

SUSP# <42,47,48>

2011/10/18a

VGATE <26,49>

EC_DRAMRST_CNTRL_PCH <7>

PWRME_CTRL <24>

VCIN0_PH <43>

BATT_FULL_LED# <41> CAPS_LED# <41> PWR_SUSP_LED# <41> BATT_CHG_LOW_LED# <41>

PCH_RSMRST# <26> EC_LID_OUT# <29> PROCHOT_IN <43> VS_ON <45>

BKOFF# <22>

PBTN_OUT# <26> PCH_PWR_EN <42>

SA_PGOOD <48>

PROCHOT_IN connect to power portion (9012 only)

1 2

RB19 43_0402_1%RB19 43_0402_1%

D

VR_HOT#<49>

VCIN0_PH connect to power portion (9012 only)

H_PECI <5>

@

1 2

RB1 0_0402_5%

H_PROCHOT#_EC

SSM3K7002F_SC59-3

BATT_TEMPA

ACIN_D

H_PROCHOT#_EC

LID_SW#

TP_CLK

TP_DATA

SYSON

VCOUT0_PH_L

VCOUT0_PH connect to power portion (9012 only)

ACIN_D

SUSP#

VR_ON

D

2

G

S

1

QB1

3

1 2

CB9 100P_0402_50V8JCB9 100P_0402_50V8J

1 2

CB10 100P_0402_50V8JCB10 100P_0402_50V8J

@

1 2

RB6 10K_0402_5%

1 2

RB35 47K_0402_5%RB35 47K_0402_5%

1 2

RB8 4.7K_0402_5%RB8 4.7K_0402_5%

1 2

RB9 4.7K_0402_5%RB9 4.7K_0402_5%

1 2

RB10 4.7K_0402_5%RB10 4.7K_0402_5%

@

1 2

RB34 0_0402_5%

RB18

330K_0402_5%

1 2

RB21 10K_0402_5%RB21 10K_0402_5%

1 2

RB23 10K_0402_5%RB23 10K_0402_5%

E

1

CB8

CB8 47P_0402_50V8J

47P_0402_50V8J

2

12

DB1RB751V40_SC76-2 DB1RB751V40_SC76-2

H_PROCHOT# <5>

+3VS

+3VL

+3VS

+3VL

ACIN <26,44>

For KB9012 EC_ON low pulse work around

4 4

RB27

100K_0402_5%

1 2

E51_TXD

A

Voltage Comparator Pins FOR 9012 A3

VCIN0 pin109 VCIN1 pin102

VCOUT0 pin104

VCOUT1 pin103

>1.2V <1.2V

HIGH (default)

HIGH

LOW

LOW (default)

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

LPC-EC-KB9012&930

Tuesday, October 16, 2012

E

of

40 53

of

40 53

of

40 53

1.0

5

Power Button

TJG-533-V-T/R_6P

3

1 2

Place on BOT Debug used @ after PVT

D D

Place on TOP

4

SW2

5

6

TJG-533-V-T/R_6P

3 4

SW3

5

6

@SW2

@

1 2

For ESD request close to SW3

+3VL

R395

R395 100K_0402_5%

100K_0402_5%

1 2

ON/OFFBTN#

1

C458

0.1U_0402_25V6

0.1U_0402_25V6 @

@

2

For EMI request

D2

2 3

L30ESD24VC3-2_SOT23-3

ON/OFFBTN# <40>

1

4

3

2

LPC Debug Port

JDB

@JDB

@

1 2 3 4 5 6 7 8 9

10 GND GND

E-T_3801K-F10N-01L

1 2

22P_0402_50V8J

Place the PAD under DDR DIMM.

C457

@

1 2 3 4 5 6 7 8 9 10 11 12

R393

1 2

22_0402_5%

22_0402_5% @

@

+3VS

CLK_PCI_DDR

1

PLT_RST# <28,34,35,40,5> CLK_PCI_DDR <28>

LPC_FRAME# <24,40> LPC_AD3 <24,40> LPC_AD2 <24,40> LPC_AD1 <24,40> LPC_AD0 <24,40>

For EMI

LED/LID/TP SMALL BOARD

Swap pin assign to avoid DDR interference

C C

BATT_CHG_LOW_LED#<40>

B B

+3VL

+3VS

+5VALW

BATT_FULL_LED#<40>

PWR_ON_LED#<40>

PWR_SUSP_LED#<40>

WL_BT_LED#<40>

LID_SW#<40>

TP_DATA<40>

TP_CLK<40> PM_SMBDATA<11,12,25,34> PM_SMBCLK<11,12,25,34>

TP_DATA TP_CLK

please place near JTP

A A

JLED

14

13

12

11

10

9

8

7

6

5

4

3

2

1

HB_A021419-SAHR31

D89

2

1

3

YSDA0502C_SOT23-3

YSDA0502C_SOT23-3 @

@

GND2 GND1

@JLED

@

16 15

Keyboard LED

Q38

Q38 AO3413_SOT23

AO3413_SOT23

+5VS

D

S

D

S

13

12

G

R587

10K_0402_5%

KBL@

KB_LED<40>

2

G

13

D

Q52

Q52 2N7002KW_SOT323-3

2N7002KW_SOT323-3 KBL@

KBL@

S

2

NEW KEYBOARD CONN.

KSI[0..7]

KSI[0..7] <40>

KSO[0..15] <40>

12

R376 300_0402_5%R376 300_0402_5%

JKB

@JKB

@

32

G2

31

G1

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

CVILU_CF20302U0RG-NH

KSO[0..15]

KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15

KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1

JKB4

CAPS_LED#

KBL@

1

C836

0.1U_0402_10V7K

2

KBL@

+3VS

CAPS_LED# <40>

+5VS_LED

JBLG

5

G1

6

G2

E-T_7182K-F04N-00R

KSO0 KSO1 KSO2 KSO3

KSI0

KSO4 KSI1 KSI2 KSI3 KSI4

KSO5 KSI5

KSO6 KSI6 KSI7

KSO7

KSO8

KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15

CAPS_LED#

Close to JKB

@JBLG

@

1 2 3 4

1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2

1 2

+5VS_LED

1 2 3 4

C406 100P_0402_50V8JC406 100P_0402_50V8J C405 100P_0402_50V8JC405 100P_0402_50V8J C404 100P_0402_50V8JC404 100P_0402_50V8J C408 100P_0402_50V8JC408 100P_0402_50V8J C425 100P_0402_50V8JC425 100P_0402_50V8J C407 100P_0402_50V8JC407 100P_0402_50V8J C431 100P_0402_50V8JC431 100P_0402_50V8J C422 100P_0402_50V8JC422 100P_0402_50V8J C423 100P_0402_50V8JC423 100P_0402_50V8J C424 100P_0402_50V8JC424 100P_0402_50V8J C409 100P_0402_50V8JC409 100P_0402_50V8J C427 100P_0402_50V8JC427 100P_0402_50V8J C411 100P_0402_50V8JC411 100P_0402_50V8J C429 100P_0402_50V8JC429 100P_0402_50V8J C421 100P_0402_50V8JC421 100P_0402_50V8J C412 100P_0402_50V8JC412 100P_0402_50V8J C415 100P_0402_50V8JC415 100P_0402_50V8J C416 100P_0402_50V8JC416 100P_0402_50V8J C417 100P_0402_50V8JC417 100P_0402_50V8J C418 100P_0402_50V8JC418 100P_0402_50V8J C419 100P_0402_50V8JC419 100P_0402_50V8J C413 100P_0402_50V8JC413 100P_0402_50V8J C410 100P_0402_50V8JC410 100P_0402_50V8J C420 100P_0402_50V8JC420 100P_0402_50V8J

C403 100P_0402_50V8JC403 100P_0402_50V8J

For EMI

Screw Hole

H12

H_4P3x3P8

H_4P3x3P8 @

@

1

H1

H2

H_2P8

H_3P0

@

1

H7

H8

H_3P0

@

1

ISPD

ZZZ

DAZ0T700100

PCB LA-9161P

PJP1

45@PJP1

45@

PJP1

H13

H14

H_3P8

H_3P8 @

@

1

PTH

H3

H_3P0

H_3P0 @

@

1

H9

H11

H_3P0

H_3P0 @

@

1

PCB Fedical Mark PAD

@

PCH

UH1

HM77R3@

UH1

HM77R3@

SA00005AGP0

Panther Point 82HM77 C-1 HM77

(Default) HM77R1@ BD82HM77 SLJ8C C1 SA00005AGH0

UH1

HM77@

UH1

HM77@

SA00005AG30

Panther Point 82HM77 C-1 HM77

H_4P3

H_4P3 @

@

H_3P0

H_3P0 @

@

FD1@FD1

@

1

H6

H5

H_3P0

H_3P0 @

@

1

H21

H10

H_3P0

H_3P0 @

@

1

FD3@FD3

FD2@FD2

@

1

CPU

(Default) CPU@ SA00004SX00

UC1

CPUI5@

UC1

CPUI5@

SA00005K690

Ivy Bridge i5-3317U R1

UC1

CPUI5R3@

UC1

CPUI5R3@

SA00005K6G0

Ivy Bridge i5-3317U R3

H15

H_3P0

H_3P0 @

@

H_3P0

H_3P0 @

@

FD4@FD4

1

H_3P0x3P7

H_3P0x3P7 @

@

VGACPU

H16

UC1

SA00005L590

Ivy Bridge i3-3217U R1

UC1

CPUI3R3@

UC1

CPUI3R3@

SA00005L5G0

Ivy Bridge i3-3217U R3

1

H_3P0

H_3P0 @

@

CPUI3@

NPTH

H17

H_3P2N

H_3P2N @

@

1

H19

H_3P2x3P7N

H_3P2x3P7N @

@

1

GPU

(Default) N13PGLR1@ SA000051A00

UV4

N13PGLR3@UV4

N13PGLR3@

SA000051A60 SA0000518C0

N13P-GL-A1

H18

H_3P2x3P7N

H_3P2x3P7N @

@

1

H20

H_3P3N

H_3P3N @

@

1

UV4

N13PGSR1@UV4

N13PGSR1@

SA000051880

N13P-GS-A2 FCBGA

UV4

N13PGSR3@UV4

N13PGSR3@

N13P-GS-A2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

3

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

2

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

TP/ISPD/KB/Screw

VCUAA

Tuesday, October 16, 2012

1

of

41 53

of

41 53

of

41 53

1.0

A

+3VALW TO +3VS

+3VALW +3VS

Q29

1

8

S

D

2

7

S

D

3

6

S

D

4

5

G

D

SI4800BDY_SO8

1 1

SI4800BDY_SO8

1

C465

2

4.7U_0805_10V4Z

1

2

0.022U_0402_25V7K

Vgs=10V,Id=9A,Rds=18.5mohm

1

C459

2

1U_0402_6.3V6K

C466

12

R412

R412 820K_0402_5%

820K_0402_5%

1

C460 4.7U_0805_10V4ZC460 4.7U_0805_10V4Z

2

R409

1 2

120K_0402_5%

61

Q10A

2

2N7002KDWH_SOT363-6

change R409 to 120k 5%

R406

470_0805_5%

Q10B

470_0805_5%

1 2 34

5

+VSB

SUSP SUSP

B

+5VALW

8 7 6 5

SI4800BDY_SO8

1

C467

2

4.7U_0805_10V4Z

C

D

E

+5VALW TO +5VS

Vgs=10V,Id=9A,Rds=18.5mohm

+5VS

Q30

1

S

D

2

S

D

3

S

D

4

G

D

0.01U_0402_25V7K

1U_0402_6.3V6K

1

C468

2

C461

12

R413

R413 820K_0402_5%

820K_0402_5%

@

1

2

4.7U_0805_10V4Z

1

C462

2

R410

1 2

200K_0402_5%

61

Q11A

2

2N7002KDWH_SOT363-6

+VSB

R407

1 2 34

2N7002KDWH_SOT363-6

5

470_0805_5%

Q11B

2

C822

C822 @

@

1

0.1U_0402_10V7K

+5VS

For EMI

2

C821

C821 @

@

1

0.1U_0402_10V7K

PCH_PWR_EN#<30,31>

PCH_PWR_EN<40>

PCH_PWR_EN#

12

R5529

100K_0402_5%

+5VALW

1 2

13

D

2

G

SB570020110

S

2N7002E-T1-E3_SOT23-3

R5545

R5545 10K_0402_5%

10K_0402_5%

Q5527

2N7002KW_SOT323-3

+1.8VS

D

S

R470

R470 470_0805_5%

470_0805_5%

1 2

13

Q190

SUSP

2

G

+1.5V to +VRAM_1.5VS

+1.5V

Q46

8

D

7

D

6

D

5

D

FDS6676AS_SO8

1

C473

C473 OPT@

OPT@

2 2

2

4.7U_0805_10V4Z

+1.05VS_VCCP to +1.05VS_DGPU

3 3

+1.05VS_DGPU

4.7U_0402_6.3V6M

+VRAM_1.5VS

1

C479

1 2 3 4

VRAM_1.5VS_GATE

1

2

0.1U_0402_25V6

+1.05VS_VCCP

C479 OPT@

OPT@ 1U_0402_6.3V6K

1U_0402_6.3V6K

2

12

R430

R430 820K_0402_5%

820K_0402_5% OPT@

OPT@

2N7002DW-T/R7_SOT363-6

2

G

OPT@Q46

OPT@

VGA_PWROK#<34>

VGA_PWROK<29,51>

S S S G

C482

C482 OPT@

OPT@

Vgs=4.5V,Id=3A,Rds<22mohm

Q56

13

D

2

G

S

OPT@

1

C686

C686 1U_0402_6.3V6K

1U_0402_6.3V6K OPT@

OPT@

2

1

2

C685

@

AO3416_SOT23-3

1

2

Vgs=10V,Id=14.5A,Rds=6mohm

1

C476

C476 OPT@

OPT@

4.7U_0805_10V4Z

2

OPT@

OPT@ R432

R432

1 2

220K_0402_5%

61

13

D

Q188

2N7002KW_SOT323-3

OPT@

S

C493

C493 OPT@

OPT@

2N7002DW-T/R7_SOT363-6

0.1U_0402_25V6

Q13A

Q13A OPT@

OPT@

2

+5VALW

12

61

+VSB

VGA_PWROK#

R434

R434 330K_0402_5%

330K_0402_5% OPT@

OPT@

Q207A

VGA_PWROK#

2

OPT@

R429

R429 OPT@

OPT@

5

OPT@

1 2

1 2 3

4

470_0805_5%

Q13B

Q13B 2N7002DW-T/R7_SOT363-6

2N7002DW-T/R7_SOT363-6 OPT@

OPT@

+5VALW

R146100K_0402_5%

+1.05VS_DGPU

R460

22_0805_5%

22_0805_5% OPT@

OPT@

1 2 3

Q207B

5

2N7002DW-T/R7_SOT363-6

OPT@

4

Reserve CAP to avoid Power Noise

+5VALW +5VALW B+

1

C23

C22

@

2

10U_0603_6.3V6K

0.1U_0402_6.3V6K

+5VALW +0.75VS

1

C29

C29 @

@

2

0.1U_0402_6.3V6K

1

C43

2

0.1U_0402_10V7K

C31

C31 @

@

For S3 CPU Power Saving

VCCP_PWRGOOD<47,48>

1

C25

C24

@

2

10U_0603_6.3V6K

0.1U_0402_6.3V6K

1

2

0.1U_0402_6.3V6K

1 2

R158 220K_0402_5%R158 220K_0402_5%

SUSP

1

C27

C26

@

2

0.1U_0402_25V6

10U_0805_25V6K

1

C34

C34 @

@

2

10U_0603_6.3V6K

5

+VCCSA

C35

C35 @

@

0.1U_0402_6.3V6K

1

2

0.75VR_EN

34

Q6B

2N7002KDWH_SOT363-6

C42

+5VALW

1

C41

C41 @

@

2

0.1U_0402_10V7K

0.1U_0402_6.3V6K

SUSP<34,5,9>

0.75VR_EN <46>

SUSP#<40,47,48>

1

C44

SUSP

2

220P_0402_50V6K

ESD request 8/6

ESD Cap., please keep original location

+5VALW

1

0.1U_0402_6.3V6K

1

C40

C28

2

0.1U_0402_6.3V6K

1

C33

C32

2

0.1U_0402_6.3V6K

+3VS

1

C37

C21

C36

C20

2

0.1U_0402_6.3V6K

1

2

0.1U_0402_6.3V6K

2

1

C38

2

0.1U_0402_6.3V6K

+5VALW

R422

R422 100K_0402_5%

100K_0402_5%

1 2 61

Q6A

Q6A 2N7002KDWH_SOT363-6

2N7002KDWH_SOT363-6

1

C39

2

0.1U_0402_6.3V6K

+0.75VS

R421

22_0805_5%

1 2

13

D

Q189

2N7002KW_SOT323-3

S

EMI request

+0.75VS +GFX_CORE

1

12

C1

2

0.1U_0402_6.3V6K

C1

680P_0402_50V7K

C30

2

G

+1.05VS_VCCP

SUSP

2

G

2N7002KW_SOT323-3

R468

R468 470_0805_5%

470_0805_5%

1 2

13

D

Q60

S

+3VS to +3VS_DGPU

+3VALW

R426

47K_0402_5%

OPT@

2

C491

0.1U_0402_10V7K

0.1U_0402_10V7K OPT@

OPT@

1

2

C492

0.01U_0402_25V7K

1

4.7U_0805_10V4Z

R433

R433 100K_0402_5%

100K_0402_5% OPT@

OPT@

4 4

DGPU_PWR_EN#

DGPU_PWR_EN<28,51>

1 2

61

Q206A

OPT@

2

2N7002DW-T/R7_SOT363-6

A

+3VS

Vgs=-4.5V,Id=3A,Rds<97mohm

S

Q54

G

2

D

OPT@

C683

D

1 3

1

@

2

AO3413_SOT23

1

C684

C684 1U_0402_6.3V6K

1U_0402_6.3V6K

2

OPT@

+3VS_DGPU

R458

470_0805_5%

OPT@

1 2 3

Q206B

2N7002DW-T/R7_SOT363-6

B

Q206B

OPT@

4

DGPU_PWR_EN#

5

+VGA_CORE

R459

470_0805_5%

OPT@

1 2 13

D

Q55

2

G

2N7002KW_SOT323-3

OPT@

S

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

D

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

DC-DC INTERFACE

VCUAA

Tuesday, October 16, 2012

E

of

42 53

of

42 53

of

42 53

1.0

A

PL1

HCB2012KF-121T50_0805

PF1

7A_32V_S1206-H-7.0A

2 1

@

PJP3

1

+

1 1

ACES_50305-00441-001

2

+

3

-

4

-

DC_IN_S2DC_IN_S1

12

PC1

1000P_0402_50V7K

1 2

PL2

HCB2012KF-121T50_0805

1 2

12

PC2

100P_0402_50V8J

12

PC3

1000P_0402_50V7K

B

VIN

12

PC4

100P_0402_50V8J

C

PH1 under CPU botten side : CPU thermal protection at 93 +-3 degree C Recovery at 56 +-3 degree C

ADP_I<40,44>

PR2

0_0402_5%

PROCHOT_IN<40> VCIN0_PH<40>

1 2

PR1

1K_0402_1%

Please locate these parts Near EC chip

+3VL

12

PR4

12.1K_0402_1%

PR5

0_0402_5%

1 2

12.1K_0402_1%

D

PL3

HCB2012KF-121T50_0805

VMB

PJP2

@PJP2

@

1

2

3

4

5

6

7

8

9

10

GND

11

2 2

SUYIN_200070GR009G106ZR

3 3

GND

12

GND

13

GND

PJSOT24C_SOT23-3

+3VALWP

(7.5A,300mils ,Via NO.= 10) OCP=10A

+5VALWP

(15A,600mils ,Via NO.= 30) OCP=20A

+3VLP +3VL

2

(100mA,40mils ,Via NO.= 2)

EC_SMCA

PD1

PR13

100_0402_1%

@

PJ332

112

JUMP_43X118

PJ352

@ PJ352

@

112

JUMP_43X118

PJ333

@ PJ333

@

112

JUMP_43X39

BATT_S1

BATT_P4 BATT_P5

EC_SMDA

2

1 2

1

3

1 2

+3VALW

+5VALW

PF2

2 1

10A_125V_S6125-F-10.0A

12

PR11

1K_0402_1%

PR12

PR12 100_0402_1%

100_0402_1%

12

PR16

PR16 1K_0402_1%

1K_0402_1%

PD2

PJSOT24C_SOT23-3

2 3

12

PC5

@ PC5

@

.1U_0402_16V7K

1

PR10

6.49K_0402_1%

6.49K_0402_1% 12

BATT_TEMPA <40>

EC_SMB_DA1 <40,44>

EC_SMB_CK1 <40,44>

@

PJ152

2

112

JUMP_43X118

@

PJ153

+1.5VP

(10A, 400mils ,Via NO.= 20) OCP=12.7A

2

112

JUMP_43X118

PJ462

@ PJ462

@

2

112

JUMP_43X118

(6A,240mils ,Via NO.= 12) OCP=7.5A

1 2

PL4

HCB2012KF-121T50_0805

1 2

12

PC6

1000P_0402_50V7K

+3VL

+1.5V

+VCCSA+VCCSAP

BATT+

12

PC7

0.01U_0402_25V7K

+0.75VSP

B+

VL

PR8

100K_0402_1%

POK<26,45>

@

2

JUMP_43X39

(0.5A,40mils ,Via NO.= 1)

JUMP_43X39

PJ76

PR9

1 2

0_0402_5%

1 2

112

VSB_N_002

12

@

+0.75VS

2

G

PC10

.1U_0402_16V7K

22K_0402_1%

1 2

VSB_N_003 13

D

S

PR3

1 2

20K_0402_1%

12

PR6

100K_0402_1%

PR7

PQ2

PQ2 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

100K_0402_1%

RTC Battery

-+

SP093MX0000

12

PC8

@

VSB_N_001

PBJ1

MAXEL_ML1220T10@

TP0610K-T1-E3_SOT23-3

0.22U_0603_25V7K

12

@PC11

@

0.1U_0402_10V7K

2

PQ1

12

PC11

13

560_0603_5%

1 2

PR14

12

PH1

12

PC9

@

100K_0402_1%_TSM0B104F4251RZ

+VSBP

0.1U_0603_25V7K

PR15

560_0603_5%

1 2

+RTCBATT

PJ3

@

+VSBP +VSB

4 4

(120mA,40mils ,Via NO.= 1)

(1.54A,60mils ,Via NO.= 3)

2

JUMP_43X39

PJ182

@ PJ182

@

2

JUMP_43X118

112

Security Classification

112

+1.8VS+1.8VSP

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Deciphered Date

C

2015/04/192012/04/19

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR-DCIN / BATT CONN / OTP

VCUAA

D

of

43 53Tuesday, October 16, 2012

of

43 53Tuesday, October 16, 2012

of

43 53Tuesday, October 16, 2012

1.0

A

B

C

D

for reverse input protection

13

D

PQ209

2

SSM3K7002FU_SC70-3

G

S

PR225

1 2

1M_0402_5%

1 1

2 2

3 3

1M_0402_5%

AON6504_POWERDFN56-8-5

PQ203

5

12

PC230

2200P_0402_50V7K

1 2

3M_0402_5%

1 2 3

4

BQ24725_ACDRV_1

Vin Dectector

Min. Typ Max. H-->L 17.23V L--> H 17.63V

ILIM and external DPM

3.97A

4 4

PR226

P1 B+VIN

12

PR231@

0_0402_5%

S

12

PC231

0.1U_0402_25V6

PR234

4.12K_0603_1%

12

PR235

PQ205

DMG4406LSS_SO8

1 2 3

4

4.12K_0603_1%

12

@

12

PC212

10U_0805_25V6K

12

PC214

10U_0805_25V6K

CSOP1SRP

CSON1

+3VALW

PC216

@

0.1U_0402_25V6

PC215

0.1U_0402_25V6

5

4

5

4

12

PC242

0.1U_0603_16V7K

BQ24725_BATDRV

PQ201

PQ201 AON7408L

AON7408L

123

4.7UH_ETQP3W4R7WFN_5.5A_20%

BQ24725_LX

AON7406L

123

PQ202

1 2

12

PR206

12

PC206

1 2

4.12K_0603_1%

PL202

4.7_1206_5%

680P_0603_50V8J

PR247

309K_0402_1%

PR249

47K_0402_1%

PR233

CHG

CSOP1

12

VIN

12

PQ207

DMG4406LSS_SO8

8 7 6 5

4

BQ24725_BATDRV_1

PR227

0.01_1206_1%

1 2

PC240

0.1U_0402_25V6

4 3

12

0.1U_0402_10V7K

1 2 3

CSON1

12

PR248

10K_0402_1%

10K_0402_1% 1 2

PC247

@PC247

@

12

PC241

0.1U_0402_25V6

PC234

0.01U_0402_50V7K

PC221

@

10U_0805_25V6K

12

PR232@

0_0402_5%

PC222

10U_0805_25V6K

ADP_V <40>

12

PC223

10U_0805_25V6K

12

PC224

2200P_0402_50V7K

BATT+

12

PC225

0.01U_0402_50V7K

12

P2

8 7 6 5

PC238

0.1U_0603_25V7K

+3VALW

ACIN<26,40>

PR238 10K_0402_1%@PR238 10K_0402_1%@

+3VL

PR239 10K_0402_1%PR239 10K_0402_1%

PR240 10K_0402_1%PR240 10K_0402_1%

VIN

1 2

0.1U_0402_25V6

12

BQ24725_ACP

BQ24725_CMSRC

BQ24725_ACDRV

1 2

PR243

270K_0402_1%

PR211

0.01_1206_1%

PC236

BQ24725_ACN

BQ24725_ACOK

12

PC244

4 3

12

PC235

12

0.1U_0402_25V6

VIN

3

0.1U_0402_25V6

PC239

1 2

1U_0603_25V6K

PU200

21

PAD

1

ACN

2

ACP

BQ24725RGRR_VQFN20_3P5X3P5

3

CMSRC

4

ACDRV

5

ACOK

PR244

154K_0402_1%

PR245

66.5K_0402_1%

66.5K_0402_1% PC245

PC245

100P_0402_50V8J

PL201

1UH_NRS4018T1R0NDGJ_3.2A_30%

2

PD230

PD230 BAS40CW_SOT323-3

BAS40CW_SOT323-3

1 12

1 2

PR228

10_1206_1%

BQ24725_VCC

BQ24725_LX

20

19

VCC

PHASE

ACDET6IOUT7SDA8SCL9ILIM

BQ24725_ACDET

12

PL201

1 2

0.047U_0402_25V7K

0.047U_0402_25V7K PC237

PC237

12

PR229

2.2_0603_5%

DH_CHG

BQ24725_BST

17

18

BTST

HIDRV

PR246

12

100_0402_5%

12

PD231

PD231 RB751V-40_SOD323-2

RB751V-40_SOD323-2

BQ24725_REGN

1U_0603_25V6K

16

REGN LODRV

GND

SRP

SRN

BATDRV

10

BQ24725_ILIM

12

PR242

100K_0402_1%

12

0.1U_0402_10V7K

PC211

10U_0805_25V6K

12

PC213

@

10U_0805_25V6K

DH_CHG

PC205

1 2

DL_CHG

15

14

PR236

10_0603_1%

1 2

13

PR237

6.8_0603_5%

SRN

1 2

12

BQ24725_BATDRV

11

1 2

PR241

357K_0402_1%

12

PC243

0.01U_0402_25V7K

EC_SMB_CK1 <40,43>

EC_SMB_DA1 <40,43>

ADP_I <40,43>

PC246

@PC246

@

Please locate the RC Near EC chip 2011-02-22

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR-CHARGER

VCUAA

D

of

44 53Tuesday, October 16, 2012

of

44 53Tuesday, October 16, 2012

of

44 53Tuesday, October 16, 2012

1.0

A

B

C

D

E

1 1

3VALW_EN<40>

B+

12

PC334

@

680P_0603_50V7K

2 2

PL331

HCB2012KF-121T50_0805

1 2

3.3V

12

PC338

0.1U_0402_25V6

+3VALWP

3/5V_B+

PC339

2200P_0402_50V7K

12

PC340

10U_0805_25V6K

PL332

4.7UH_ETQP3W4R7WFN_5.5A_20%

1

+

PC331

220U_6.3V_M+PC331

220U_6.3V_M

2

12

PR336

4.7_1206_5%

SNUB_3V

12

PC336

680P_0603_50V8J

PQ331

AON7408L

123

5

4

AON7406L

AON7406L PQ332

PQ332

PC335

0.1U_0402_10V7K

0.1U_0402_10V7K 1 2

POK<26,43>

BST1_3V

2.2_0402_1%

1 2

3/5V_B+

SSM3K7002FU_SC70-3

100P_0402_25V8K

14K_0402_1%

PR333

Peak Current 7.5A OCP current 10A Delta I=1.160A ,ripple=1.160 x17m=19.27mV FSW=455kHz

3 3

DCR 35mohm +/-15% TYP MAX H/S Rds(on) :27mohm , 34mohm

EC_ON<40>

VS_ON<40>

L/S Rds(on) :19mohm , 23.5mohm

PC345

1 2

PR330

1 2

PR331

20K_0402_1%

1 2

BST_3V

UG_3V

LX_3V

LG_3V

499K_0402_1%

1 2

12

PC360

0.1U_0603_25V7K

0_0402_5%

1 2

PQ3

@

PQ3

@

2

FB_3V

10

PR334

PR340

2.2K_0402_1%

1 2

PR341

S

G

D

1 3

5

FB2

6

PGOOD

7

BOOT2

8

UGATE2

9

PHASE2

LGATE2

VIN11ENLDO12SECFB13LDO514LDO3

12

PR338

PC342

100K_0402_1%

1U_0603_10V6K

12

PC346

@

0.1U_0402_25V6

1 2

4

12

PC343

PR337

ENTRIP2

4.7U_0805_25V6-K

PR335

0_0402_5%

PR342

1 2

235K_0402_1%

3

TON

1 2

PR357

FB_5V

1 2

156K_0402_1%

54.9K_0402_1%

2

1

FB1

PAD

ENTRIP1

BYP1

BOOT1

UGATE1

PHASE1

LGATE1

PU330

15

RT8243AZQW_WQFN20_3X3

VL

12

PC359

4.7U_0805_10V6K

PR332

100K_0402_5%

PR350

30K_0402_1%

1 2

PR351

19.1K_0402_1%

1 2

12

PC344

21 20

19

18

17

16

PC344

1U_0603_10V6K

PR355

2.2_0402_1%

BST_5V BST1_5V

1 2

UG_5V

LX_5V

LG_5V

+3VLP

12

PC341

4.7U_0805_10V6K

3/5V_B+

12

PC353

12

PC354

0.1U_0402_25V6

0.1U_0402_25V6 2200P_0402_50V7K

2200P_0402_50V7K

PC355

0.1U_0402_10V7K

0.1U_0402_10V7K 1 2

12

PC358

PC361

5

10U_0805_25V6K

4.7U_0805_25V6-K

PQ352

AON7212L_DFN8-5

4

PQ351

AON7518

123

S COIL 3.3UH +-20% KJ1040-3R3M 11A

1 2

5

12

PR356

4.7_1206_5%

SNUB_5V

123

12

PC356

680P_0603_50V8J

PL352

1

+

PC351

2

150U_D2_6.3VY_R15M

5V Peak Current 15A OCP current 18A FSW=400kHz Delta I=2.791A,ripple=2.791*15m=41.865mV DCR 13.2mohm +/-5% TYP MAX H/S Rds(on) :11.2mohm , 14mohm L/S Rds(on) :6.2mohm , 7.8mohm

+5VALWP

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

PWR-3.3VALWP/5VALWP

VCUAA

45 53Tuesday, October 16, 2012

E

1.0

of

A

1 1

B

C

D

0.75Volt +/- 5%

PL151

HCB1608KF-121T30_0603

B+

2 2

1 2

PL152

1UH_VMPI0703AR-1R0M-Z01_11A_20%

PL152

+1.5VP

1

+

PC157

2

330U_D2_2.5VY_R9M

Mode Level +0.75VSP VTTREF_1.5V S5 L off off S3 L off on

3 3

S0 H on on

Note: S3 - sleep ; S5 - power off

1.5V Peak Current 10A OCP current 12.7A FSW=500kHz

12

1.5V_B+

12

PC152

2200P_0402_50V7K

12

SNUB_+1.5VP

12

PC153

@

4.7U_0805_25V6-K

PR156

@PR156

@

4.7_1206_5%

PC156

@PC156

@ 680P_0402_50V7K

680P_0402_50V7K

12

PC154

10U_0805_25V6K

SYSON<40>

PR155

0_0603_5%

PC164

PC166

@PC166

@

0_0603_5%

1 2

PR154

0_0603_5%

1 2

SW_1.5V

DL_1.5V

12

EN_1.5V

BST_1.5V-1

DH_1.5V-1

PC155

4

1 2

0.1U_0603_25V7K

PR163

0_0402_5%

1 2

+5VALW

PR159

5.1_0603_5%

1 2

1U_0603_10V6K

12

0.1U_0402_10V7K

5

PQ151

AON7408L

123

5

PQ152

FDMC7692S_MLP8-5

123

BST_1.5V

DH_1.5V

PR158

16.2K_0402_1%

16.2K_0402_1% 1 2

PC162

1U_0603_10V6K

1 2

VDD_1.5V

+5VALW

1.5V_B+

0.75VR_EN<42>

CS_1.5V

15

LGATE

14

PGND

13

CS

12

VDDP

11

VDD

PR161

887K_0402_1%

1 2

17

UGATE

TON

9

TON_1.5V

12

18

BOOT

S5

8

19

7

EN_0.75VSP

12

16

PHASE

RT8207MZQW_WQFN20_3X3

PGOOD

10

PR164

0_0402_5%

20

PU150

VTT

PAD

VLDOIN

VTTGND

VTTSNS

GND

VTTREF

VDDQ

FB

S3

6

FB_1.5V

PC167

0.1U_0402_10V7K

21 1

2

3

4

5

VTTREF_1.5V

PR162

PR162 10K_0402_1%

10K_0402_1%

1 2

PR160

10.2K_0402_1%

+1.5V

+1.5VP

12

Peak Current 1.5A OCP Current 1.5A

12

PC160

PC159

10U_0805_6.3V6K

+1.5VP

PC165

PC165 .1U_0402_16V7K

.1U_0402_16V7K

12

PC161

@

10U_0805_6.3V6K

12

PC163

0.033U_0402_16V7K

+0.75VSP

DCR 10mohm TYP MAX H/S Rds(on) :27mohm , 34mohm L/S Rds(on) :9.6mohm , 13mohm

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

C

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

+1.5VP/+0.75VSP

Tuesday, October 16, 2012

VCUAA

D

of

46 53

of

46 53

of

46 53

1.0

5

D D

60.4K_0402_1%

12

VCCP_PWRGOOD<42,48>

PR404

10_0402_1%

1 2

PR411

PR410

SUSP#<40,42,48>

C C

PC408

0.1U_0402_25V6

VCCIO_SENSE_VSS<8>

VCCIO_SENSE<8>

B B

4

PR408

9.76K_0402_1%

1 2

11K_0402_1%

1 2

PR409 @ PR409

@

1 2

10K_0402_1%

PC413

0.01UF_0402_25V7K

1 2

PR402

10_0402_5%

1 2

PC412

PC412 1000P_0402_50V7K

1000P_0402_50V7K

1 2

12

PC407

.1U_0402_16V7K

PR403

0_0402_5%

1 2

PU400

1

VREF

2

REFIN

3

GSNS

4

VSNS

PC409

0.01UF_0402_25V7K

1 2

@

PR401

10_0402_1%

1 2

+3VS

PR413

100K_0402_1%

1 2

PR412

12K_0402_1%

1 2

16

17

PAD

TPS51219RTER_QFN16_3X3

COMP5TRIP6GND

PR407

64.9K_0402_1%

PGOOD

12

14

15

EN

MODE

7

3

PR405

2.2_0603_5%

1 2

13

BST

SW

DH

PGND

8

DL

V5

12

11

10

9

LX_1.05VS_VCCP

DH_1.05VS_VCCP

DL_1.05VS_VCCP

+5VALW

12

PC410

1U_0603_10V6K

1 2

PC405

0.1U_0603_25V7K

2

PL401

FBMA-L11-201209-121LMA50T_0805

1.05_B+

12

5

PQ401

4

PQ401

S TR AON7514 1N DFN

123

5

PQ402

S TR AON6508 1N DFN

123

PC402

22U_0805_6.3VAM

0.24UH_FDUE0630J-H-R24M-P3_22A_20%

PR406

1 2

4.7_0402_1%

SNUB_+1.05VSP

12

PC406

680P_0402_50V7K

FBMA-L11-201209-121LMA50T_0805

12

PC403

22U_0805_6.3VAM

PL402

1 2

PC411

2200P_0402_25V7K

1

12

+5VALW

+1.05VS_VCCP

PC414

1000P_0402_50V7K

1 2

1.05V Peak Current 14A OCP current 15.08A FSW=300kHz Delta I=5.883A,Rippe=5.883x 4.5m=26.473Mv DCR 3.7ohm + TYP MAX H/S Rds(on) :5.6mohm , 6.8mohm

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2012/04/19

3

Compal Secret Data

Deciphered Date

2015/04/19

2

L/S Rds(on) :3.7mohm , 5mohm

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

Compal Electronics, Inc.

PWR-V1.05SP/16V

Tuesday, October 16, 2012

VCUAA

1

47 53

of

1.0Custom

5

4

3

2

1

D D

The 1k PD on the VCCSA VIDs are empty. These should be stuffed to ensure that VCCSA VID is 00 prior to VCCIO stability.

VID [0] VID[1] VCCSA Vout 0 0 0.9V 0 1 0.85V 1 0 0.775V 1 1 0.750V

PR470

+3VS

12

PR469

100K_0402_5%

SA_PGOOD<40>

PR472

0_0402_5%

12

100K_0402_5%

+VCCSA_PWRGD

PR470

0_0402_5%

0_0402_5% 1 2

PR471

0_0402_5%

0_0402_5% 1 2

PC475

@PC475

@

0.033U_0402_16V7K

0.033U_0402_16V7K 1 2

H_VCCSA_VID1 <9>

H_VCCSA_VID0 <9>

+5VALW

PR468

PR473

10_0402_1%

12

3300P_0402_50V7K

10_0402_1%

19

20

21

22

23

24

PC480

12

PU460

PGND

VIN

PC473

2.2U_0603_10V7K

1 2

PC468

10U_0805_25V6K

+VCCSA_PWR_SRC

2.2U_0603_10V7K 1 2

0.22U_0402_16V7K~D

PC479

C C

12

1 2

PC470

PC469

0.1U_0402_25V6

PC469

10U_0805_25V6K

PC471

PL461

HCB1608KF-121T30_0603

+5VALW

B B

1 2

PC471

2200P_0402_25V7K

PC472

1 2

1U_0603_10V6K

12

18

17

16

V5FILT

V5DRV

PGOOD

TPS51463RGER_QFN24_4X4~D

COMP

GND

VREF

3

1

2

12

PR476

5.1K_0402_1%

PC481

0.01U_0402_25V7K

+VCCSA_EN

14

15

13

EN

VID0

VID1

VOUT

SLEW

5

4

1 2

+VCCSA_BT

12

BST

+VCCSA_PHASE

11

SW

10

SW

9

SW

8

SW

7

SW

25

TP

MODE

6

PR475

PR475 100K_0402_5%

100K_0402_5%

PR468

0_0402_5%

0_0402_5% 1 2

PR474

2.2_0603_1%

1 2

12

+VCCSA_BT_1

12

PR466

4.7_1206_5%

12

PC466

PC466 680P_0402_50V7K

680P_0402_50V7K

VCCP_PWRGOOD <42,47>

PC474

0.1U_0402_25V6

0.1U_0402_25V6 1 2

0.47UH_VMPI0703AR-1R0M-Z01_11A_20%

PL462

1 2

output voltage adjustable network

VCCSA TDC 4.2A Peak Current 6.0A OCP current 7.5A Frequce = 700K

12

PC476

.1U_0402_16V7K

PR465

100_0402_5%

PR467

0_0402_5%

PC461

1 2

22U_0805_6.3V6M

12

PC462

1 2

22U_0805_6.3V6M

12

PC477

PC463

2200P_0402_25V7K

+VCCSA_SENSE <9>

PC478

1 2

22U_0805_6.3V6M

1 2

22U_0805_6.3V6M

+VCCSAP

PU180

PL181

HCB1608KF-121T30_0603

+5VALW

A A

1 2

12

PC184

PC184 22U_0805_6.3VAM

22U_0805_6.3VAM

PR181

EN_1.8V

SUSP#<40,42,47>

1 2

150K_0402_1%

499K_0402_1%

12

@

PR182

12

PC185

0.1U_0402_10V7K

@

PU180

SY8032ABC_SOT23-6

SY8032ABC_SOT23-6 4

IN

LX

5

PG

GND

FB6EN

LX_1.8V

3 2 1

PR186

PL182

1UH_NRS4018T1R0NDGJ_3.2A_30%

1 2

PR183

20K_0402_1%

4.7_0402_1%

1 2

FB_1.8V

12

PC186

680P_0603_50V7K

12

PR184

10K_0402_1%

12

PC187

68P_0402_50V8J

12

PC182

22U_0805_6.3VAM

12

PC183

22U_0805_6.3VAM

+1.8VSP

VCCSA

Peak Current 1.54A OCP current 1.078A

DELL CONFIDENTIAL/PROPRIETARY

123

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

Title

Size Document Number Rev

Date: Sheet

123

PWR-VCCSAP/1.8VSP

VCUAA

1

1.0

48 53Tuesday, October 16, 2012

1.0

of

A

1 1

VCC

12

@

PR507

PR510

66.5K_0402_1%

10K_0402_1%

12

PR519

PR516

10K_0402_1%

2 2

PR532

PR532 0_0402_5%

0_0402_5%

VCC

1 2

PH503

1 2

10K_0402_1%_ERTJ0EG103FA@

PR536

0_0402_5%

VCC

1 2

PH504

1 2

10K_0402_1%_ERTJ0EG103FA@

3 3

+1.05VS_VCCP

4 4

A

+1.05VS_VCCP

+3VS

0.1U_0402_25V6

13.3K_0402_1%

12

PR508

12

PR517

PR533

1 2

PC524

@PC524

@

12

PR509

66.5K_0402_1%

12

PR518

10K_0402_1%

PC513

10K_0402_1%

PR537

8.66K_0402_1%

1 2

12

B

12

PR511

@PR511

@

51K_0402_1%

12

PR520

33K_0402_1%

PH502

10K_0402_1%_ERTJ0EG103FA

0.1U_0402_25V6

OCSET

12

PR534

PR543 75_0402_1%PR543 75_0402_1%

PR545 10K_0402_1%PR545 10K_0402_1%

VR_SVID_ALRT#<8>

VR_SVID_DAT<8> VR_SVID_CLK<8>

B

12

10K_0402_1%

12

10K_0402_1%

12

PR523

1 2

2.55K_0402_1%

12

PR529

1 2

OCSETA

12

PR541

10K_0402_1%

1 2

PR548 150_0402_1%@ PR548 150_0402_1%@

1 2

PR549 130_0402_1%PR549 130_0402_1%

1 2

PR552 54.9_0402_1%PR552 54.9_0402_1%

VGATE<26,40>

VCC

PH501

10K_0402_1%_ERTJ0EG103FA

PC514

432_0402_1%

SETINI TEMPMAX

ICCMAX ICCMAXA

1 2

PR547

PR530

0.1U_0402_25V6

+5VALW

SETINIA

12

2.55K_0402_1%

432_0402_1%

PR515

2.2_0402_1%

VCC

PC502

2.2U_0603_10V6K

PR540

53.6K_0402_1%

VR_HOT#

VGATE

VR_SVID_ALRT# VR_SVID_DAT VR_SVID_CLK

C

PR501

@PR501

@

100_0402_5%

PR503

0_0402_5%

11 12 13 14 15 16 17 18 19 20

PR556

0_0402_5%

@

PR558

100_0402_5%

12

0.1U_0402_25V6

12

SETINI TMPMAX ICCMAX ICCMAXA TSEN OCSET TSENA OCSETA IBIAS VRHOT

VR_HOT# <40>

12

0_0402_5%

1 2

12

PC528

0.1U_0402_25V6

+CPU_CORE

12

PC501

@PC501

@

1 2

12

PR504

0_0402_5%

RNTC1N

12

PR542

3.3K_0402_1%

PH505

RNTC1P

10K_0402_1%_ERTJ0EG103FA

10

9

VCC

SETINIA

RT8167BGQW WQFN 40P PWM

VR_READY

VRA_READY

21

22

PH506

10K_0402_1%_ERTJ0EG103FA

12

PR557

@PC528

@

12

@ PR559

@

100_0402_5%

+GFX_CORE

PR502

@PR502

@

100_0402_5%

12

PR521

17.4K_0402_1%

7

8

RGND

GFXPS2

ALERT

VDIO

23

24

PR551

RNTCAP

12

RNTCAN

PR559

VCCSENSE <8>VSSSENSE<8>

12

PC503

PC503 390P_0402_50V7K

390P_0402_50V7K

PR514

3.3K_0402_1%

12

PC509

PC509 390P_0402_50V7K

390P_0402_50V7K

FB_CPU

6

5

FB

COMP

VCLK

RGNDA

25

26

12

16.2K_0402_1%

12

PR554

12

PR555

VCC_AXG_SENSE <9>VSS_AXG_SENSE<9>

3

4

ISEN1P

ISEN1N

COMPA

FBA

28

27

FB_GFX

12

3.3K_0402_1%

D

BOOT_CPU

1

2

BOOT1

TONSET

UGATE1 PHASE1 LGATE1

LGATEA PHASEA UGATEA

BOOTA

TONSETA

ISENAP

ISENAN

30

29

PC522

330P_0402_50V7K

PC523

PC523 220P_0402_50V8J

220P_0402_50V8J

D

PU500

GND

PVCC

EN

0.1U_0402_25V6

PR505

2.2_0603_5%

1 2

41 40 39 38 37 36 35 34 33 32 31

PC521

0.22U_0603_10V7K

UG_CPU PHASE_CPU LG_CPU

LG_GFX PHASE_GFX UG_GFX BOOT_GFX EN_GFX

12

PC505

1 2

PC515

12

PR528

PR528 10K_0402_1%

10K_0402_1%

12

PVCC

2.2U_0603_10V6K

1 2

E

PR513

PR512

49.9K_0402_1%

1 2

VCC

1 2

PR560

@PR560

@

10K_0402_1%

0.1U_0402_25V6

+5VALW

PR531

1 2

0_0402_5%

VR_ON <40>

PR535

PR538

57.6K_0402_1%

1 2

0_0402_5%

2.2_0603_5%

1 2

E

PC516

0.1U_0402_25V6

PR525

PR544

2.2_0603_5%

1 2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PR513

2.2_0402_1%

1 2

12

PC507

0.1U_0402_25V6

PR522

0_0603_5%

1 2

S TR AON6504 1N DFN

12

PC512

2.2_0402_1%

1 2

12

PC525

0.22U_0603_10V7K

1 2

S TR AON6504 1N DFN

0.1U_0402_25V6

F

+CPU_5V

12

PC504

PC508

22U_0805_6.3VAM

PQ503

PQ503 S TR AON7514 1N DFN

S TR AON7514 1N DFN

3 5

241

5

4

PQ502

123

PR539

S TR AON7514 1N DFN

PC527

2012/04/19 2015/04/19

PQ507

PQ506

12

4

F

+GFX_5V

3 5

241

5

123

Compal Secret Data

22U_0805_6.3VAM

PR506

4.7_0402_1%

1 2

PC506

680P_0402_50V7K

1 2

12

PC517

AON7514 SB00000VA00

PR526

4.7_0402_1%

1 2

PC526

680P_0402_50V7K

1 2

Deciphered Date

22U_0805_6.3VAM

G

PL501

HCB2012KF-121T50_0805

1 2

12

1

+

PC500

PC510

12

PC500

1 2

PC529

2

680P_0603_50V8J

0.1U_0402_25V6

0.1U_0402_25V6 S_A-P_CAP 220U 6.3V M 6.3X4.2 R17M VLPS

S_A-P_CAP 220U 6.3V M 6.3X4.2 R17M VLPS

PL502

0.12UH FDUE0630-H-R12M=P3 32.5A

1 2

PR524

1.58K_0402_1%

PR527

@PR527

@

1 2

1.69K_0402_1%

1 2

PC511

0.1U_0402_25V6

1 2

CPU_CORE TDC 16A Peak Current 29A OCP current 48.5A Load line -2.9mV/A FSW=700kHz DCR 0.63mohm +/-7% TYP MAX H/S Rds(on) :6.7mohm , 8.5mohm L/S Rds(on) :2.2mohm , 3.3mohm

+CPU_5V

12

PC518

PC519

PC530

1 2

0.1U_0402_25V6

680P_0603_50V8J

22U_0805_6.3VAM

GFX_CORE TDC 21.5A Peak Current 33A OCP current 48.5A Load line -3.9mV/A FSW=700kHz DCR 0.63mohm +/-7% TYP MAX H/S Rds(on) :6.7mohm , 8.5mohm L/S Rds(on) :2.2mohm , 3.3mohm

680P_0603_50V8J

PL503

0.12UH FDUE0630-H-R12M=P3 32.5A

1 2

PR550

1.58K_0402_1%

1 2

PR553

@PR553

@ 2K_0402_1%

2K_0402_1%

1 2

PC520

0.1U_0402_25V6

1 2

Compal Electronics, Inc.

Title

PWR- CPU GFX CORE

Size Document Number Rev

A2

Date: Sheet

G

+CPU_CORE

+GFX_CORE

+5VALW

LA-8551P

H

1.0

of

49 53Tuesday, October 16, 2012

of

49 53Tuesday, October 16, 2012

of

49 53Tuesday, October 16, 2012

H

5

4

3

2

1

+GFX_CORE

+CPU_CORE

1

12

PC806

2.2U_0402_6.3V6M

D D

2.2U_0402_6.3V6M

12

PC807

2.2U_0402_6.3V6M

12

PC808

2.2U_0402_6.3V6M

12

PC809

2.2U_0402_6.3V6M

12

PC810

2.2U_0402_6.3V6M

PC853

2

1

PC854

2

22U_0805_6.3V6M

1

2

1

PC855

2

22U_0805_6.3V6M

1

PC856

2

22U_0805_6.3V6M

1

PC857

2

22U_0805_6.3V6M

PC858

22U_0805_6.3V6M

+1.05VS_VCCP

12

PC811

2.2U_0402_6.3V6M

12

PC812

2.2U_0402_6.3V6M

12

PC813

2.2U_0402_6.3V6M

12

PC814

2.2U_0402_6.3V6M

12

PC815

2.2U_0402_6.3V6M

12

PC860

10U_0603_6.3V6M

12

PC866

1U_0402_6.3V6K

12

PC861

12

PC867

12

PC859

12

PC816

2.2U_0402_6.3V6M

C C

12

PC817

2.2U_0402_6.3V6M

12

PC818

2.2U_0402_6.3V6M

12

PC819

2.2U_0402_6.3V6M

12

PC820

2.2U_0402_6.3V6M

12

PC821

2.2U_0402_6.3V6M

PC859

12

PC865

12

PC862

10U_0603_6.3V6M

12

PC868

1U_0402_6.3V6K

12

PC863

10U_0603_6.3V6M

12

PC869

1U_0402_6.3V6K

PC864

10U_0603_6.3V6M

PC870

1U_0402_6.3V6K

12

PC454

@

22U_0805_6.3VAM

12

PC427

1U_0402_6.3V6K

12

PC417

12

PC428

1U_0402_6.3V6K

12

PC418

22U_0805_6.3VAM

12

PC430

PC429

1U_0402_6.3V6K

12

PC419

22U_0805_6.3VAM

12

PC431

1U_0402_6.3V6K

12

PC420

22U_0805_6.3VAM

12

PC432

1U_0402_6.3V6K

PC421

PC433

12

PC422

22U_0805_6.3VAM

12

PC434

1U_0402_6.3V6K

12

PC423

22U_0805_6.3VAM

12

PC435

1U_0402_6.3V6K

12

PC424

22U_0805_6.3VAM

12

PC436

1U_0402_6.3V6K

12

PC425

22U_0805_6.3VAM

12

PC437

1U_0402_6.3V6K

12

PC426

22U_0805_6.3VAM

12

PC438

1U_0402_6.3V6K

PC453

22U_0805_6.3VAM

PC439

1U_0402_6.3V6K

+CPU_CORE

1

PC834

PC834 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC822

PC822 22U_0805_6.3V6M

22U_0805_6.3V6M

2

B B

1

PC828

PC828 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC835

PC835 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC823

PC823 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC829

PC829 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC824

PC824 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC830

PC830 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC825

PC825 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC831

PC831 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC826

PC826 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC832

PC832 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC827

PC827 22U_0805_6.3V6M

22U_0805_6.3V6M

2

1

PC833

PC833 22U_0805_6.3V6M

22U_0805_6.3V6M

2

12

PC874

1U_0402_6.3V6K

12

PC876

1U_0402_6.3V6K

PC875

1U_0402_6.3V6K

12

PC873

PC872

1U_0402_6.3V6K

1

+

PC852

2

470U_D2_2VM_R4.5M

12

PC440

1U_0402_6.3V6K

12

PC441

1U_0402_6.3V6K

12

PC442

1U_0402_6.3V6K

12

PC443

1U_0402_6.3V6K

12

PC444

1U_0402_6.3V6K

12

PC445

1U_0402_6.3V6K

12

PC446

1U_0402_6.3V6K

12

PC447

1U_0402_6.3V6K

12

PC448

1U_0402_6.3V6K

12

PC449

1U_0402_6.3V6K

12

PC450

1U_0402_6.3V6K

PC415

@

330U_D2_2V_Y

12

PC451

1U_0402_6.3V6K

1

+

2

@

PC452

1U_0402_6.3V6K

1

+

2

PC416

330U_D2_2V_Y

+CPU_CORE

1

+

PC802

PC802 330U_D2_2V_Y

330U_D2_2V_Y

2

A A

5

1

+

PC803

PC803 330U_D2_2V_Y

330U_D2_2V_Y

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Chief River ULV 330uF*9m 22uF 10uF

CPU

GFX_CORE

1.05V_VCCP

Compal Secret Data

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

2

1

2

14

66

11

Title

PWR - PROCESSOR DECOUPLING

Size Document Number Rev

Date: Sheet

2.2uF 1uF

16

11

26

Compal Electronics, Inc.

VCUAA

1

of

50 53Tuesday, October 16, 2012

of

50 53Tuesday, October 16, 2012

of

50 53Tuesday, October 16, 2012

1.0

A

1 1

PR9091K_0402_1% PR9091K_0402_1%

1 2

PR9101K_0402_1% PR9101K_0402_1%

1 2

PR9111K_0402_1% @PR9111K_0402_1% @

1 2

PR9121K_0402_1% @PR9121K_0402_1% @

1 2

PR9421K_0402_1% PR9421K_0402_1%

1 2

PR9461K_0402_1% @PR9461K_0402_1% @

1 2

PC908

1000P_0402_50V7K

PR923

2 2

VGA_VSS_SENSE<15>

VGA_VCC_SENSE<15>

3 3

PR923

0_0402_5%

PR924

0_0402_5%

12

VGA_VID_0 VGA_VID_1 VGA_VID_2 VGA_VID_3 VGA_VID_4 VGA_VID_5

12

B

12 12 12 12 12 12

PR938

24.9K_0402_1%

24.9K_0402_1% 1 2

1 2

PC907

220P_0402_50V7K

1 2

PR921

1K_0402_1%

PR901 1K_0402_1%@ PR901 1K_0402_1%@ PR903 1K_0402_1%@ PR903 1K_0402_1%@ PR904 1K_0402_1%PR904 1K_0402_1% PR907 1K_0402_1%PR907 1K_0402_1% PR902 1K_0402_1%@ PR902 1K_0402_1%@ PR940 1K_0402_1%PR940 1K_0402_1%

+3VS

VGA_PWROK<29,42>

47P_0402_50V8J

VGA_COMP-1

PC906

1 2

470P_0402_50V8J

Connect to input caps

PC905

PR922

20K_0402_1%

6.81K_0402_1%

C

+3VS

12

PR925

+VGA_B+

PR933

80.6K_0402_1%

12

PR908

PR908 1K_0402_1%

1K_0402_1%

VGA_FB VGA_COMP

VGA_VCC VGA_ILIM

1 2

VGA_CSCOMP

1 2

PC904

1 2

0.1U_0402_16V7K

PU900

1 2 3 4 5 6 7 8

VGA_IREF

PR926

1 2

80.6K_0402_1%

PR930

1K_0402_1%

PR913

PWRGD IMON CLKEN# FBRTN FB COMP GPU ILIM

PR927

12

<28,42>

<13>

VGA_VID_4

VGA_VID_3

VGA_VID_2

DGPU_PWR_EN

VGA_VID_1

VGA_VID_0

PR917 0_0402_5%PR917 0_0402_5%

PR915 0_0402_5%PR915 0_0402_5%

PR914 0_0402_5%PR914 0_0402_5%

PR916 0_0402_5%PR916 0_0402_5%

1 2

330K_0402_1%

VGA_EN

32

VGA_RPM

1 2

237K_0402_1%

VGA_RAMP-1

1 2

EN

ADP3211AMNR2G_QFN32_5X5

IREF9RPM10RT11RAMP12LLINE13CSREF14CSFB15CSCOMP

PR928

1 2

VID1

VID2

VID3

VID4

VID031VID130VID229VID328VID427VID526VID6

VGA_RT

VGA_RAMP

12

1 2

301K_0402_1%

PR929 422K_0402_1%PR929 422K_0402_1%

D

<13>

VGA_VID_5

PR918 0_0402_5%PR918 0_0402_5%

PR919 0_0402_5%PR919 0_0402_5%

1 2

VGA_CSFB

<13>

PR920 0_0402_5%PR920 0_0402_5%

1 2

25

VCC

BST

DRVH

SW PVCC DRVL PGND AGND AGND

16

VGA_CSCOMP

12

1000P_0402_50V7K

PC913

24 23 22 21 20 19 18 17 33

+5VS

PR936

PR936 10_0603_1%

10_0603_1%

1 2

VGA_VCC

VGA_BOOST

VGA_DRVH VGA_SW

VGA_DRVL

12

PC916

PC916 1U_0603_10V6K

1U_0603_10V6K

1 2

2.2_0603_5%

12

PC914

PC914 560P_0402_50V7K

560P_0402_50V7K

PR905

0_0603_5%

PR939

0_0603_5%

@

VGA_BOOST-1

PR937

12

2.2U_0603_10V6K

E

PC909

0.22U_0603_25V7K

0.22U_0603_25V7K 1 2

+5VS

12

PC915

12

PR934

PR934 220K_0402_1%

220K_0402_1%

5

PQ901

AON7518

4

123

5

PQ902

4

123

12

PH901

@PH901

@

220K_0402_5%_TSM0B224J4702RE

4

S TR AON6508 1N DFN

200K_0603_1%

F

+VGA_B+

12

PC918

10U_0805_25V6K

PL902

1 2

12

PC919

10U_0805_25V6K

PC917

5

123

5

123

PR935

PC917

10U_0805_25V6K

PQ904

AON7518

0.36UH_TMPC1203H-R36MG-D_30A_20%

12

PR906

4.7_1206_5%

PQ903

12

S TR AON6508 1N DFN

PC910

680P_0603_50V8J

12

G

VGA_Core TDC 35A Peak Current 42A OCP current 65A Load line FSW=300kHz DCR 1.5~1.8mohm +/-5% TYP MAX H/S Rds(on) :11.2mohm , 14mohm L/S Rds(on) :3.7mohm , 5mohm

Total capacitor 1320u ESR=2.25m ohm

PL901

HCB2012KF-121T50_0805

1 2

12

PC901

PC903

68P_0402_50V8J

12

PC902

0.1U_0402_25V6

0.1U_0402_25V6 220P_0402_25V8K

220P_0402_25V8K

12

+VGA_CORE

1

+

PC996

2

1

+

PC997

2

330U_D2_2V_Y

1

+

PC998

PC999

2

330U_D2_2V_Y

H

B+

12

PC911

1000P_0402_50V7K

+VGA_CORE

4 4

Under VGA Core

12

PC929

4.7U_0603_6.3V6M

12

PC921

4.7U_0603_6.3V6M

12

PC932

0.1U_0402_10V7K

A

12

PC941

4.7U_0603_6.3V6M

12

PC935

4.7U_0603_6.3V6M

12

PC939

0.1U_0402_10V7K

PC930

4.7U_0603_6.3V6M

PC936

4.7U_0603_6.3V6M

PC938

0.1U_0402_10V7K

12

PC925

4.7U_0603_6.3V6M

12

PC922

4.7U_0603_6.3V6M

12

PC928

0.1U_0402_10V7K

12

PC933

4.7U_0603_6.3V6M

12

PC937

4.7U_0603_6.3V6M

12

PC927 @ PC927

@

0.1U_0402_10V7K

12

PC924

4.7U_0603_6.3V6M

12

PC942

4.7U_0603_6.3V6M

12

PC934 @ PC934

@

0.1U_0402_10V7K

12

PC943

4.7U_0603_6.3V6M

PC931

4.7U_0603_6.3V6M

12

PC923 @ PC923

@

0.1U_0402_10V7K

B

PC940

4.7U_0603_6.3V6M

PC926 @ PC926

@

0.1U_0402_10V7K

+VGA_CORE

1

2

12

Near VGA Core

1

PC952

2

@ PC952

@

22U_0805_6.3V6M

12

PC945

4.7U_0603_6.3V6M

PC953

2

@ PC953

@

22U_0805_6.3V6M

12

PC949

4.7U_0603_6.3V6M

12

PC948

22U_0805_6.3V6M

12

PC947

4.7U_0603_6.3V6M

C

PC950

@

47U_0805_4V6

PC946

4.7U_0603_6.3V6M

1

2

12

PC944

22U_0805_6.3V6M

PC951

4.7U_0603_6.3V6M

12

1000P_0402_50V7K

1 2

0_0402_5%

PR931

0_0402_5%

VGA_CSCOMP

D

PC912

+3VL

@

PR932

PR931 PR932 LL

X

@0

V

0@

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

E

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

F

12

PR943

12.1K_0402_1%

PR945

0_0402_5%

MOS_TEMP<40>

1 2

12

PC974

@PC974

@

0.1U_0402_10V7K

Title

Size Document Number Rev

Date: Sheet

G

12.1K_0402_1%

12

PH2

100K_0402_1%_TSM0B104F4251RZ

Compal Electronics, Inc.

+VGA_COREP

LA-8712P

1.0

of

51 53Tuesday, October 16, 2012

of

51 53Tuesday, October 16, 2012

of

51 53Tuesday, October 16, 2012

H

5

4

3

2

1

Version change list (P.I.R. List) Page 1 of 1

for PWR

Reason for change PG# Modify List Date PhaseItem

1

D D

2

HW command (Follow QFKAA)

change PR330 13K to 14K45

45

change PR351 20K to 19.1K

2012/5/17

DVT

4

5

6

7

8

9

C C

10

11

12

fine tune 1.5V ocp =12.6A

fine the 1.05V vout volatge=1.059V

fine tune the CPU load line =2.7mV

fine tune the GFX load line =3.7mV

fine tune the GFX OCP setting

purchaser command for cost down plane

for 1.05V high frequeence change to remote sense

for 1.05V high frequeence 47 change PR412 100k to 12K

13 14

15

16

17

B B

18

19

20 21

22

23

24 25

A A

26

27

change the same solution for 2nd sourcd 44

change the same solution for 2nd sourcd 46

fine tune 1.05V vout volatge=1.059V

fine tune the CPU DCR sense

fine tune the 5V OCP=18A

fine tune 3.3V OCP =10A

for 1.05V high frequeence 47

for 1.05V high frequeence

change the 3v/5v IC version

change 1.5V chokethe same part number with PL462

change 1.05V high frequeence OCP=16.5A

change charger current =3.46A

change the PF2 for design change

5

4

change PR158 13.3K to 16.2K

46

47

change PR411 10.5K to 9.76K

49

change PR521 14.3K to 17.4K

change PR551 10.5K to 16.2K

49

change PC522 560P to 330P

change PR537 13.3K to 8.66K

49

change PU460 SY8037D to TPS51463

48

47 2012/5/24

add PR402 reserve PR401

2012/5/17

2012/5/21

2012/5/22

2012/5/24

44change the same solution for 2nd sourcd

change PQ203 TPCA8057 to AON6504

change PR227 with the same PR211

change PC157 with the same PC996

change PR410 12K to 11K

47

49 change PR538 49.9K to 57.6K

49

change PR550 1.13K to 1.58K

change PR357 120K to 133K

45

change PR337 120K to 200K

change PL402 0.47u to 0.24u

Reserve the PC415 and PC416

47

2012/5/24

2012/5/25 DVT

2012/5/25

45 change the PU330 RT8243B to RT8243A 2012/5/25 DVT

46 change the PL152 SH00000GJ00 to SH00000KS00

47

48

43

change the PR407 75K to 64.9K

change the PR241 150 Kto 357K

change the PF2 8A to 10A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

Compal Secret Data

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

2

2012/5/25

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

DVT

PIR (PWR)

VCUAA

DVT

DVT2012/5/25

DVT

1

1.0

of

52 53Tuesday, October 16, 2012

A

B

C

D

E

HW PIR (Product Improve Record)

VCUAA LA-9161P SCHEMATIC CHANGE LIST REVISION CHANGE: 0.3 TO 1.0

----------------------------------------------------------------------------------------------------------------------------------Item Page Date Request Solution

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1) 24 2012/7/23A Change RTCBATT power rail from GCLK to original design DH1 mount always

2) 24 2012/7/23A remove BIOS socket UH3 mount always

1 1

3) 41 2012/7/23A remove debug SW Change SW2 to @

4) 38 2012/7/26A EMI request CA71,CA72,CA75,CA76 mount SE025102K80/1000pF

5) 41 2012/8/3A Update JBLG footprint Change JBLG footprint to E-T_7182K_F04N-00R_4P

6) 41 2012/8/3A Update H20 Change H20 from 3P8 to 3P3 size

7) 05 2012/8/6C remove JTAG for ESD request remove T5, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17

8) 42 2012/8/6D ESD request mount C20,C21,C28,C30,C32,C33,C36,C37,C38,C39,C40; add C44 on SUSP

9) 2012/8/6D Change footprint of 0ohm to Short_pad Change location: LL2, R1, R16, R17, R388, RA17, RA18, RA28, RB1,RB32, RB34, RC119, RC183, RC73, RC88, RC92, RC94, RC95, RH128, RH208, RH213, RH214, RH221, RH242, RH244, RH246, RH247, RH249, RH25, RH286, RH311, RH312, RH314, RL433, RV182, RV80, RV81

10) 41 2012/8/6D Change PCB PN Change to DAZ0T700100

11) 34 2012/8/6D EMI request Change CM18 from 47pF to 680pF

12) 42 2012/8/6D EMI request Add C1(680pF) on +GFX_CORE, place close to CPU

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3 3

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2012/04/19 2015/04/19

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

HW-PIR

53 53Tuesday, October 16, 2012

E

1.0

of

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