Toshiba Satellite C50 Schematics
5
4
3
2
1
SYSTEM PAGE REF.
01. Block Diagram
02. System Setting
03. CPU(1)_DMI,PEG,FDI
04. CPU(2)_CLK,MISC,JTAG,DDI
05. CPU(3)_DDR3
06. CPU(4)_PROCESSOR POWER
07. CPU(5)_***
08. CPU(6)_GND
09. CPU(7)_RESERVED
10. CPU_PCH_XDP
D D
16. DDR3(1)_SO-DIMM0
17. DDR3(2)_SO-DIMM1
18. DDR3(3)_CA/DQ Voltage
20. PCH(1)_SATA,IHDA,RTC
21. PCH(2)_CLK,SMB,PEG,LPC
22. PCH(3)_FDI,DMI,SYS PWR
23. PCH(4)_DP,PCI,CRT
24. PCH(5)_PCIE,NVRAM,USB
25. PCH(6)_CPU,GPIO,MISC
26. PCH(7)_POWER,GND
27. PCH(8)_POWER,GND
28. PCH(9)_SPI,SMB
30. EC_IT8528
31. TP / Keyboard
32. RST_Reset Circuit
33 LAN-QCA8171/72
34. LAN_RJ45
36. AUD(1)_92HD95
37. AUD(2)_HP/MIC JACK
40. CB(1)_AU6465
44. BUG_Debug
45. LVDS_output
46 CRT CON
48. TV(1)_HDMI
50. THERMAL / FAN
C C
51. SATA HDD/ODD
52. USB JACK
53. MINICARD_WLAN
56. LED
57. DSG_Discharge
60. DC_DC/BAT CONN
65. ME_CONN,Skew Hole
70.VGA-PCIE
71.VGA-N14-FRAME BUFFER
72.VGA-RGB,XTAL
73.VGA-LVDS_HDMI
74.VGA-GPIO,STRAP
75.VGA-Power,GND
76.VGA-FBA_HYNIX DDR3 [31:0]
77.VGA-FBA_HYNIX DDR3 [63:32]
80_POWER_VCORE
81_POWER_SYSTEM
82_POWER_ +1.05VS
83_POWER_DDR & VTT
84_POWER_1.5VS
86_POWER_***
87_POWER_VGA_VCORE
88_POWER_CHARGER
89_POWER_****
90_POWER_DETECT
91_POWER_LOAD SWITCH
B B
92_POWER_PROTECT
93_POWER_SIGNAL
94_POWER_FLOWCHART
95. POWER_ HISTORY
Panel
Touchpad and Keyboard
LVDS
Page 45
AUDIO Jack
RJ45
Page 35
A01 Power SW
A03 TP
A04 IO_USB
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A A
5
PT10SG platform Rev1.1
N14P-GV2
Page 70
eDP to LVDS
eDP
RTD2132
Page 45
HDMI
Page 48
DDIC
CRT
Page 46
Debug Conn.
ITE IT8528
Analog Fan
Page 50
Codec
Page 37
ID92HD95
MiniCard
WLAN + BT3.0
LAN
AR8172/AR8171
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4
PCIE x8
CRT
Page 44
Page 30Page 31
Page 36
Page 53
Page 33~34
BLOCK DIAGRAM
CPU
Haswell
FDI x 2
LPC
PCH
Lynx Point
SPI ROM
Page 28
PCIE
SATA
Azalia
3
9
USB 2.0
4
3
DDR3 1600MHz
Page 3~9
DMI x4
USB 2.0
Page 20~28
4
HDD
Page 51
5
ODD
Page 51
Discharge Circuit
Reset Circuit
Page 57
Page 32
DDR3L SO-DIMM x 2
0
1
1
2
2
3
4
USB 3.0
USB 3.0
Touch Panel
(Reserved)
5
8
DC & BATT. Conn.
Camera
Card Reader
Skew Holes
2
Page 60
Page 65
Page 16~18
USB Port(left front)
USB Port(left back)
USB 2.0(right front)
USB 2.0(right back)
Page 45
Page 54
Page 40
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet
Date: Sheet
Page 52
Page 52
Page 52
Page 52
Power
+VCORE
+VGFX_CORE
System (5V & 3.3V)
DDR & VCCP
VCCSA & VTT
+1.8VS
+VGA_VCORE
BATTERY CHARGER
DETECT
LOAD SWITCH
Power Protect
PT10SG
PT10SG
PT10SG
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
Page 80
Page 81
Page 82
Page 83
Page 84
Page 87
Page 88
Page 90
Page 91
Page 92
Block Diagram
Block Diagram
Block Diagram
Ruby Tsai
Ruby Tsai
Ruby Tsai
1 104Tuesday, February 26, 2013
1 104Tuesday, February 26, 2013
1 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
5
4
3
2
1
PCH_CPT
GPIO
D D
C C
B B
PCH_CPT
GPIO
GPIO 00
GPIO 01
GPIO 02
GPIO 03 SATA_ODD_DA#
GPIO 04
GPIO 05
GPIO 06
GPIO 07
GPIO 08
GPIO 09
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22
GPIO 23
GPIO 24
GPIO 25
GPIO 26
GPIO 27
GPIO 28
GPIO 29
GPIO 30
GPIO 31
GPIO 33
GPIO 34
GPIO 35
GPIO 36
GPIO 37
GPIO 38
GPIO 39
GPIO 40
GPIO 41
GPIO 42
GPIO 43
GPIO 44
GPIO 45
GPIO 46
GPIO 47
GPIO 48
GPIO 49
GPIO 50
GPIO 51
GPIO 52
GPIO 53
GPIO 54
GPIO 55
GPIO 56
GPIO 57
GPIO 58
GPIO 59
GPIO 60
GPIO 61
GPIO 62
GPIO 63
GPIO 64
GPIO 65
GPIO 66
GPIO 67
GPIO 68
GPIO 69
GPIO 70
GPIO 71 +3VS
GPIO 72
GPIO 73
GPIO 74 SML1_ALERT#
Signal Name PowerUse As
PCB_ID2 EXT PD REV PU +3VS
PCB_ID3
PCB_ID10
PCB_ID11
PCB_ID4
PCB_ID5
GPIO8
PM_LANPHY_EN
GPIO16
DGPU_PWROK
BBS_BIT0_R
CLK_REQ_WLAN# +3VS
SATA_DET0_R_N
BT_ON/OFF#
AC_PRESENT_R
+15.7V_PWRGD
PCB_ID0
PCB_ID1
OC3#/GPIO42
CLK_TV_REQ#
PCB_ID6
DGPU_HOLD_RST#
BBS_BIT1
PCB_ID9
STP_A16OVR
CLK_REQ_PEG_B#
GPIO57
SML1_CLK
PM_SUS_STAT#
SUSCLK_C
SLP_S5#
KB_LED_ID
CLK_USB48_CR_R
PCB_ID14
PCB_ID12
SATA_ODD_PWRGT
LNB_EN
PCB_ID7
GPIO72
CLK_REQ0# +3VSUS_ORGEXT PU
SML1_DATGPIO 75
Internal &
External
Pull-up/down
EXT PD REV PU +3VS
REV PU REV PD
EXT PU
REV PU REV PD
EXT PU REV PDPCB_ID8
EXT PU REV PD
EXT PU
EXT PUOC6#/GPIO10
EXT PU +3VSUS_ORG
EXT PU
EXT PU
EXT PU CLK_REQ1#
REV PU REV PD
EXT PU REV PD
EXT PU
EXT PDWLAN_LED
T2133SNN_LPC_DRQ#1
EXT PU REV PD
EXT PUCLK_REQ4#
REV PUGPIO27
T2205SLP_WLAN#
T2001HDA_DOCK_EN#
EXT PU
EXT PDGPIO36
EXT PD REV PUFDI_OVRVLTG
EXT PD REV PU
REV PU EXT PD
EXT PU
EXT PU
EXT PU
EXT PU
EXT PU
EXT PU
EXT PU
EXT PU
REV PU REV PD
EXT PU
EXT PU
REV PU REV PD
REV PU REV PD
REV PU
EXT PU
REV PD
EXT PU
REV PU
EXT PU
EXT PU
EXT PU
T2203
REV PD
T2204
T2111
EXT PU REV PD
REV PU REV PD
REV PU
EXT PU
REV PU REV PD
EXT PU REV PD
EXT PU
EXT PU
+3VS
+3VS
+3VS
+3VS
+3VS
+3VSREV PU REV PD
+3VSUS_ORGREV PU REV PD
+3VSUS_ORGOC5#/GPIO9
+3VSUS_ORG
+3VSUS_ORGEXT PUSMLA_ALERT#
+3VSUS_ORGEXT_SCI#
+3VSUS_ORGEXT PUOC7#/GPIO14
+3VSUS+ORGEXT PUEXT_SMI#
+3VS
+3VSEXT PU
+3VS
+3VS
+3VS
+3VSUS+ORG
+3VSUS_ORGEXT PU REV PDCLK_REQ_LAN#
+3VSUS_ORG
+VCCDSW
+3VSUS_ORGEXT PUWLAN_ON
+3VSUS_ORGEXT PUSUS_PWR_ACK_R
+VCCDSWEXT PU
+3VS
+3VSEXT PUCRT_IN#
+3VS
+3VS
+3VS
+3VSUS_ORGOC1#/GPIO40
+3VSUS_ORGOC2#/GPIO41
+3VSUS_ORG
+3VSUS_ORGOC4#/GPIO43
+3VSUS_ORG
+3VSUS_ORGCLK_REQ6#
+3VSUS_ORGCLK_REQ7#
+3VSUS_ORGCLKREQ_PEG#
+3VS
+3VSSATA_ODD_PRSNT#_R
+3VS
+3VS
+3VS
+3VSDGPU_PWM_SELECT#
+3VSVGA_PWRON
+3VSUS_ORG
+3VSUS_ORG
+3VSUS_ORG
+3VSUS_ORGOC0#/GPIO59
+3VSUS_ORGDRAMRST_CNTRL_PCH
+3VS
+3VS
+3VS
+3VS
+3VSGPIO70
+VCCDSW
+3VSUS_ORG
+3VSUS_ORGEXT PU
EC
ITE8528
Use AsEC GPIO
PWR_WHITE_LED#GPA0
GPA1
GPA2
GPA4 FB_CLAMP_TGL_REQ#
GPA5 CHGCB2#
GPA6
GPA7
GPB3
GPB4
GPB6 RCIN#
GPC0
GPC1
GPC2
GPC3
GPC6
GPC7
GPD0 PM_SUSB#
GPD2
GPD3
GPD4 EXT_SMI#
GPD6
GPD7
GPE2
GPE3
GPE4
GPE6
GPE7
GPF1 ME_SUSPWRDNACK
GPF2
GPF3
GPF5 TP_DAT
GPF6
GPF7
GPG1
GPG2
GPG6
GPH0
GPH1
GPH2
GPH3
GPH4
GPH5
GPH6
GPI0
GPI1
GPI2
GPI3
GPI4
GPI5
GPI6
GPI7
GPJ0
GPJ1
GPJ2
GPJ3
GPJ4
GPJ5
GPJ6
GPJ7
BAT_ORG_LED#
AOAC_RST#(test point)
DC_IN_LED#GPA3
THERM_ALERT#_EC
PCH_FLASH_DESCRIPTOR
NUM_LED#GPB0
CAP_LED#GPB1
THRO_CPUGPB2
SMB0_CLK
SMB0_DAT
A20GATEGPB5
PM_RSMRST#GPB7
RF_ON(Test point)
SMB1_CLK
SMB1_DAT
KSO16
AC_IN_OCGPC4
KSO17GPC5
BAT1_IN_OC#
ME_AC_PRESENT
PM_SUSC#GPD1
BUF_PLT_RST#
EXT_SCI#
PM_PWROKGPD5
FAN0_TACH
USBP01_EN
VSUS_ONGPE0
SUSC_EC#GPE1
SUSB_EC#
CPU_VRON
PWR_SW#_M
USB_OC01#_ECGPE5
LID_SW#
USB_OC2#_EC
BAT_LEARNGPF0
PM_PWRBTN#
SUSACK#(Test_point)
TP_CLKGPF4
H_PECI_EC
LCD_BACKOFF#
HDMI_HPD_MGPG0
FDIO2(Test point)
AOAC_PWREN(Test point)
FDIO3(Test point)
PM_CLKRUN#
CHGCB0#
CHGCB1#
SPI_CS#1
SPI_CLK
SPI_SO
SPI_SI
AD_IINP
SUS_PWRGD
ALL_SYSTEM_PWRGD
VRM_PWRGD
ADAPT_AD
EC_SLP_SUS#(Test point)
WLAN_WAKE#(Test point)
IMON(Test point)
HDIO2(Test point)
HDIO3(Test point)
OP_SD#
USBSLP_EN
FB_CLAMP
CTL_FAN
SW_RTCRST
BACK_EN
Signal Name
LAD0 LPC_AD0
LAD1
LAD2
LAD3
LCLK
LFRAME#
LRESET#
SERIRQ
WRST#
PECI H_PECI_EC
FSCK SCK
FMISO SO
FMOSI SI
FSCE# SCE#
KSI0 KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
@
N/A
/UMA
/VGA
/DSC
/UMA/VGA
/VGA/DSC
/EMI
@/EMI
/Giga
/EMIGiga
/10_100
/CRT/UMA/VGA
/CRT/DSC
/LVDS/UMA/VGA
/LVDS/DSC
/HDMI
/HDMI/UMA/VGA
/HDMI/DSC
/USB3.0_U
/USB2.0_U
/USB3.0
/USB2.0
/USBSLP
/NON-USBSLP
/TP_A
/TP_B
/WOWL
/non-WOWL non wake on WLAN
LPC_AD1
LPC_AD2
LPC_AD3
CLK_KBCPCI_PCH
LPC_FRAME#
BUF_PLT_RST#
INT_SERIRQ
EC_RST#
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
UMA only
Optimus only
discrete only
都都都都都都都都都都都都
UMA,Optimus
Optimus,Discrete
EMI
都都都都都都都都
EMI
預預預預預預預預預預預預預預預預都都都都
Giga
都都都都都都都都要要要要
Giga EMI
都都都都都都都都要要要要
/10_100 transformer
CRT
在在在在
UMA,Optimus
CRT Discrete only
LVDS
在在在在
UMA,Optimus
LVDS Discrete only
HDMI
都都都都都都都都
HDMI
在在在在
UMA,Optimus
HDMI Discrete only
Right Up
都都都都都都都都
USB3.0
Right Up
都都都都都都都都
USB2.0
Right down
都都都都都都都都
USB3.0
都都都都都都都都
USB2.0
Right down
USB sleep charge
USB sleep don't charge
TouchPad Type A
TouchPad Type B
wake on WLAN
都都都都都都都都都都都都
都都都都都都都都
都都都都都都都都
都都都都都都都都
都都都都都都都都
都都都都都都都都
都都都都都都都都
Signal NameUse AsEC Name
SM_BUS ADDRESS :
SM-Bus Device
SO-DIMM 0
SO-DIMM 1
PCIE 1
NC
NC
PCIE 2
Minicard WLAN
PCIE 3
LAN
PCIE 4
NC
PCIE 5
NC
PCIE 6
PCIE 7
NC
PCIE 8
NC
NC
SATA0
SATA1
NC
SATA2
NC
SATA3
NC
SATA HDDSATA4
SATA5
SATA ODD
USB3 1 USB3.0 Port (1)
USB3.0 Port (2)USB3 2
NC
USB3 3
NC
USB3 4
NC
USB3 5
NC
USB3 6
SM-Bus Address
1010000x ( A0h )
1010001x ( A4h )
USB2.0 Port(Reserved)
USB 0
USB2.0 Port(debug)
USB 1
USB3.0 Port (1)
USB 2
USB3.0 Port (2)
USB 3
Touch Panel (reserved)
USB 4
Camera
USB 5
NC
USB 6
NC
USB 7
Card Reader
USB 8
USB 9
WiFi/WiMax
NC
USB 10
NC
USB 11
NC
USB 12
NC
USB 13
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A A
Title :
Title :
Title :
System Setting
System Setting
System Setting
Engineer:
Ruby Tsai
Engineer:
Ruby Tsai
Engineer:
BG1\COR E
BG1\COR E
BG1\COR E
Size Project Name
Size Project Name
Size Project Name
D
D
D
PT10SG
PT10SG
PT10SG
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
Ruby Tsai
2 104Tuesday, Feb ruary 26, 201 3
2 104Tuesday, Feb ruary 26, 201 3
2 104Tuesday, Feb ruary 26, 201 3
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
5
4
3
2
1
+VCCIOA_OUT
U0301A
D D
C C
B B
DMI_TXN022
DMI_TXN122
DMI_TXN222
DMI_TXN322
DMI_TXP022
DMI_TXP122
DMI_TXP222
DMI_TXP322
DMI_RXN022
DMI_RXN122
DMI_RXN222
DMI_RXN322
DMI_RXP022
DMI_RXP122
DMI_RXP222
DMI_RXP322
FDI_CSYNC22
FDI_INT22
D21
C21
B21
A21
D20
C20
B20
A20
D18
C17
B17
A17
D17
C18
B18
A18
H29
J29
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
FDI_CSYNC
DISP_INT
Haswell rPGA EDS
DMI FDI
PEG_RCOMP
PEG_RXN_10
PEG_RXN_11
PEG_RXN_12
PEG_RXN_13
PEG_RXN_14
PEG_RXN_15
PEG
PEG_RXP_10
PEG_RXP_11
PEG_RXP_12
PEG_RXP_13
PEG_RXP_14
PEG_RXP_15
PEG_TXN_10
PEG_TXN_11
PEG_TXN_12
PEG_TXN_13
PEG_TXN_14
PEG_TXN_15
PEG_RXN_0
PEG_RXN_1
PEG_RXN_2
PEG_RXN_3
PEG_RXN_4
PEG_RXN_5
PEG_RXN_6
PEG_RXN_7
PEG_RXN_8
PEG_RXN_9
PEG_RXP_0
PEG_RXP_1
PEG_RXP_2
PEG_RXP_3
PEG_RXP_4
PEG_RXP_5
PEG_RXP_6
PEG_RXP_7
PEG_RXP_8
PEG_RXP_9
PEG_TXN_0
PEG_TXN_1
PEG_TXN_2
PEG_TXN_3
PEG_TXN_4
PEG_TXN_5
PEG_TXN_6
PEG_TXN_7
PEG_TXN_8
PEG_TXN_9
PEG_TXP_0
PEG_TXP_1
PEG_TXP_2
PEG_TXP_3
PEG_TXP_4
PEG_TXP_5
PEG_TXP_6
PEG_TXP_7
PEG_TXP_8
PEG_TXP_9
PEG_TXP_10
PEG_TXP_11
PEG_TXP_12
PEG_TXP_13
PEG_TXP_14
PEG_TXP_15
E23
M29
K28
M31
L30
M33
L32
M35
L34
E29
D28
E31
D30
E35
D34
E33
E32
L29
L28
L31
K30
L33
K32
L35
K34
F29
E28
F31
E30
F35
E34
F33
D32
H35
H34
J33
H32
J31
G30
C33
B32
B31
A30
B29
A28
B27
A26
B25
A24
J35
G34
H33
G32
H31
H30
B33
A32
C31
B30
C29
B28
C27
B26
C25
B24
PEG_COMP
PCIENB_RXN7
PCIENB_RXN6
PCIENB_RXN5
PCIENB_RXN4
PCIENB_RXN3
PCIENB_RXN2
PCIENB_RXN1
PCIENB_RXN0
PCIENB_RXP7
PCIENB_RXP6
PCIENB_RXP5
PCIENB_RXP4
PCIENB_RXP3
PCIENB_RXP2
PCIENB_RXP1
PCIENB_RXP0
PEG_TXN8_C
PEG_TXN9_C
PEG_TXN10_C
PEG_TXN11_C
PEG_TXN12_C
PEG_TXN13_C
PEG_TXN14_C
PEG_TXN15_C
PEG_TXP8_C
PEG_TXP9_C
PEG_TXP10_C
PEG_TXP11_C
PEG_TXP12_C
PEG_TXP13_C
PEG_TXP14_C
PEG_TXP15_C
C0309 0.22UF/10V /VGA/DSC
C0310 0.22UF/10V /VGA/DSC
C0311 0.22UF/10V /VGA/DSC
C0312 0.22UF/10V /VGA/DSC
C0313 0.22UF/10V /VGA/DSC
C0314 0.22UF/10V /VGA/DSC
C0315 0.22UF/10V /VGA/DSC
C0316 0.22UF/10V /VGA/DSC
C0325 0.22UF/10V /VGA/DSC
C0326 0.22UF/10V /VGA/DSC
C0327 0.22UF/10V /VGA/DSC
C0328 0.22UF/10V /VGA/DSC
C0329 0.22UF/10V /VGA/DSC
C0330 0.22UF/10V /VGA/DSC
C0331 0.22UF/10V /VGA/DSC
C0332 0.22UF/10V /VGA/DSC
1 2
R0301 24.9Ohm1%
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
PCIENB_RXN[7:0] 70
PCIENB_RXP[7:0] 70
+VCCIOA_OUT
+VCCIOA_OUT 4,6
PEG Compensation
Enable PCIE Lane Reversal
Need to PD CFG[2]
PCIEG_TXN7 70
PCIEG_TXN6 70
PCIEG_TXN5 70
PCIEG_TXN4 70
PCIEG_TXN3 70
PCIEG_TXN2 70
PCIEG_TXN1 70
PCIEG_TXN0 70
PCIEG_TXP7 70
PCIEG_TXP6 70
PCIEG_TXP5 70
PCIEG_TXP4 70
PCIEG_TXP3 70
PCIEG_TXP2 70
PCIEG_TXP1 70
PCIEG_TXP0 70
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SOCKET_947P
12V012BSM001
A A
5
4
If Support PCIE Gen3, change AC Cap to 0.22uF
3
Title :
Title :
Title :
Engineer:
Engineer:
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
PT10SG
PT10SG
PT10SG
Engineer:
CPU(1)_DMI,PEG,FDI
CPU(1)_DMI,PEG,FDI
CPU(1)_DMI,PEG,FDI
Ruby Tsai
Ruby Tsai
Ruby Tsai
3 104Tuesday, February 26, 2013
3 104Tuesday, February 26, 2013
3 104Tuesday, February 26, 2013
of
of
1
of
Rev
Rev
Rev
1.1
1.1
1.1
5
CPU(2)_CLK,MISC,JTAG,DDI
CPU(2)_CLK,MISC,JTAG,DDI
CPU(2)_CLK,MISC,JTAG,DDI
4
3
2
1
+VCCIO_OUT
EDP_HPD#
+1.35V_VCCDDQ
+3VSUS
+3V
+1.05VS
+VCCIOA_OUT
+VCCIO_OUT
10KOhm
R0489
1 2
3
D
Q0404
2N7002
1
G
S
2
pull down 100K ohm at P.45
0917 Ken
U0301H
Haswell rPGA EDS
MISC
PWR
CLOCKTHERMAL
Haswell rPGA EDS
DDI
eDP
SM_RCOMP_0
SM_RCOMP_1
SM_RCOMP_2
DDR3
SM_DRAMRST#
JTAG
BPM_N_0
BPM_N_1
BPM_N_2
BPM_N_3
BPM_N_4
BPM_N_5
BPM_N_6
BPM_N_7
EDP_AUXN
EDP_AUXP
EDP_HPD
EDP_RCOMP
EDP_DISP_UTIL
EDP_TXN_0
EDP_TXP_0
EDP_TXN_1
EDP_TXP_1
FDI_TXN_0
FDI_TXP_0
FDI_TXN_1
FDI_TXP_1
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
1 2
12
12
12
DP0_AUXN 45
DP0_AUXP 45
DP_L0N_APU 45
DP_L0P_APU 45
FDI_TXN0 22
FDI_TXP0 22
FDI_TXN1 22
FDI_TXP1 22
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
+VCCIOA_OUT
1
T0421
Ruby 0925
CPUDRAMRST# 5
T0403
T0404
T0405
T0406
T0407
T0408
T0409
T0410
T0411
T0412
T0413
T0414
T0415
T0416
T0417
T0418
AP3
SM_RCOMP_0
AR3
SM_RCOMP_1
AP2
SM_RCOMP_2
AN3
AR29
AT29
AM34
AN33
AM33
AM31
TDI
AL33
AP33
AR30
AN31
AN29
AP31
AP30
AN28
AP29
AP28
M27
N27
P27
E24
R27
P35
R35
N34
P34
P33
R33
N32
P32
XDP_PRDY#
XDP_PREQ#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_TDI
XDP_TDO
XDP_DBRESET#
XDP_BPM0
XDP_BPM1
XDP_BPM2
XDP_BPM3
XDP_BPM4
XDP_BPM5
XDP_BPM6
XDP_BPM7
DP_COMP
EDP_DISP_UTIL
R0418 100Ohm1%
R0419 75Ohm1%
R0420 100Ohm1%
EDP_HPD#
R0402 24.9Ohm1%
1
T0401
1
T0402
1 2
R0404 62Ohm
+VCCIO_OUT
Stuff R0408
D D
Intel MOW WW14: stuff
H_CPUPWRGD PD 10Kohm
CLK_DP_SSC _P_R
CLK_DP_SSC _N_R
C C
VCCST
XDP_TDO
XDP_TCK
XDP_TRST#
XDP_DBRESET#
R1.1
/DSC
1 2
R0445 10KOhm
1 2
R0446 10KOhm
/DSC
1 2
R0414 51Ohm
1 2
R0441 51Ohm
1 2
R0442 51Ohm
1 2
R0424 1KOhm@
H_PECI25
H_THRMTR IP#25,32
H_PM_SYNC22
H_CPUPW RGD25
PCH_PLTRS T_CPU25
CLK_DP_N21
CLK_DP_P21
CLK_DP_SSC _N21
CLK_DP_SSC _P21
CLK_EXP_N21
CLK_EXP_P21
+VCCIO_OUT
SSC CLOCK TERMINATION
Stuff R0445 & R0446 only when SSC clock not used
+1.05VS
+3VS
1 2
VCCST
R0488 0Ohm@
1 2
R0403 56Ohm
SP0401 R 0402
12
R040810KOhm
1 2
R0460 0Ohm
1 2
R0426 0Ohm
1 2
R0425 0Ohm
1 2
R0431 0Ohm
1 2
R0430 0Ohm
1 2
R0423 0Ohm
1 2
R0422 0Ohm
HDMI_TXN2_PCH48
HDMI_TXP2_PCH48
HDMI_TXN1_PCH48
HDMI_TXP1_PCH48
HDMI_TXN0_PCH48
HDMI_TXP0_PCH48
HDMI_CLKN_PC H48
HDMI_CLKP_PCH48
DDI Port B: N/A
DDI Port C: HDMI
DDI Port D: N/A
DDI signals Mapping, check 497750
12
12
SP0402R0 402
12
SP0403R0402
TP_SKTOCC# _R
TP_CATERR# _R
H_PROCHOT# _DH_PROCHOT#
H_THRMTR IP#_R
H_PM_SYNC_R
H_CPUPW RGD_R
VDDPWRGOOD_ R
BUF_CPU_RST #
CLK_DP_N_R
CLK_DP_P_R
CLK_DP_SSC _N_R
CLK_DP_SSC _P_R
CLK_EXP_N_R
CLK_EXP_P_R
DPC_TXN2
DPC_TXP2
DPC_TXN1
DPC_TXP1
DPC_TXN0
DPC_TXP0
DPC_CLKN
DPC_CLKP
U0301B
AP32
SKTOCC#
AN32
CATERR#
AR27
PECI
AK31
FC1
AM30
PROCHOT#
AM35
THERMTRIP#
AT28
PM_SYNC
AL34
PWRGOOD
AC10
SM_DRAMPWROK
AT26
PLTRSTIN#
G28
DPLL_REF_CLKN
H28
DPLL_REF_CLKP
F27
SSC_DPLL_REF_CLKN
E27
SSC_DPLL_REF_CLKP
D26
BCLKN
E26
BCLKP
SOCKET_947P
12V012BSM001
T28
U28
T30
U30
U29
V29
U31
V31
T34
U34
U35
V35
U32
T32
U33
V33
P29
R29
N28
P28
P31
R31
N30
P30
SOCKET_947P
12V012BSM001
DDIB_TXBN_0
DDIB_TXBP_0
DDIB_TXBN_1
DDIB_TXBP_1
DDIB_TXBN_2
DDIB_TXBP_2
DDIB_TXBN_3
DDIB_TXBP_3
DDIC_TXCN_0
DDIC_TXCP_0
DDIC_TXCN_1
DDIC_TXCP_1
DDIC_TXCN_2
DDIC_TXCP_2
DDIC_TXCN_3
DDIC_TXCP_3
DDID_TXDN_0
DDID_TXDP_0
DDID_TXDN_1
DDID_TXDP_1
DDID_TXDN_2
DDID_TXDP_2
DDID_TXDN_3
DDID_TXDP_3
+VCCIO_OUT 6,32,57
+1.35V_VCCDDQ 6
+3VSUS 22,23,27,28,30,3 3,37,53,81,92
+3V 23,44,45,57,91
+1.05VS 26,27,32,57,80,8 2
+VCCIOA_OUT 3,6
https://t.me/schematicslaptop
https://t.me/biosarchive
EDP_HPD
eDP_HPD 45
Ruby 0925
B B
1 2
R0486 0Ohm@
H_PROCHOT#
R1.1 Add PWRLIMIT#
Q0401
2N7002
3
D
1
THRO_CPU
G
S
2
THRO_CPU 30
https://t.me/biosarchive
https://t.me/schematicslaptop
https://t.me/schematicslaptop
PM_DRAM_PW RGD22
Intel MOW WW14:
change R0449, R0450 va lue
R1.1
+1.35V_VCCDDQ
0.87 Volt
3.3KOhm
R0450
12
12
R0449
1.8KOHM
1 2
R0451 0Ohm
VR_HOT#80
VDDPWRGOOD_ R
https://t.me/biosarchive
A A
Power good for +1.35V_VCCDDQ (delay > 15ns)
Processor may be damaged if VIH exceeds the maximum voltage for extended periods.
SM_DRAMPWROK VIH MAX = 1.0V ; VIH MIN=0.45*VDDQ
5
4
0919 Ken
Title :
Title :
Title :
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
2
Date: Sheet
Ruby Tsai
Ruby Tsai
Ruby Tsai
4 104Tuesday, February 26, 2013
4 104Tuesday, February 26, 2013
4 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
5
4
+1.35V
3
+1.35V 6,16,18,57,83
2
1
M_A_D[63:0]16
D D
C C
DIMM_VREF_CA1 8
DIMM0_VREF_DQ18
B B
DIMM1_VREF_DQ18
Remove power reduction circuit
0928 Ruby
CPU driven VREF path is stuffed by default
CRB 0.7
DDR_CA_VREF
DDR_WR_VREF01
DDR_WR_VREF02
M_A_D0
M_A_D1
M_A_D2
M_A_D3
M_A_D4
M_A_D5
M_A_D6
M_A_D7
M_A_D8
M_A_D9
M_A_D10
M_A_D11
M_A_D12
M_A_D13
M_A_D14
M_A_D15
M_A_D16
M_A_D17
M_A_D18
M_A_D19
M_A_D20
M_A_D21
M_A_D22
M_A_D23
M_A_D24
M_A_D25
M_A_D26
M_A_D27
M_A_D28
M_A_D29
M_A_D30
M_A_D31
M_A_D32
M_A_D33
M_A_D34
M_A_D35
M_A_D36
M_A_D37
M_A_D38
M_A_D39
M_A_D40
M_A_D41
M_A_D42
M_A_D43
M_A_D44
M_A_D45
M_A_D46
M_A_D47
M_A_D48
M_A_D49
M_A_D50
M_A_D51
M_A_D52
M_A_D53
M_A_D54
M_A_D55
M_A_D56
M_A_D57
M_A_D58
M_A_D59
M_A_D60
M_A_D61
M_A_D62
M_A_D63
AR15
AT14
AM14
AN14
AT15
AR14
AN15
AM15
AM9
AN9
AM8
AN8
AR9
AR8
AJ10
AK10
AG4
AG5
AG1
AG2
AM3
AT9
AT8
AJ9
AK9
AJ6
AK6
AJ7
AK7
AF4
AF5
AF1
AF2
J1
J2
J5
H5
H2
H1
J4
H4
F2
F1
D2
D3
D1
F3
C3
B3
B5
E6
A5
D6
D5
E5
B6
A6
E12
D12
B11
A11
E11
D11
B12
A12
F16
F13
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
SM_VREF
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Haswell rPGA EDS
U0301C
RSVD_AC7
SA_CK_N_0
SA_CK_P_0
SA_CKE_0
SA_CK_N_1
SA_CK_P_1
SA_CKE_1
SA_CK_N_2
SA_CK_P_2
SA_CKE_2
SA_CK_N_3
SA_CK_P_3
SA_CKE_3
SA_CS_N_0
SA_CS_N_1
SA_CS_N_2
SA_CS_N_3
SA_ODT_0
SA_ODT_1
SA_ODT_2
SA_ODT_3
SA_BS_0
SA_BS_1
SA_BS_2
VSS1
SA_RAS#
SA_WE#
SA_CAS#
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
SA_MA_15
SA_DQS_N_0
SA_DQS_N_1
SA_DQS_N_2
SA_DQS_N_3
SA_DQS_N_4
SA_DQS_N_5
SA_DQS_N_6
SA_DQS_N_7
SA_DQS_P_0
SA_DQS_P_1
SA_DQS_P_2
SA_DQS_P_3
SA_DQS_P_4
SA_DQS_P_5
SA_DQS_P_6
SA_DQS_P_7
SOCKET_947P
12V012BSM001
AC7
U4
V4
AD9
U3
V3
AC9
U2
V2
AD8
U1
V1
AC8
M7
L9
M9
M10
M8
L7
L8
L10
V5
U5
AD1
V10
U6
U7
U8
V8
AC6
V9
U9
AC5
AC4
AD6
AC3
AD5
AC2
V6
AC1
AD4
V7
AD3
AD2
AP15
AP8
AJ8
AF3
J3
E2
C5
C11
AP14
AP9
AK8
AG3
H3
E3
C6
C12
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_B_D[63:0]17
M_A_DIM0_CLK#0 16
M_A_DIM0_CLK0 16
M_A_DIM0_CKE0 16
M_A_DIM0_CLK#1 16
M_A_DIM0_CLK1 16
M_A_DIM0_CKE1 16
M_A_DIM0_CS#0 16
M_A_DIM0_CS#1 16
M_A_DIM0_ODT0 16
M_A_DIM0_ODT1 16
M_A_BS0 16
M_A_BS1 16
M_A_BS2 16
R1.10
M_A_RAS# 16
M_A_WE# 16
M_A_CAS# 16
M_A_A[15:0] 16
R1.10
M_A_DQS#[7:0] 16
M_A_DQS[7:0] 16
M_B_D0
M_B_D1
M_B_D2
M_B_D3
M_B_D4
M_B_D5
M_B_D6
M_B_D7
M_B_D8
M_B_D9
M_B_D10
M_B_D11
M_B_D12
M_B_D13
M_B_D14
M_B_D15
M_B_D16
M_B_D17
M_B_D18
M_B_D19
M_B_D20
M_B_D21
M_B_D22
M_B_D23
M_B_D24
M_B_D25
M_B_D26
M_B_D27
M_B_D28
M_B_D29
M_B_D30
M_B_D31
M_B_D32
M_B_D33
M_B_D34
M_B_D35
M_B_D36
M_B_D37
M_B_D38
M_B_D39
M_B_D40
M_B_D41
M_B_D42
M_B_D43
M_B_D44
M_B_D45
M_B_D46
M_B_D47
M_B_D48
M_B_D49
M_B_D50
M_B_D51
M_B_D52
M_B_D53
M_B_D54
M_B_D55
M_B_D56
M_B_D57
M_B_D58
M_B_D59
M_B_D60
M_B_D61
M_B_D62
M_B_D63
AR18
AT18
AM17
AM18
AR17
AT17
AN17
AN18
AT12
AR12
AN12
AM11
AT11
AR11
AM12
AN11
AR5
AR6
AM5
AM6
AN5
AN6
AK4
AM1
AN1
AK2
AK1
AT5
AT6
AJ4
AJ1
AJ2
G10
E15
D15
A15
B15
E14
D14
A14
B14
J10
L2
M2
L4
M4
L1
M1
L5
M5
G7
J8
G8
G9
J7
J9
A8
B8
A9
B9
D8
E8
D9
E9
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
Haswell rPGA EDS
U0301D
RSVD1
SB_CKN0
SB_CK0
SB_CKE_0
SB_CKN1
SB_CK1
SB_CKE_1
SB_CKN2
SB_CK2
SB_CKE_2
SB_CKN3
SB_CK3
SB_CKE_3
SB_CS_N_0
SB_CS_N_1
SB_CS_N_2
SB_CS_N_3
SB_ODT_0
SB_ODT_1
SB_ODT_2
SB_ODT_3
SB_BS_0
SB_BS_1
SB_BS_2
VSS2
SB_RAS#
SB_WE#
SB_CAS#
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
SB_MA_15
SB_DQS_N_0
SB_DQS_N_1
SB_DQS_N_2
SB_DQS_N_3
SB_DQS_N_4
SB_DQS_N_5
SB_DQS_N_6
SB_DQS_N_7
SB_DQS_P_0
SB_DQS_P_1
SB_DQS_P_2
SB_DQS_P_3
SB_DQS_P_4
SB_DQS_P_5
SB_DQS_P_6
SB_DQS_P_7
SOCKET_947P
12V012BSM001
AG8
Y4
AA4
AF10
Y3
AA3
AG10
Y2
AA2
AG9
Y1
AA1
AF9
P4
R2
P3
P1
R4
R3
R1
P2
R7
P8
AA9
R10
R6
P6
P7
R8
Y5
Y10
AA5
Y7
AA6
Y6
AA7
Y8
AA10
R9
Y9
AF7
P9
AA8
AG7
AP18
AP11
AP5
AJ3
L3
H9
C8
C14
AP17
AP12
AP6
AK3
M3
H8
C9
C15
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DIM0_CLK#0 17
M_B_DIM0_CLK0 17
M_B_DIM0_CKE0 17
M_B_DIM0_CLK#1 17
M_B_DIM0_CLK1 17
M_B_DIM0_CKE1 17
M_B_DIM0_CS#0 17
M_B_DIM0_CS#1 17
M_B_DIM0_ODT0 17
M_B_DIM0_ODT1 17
M_B_BS0 17
M_B_BS1 17
M_B_BS2 17
R1.10
M_B_RAS# 17
M_B_WE# 17
M_B_CAS# 17
M_B_A[15:0] 17
R1.10
M_B_DQS#[7:0] 17
M_B_DQS[7:0] 17
close to SO-DIMM
https://t.me/schematicslaptop
https://t.me/biosarchive
A A
https://t.me/schematicslaptop
DDR3_DRAMRST#16,17 CPUDRAMRST# 4
https://t.me/biosarchive
5
4
0919 Ken
C0502
0.1UF/10V
R0508 0Ohm
12
@
1 2
3
Remove power reduction circuit
0928 Ruby
Title :
Title :
Title :
CPU(2)_DDR3
CPU(2)_DDR3
1
CPU(2)_DDR3
Ruby Tsai
Ruby Tsai
Ruby Tsai
of
of
of
5 104Tuesday, February 26, 2013
5 104Tuesday, February 26, 2013
5 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
Engineer:
Engineer:
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
PT10SG
PT10SG
PT10SG
Engineer:
5
4
3
2
1
https://t.me/schematicslaptop
https://t.me/biosarchive
D D
Remove S3 power reduction cir cuit
0928 Ruby
JP0601
+1.35V
C C
2
3MM_OPEN_5MIL
112
1009 Ruby remove 1/16 R1.1
12
R1.10
vx_c0805_h57_small
12
vx_c0603_small
12
@
@
C0618
C0631
22UF/6.3V
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
C0620
10UF/6.3V
vx_c0603_small
C0621
10UF/6.3V
vx_c0603_small
https://t.me/schematicslaptop
https://t.me/biosarchive
12
12
@
C0657
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
12
C0625
10UF/6.3V
vx_c0603_small
@
C0629
22UF/6.3V
@
C0603
10UF/6.3V
12
@
C0630
22UF/6.3V
vx_c0805_h57_small
12
@
C0602
10UF/6.3V
vx_c0603_small
12
12
@
C0633
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
12
@
C0626
10UF/6.3V
vx_c0603_small
vx_c0603_small
@
C0628
22UF/6.3V
@
C0622
10UF/6.3V
vx_c0603_small
12
12
@
C0658
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
12
@
C0624
10UF/6.3V
vx_c0603_small
@
C0616
22UF/6.3V
@
C0627
10UF/6.3V
12
12
@
C0632
22UF/6.3V
vx_c0805_h57_small
12
@
C0619
10UF/6.3V
vx_c0603_small
+VCORE
+1.35V_VCCDDQ
@
C0659
22UF/6.3V
Decoupling guide from Intel (EE)
VDDQ 22uF * 2pcs (stuff)
10uF * 2pcs (stuff)
330uF * 1pcs (stuff)
Decoupling guide from Intel ( EE)
+VCORE 10uF * 11pcs (stuff)
22uF * 19pcs (stuff)
470uF * 5pcs (stuff)
+VCORE
B B
12
12
C0604
C0605
22UF/6.3V
vx_c0805_h57_small
12
vx_c0805_h57_small
12
vx_c0805_h57_small
A A
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
C0634
C0635
22UF/6.3V
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
C0645
C0646
22UF/6.3V
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
C0606
22UF/6.3V
vx_c0805_h57_small
12
C0636
22UF/6.3V
vx_c0805_h57_small
12
C0647
22UF/6.3V
vx_c0805_h57_small
12
12
12
C0607
22UF/6.3V
C0637
22UF/6.3V
C0648
22UF/6.3V
12
C0608
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
C0638
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
C0649
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
VR_SVID_DATA80
12
12
12
12
C0609
22UF/6.3V
vx_c0805_h57_small
12
C0639
22UF/6.3V
vx_c0805_h57_small
12
C0650
22UF/6.3V
vx_c0805_h57_small
Placement note:
1. R0602 close to CPU
2. R0603 close to CPU
3. R0605 close to VR
4. R0608 close to CPU
5. R0607 close to VR
6. R0611 close to CPU
1 2
12
C0611
C0610
22UF/6.3V
22UF/6.3V
vx_c0805_h57_small
12
C0641
C0640
22UF/6.3V
22UF/6.3V
vx_c0805_h57_small
12
C0651
22UF/6.3V
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
R0607
130Ohm
1%
R0625 0Ohm
1 2
12
C0612
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
C0652
22UF/6.3V
vx_c0805_h57_small
vx_c0805_h57_small
12
C0654
C0655
22UF/6.3V
1 2
12
C0613
22UF/6.3V
vx_c0805_h57_small
12
C0653
22UF/6.3V
Unstuff R0622
Intel MOW WW09: renamed
VCCIO2PCH to RSVD
+VCCIO_OUT+VCCIO_OUT +VCCIO_OUT
R0608
130Ohm
1%
VR_SVID_CLK80
Power team suggestion
12
C0614
22UF/6.3V
1 2
+VCCIO_OUT
R1.10
R0605
54.9Ohm
1%
VR_SVID_ALERT#80
1 2
R0624
0Ohm
If XDP not implemented, then Route Processor PWR_DEBUG as a test point.
This Test point must be clearly labeled
(shark bay check list 497750)
R1.1
12
+VCCIOA_OUT
R0603
75Ohm
1%
+VCCIO2PCH
+VCCIO_OUT
R0621 0Ohm
R0622 0Ohm@
R0623 0Ohm
100 ohm in powe r circuit
0921 Ken
+VCCIO_OUT_R
+VCCIO2PCH_R
+VCCIOA_OUT_R
12
12
C0661
0.01UF/50V
R0602 43Ohm
T0606
T0602
T0603
T0605
T0604
1 2
VCCSENSE80
1 2
1 2
1 2
C0660
0.01UF/50V
R0620
0Ohm
T0601
Intel, 0206
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
1
1
1
1
1
VCC_SENSE_R
1
+VCORE
+1.35V_VCCDDQ
+1.35V
+VCORE
+VCCIO_OUT
+VCCIO2PCH
+VCCIOA_OUT
U0301E
K27
RSVD23
L27
RSVD22
T27
RSVD21
V27
RSVD20
AB11
VDDQ13
AB2
VDDQ12
AB5
VDDQ11
AB8
VDDQ10
AE11
VDDQ9
AE2
VDDQ8
AE5
VDDQ7
AE8
VDDQ6
AH11
VDDQ14
K11
VDDQ15
N11
VDDQ5
N8
VDDQ16
T11
VDDQ4
T2
VDDQ17
T5
VDDQ3
T8
VDDQ18
W11
VDDQ2
W2
VDDQ19
W5
VDDQ1
W8
VDDQ20
N26
RSVD19
K26
VCC103
AL27
RSVD18
AK27
RSVD24
AL35
VCC_SENSE
E17
RSVD27
AN35
VCCIO_OUT
A23
RSVD25
F22
VCOMP_OUT
W32
RSVD30
AL16
RSVD29
J27
RSVD26
AL13
RSVD28
AM28
VIDALERT#
AM29
VIDSCLK
AL28
VIDSOUT
AP35
VSS3
H27
PWR_DEBUG
AP34
VSS4
AT35
RSVD_TP4
AR35
RSVD_TP3
AR32
RSVD_TP2
AL26
RSVD_TP1
AT34
VSS5
AL22
VSS6
AT33
VSS7
AM21
VSS8
AM25
VSS9
AM22
VSS10
AM20
VSS11
AM24
VSS12
AL19
VSS13
AM23
VSS14
AT32
VSS15
Y25
VCC11
Y26
VCC10
Y27
VCC9
Y28
VCC8
Y29
VCC7
Y30
VCC6
Y31
VCC5
Y32
VCC4
Y33
VCC3
Y34
VCC2
Y35
VCC1
SOCKET_947P
12V012BSM001
+1.35V_VCCDDQ 4
+1.35V 16,18,57,83
+VCORE 9,57,80
+VCCIO_OUT 4,32,57
+VCCIO2PCH 27
+VCCIOA_OUT 3,4
Haswell rPGA EDS
VCC100
VCC99
VCC98
VCC97
VCC96
VCC95
VCC94
VCC93
VCC92
VCC91
VCC90
VCC89
VCC88
VCC87
VCC86
VCC85
VCC84
VCC83
VCC82
VCC81
VCC80
VCC79
VCC78
VCC77
VCC76
VCC75
VCC74
VCC73
VCC72
VCC71
VCC70
VCC69
VCC68
VCC67
VCC66
VCC65
VCC64
VCC63
VCC62
VCC61
VCC60
VCC59
VCC58
VCC57
VCC56
VCC55
VCC54
VCC53
VCC52
VCC51
VCC50
VCC49
VCC48
VCC102
VCC101
VCC47
VCC46
VCC45
VCC44
VCC43
VCC42
VCC41
VCC40
VCC39
VCC38
VCC37
VCC36
VCC35
VCC34
VCC33
VCC32
VCC31
VCC30
VCC29
VCC28
VCC27
VCC26
VCC25
VCC24
VCC23
VCC22
VCC21
VCC20
VCC19
VCC18
VCC17
VCC16
VCC15
VCC14
VCC13
VCC12
AA26
AA28
AA34
AA30
AA32
AB26
AB29
AB25
AB27
AB28
AB30
AB31
AB33
AB34
AB32
AC26
AB35
AC28
AD25
AC30
AD28
AC32
AD31
AC34
AD34
AD26
AD27
AD29
AD30
AD32
AD33
AD35
AE26
AE32
AE28
AE30
AG28
AG34
AE34
AF25
AF26
AF27
AF28
AF29
AF30
AF31
AF32
AF33
AF34
AF35
AG26
AH26
AH29
AG30
AG32
AH32
AH35
AH25
AH27
AH28
AH30
AH31
AH33
AH34
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
G25
H25
J25
K25
L25
M25
N25
P25
R25
T25
U25
U26
V25
V26
W26
W27
+VCORE
Cap of 470UF or more place at power schematic
Title :
Title :
Title :
CPU(4)_PWR
CPU(4)_PWR
CPU(4)_PWR
Ruby Tsai
Ruby Tsai
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Ruby Tsai
6 104Tuesday, February 26, 2013
6 104Tuesday, February 26, 2013
6 104Tuesday, February 26, 2013
of
of
of
Rev
Rev
Rev
1.1
1.1
1.1
5
D D
C C
B B
4
3
2
1
A A
Title :
Title :
Title :
CPU(4)_PWR
CPU(4)_PWR
CPU(4)_PWR
5
https://t.me/schematicslaptop
https://t.me/biosarchive
4
https://t.me/schematicslaptop
https://t.me/biosarchive
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
2
Date: Sheet
https://t.me/schematicslaptop
Ruby Tsai
Ruby Tsai
Ruby Tsai
7 104Tuesday, February 26, 2013
7 104Tuesday, February 26, 2013
7 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
https://t.me/biosarchive
5
Haswell rPGA EDS
U0301F
A10
VSS16
A13
VSS127
A16
VSS238
A19
VSS268
A22
VSS279
A25
D D
C C
B B
A A
5
A27
A29
A31
A33
AA11
AA25
AA27
AA31
AA29
AB1
AB10
AA33
AA35
AB3
AC25
AC27
AB4
AB6
AB7
AB9
AC11
AD11
AC29
AC31
AC33
AC35
AD7
AE1
AE10
AE25
AE29
AE3
AE27
AE35
AE4
AE6
AE7
AE9
AF11
AF6
AF8
AG11
AG25
AE31
AG31
AE33
AG6
AH1
AH10
AH2
AG27
AG29
AH3
AG33
AG35
AH4
AH5
AH6
AH7
AH8
AH9
AJ11
AJ5
AK11
AK25
AK26
AK28
AK29
AK30
AK32
E19
A3
A4
A7
VSS290
VSS301
VSS312
VSS323
VSS17
VSS28
VSS39
VSS50
VSS61
VSS72
VSS83
VSS94
VSS105
VSS116
VSS128
VSS139
VSS150
VSS161
VSS172
VSS183
VSS194
VSS205
VSS216
VSS227
VSS239
VSS250
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS288
VSS289
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS313
SOCKET_947P
12V012BSM001
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
AK34
AK5
AL1
AL10
AL11
AL12
AL14
AL15
AL17
AL18
AL2
AL20
AL21
AL23
E22
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AM10
AM13
AM16
AM19
E25
AM32
AM4
AM7
AN10
AN13
AN16
AN19
AN2
AN21
AN24
AN27
AN30
AN34
AN4
AN7
AP1
AP10
AP13
AP16
AP19
AP4
AP7
W25
AR10
AR13
AR16
AR19
AR2
AR22
AR25
AR28
AR31
AR34
AR4
AR7
AT10
AT13
AT16
AT19
AT21
AT24
AT27
AT3
AT30
AT4
AT7
B10
B13
B16
B19
B2
B22
4
4
3
Haswell rPGA EDS
U0301G
B34
VSS84
B4
VSS85
B7
VSS86
C1
VSS87
C10
VSS88
C13
VSS89
C16
VSS90
C19
VSS91
C2
VSS92
C22
VSS93
C24
VSS95
C26
VSS96
C28
VSS97
C30
VSS98
C32
VSS99
C34
VSS100
C4
VSS101
C7
VSS102
D10
VSS103
D13
VSS104
D16
VSS106
D19
VSS107
D22
VSS108
D25
VSS109
D27
VSS110
D29
VSS111
D31
VSS112
D33
VSS113
D35
VSS114
D4
VSS115
D7
VSS117
E1
VSS118
E10
VSS119
E13
VSS120
E16
VSS121
E4
VSS122
E7
VSS123
F10
VSS124
F11
VSS125
F12
VSS126
F14
VSS129
F15
VSS130
F17
VSS131
F18
VSS132
F20
VSS133
F21
VSS134
F23
VSS135
F24
VSS136
F26
VSS137
F28
VSS138
F30
VSS140
F32
VSS141
F34
VSS142
F4
VSS143
F6
VSS144
F7
VSS145
F8
VSS146
F9
VSS147
G1
VSS148
G11
VSS149
G2
VSS151
G27
VSS152
G29
VSS153
G3
VSS154
G31
VSS155
G33
VSS156
G35
VSS157
G4
VSS158
G5
VSS159
H10
VSS160
H26
VSS162
H6
VSS163
H7
VSS164
J11
VSS165
J26
VSS166
J28
VSS167
J30
VSS168
J32
VSS169
J34
VSS170
J6
VSS171
K1
VSS173
SOCKET_947P
3
12V012BSM001
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS_SENSE
RSVD31
K10
K2
K29
K3
K31
K33
K35
K4
K5
K7
K8
K9
L11
L26
L6
M11
M26
M28
M30
M32
M34
M6
N1
N10
N2
N29
N3
N31
N33
N35
N4
N5
N6
N7
N9
P11
P26
P5
R11
R26
R28
R30
R32
R34
R5
T1
T10
T29
T3
T31
T33
T35
T4
T6
T7
T9
U11
U27
V11
V28
V30
V32
V34
W1
W10
W3
W35
W4
W6
W7
W9
Y11
H11
AL24
F19
T26
AK35
AK33
2
1
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Placement note:
1. R0801 close to CPU
VSS_SENSE_R
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
B
B
B
Date: Sheet
Date: Sheet
2
Date: Sheet
12
R0801
0Ohm
100 ohm in power circuit
0921 Ken
PT10SG
PT10SG
PT10SG
VSSSENSE 80
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
CPU(6)_GND
CPU(6)_GND
CPU(6)_GND
Ruby Tsai
Ruby Tsai
Ruby Tsai
8 104Tuesday, February 26, 2013
8 104Tuesday, February 26, 2013
8 104Tuesday, February 26, 2013
of
of
of
Rev
Rev
Rev
1.1
1.1
1.1
5
4
3
2
1
CFG strapping information:
CFG[1:0]: Reserved configuration lane.
D D
CFG[2]: PCIE Static Numbering Lane Reversal- CFG[2] is for the 16x
- 1: (Default) Normal Operation, Lane # definition matches sockect pin map definition
- 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
CFG[4]: eDP enable
-1 = Disabled
-0 = Enabled
CFG[6:5]: PCI Express Port Bifurcation Straps
-00 = 1 x8, 2 x4 PCI Express*
-01 = reserved
-10 = 2 x8 PCI Express*
-11 = 1 x16 PCI Express*
CFG[19:7]: Reserved configuration lane.
C C
CFG2
R0902 1KOhm
CFG4
R0903 1KOhm
B B
CFG5
R0904 1KOhm@
The CFG signals have a default value of '1'
1% to 5%
JR 0924
1 2
1 2
1 2
T0903
T0904
+VCORE
12
T0901
T0902
12
T0906
T0907
T0908
T0909
T0910
T0911
T0912
T0913
T0914
T0915
T0916
T0917
T0918
T0919
T0920
T0921
R0907 49.9Ohm
R0908 49.9Ohm
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1
1
H_CPU_R SVD30
1
1
H_CPU_R SVD40
1
CFG0
1
CFG1
1
CFG2
1
CFG3
1
CFG4
1
CFG5
1
CFG6
1
CFG7
1
CFG8
1
CFG9
1
CFG10
1
CFG11
1
CFG12
1
CFG13
1
CFG14
1
CFG15
AT1
AT2
AD10
A34
A35
W29
W28
G26
W33
AL30
AL29
C35
B35
AL25
W30
W31
W34
AT20
AR20
AP20
AP22
AT22
AN22
AT25
AN23
AR24
AT23
AN20
AP24
AP26
AN25
AN26
AP25
F25
U0301I
RSVD_TP17
RSVD_TP16
RSVD2
RSVD_TP15
RSVD_TP14
RSVD_TP18
RSVD_TP19
TESTLO1
RSVD3
RSVD4
RSVD5
VCC104
RSVD_TP13
RSVD_TP12
RSVD_TP20
RSVD_TP21
RSVD_TP22
TESTLO2
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
SOCKET_ 947P
12V012B SM001
Haswell rPGA EDS
RSVD_TP11
RSVD_TP10
RSVD_TP9
RSVD_TP8
CFG_RCOMP
CFG_16
CFG_18
CFG_17
CFG_19
RSVD6
FC2
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD_TP7
RSVD_TP6
RSVD_TP5
RSVD16
RSVD17
VSS258
VSS259
C23
B23
D24
D23
AT31
CFG_RCO MP
AR21
CFG16
AR23
CFG17
AP21
CFG18
AP23
CFG19
AR33
G6
VCCST_P WRGD
AM27
AM26
F5
AM2
K6
E18
U10
P10
B1
NC
A2
AR1
E21
E20
AP27
AR26
AL31
AL32
1
T0922
1
T0923
1
T0924
1
T0925
R0912 6.04KOHM@
12
1 2
1 2
R0913
2.67KOhm
@
R091049.9Ohm
PM_PW ROK 22 ,30,92
1001 Ken
CFG6
remove CFG7 pull down resist
shark bay check list 497750
Ken
CFG9
1 2
R0905 1KOhm@
1 2
R0911 1KOhm@
+VCORE
+VCORE 6,57,80
Sighting 495482
R1.10
A A
5
4
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3
Title :
Title :
Title :
Engineer:
Engineer:
BG1/HW RD Center
BG1/HW RD Center
BG1/HW RD Center
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
PT10SG
PT10SG
PT10SG
Engineer:
CPU(7)_RESERVED
CPU(7)_RESERVED
CPU(7)_RESERVED
Ruby Tsai
Ruby Tsai
Ruby Tsai
1
Rev
Rev
Rev
1.1
1.1
9 104Tuesday, February 26, 201 3
9 104Tuesday, February 26, 201 3
9 104Tuesday, February 26, 201 3
1.1
of
of
of
5
4
3
2
1
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D D
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C C
B B
A A
Title :
Title :
Title :
CPU_PCH_XDP
CPU_PCH_XDP
CPU_PCH_XDP
Ruby Tsai
Ruby Tsai
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Ruby Tsai
10 104Tuesday, February 26, 2013
10 104Tuesday, February 26, 2013
10 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
5
+1.35V
+1.35V_DDR3
+0.675VS
+3VS
+V_VREF_CA_DIMM0
+V_VREF_DQ_DIMM0
D D
+1.35V 6,18,57,83
+1.35V_DDR3 17
+0.675VS 17,57,8 3
+3VS 4,17,20,21,22,23,25 ,26,27,28,30,31,32,36,40,4 5,46,48,50,51,53,57,91,92
+V_VREF_CA_DIMM0 17,18
+V_VREF_DQ_DIMM0 18
4
+1.35V_DDR3+1.35V
JP1601
2
112
3mm_open_5mil_m1 m2
3
Remove CE1603
0928 Ruby
Layout Note: Place these caps near SO DIMM 0
12
C1609
10UF/6.3V
12
C1610
10UF/6.3V
12
C1611
10UF/6.3V
12
C1612
10UF/6.3V
@
2
+0.675VS+1.35V_DDR3
12
C1613
10UF/6.3V
@
12
C1620
10UF/6.3V
@
12
C1616
1UF/6.3V
12
C1617
1UF/6.3V
12
C1618
1UF/6.3V
@
12
C1619
1UF/6.3V
@
1
M_A_A[15:0]5
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
1 2
1 2
SMB_CLK_S_CH A
SMB_DAT_S_CHA
M_A_A15
R1.10
M_A_DQS7
M_A_DQS#7
M_A_DQS6
M_A_DQS#6
M_A_DQS5
M_A_DQS#5
M_A_DQS4
M_A_DQS#4
M_A_DQS3
M_A_DQS#3
M_A_DQS2
M_A_DQS#2
M_A_DQS1
M_A_DQS#1
M_A_DQS0
M_A_DQS#0
C C
M_A_DIM0_CLK0
M_A_DIM0_CLK#0
M_A_DIM0_CLK1
M_A_DIM0_CLK#1
12
12
C1621
10PF/50V
@
C1626
10PF/50V
@
12
12
1%
R1603
150Ohm
@
1%
R1604
150Ohm
@
PLACE CLOSE TO SODIMM
B B
For RF
M_A_DIM0_CKE1
M_A_DIM0_CKE0
SMB_CLK_S_CH A
SMB_DAT_S_CHA
12
12
C1627
C1628
10PF/50V
10PF/50V
@
@
A A
12
C1629
10PF/50V
@
12
C1630
10PF/50V
@
M_A_DIM0_CLK15
M_A_DIM0_CLK#15
M_A_DIM0_CLK05
M_A_DIM0_CLK#05
M_A_DIM0_CS#15
M_A_DIM0_CS#05
M_A_DIM0_ODT15
M_A_DIM0_ODT05
M_A_DIM0_CKE15
M_A_DIM0_CKE05
SMBus Slave Address: A0H
M_A_DQS[7:0]5
M_A_DQS#[7:0]5
DM should connect to GND directly
Design Guide 1.0 P.88 (436735)
SMB_CLK_S17,28,31,45,5 3
SMB_DAT_S17,28,31,45,53
M_A_WE#5
M_A_RAS#5
M_A_CAS#5
M_A_BS25
M_A_BS15
M_A_BS05
R1605 10KOhm
R1606 10KOhm
SP1601 R040 2
SP1602 R040 2
12
12
J1601A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
102
CK1
104
CK1#
101
CK0
103
CK0#
121
S1#
114
S0#
120
ODT1
116
ODT0
113
WE#
110
RAS#
115
CAS#
79
BA2
108
BA1
109
BA0
74
CKE1
73
CKE0
201
SA1
197
SA0
188
DQS7
186
DQS#7
171
DQS6
169
DQS#6
154
DQS5
152
DQS#5
137
DQS4
135
DQS#4
64
DQS3
62
DQS#3
47
DQS2
45
DQS#2
29
DQS1
27
DQS#1
12
DQS0
10
DQS#0
187
DM7
170
DM6
153
DM5
136
DM4
63
DM3
46
DM2
28
DM1
11
DM0
202
SCL
200
SDA
DDR3_DIMM_204 P
12V02GISM000
0
1
2
3
4
5
6
7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RESET#
5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
M_A_D7
7
M_A_D0
15
M_A_D5
M_A_D3
M_A_D4
M_A_D1
M_A_D6
M_A_D2
M_A_D20
M_A_D21
M_A_D19
M_A_D23
M_A_D17
M_A_D22
M_A_D18
M_A_D16
M_A_D33
M_A_D38
M_A_D39
M_A_D37
M_A_D36
M_A_D32
M_A_D34
M_A_D35
M_A_D52
M_A_D53
M_A_D50
M_A_D48
M_A_D49
M_A_D51
M_A_D55
M_A_D54
0~7
8~15
16~23
24~31
32~39
40~47
48~55
56~63
17
4
6
16
18
21
M_A_D8
23
M_A_D10
33
M_A_D12
35
M_A_D13
22
M_A_D9
24
M_A_D11
34
M_A_D15
36
M_A_D14
39
41
51
53
40
42
50
52
57
M_A_D25
59
M_A_D29
67
M_A_D30
69
M_A_D31
56
M_A_D28
58
M_A_D24
68
M_A_D27
70
M_A_D26
129
131
141
143
130
132
140
142
147
M_A_D45
149
M_A_D40
157
M_A_D47
159
M_A_D46
146
M_A_D43
148
M_A_D41
158
M_A_D44
160
M_A_D42
163
165
175
177
164
166
174
176
181
M_A_D61
183
M_A_D60
191
M_A_D59
193
M_A_D62
180
M_A_D58
182
M_A_D56
192
M_A_D63
194
M_A_D57
30
H:8mm
5
4
M_A_D[63:0] 5
DDR3_DRAMRST # 5,17
3
+1.35V_DDR3
12
12
C1605
0.1UF/16V
C1606
0.1UF/16V
Layout Note: Place these caps near SO DIMM 0
1
PM_EXTTS#0_DIM_A
T1601
Reserve
+V_VREF_CA_DIMM0
12
12
C1624
C1623
2.2UF/10V
0.1UF/16V
@
+V_VREF_DQ_DIMM0
12
12
C1622
C1625
2.2UF/10V
0.1UF/16V
@
J1601B
75
VDD1
81
VDD3
87
VDD5
93
VDD7
99
VDD9
105
VDD11
111
VDD13
117
VDD15
123
VDD17
2
VSS1
8
VSS3
13
VSS5
19
VSS7
25
VSS9
31
VSS11
37
VSS13
43
VSS15
48
VSS17
54
VSS19
60
VSS21
65
VSS23
71
VSS25
127
VSS27
133
VSS29
138
VSS31
144
VSS33
150
VSS35
155
VSS37
161
VSS39
167
VSS41
172
VSS43
178
VSS45
184
VSS47
189
VSS49
195
VSS51
198
EVENT#
125
TEST
77
NC1
122
NC2
126
VREFCA
1
VREFDQ
DDR3_DIMM_204 P
12V02GISM000
2
VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
VDD14
VDD16
VDD18
VSS2
VSS4
VSS6
VSS8
VSS10
VSS12
VSS14
VSS16
VSS18
VSS20
VSS22
VSS24
VSS26
VSS28
VSS30
VSS32
VSS34
VSS36
VSS38
VSS40
VSS42
VSS44
VSS46
VSS48
VSS50
VSS52
GND1
GND2
NP_NC1
NP_NC2
VTT1
VTT2
VDDSPD
76
82
88
94
100
106
112
118
124
3
9
14
20
26
32
38
44
49
55
61
66
72
128
134
139
145
151
156
162
168
173
179
185
190
196
207
208
205
206
203
204
199
12
+0.675VS
C1615
0.1UF/16V
+1.35V_DDR3
12
12
C1607
C1608
0.1UF/16V
0.1UF/16V
+3VS
12
C1614
2.2UF/10V
@
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
PT10SG
PT10SG
PT10SG
1
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
DDR3L(1)_SO-DIMM0
DDR3L(1)_SO-DIMM0
DDR3L(1)_SO-DIMM0
Ruby Tsai
Ruby Tsai
Ruby Tsai
16 104T uesday, February 26, 2013
16 104T uesday, February 26, 2013
16 104T uesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
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5
4
3
2
1
+1.35V_DDR3
+0.675VS
+V_VREF_CA_DIMM1
+V_VREF_DQ_DIMM1
D D
C C
+3VS
M_B_DIM0_CLK0
M_B_DIM0_CLK#0
M_B_DIM0_CLK1
M_B_DIM0_CLK#1
PLACE CLOSE TO SODIMM
B B
12
12
C1727
10PF/50V
@
A A
+1.35V_DDR3 16
+0.675VS 16,57,83
+3VS 4,16,20,21,22,23,25,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92
+V_VREF_CA_DIMM1 16,18
+V_VREF_DQ_DIMM1 18
12
C1720
10PF/50V
@
C1721
10PF/50V
@
12
1%
150Ohm
R1707
@
1%
150Ohm
R1708
@
12
12
For RF
M_B_DIM0_CKE1
M_B_DIM0_CKE0
SMB_CLK_S_CHB
SMB_DAT_S_CHB
12
C1728
10PF/50V
@
12
C1729
10PF/50V
@
C1730
10PF/50V
@
SMB_CLK_S16,28,31,45,53
SMB_DAT_S16,28,31,45,53
M_B_A[15:0]5
M_B_DIM0_CLK15
M_B_DIM0_CLK#15
M_B_DIM0_CLK05
M_B_DIM0_CLK#05
M_B_DIM0_CS#15
M_B_DIM0_CS#05
M_B_DIM0_ODT15
M_B_DIM0_ODT05
M_B_DIM0_CKE15
M_B_DIM0_CKE05
+3VS
M_B_DQS[7:0]5
M_B_DQS#[7:0]5
SP1701 R0402
SP1702 R0402
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_WE#5
M_B_RAS#5
M_B_CAS#5
M_B_BS25
M_B_BS15
M_B_BS05
1 2
R1705 10KOhm
1 2
R1706 10KOhm
R1.10
M_B_DQS7
M_B_DQS#7
M_B_DQS6
M_B_DQS#6
M_B_DQS5
M_B_DQS#5
M_B_DQS4
M_B_DQS#4
M_B_DQS3
M_B_DQS#3
M_B_DQS2
M_B_DQS#2
M_B_DQS1
M_B_DQS#1
M_B_DQS0
M_B_DQS#0
12
SMB_CLK_S_CHB
12
SMB_DAT_S_CHB
Remove CE1603
0928 Ruby
J1701A
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
102
CK1
104
CK1#
101
CK0
103
CK0#
121
S1#
114
S0#
120
ODT1
116
ODT0
113
WE#
110
RAS#
115
CAS#
79
BA2
108
BA1
109
BA0
74
CKE1
73
CKE0
201
SA1
197
SA0
188
DQS7
186
DQS#7
171
DQS6
169
DQS#6
154
DQS5
152
DQS#5
137
DQS4
135
DQS#4
64
DQS3
62
DQS#3
47
DQS2
45
DQS#2
29
DQS1
27
DQS#1
12
DQS0
10
DQS#0
187
DM7
170
DM6
153
DM5
136
DM4
63
DM3
46
DM2
28
DM1
11
DM0
202
SCL
200
SDA
DDR3_DIMM_204P
12V02GISM001
0
1
2
3
4
5
6
7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RESET#
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
30
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5
4
H:4mm
Layout Note: Place these caps near SO DIMM 1
12
C1710
10UF/6.3V
M_B_D[63:0] 5
C1711
10UF/6.3V
Layout Note: Place these caps near SO DIMM 1
M_B_D0
M_B_D7
M_B_D3
M_B_D2
M_B_D1
M_B_D5
M_B_D4
M_B_D6
M_B_D10
M_B_D14
M_B_D12
M_B_D13
M_B_D8
M_B_D9
M_B_D11
M_B_D15
M_B_D16
M_B_D17
M_B_D18
M_B_D23
M_B_D20
M_B_D21
M_B_D22
M_B_D19
M_B_D29
M_B_D28
M_B_D26
M_B_D31
M_B_D30
M_B_D25
M_B_D27
M_B_D24
M_B_D33
M_B_D37
M_B_D34
M_B_D35
M_B_D32
M_B_D36
M_B_D39
M_B_D38
M_B_D44
M_B_D45
M_B_D43
M_B_D42
M_B_D40
M_B_D41
M_B_D46
M_B_D47
M_B_D53
M_B_D55
M_B_D51
M_B_D49
M_B_D52
M_B_D54
M_B_D50
M_B_D48
M_B_D60
M_B_D56
M_B_D58
M_B_D63
M_B_D62
M_B_D61
M_B_D57
M_B_D59
12
C1709
10UF/6.3V
12
0~7
8~15
16~23
24~31
32~39
40~47
48~55
56~63
DDR3_DRAMRST# 5,16
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3
12
C1712
10UF/6.3V
@
+1.35V_DDR3
12
C1713
10UF/6.3V
@
12
C1705
0.1UF/16V
T1701
ReserveSMBus Slave Address: A4H
+V_VREF_CA_DIMM1
+V_VREF_DQ_DIMM1
12
C1726
10UF/6.3V
12
1
PM_EXTTS#0_DIM_B
12
C1724
2.2UF/10V
@
12
C1722
2.2UF/10V
@
@
C1706
0.1UF/16V
12
12
C1723
0.1UF/16V
C1725
0.1UF/16V
+0.675VS+1.35V_DDR3
12
12
C1716
1UF/6.3V
J1701B
75
VDD1
81
VDD3
87
VDD5
93
VDD7
99
VDD9
105
VDD11
111
VDD13
117
VDD15
123
VDD17
2
VSS1
8
VSS3
13
VSS5
19
VSS7
25
VSS9
31
VSS11
37
VSS13
43
VSS15
48
VSS17
54
VSS19
60
VSS21
65
VSS23
71
VSS25
127
VSS27
133
VSS29
138
VSS31
144
VSS33
150
VSS35
155
VSS37
161
VSS39
167
VSS41
172
VSS43
178
VSS45
184
VSS47
189
VSS49
195
VSS51
198
EVENT#
125
TEST
77
NC1
122
NC2
126
VREFCA
1
VREFDQ
DDR3_DIMM_204P
12V02GISM001
2
12
12
C1717
1UF/6.3V
VDD2
VDD4
VDD6
VDD8
VDD10
VDD12
VDD14
VDD16
VDD18
VSS2
VSS4
VSS6
VSS8
VSS10
VSS12
VSS14
VSS16
VSS18
VSS20
VSS22
VSS24
VSS26
VSS28
VSS30
VSS32
VSS34
VSS36
VSS38
VSS40
VSS42
VSS44
VSS46
VSS48
VSS50
VSS52
GND1
GND2
NP_NC1
NP_NC2
VTT1
VTT2
VDDSPD
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
C1718
1UF/6.3V
@
76
82
88
94
100
106
112
118
124
3
9
14
20
26
32
38
44
49
55
61
66
72
128
134
139
145
151
156
162
168
173
179
185
190
196
207
208
205
206
203
204
199
C1719
1UF/6.3V
@
12
C1707
0.1UF/16V
+0.675VS
12
PT10SG
PT10SG
PT10SG
C1715
0.1UF/16V
+1.35V_DDR3
12
Engineer:
Engineer:
Engineer:
C1708
0.1UF/16V
+3VS
12
C1714
2.2UF/10V
@
Title :
Title :
Title :
1
DDR3(2)_SO-DIMM1
DDR3(2)_SO-DIMM1
DDR3(2)_SO-DIMM1
Ruby Tsai
Ruby Tsai
Ruby Tsai
17 104Tuesday, February 26, 2013
17 104Tuesday, February 26, 2013
17 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
5
4
3
2
1
DDR3L Vref
+1.35V
+V_VREF_DQ_DIMM0
+V_VREF_CA_DIMM0
+V_VREF_DQ_DIMM1
+V_VREF_CA_DIMM1
+1.35V 6,16,57,83
+V_VREF_DQ_DIMM0 16
+V_VREF_CA_DIMM0 16,17
+V_VREF_DQ_DIMM1 17
+V_VREF_CA_DIMM1 16,17
https://t.me/schematicslaptop
D D
C C
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M3
M3: CPU driven VREF path is stuffed be default.
M1: VREF_DQ driven by a Voltage Divider Network during Processor power-off
+V_VREF_DQ_DIMM0
1 2
12
12
C1805
0.022UF/16V
R1819
24.9Ohm
1%
R1821 0Ohm
0921Ken
1 2
R1822 0Ohm
12
C1804
0.022UF/16V
12
R1818
24.9Ohm
1%
@
12
12
R1814
0Ohm
C1802
0.1UF/16V
+1.35V
1 2
12
+V_VREF_DQ_DIMM1
R1810
1KOhm
R1809
1KOhm
12
C1803
0.1UF/16V
+1.35V
R1815
1KOhm
1 2
12
R1816
1KOhm
Intel
DG, 486713
0920 JR
DIMM0_VREF_DQ5
DIMM1_VREF_DQ5
M1
Intel 0203
M3+M1: Default Recommendation
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+V_VREF_CA_DIMM0
M3
B B
DIMM_VREF_CA5
0921Ken
1 2
R1823 0Ohm
1 2
R1824 0Ohm
+V_VREF_CA_DIMM1
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12
C1801
0.1UF/16V
+1.35V
R1807
1KOhm
1 2
12
R1808
1KOhm
Intel
DG, 486713
0920 JR
Title :
Title :
Title :
DDR3(3)_CA/DQ Voltage
DDR3(3)_CA/DQ Voltage
DDR3(3)_CA/DQ Voltage
Ruby Tsai
Ruby Tsai
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet
2
Date: Sheet
Ruby Tsai
18 104Tuesday, February 26, 2013
18 104Tuesday, February 26, 2013
18 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
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12
C1806
0.022UF/16V
12
R1820
24.9Ohm
1%
M1
A A
5
4
3
5
4
3
2
1
RTC battery
12
1
JRST2001
1
2
SGL_JUMP
2
@
1
JRST2002
1
2
SGL_JUMP
2
@
JRST2002
Shunt
Open
(Default)
1 2
+RTC_BAT
@
R1.10
R2001 1KOhm
12
3
J2001
4
BATT_HOLDER_2P
D D
+VCC_RTC
RTCRST# RC delay
should be 18ms~25ms
R2003 20KOhm
R2005
1MOhm
R2004 20KOhm
C C
GND
12
5%
12
C2004
1UF/6.3V
GND GND
12
12
5%
12
C2005
1UF/6.3V
Request by CSC
for CMOS clear
function
CMOS Settings
Clear CMOS
12V20GBSM000
M : 1220-001O000
GNDGND
Keep CMOS
INTVRMEN: Integrated SUS 1.05V VRM Enables
Low: Enable External VRs
High:Enable Internal VRs
PCH_INTVRMEN
B B
R2030 330KOhm
D2001
1
2
0.8V/0.2mA
07V030000001
TPM Settings
Clear ME RTC
Registers
Keep ME RTC
Registers
Q2001
2N7002
@
12/3 R1.1
GND
+VCC_RTC+3VA+RTCBAT
3
12
C2003
1UF/6.3V
GND
JRST2001
Shunt
Open
(Default)
3
D
1
G
S
2
@
R2026
10KOhm
1 2
GND
EC reset CMOS f eature
SW_RTCRST 30
T2015
PCH_FLASH_DESCRIPTOR30
1
T2012
T2011
GND
GND
1
+VCC_RTC
1
ACZ_BCLK_AUD36
ACZ_SYNC_AUD36
SB_SPKR36
ACZ_RST#_AUD36,37
ACZ_SDIN036
ACZ_SDOUT_AUD36
EXT_SCI#30
C2001
12
XTAL_32K_X1_C
15PF/50V
2
3
NC
0920 JR
12
C2002 15PF/50V
R2006 330KOhm
1
T2001
1
T2023
1
T2024
1
T2025
1
T2026
1
T2027
SP2005
1 2
R0402
14
X2001
32.768KHZ
1 2
R2052 33Ohm
R2051 33Ohm
R2053 33Ohm
SP2006
12
NB_R0402_20MIL_SMALL
R2054 33Ohm
1 2
R2058 10KOhm
GND
12
R2002
10MOhm
XTAL_32K_X1
XTAL_32K_X2
SRTC_RST#
SM_INTRUDER#
PCH_INTVRMEN
RTC_RST#
HDA_BCLK_R
HDA_SYNC_R
HDA_RST#_R
1
T2022
HDA_SDI3
HDA_SDO_R
HDA_DOCK_EN#
PCH_JTAG_TCK_BUF
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
1 2
R2055 0Ohm
@
PM_TEST_RST_N
+3VSUS_ORG
+3VSUS_ORG
U2001A
B5
RTCX1
B4
RTCX2
B9
SRTCRST#
A8
INTRUDER#
G10
INTVRMEN
D9
RTCRST#
B25
HDA_BCLK
A22
HDA_SYNC
AL10
SPKR
C24
HDA_RST#
L22
HDA_SDI0
K22
HDA_SDI1
G22
HDA_SDI2
F22
HDA_SDI3
A24
HDA_SDO
B17
DOCKEN#/GPIO33
C22
HDA_DOCK_RST#/GPIO13
AB3
JTAG_TCK
AD1
JTAG_TMS
AE2
JTAG_TDI
AD3
JTAG_TDO
F8
TP25
C26
TP22
AB6
TP20
POINT
02V000000013
+VCC_RTC
+12VS
+1.5VS
+VCC_RTC 22,27
+3VA
+3VA 27,30,33,57,60,65,81,88,93
+3VS
+3VS 4,16,17,21,22,23,25,26, 27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92
+3VSUS_ORG 21,22,24,25,26,27
+12VS 28,48,57,91
+1.5VS 21,22,24,26,27,53,57,84
LPT_PCH_M_EDS
SATA_RXN_0
SATA_RXP_0
SATA_TXN_0
SATA_TXP_0
SATA_RXN_1
SATA_RXP_1
SATA_TXN_1
SATA_TXP_1
SATA
JTAGRTC AZALIA
SATA_RXN_2
SATA_RXP_2
SATA_TXN_2
SATA_TXP_2
SATA_RXN_3
SATA_RXP_3
SATA_TXN_3
SATA_TXP_3
SATA_RXN4/PERN1
SATA_RXP4/PERP1
SATA_TXN4/PETN1
SATA_TXP4/PETP1
SATA_RXN5/PERN2
SATA_RXP5/PERP2
SATA_TXN5/PETN2
SATA_TXP5/PETP2
SATA_RCOMP
SATA0GP/GPIO21
SATA1GP/GPIO19
SATALED#
SATA_IREF
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BC8
BE8
AW8
AY8
BC10
BE10
AV10
AW10
BB9
BD9
AY13
AW13
BC12
BE12
AR13
AT13
BD13
BB13
AV15
AW15
BC14
BE14
AP15
AR15
AY5
SATA_COMP
AP3
SATA_LED#
AT1
SATA_DET0_R_N
AU2
BBS_BIT0_R
Int. PU
BD4
BA2
TP9
TP8
SATA_IREF
BB2
0927 Ruby
SATA_RXN0 51
SATA_RXP0 51
SATA_TXN0 51
SATA_TXP0 51
SATA_RXN2 51
SATA_RXP2 51
SATA_TXN2 51
SATA_TXP2 51
1 2
R2007 7.5KOhm
1 2
R2025 10KOhm
@
R2057 0Ohm
R2056 0Ohm
12
12
SATA HDD
SATA ODD
1
+1.5VS
+1.5VS
+3VS
T2028
BBS_BIT0 23
R1.0
For JTAG to pull high and low.
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TCK_BUF
A A
5
1 2
R2040 220Ohm1% /XDP
1 2
R2038 220Ohm1% /XDP
1 2
R2039 220Ohm1% /XDP
1 2
R2041 100Ohm1% /XDP
1 2
R2042 100Ohm1% /XDP
1 2
R2043 100Ohm1% /XDP
1 2
R2044 51Ohm /XDP
+3VSUS_ORG
GND
4
Strap information:
HDA_SPKR: No reboot strap
Low: Disable (Default)
High:Enable
HDA_SDO:
1.Flash descriptor security:
Sampled Low: in effect.
Sampled High: override
2.HDA_SDO which sample high on the rising edge of PWROK
Will also disable Intel ME.
HDA_DOCK_EN#:
Reserved
[0216] : ACZ_SYNC strap is no longer supported on LPT, by Intel FAE Stu.
3
SB_SPKR
Ruby 0925
HDA_SDO_R
1 2
R2020 1KOhm@
1 2
R2034 1KOhm@
+3VS
+3VS
+3VSUS_ORG
2
SATA_DET0_R_N
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
1 2
R2027 10KOhm
R1.10
Engineer:
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
1
Title :
Title :
Title :
PCH(1)_SATA,IHDA,RTC,LPC
PCH(1)_SATA,IHDA,RTC,LPC
PCH(1)_SATA,IHDA,RTC,LPC
Ruby Tsai
Ruby Tsai
Ruby Tsai
20 104Tuesday, February 26, 2013
20 104Tuesday, February 26, 2013
20 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
5
Y43
Y45
AA44
AA42
AB43
AB45
AD43
AD45
AF43
AF45
AE44
AE42
AB40
AB39
AJ44
AJ42
AH43
AH45
AB1
AF1
AF3
T3
V3
AA2
AE4
Y3
D44
E44
B42
F41
A40
1 2
1
1
1
1
12
12
R211122Ohm
CLK_REQ0#
CLK_REQ1#
CLK_PCIE_WLAN#_R
CLK_PCIE_WLAN_R
CLK_REQ2#C LK_REQ2#
CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R
CLK_REQ3_LAN#
CLK_REQ4#
CLK_TV_REQ#
CLK_REQ6#
CLK_REQ7#
CLK_XDP_N
CLK_XDP_P
CLKOUT_PCI0
CLKOUT_PCI1
R211022Ohm
CLK_KBCPCI_R
CLK_DEBUG_R
CLK_PCI_DBG_R
D D
1 2
CLK_PCIE_WLAN#53
CLK_PCIE_WLAN53
CLK_REQ_WLAN#53
CLK_PCIE_LAN#33
CLK_PCIE_LAN33
CLK_REQ_LAN#33
C C
CLK_KBCPCI_PCH30
CLK_DEBUG44
R2122 0Ohm
1 2
R2123 0Ohm
1 2
R2158 0Ohm
1 2
R2159 0Ohm
T2141
100MHz
T2142
CLK_PCI_FB
T2127
SP2105 R0402
T2101
C2103
10PF/50V
1 2
@
Reserved for Wireless team
GND
4
U2001C
CLKOUT_PCIE_N_0
CLKOUT_PCIE_P_0
PCIECLKRQ0#/GPIO73
CLKOUT_PCIE_N_1
CLKOUT_PCIE_P_1
PCIECLKRQ1#/GPIO18
CLKOUT_PCIE_N_2
CLKOUT_PCIE_P_2
PCIECLKRQ2#/GPIO20/SMI#
CLKOUT_PCIE_N_3
CLKOUT_PCIE_P_3
PCIECLKRQ3#/GPIO25
CLKOUT_PCIE_N_4
CLKOUT_PCIE_P_4
PCIECLKRQ4#/GPIO26
CLKOUT_PCIE_N5
CLKOUT_PCIE_P_5
PCIECLKRQ5#/GPIO44
CLKOUT_PCIE_N_6
CLKOUT_PCIE_P_6
PCIECLKRQ6#/GPIO45
CLKOUT_PCIE_N_7
CLKOUT_PCIE_P_7
PCIECLKRQ7#/GPIO46
CLKOUT_ITPXDP
CLKOUT_ITPXDP_P
CLKOUT_33MHZ0
CLKOUT_33MHZ1
CLKOUT_33MHZ2
CLKOUT_33MHZ3
CLKOUT_33MHZ4
CLOCK SIGNAL
POINT
02V000000013
LPT_PCH_M_EDS
CLKOUT_PEG_A
CLKOUT_PEG_A_P
PEGA_CLKRQ#/GPIO47
CLKOUT_PEG_B
CLKOUT_PEG_B_P
PEGB_CLKRQ#/GPIO56
CLKOUT_DMI
CLKOUT_DMI_P
CLKOUT_DP
CLKOUT_DP_P
CLKOUT_DPNS
CLKOUT_DPNS_P
CLKIN_DMI
CLKIN_DMI_P
CLKIN_GND
CLKIN_GND_P
CLKIN_DOT96N
CLKIN_DOT96P
CLKIN_SATA
CLKIN_SATA_P
REFCLK14IN
CLKIN_33MHZLOOPBACK
XTAL25_OUT
XTAL25_IN
CLKOUTFLEX0/GPIO64
CLKOUTFLEX1/GPIO65
CLKOUTFLEX2/GPIO66
CLKOUTFLEX3/GPIO67
ICLK_IREF
DIFFCLK_BIASREF
TP19
TP18
AB35
AB36
AF6
Y39
Y38
U4
AF39
AF40
AJ40
AJ39
AF35
AF36
AY24
AW24
AR24
AT24
H33
G33
BE6
BC6
F45
D17
AL44
AM43
C40
F38
F36
F39
AM45
AD39
AD38
AN44
CLK_PCIE_PEG#_R
CLK_PCIE_PEG_R
CLKREQ_PEG#
CLK_REQ_PEG_B#
CLK_BUF_EXP_N
CLK_BUF_EXP_P
CLK_BUF_CPYCLK_N
CLK_BUF_CPYCLK_P
CLK_BUF_DOT96_N
CLK_BUF_DOT96_P
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P
CLK_BUF_REF14
CLK_PCI_FB
XTAL_25M_OUT
XTAL_25M_IN
KB_LED_ID
CLK_USB48_CR_R
PCB_ID14
PCB_ID12
ICLK_IREF
DIFFCLK_BIASREF
3
+3VS
+1.5VS
+3VSUS_ORG
+VCCAXCK_VRM
1 2
R2124 0Ohm
1 2
R2127 0Ohm
0927 Ken
1 2
1
R21450Ohm
1 2
R2146 7.5KOhm
CLK_USB48_CR_R
+3VS 4,16,17,20,22,23,25,26,27,28,30,31,32, 36,40,45,46,48,50,51,53,57,91,92
+1.5VS 20,22,24,26,27,53,57,84
+3VSUS_ORG 20,22,24,25,26,27
+VCCAXCK_VRM 27
T2111
PCB_ID14 25
PCB_ID12 25
+1.5VS
CLK_PCIE_PEG#_PCH 70
CLK_PCIE_PEG_PCH 70
CLKREQ_PEG# 70
CLK_EXP_N 4
CLK_EXP_P 4
CLK_DP_SSC_N 4
CLK_DP_SSC_P 4
CLK_DP_N 4
CLK_DP_P 4
+VCCAXCK_VRM
1 2
R2165 22Ohm
@
100MHz
100MHz
135MHz
135MHz
25-MHz is required in:
1. FCIM
2. BTM for PCH Display Clock gereration
in Integrated Graphics platforms
SP2111
R0402
1 2
12
R2142 1MOhm
12
10PF/50V
C2104
2
12PF/50V
1 2
XTAL_25M_OUT_C
C2102
13
25MHZ
X2103
2
4
12PF/50V
1 2
C2101
R1.1 12/5
CLK_USB48_CR 40
1
CLK_BUF_CPYCLK_P
CLK_BUF_CPYCLK_N
CLK_BUF_EXP_P
CLK_BUF_EXP_N
CLK_BUF_DOT96_P
CLK_BUF_DOT96_N
CLK_BUF_CKSSCD_N
CLK_BUF_CKSSCD_P
CLK_BUF_REF14
INT_SERIRQ
GND
GND
GND
PCH CLKREQ Setting:
CLK_REQ1#
CLK_REQ_WLAN#
CLK_REQ4#
CLKREQ_PEG#
CLK_REQ0#
CLK_TV_REQ#
CLK_REQ6#
CLK_REQ7#
CLK_REQ_PEG_B#
CLK_REQ_LAN#
1009 Ruby
3 4
10KOhm
1 2
10KOhm
3 4
10KOhm
1 2
10KOhm
3 4
10KOhm
1 2
10KOhm
1 2
10KOhm
3 4
10KOhm
1 2
R2116 10KOhm
CLOCK TERMINATION for FCIM
Default power-on mode is ICC.
1 2
R2129 10KOhm
3 4
1 2
R2134 10KOhm
R2136 10KOhm
R2131 10KOhm
R2132 10KOhm
R2128 10KOhm
R2149 10KOhm
R2133 10KOhm
R2350 10KOhm
10KOhm
10KOhm
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
RN2107B
RN2107A
0919 Ken
RN2108B
RN2108A
RN2109B
RN2109A
RN2110B
RN2110A
RN2111A
RN2111B
GND
+3VS
+3VS
+3VSUS_ORG
U2001D
AL11
AJ11
AJ10
A20
C20
A18
C18
B21
D21
G20
AJ7
AL7
AH1
AH3
AJ4
AJ2
LAD_0
LAD_1
LAD_2
LAD_3
LFRAME#
LDRQ0#
LDRQ1#/GPIO23
SERIRQ
SPI_CLK
SPI_CS0#
SPI_CS1#
SPI_CS2#
SPI_MOSI
SPI_MISO
SPI_IO2
SPI_IO3
POINT
02V000000013
LPC_AD030,44
LPC_AD130,44
B B
R1.1 2/19
A A
LPC_AD230,44
LPC_AD330,44
LPC_FRAME#30,44
PCB_ID1525
INT_SERIRQ30,44
SPI_CS#028
SPI_CS#130
SPI_WP_IO228,30
SPI_HOLD#_IO328,30
PCB_ID15
SPI_CLK28,30
SPI_SI28,30
SPI_SO28,30
1
SNN_PCH_DRQ#0
T2132
Serial Interrupt Request
LPT_PCH_M_EDS
N7
TP1
TP2
TP4
TP3
R10
U11
N8
U8
R7
H6
K6
N11
AF11
AF10
AF7
BA45
BC45
BE43
BE44
AY43
SMLA_ALERT#
DRAMRST_CNTRL_PCH
SML0_CLK
SML0_DAT
SML1_ALERT#
SML1_CLK
SML1_DAT
CL_CLK
CL_DATA
CL_RST#
12
R2119
8.2KOhm
GND
SMBus
SPILPC
C-Link
Thermal
SMBALERT#/GPIO11
SMBCLK
SMBDATA
SML0ALERT#/GPIO60
SML0CLK
SML1ALERT#/PCHHOT#/GPIO74
SML0DATA
SML1CLK/GPIO58
SML1DATA/GPIO75
CL_CLK
CL_DATA
CL_RST#
TD_IREF
1
T2151
1
T2152
1
T2153
1
T2154
GND
SCL_3A 28
SDA_3A 28
SML1_CLK 28
SML1_DAT 28
0921 Ken
CLK_REQ_WLAN#
CLK_REQ_LAN#
CLKREQ_PEG#
Default : Clock free run. (PD 10K).
Reserver 10K PU for power saving purpose.
SMLA_ALERT#
SCL_3A
SDA_3A
DRAMRST_CNTRL_PCH
SML0_CLK
SML0_DAT
SML1_CLK
SML1_DAT
SML1_ALERT#
1 2
R2138 10KOhm@
1 2
R2137 10KOhm@
1 2
R2141 10KOhm@
1 2
R2118 10KOhm
1 2
2.2KOhm
3 4
2.2KOhm
1 2
R2130 1KOhm
5 6
2.2KOhm
7 8
2.2KOhm
R2163 2.2KOhm
R2164 2.2KOhm
1 2
R2125 10KOhm
RN2112A
RN2112B
RN2112C
RN2112D
12
12
GND
+3VSUS_ORG
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Title :
Title :
Title :
PCH(2)_PCIE,CLK,SMB,PEG
PCH(2)_PCIE,CLK,SMB,PEG
PCH(2)_PCIE,CLK,SMB,PEG
Ruby Tsai
Ruby Tsai
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet
2
Date: Sheet
Ruby Tsai
21 104Tuesday, February 26, 2013
21 104Tuesday, February 26, 2013
21 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
5
DMI_RXN03
DMI_RXN13
DMI_RXN23
DMI_RXN33
DMI_RXP03
DMI_RXP13
D D
If SUSWARN #/SUS_ACK # handshake
is not used, these signals are tied on the board
DG, 486713
CHKLST, 497750
0920 JR
C C
DMI_RXP23
DMI_RXP33
DMI_TXN03
DMI_TXN13
DMI_TXN23
DMI_TXN33
DMI_TXP03
DMI_TXP13
DMI_TXP23
DMI_TXP33
+1.5VS
+1.5VS
SUSACK#30
PM_PWROK9,30,92
PM_DRAM_PWRGD4
PM_RSMRST#30
ME_SUSPWRDNACK30
PM_PWRBTN#30
ME_AC_PRESENT30
R2242 0Ohm
R2202 7.5KOhm
SUS_PWR_ACK_R
SUSACK#_PCH
+3VS
SYS_PWROK SYS_PWROK_R
1
T2202
1
T2205
12
1 2
R2208 0Ohm
R2203 0Ohm@
R2205 10KOhm
R2210 0Ohm
R2211 0Ohm
R2240 0Ohm
R2212 0Ohm
SP2218 R0402
SP2214 R0402
SP2219 R0402
1 2
1 2
1 2
12
12
12
12
12
12
12
4
DMI_IREF
DMI_RCOMP
SUSACK#_R
PM_PCH_PWROK_R
PM_APWROK_R
PM_RSMRST_R
SUS_PWR_ACK_R
AC_PRESENT_R
GPIO72
RI#
SLP_WLAN#
U2001B
AW22
DMI_RXN_0
AR20
DMI_RXN_1
AP17
DMI_RXN_2
AV20
DMI_RXN_3
AY22
DMI_RXP_0
AP20
DMI_RXP_1
AR17
DMI_RXP_2
AW20
DMI_RXP_3
BD21
DMI_TXN_0
BE20
DMI_TXN_1
BD17
DMI_TXN_2
BE18
DMI_TXN_3
BB21
DMI_TXP_0
BC20
DMI_TXP_1
BB17
DMI_TXP_2
BC18
DMI_TXP_3
BE16
DMI_IREF
AW17
TP12
AV17
TP7
AY17
DMI_RCOMP
R6
SUSACK#
AM1
SYS_RESET#
AD7
SYS_PWROK
F10
PWROK
AB7
APWROK
H3
DRAMPWROK
J2
RSMRST#
J4
SUSWARN#/SUSPWRNACK/GPIO30
K1
PWRBTN#
E6
ACPRESENT/GPIO31
K7
BATLOW#/GPIO72
N4
RI#
AB10
TP21
D2
SLP_WLAN#/GPIO29
POINT
02V000000013
LPT_PCH_M_EDS
DMI
System Power
Management
FDI
FDI_RXN_0
FDI_RXN_1
FDI_RXP_0
FDI_RXP_1
TP16
TP15
TP10
FDI_CSYNC
FDI_INT
FDI_IREF
TP17
TP13
FDI_RCOMP
DSWVRMEN
DPWROK
WAKE#
CLKRUN#
SUS_STAT#/GPIO61
SUSCLK/GPIO62
SLP_S5#/GPIO63
SLP_S4#
SLP_S3#
SLP_A#
SLP_SUS#
PMSYNCH
SLP_LAN#
3
AJ35
AL35
AJ36
AL36
AV43
AY45
TP5
AV45
AW44
AL39
AL40
AT45
AU42
AU44
AR44
C8
L13
K3
AN7
U7
Y6
Y7
C6
H1
F3
F1
AY3
G5
FDI_CSYNC_R
FDI_INT_R
DSWODVREN
PCH_DPROK
PM_CLKRUN#
PM_SUS_STAT#
SUSCLK_C
SLP_S5#
SLP_S4#_R
SLP_S3#_R
SLP_DSW#_R
1 2
SP2202 R0402
1 2
SP2201 R0402
FDI_IREF
FDI_RCOMP
R2215 330KOhm@
R2214 330KOhm
1 2
SP2220 R0402
1 2
SP2206 R0402
1 2
SP2207 R0402
1 2
R22430Ohm
1 2
R2206 7.5KOhm
GND
PM_RSMRST_R
1
1
1
1
FDI_TXN0 4
FDI_TXN1 4
FDI_TXP0 4
FDI_TXP1 4
FDI_CSYNC 3
FDI_INT 3
+VCC_RTC
PCIE_WAKE# 33,53
PM_CLKRUN# 30
T2203
T2210
1
T2204
PM_SUSC# 30
PM_SUSB# 30
T2207
T2209
H_PM_SYNC 4
1
T2206
2
+3VSUS_ORG
+3VS
+1.5VS
+VCC_RTC
+3VSUS
+5VSUS
+12VSUS
+VCCDSW
+1.5VS
+1.5VS
DSWODVREN - On Die DSW VR Enable
HIGH - Enabled(DEFAULT) ; LOW-Disabled
1
+3VSUS_ORG 20,21,24,25,26,27
+3VS 4,16,17,20,21,23,25,26,27,28,30,31,32, 36,40,45,46,48,50,51,53,57,91,92
+1.5VS 20,21,24,26,27,53,57,84
+VCC_RTC 20,27
+3VSUS 23,27,28,30,33,37,53,81,92
+5VSUS 51,52,81,83
+12VSUS 33,51,81,91
+VCCDSW 25,27
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+3VSUS
B B
DELAY_VR_AND_ALL_SYS92
A A
PM_PWROK
5
Remove DS3 circuit
0928 Ruby
1 2
SP2209 R0402
1 2
SP2210 R0402
U2201
A
1
B
2
3 4
GND
Vcc=2~5.5
R2209 0Ohm@
5
VCC
Y
12
SYS_PWROK
PCIE_WAKE#
ME_AC_PRESENT
GPIO72
0921 Ken
PM_CLKRUN#
PM_PWROK
4
3
1 2
R2220 8.2KOhm
1 2
R2221 10KOhm
SUSCLK_C
+3VS
1 2
R2249 1KOhm@
RI#
ME_SUSPWRDNACK
GND
PLL ON DIE VR ENABLE
HIGH - ENABLED (DEFAULT)
GND
LOW - DISABLED
R2226 10KOhm
R2228 10KOhm
R2224 10KOhm
2
R1.1
0921 Ken
1 2
1 2
1 2
1 2
R2223 10KOhm
1 2
R2227 10KOhm
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+VCCDSW
+3VSUS_ORG
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
C
C
C
PT10SG
PT10SG
Date: Sheet
Date: Sheet
Date: Sheet
PT10SG
Title :
Title :
Title :
Engineer:
Engineer:
Engineer:
1
PCH(3)_FDI,DMI,SYS PWR
PCH(3)_FDI,DMI,SYS PWR
PCH(3)_FDI,DMI,SYS PWR
Ruby Tsai
Ruby Tsai
Ruby Tsai
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
22 104Tuesday, February 26, 2013
22 104Tuesday, February 26, 2013
22 104Tuesday, February 26, 2013
5
4
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3
2
+3VS
+3V
+3VS 4,16,17,20,21,22,25,26,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92
+3V 44,45,57,91
+3VS
1
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D D
CRT_B_PCH46
CRT_G_PCH46
CRT_R_PCH4 6
+3VS
R2309 1KOhm@
R2307 1KOhm@
C C
R2308 1KOhm@
R2320 10KOhm@
R2322 10KOhm
R2323 10KOhm
R2355 2.2KOhm
R2356 2.2KOhm
50 ohm
50 ohm
50 ohm
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
CRT Disable: (For discrete graphic)
1. NC:
CRT_R,CRT_G,CRT_B
CRT_HSYCN,CRT_VSYNC
2. 1KΩ+-5% pull-down to GND:
B B
DAC_IREF
BBS_BIT0,BBS_BIT1 : Boot BIOS Strap
Boot BIOS Strap
0 1
1
1
SHORT_PIN
Close to CPU
L_BKLT_CTRL
eDP_BL_EN
EDP_VDD_EN
DGPU_PWM_SELEC T#
DGPU_HOLD_RST#
DGPU_PWR_EN
DDC_CLK_PCH
DDC_DATA_PCH
3. Connected to GND:
4. Connect to +V3.3:
BBS_BIT0BBS_BIT1
0
0
1
JP2301
12
SHORT_PIN
JR 0924
CRT_ITRN
VCCADAC
Boot BIOS Location
LPC0
Reserved (NAND)
Reserved
SPI
(PCH)
JP2302
Ruby 0925
12
JP2303
12
SHORT_PIN
12
12
R2305
R2304
150Ohm
/UMA/VGA
150Ohm
/UMA/VGA
/UMA/VGA
GND
R2306
150Ohm
1/14 R1.1
STP_A16OVR:
A16 swap override Strap/
Top-Block swap override jumper
Low=Enabled A16 swap override/
Top-Block swap override
High=Default
37.5 ohm
37.5 ohm
37.5 ohm
12
+3VS
DGPU_HOLD_RST#70
CRT_B_J
CRT_G_J
CRT_R_J
DDC_CLK_PCH46
DDC_DATA_PCH46
CRT_HSYNC_PCH46
CRT_VSYNC_PCH46
GND
L_BKLT_CTRL45
PCB_ID925
SP2306 R0402
5 6
10KOhm
3 4
10KOhm
1 2
10KOhm
7 8
10KOhm
1/14 R1.1
strap Pin
1
T2304
PLT_RST#
SP2304
SP2305
R2303
1 2
RN2301C
RN2301B
RN2301A
RN2301D
GND
R0402
1 2
CRT_HSYNC_R
1 2
CRT_VSYNC_R
R0402
1 2
649OHM
DGPU_PWM_SELEC T#
DAC_IREF
eDP_BL_EN
EDP_VDD_EN
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
DGPU_HOLD_RST#
PCB_ID9
DGPU_PWR_EN
BBS_BIT1
STP_A16OVR
U2302
1
A
VCC
2
B
GND3Y
SN74LVC1G08DCKR
1 2
@
R2325 0Ohm
Int. PU
Int. PU
5
4
T45
U44
V45
M43
M45
N42
N44
U40
U39
N36
K36
G36
H20
L20
K17
M20
A12
B13
C12
C10
A10
AL6
+3V
U2001E
VGA_BLUE
VGA_GREEN
VGA_RED
VGA_DDC_CLK
VGA_DDC_DATA
VGA_HSYNC
VGA_VSYNC
DAC_IREF
VGA_IRTN
EDP_BKLTCTL
EDP_BKLTEN
EDP_VDDEN
PIRQA#
PIRQB#
PIRQC#
PIRQD#
GPIO50
GPIO52
GPIO54
GPIO51
GPIO53
GPIO55
POINT
02V000000013
12
GND
R2326
100KOhm
R1.10
LPT_PCH_M_EV
DISPLAY
LVDSCRT
PCI
0921Ken
BUF_PLT_RST# 30,32,33,40,53,70
DDPB_CTRLCLK
DDPB_CTRLDATA
DDPC_CTRLCLK
DDPC_CTRLDATA
DDPD_CTRLCLK
DDPD_CTRLDATA
DDPB_AUXN
DDPC_AUXN
DDPD_AUXN
DDPB_AUXP
DDPC_AUXP
DDPD_AUXP
DDPB_HPD
DDPC_HPD
DDPD_HPD
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PME#
PLTRST#
RN2303B
2.2KOhm
/UMA/VGA
R40
R39
R35
R36
N40
N38
Strap information:
H45
There signals have a weak internal pull down
K43
DDPB_CTRLDATA: "0" = Port is not detected; "1"= Port is detected
DDPC_CTRLDATA: "0" = Port is not detected; "1"= Port is detected
J42
DDPD_CTRLDATA: "0" = Port is not detected; "1"= Port is detected
H43
K45
J44
K40
K38
H39
G17
PCB_ID10
F17
L15
PCB_ID11
M15
PCB_ID8
AD10
Y11
1/14 R1.1
RN2303A
2.2KOhm
/UMA/VGA
3 4
1 2
PCB_ID10 25
R2330 10KOhm
PCB_ID11 25
PCB_ID8 25
PCI_PME#
PLT_RST#
Ruby 0924
HDMI_DDC_CLK_PCH 48
HDMI_DDC_DATA_PCH 48
HDMI_HPD_PCH 48
+3VS
1 2
1
SATA_ODD_DA# 51
T2301
Sampled on rising edge of PWROK.
A A
BBS_BIT020
BBS_BIT0
BBS_BIT1
R1.1
This signal has a weak internal pull-up.
Ken
5
1 2
R2317 1KOhm@
1 2
R2318 1KOhm@
1 2
R2328 10KOhm@
1 2
R2329 10KOhm@
GND
+3VS
STP_A16OVR
R2319 1KOhm@
4
1 2
GND
U2303
@
VGA_PWRON74,91
+3VSUS
3
5
4
R2357 0Ohm
1
A
VCC
2
B
GND3Y
SN74LVC1G08DCKR
1 2
GND
SUSB_EC# 30 ,57,91,92
2
DGPU_PWR_EN
Title :
Title :
Title :
PCH(4)_DP,LVDS,CRT
PCH(4)_DP,LVDS,CRT
Engineer:
Engineer:
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
PT10SG
PT10SG
PT10SG
Engineer:
PCH(4)_DP,LVDS,CRT
1
Ruby Tsai
Ruby Tsai
Ruby Tsai
23 104Tuesday, February 26, 2013
23 104Tuesday, February 26, 2013
23 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
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5
4
3
2
1
+3VSUS
+3VSUS_ORG
+1.5VS
U2001I
D D
PCIE_RXN_WLAN53
WLAN
LAN
C C
PCIE_RXP_WLAN53
PCIE_TXN_WLAN53
PCIE_TXP_WLAN53
PCIE_RXN_LAN33
PCIE_RXP_LAN33
PCIE_TXN_LAN33
PCIE_TXP_LAN33
+1.5VS
+1.5VS
1 2
C2403 0.1UF/16V
1 2
C2404 0.1UF/16V
1 2
C2407 0.1UF/16V
1 2
C2408 0.1UF/16V
R2402 0Ohm
R2401 7.5KOhm
12
1 2
PCIE_TXN_WLAN_C
PCIE_TXP_WLAN_C
PCIE_TXN_LAN_C
PCIE_TXP_LAN_C
PCIE_IREF
PCIE_RCOMP
AW31
AY31
BE32
BC32
AT31
AR31
BD33
BB33
AW33
AY33
BE34
BC34
AT33
AR33
BE36
BC36
AW36
AV36
BD37
BB37
AY38
AW38
BC38
BE38
AT40
AT39
BE40
BC40
AN38
AN39
BD42
BD41
BE30
BC30
BB29
BD29
PERN1/USB3RN3
PERP1/USB3RP3
PETN1/USB3TN3
PETP1/USB3TP3
PERN2/USB3RN4
PERP2/USB3RP4
PETN2/USB3TN4
PETP2/USB3TP4
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
PERN_6
PERP_6
PETN_6
PETP_6
PERN_7
PERP_7
PETN_7
PETP_7
PERN_8
PERP_8
PETN_8
PETP_8
PCIE_IREF
TP11
TP6
PCIE_RCOMP
POINT
02V000000013
LPT_PCH_M_EDS
PCIe
B37
USB2N0
D37
USB2P0
A38
USB2N1
C38
USB2P1
A36
USB2N2
C36
USB2P2
A34
USB2N3
C34
USB2P3
B33
USB2N4
D33
USB2P4
F31
USB2N5
G31
USB2P5
K31
USB2N6
L31
USB2P6
G29
USB2N7
H29
USB2P7
A32
USB2N8
C32
USB2P8
A30
USB2N9
C30
USB2P9
B29
USB2N10
D29
USB2P10
A28
USB2N11
C28
USB2P11
G26
USB2N12
F26
USB2P12
F24
USB2N13
USB
USB2P13
USB3RN1
USB3RP1
USB3TN1
USB3TP1
USB3RN2
USB3RP2
USB3TN2
USB3TP2
USB3RN5
USB3RP5
USB3TN5
USB3TP5
USB3RN6
USB3RP6
USB3TN6
USB3TP6
USBRBIAS#
USBRBIAS
TP24
TP23
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
G24
AR26
AP26
BE24
BD23
AW26
AV26
BD25
BC24
AW29
AV29
BE26
BC26
AR29
AP29
BD27
BE28
K24
K26
M33
L33
P3
V1
U2
P1
M3
T1
N2
M1
USB_BIAS#
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO9
OC6#/GPIO10
OC7#/GPIO14
1 2
R2416 22.6Ohm
USBCOMP (R2416): TIE TRACES TOGETHER CLOSE
TO PINS,WITH LENGTH NO
LONGER THAN 450 MILS TO RESISTOR
7 8
10KOhm
1 2
10KOhm
3 4
10KOhm
1 2
10KOhm
7 8
10KOhm
5 6
10KOhm
3 4
10KOhm
5 6
10KOhm
USB_PN0 52
USB_PP0 52
USB_PN1 52
USB_PP1 52
USB_PN2 52
USB_PP2 52
USB_PN3 52
USB_PP3 52
USB_PN4 45
USB_PP4 45
USB_PN5 45
USB_PP5 45
USB_PN8 40
USB_PP8 40
USB_PN9 53
USB_PP9 53
RN2401D
RN2401A
RN2401B
RN2402A
RN2402D
RN2401C
RN2402B
RN2402C
USB port(daughter board, 17 on ly)
USB port (Debug Port, daughter board)
USB port
USB port
TP
Camera
Card Reader
WIFI/BT module
USB3_RX1_N 52
USB3_RX1_P 52
USB3_TX1_N 52
USB3_TX1_P 52
USB3_RX2_N 52
USB3_RX2_P 52
USB3_TX2_N 52
USB3_TX2_P 52
GND
Place within 500 mils of PCH
+3VSUS_ORG
+3VSUS 22,23,27,28,30,33,37,53,81,92
+3VSUS_ORG 20,21,22,25,26,27
+1.5VS 20,21,22,26,27,53,57,84
1
USB CONN location
3
2
TP
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Title :
Title :
Title :
PCH(5)_PCI,NVRAM,USB
PCH(5)_PCI,NVRAM,USB
PCH(5)_PCI,NVRAM,USB
Ruby Tsai
Ruby Tsai
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
C
C
C
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
Ruby Tsai
24 104Tuesday, February 26, 2013
24 104Tuesday, February 26, 2013
24 104Tuesday, February 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
5
BIOS Rev. SKU
ID0 ID1 ID2 PCB Rev.
0 0 0 R1.0
1 0 0 R1.1
0 1 0 R2.0
1 1 0 R2.1
0 0 1 TBD
1 0 1 TBD
0 1 1 TBD
D D
EXT_SMI #
PM_LANPHY_E N
WLAN_O N
BT_ON/OF F#
GPIO8
GPIO57
GPIO8
C C
DGPU_PW ROK
12/3 R1.1
1031 Daniel
GPIO69
GPIO34
1203 Ruby
GPIO16
SATA_O DD_PRS NT#_R
0925 Ken
GPIO27
B B
1 1 1 TBD
CPU. PWR
ID7 ID8 CPU PWR.
0 0 CPU 17W
1 0 CPU 35W
0 1 CPU 45W
1 1 TBD
+3VSUS_O RG
12
R2529 1K Ohm
12
R2538 10KOhm
0925 Ken
R2591 10 0KOhm@
1120 Ken
R2592 10 0KOhm@
R2531 10KOhm@
0927 Ken
0928 JR
R2541 10KOhm
@
R2590 10KOhm@
R2539 10KOhm
R2545 10KOhm
R2537 10KOhm
R2546 10 KOhm
R2520 10 KOhm
R2548 10 KOhm@
remove DDR_VOLT_DEL
0920 Ken
1 2
R2518 1K Ohm1%
+3VS GND
@
Functional Strap Definitions
Usage: TLS Confidentiality(Intel Crypto Transport Layer Security)
"0" = Disable
"1" = Enable
Clear password for TODs required
Place ONTO D-part
GND
JRST25 01
112
SGL_JUMP
2
12
12
12
12
12/3 R1.1
12
12
12
12
12
12
12
FDI_OV RVLTG
GPIO36
0925 Ken
GPIO16
R2538:
Stuff -> non Intel LAN
No stuff -> Intel LAN( Pull up on chip side)
GND
+3VS
+VCCDSW
1 2
R2519 10 0KOhm
1 2
R2589 10 KOhm
Functional Strap Definitions
Usage: Reserved
PCB_ID3
1: Starndard
0: Entry
GND
PCB_ID4
1: Premium
0: Mainstream
T2501
1
EXT_SMI #3 0,44
DGPU_PW ROK87,91,92
WLAN_L ED56
BT_ON/OF F#53
WLAN_O N53
CRT_IN#46
SATA_O DD_PRS NT#_R51
SATA_O DD_PW RGT51
0917 Ken
IO Flexible:
GPIO70
GPIO70
PCB_ID5
1:USB3.0*2
0:USB3.0*1
1 2
SP2501 R 0402
12/3 R1.1
R2556 10 KOhm@
R2558 10KOhm@
PCB_ID 2
PCB_ID 3
PCB_ID 4
PCB_ID 5
GPIO8
PM_LANPHY_E N
GPIO15
GPIO16
DGPU_PW ROK
GPIO27
GPIO34
GPIO36
FDI_OV RVLTG
PCB_ID 0
PCB_ID 1
PCB_ID 6
GPIO57
GPIO69
GPIO70
PCB_ID 7
GND
12
12
4
LPT_PCH_M_EDS
GPIO
PCB_ID10
1: UMA
0: PX
NCTF
CPU/Misc
PROCPWRGD
PLTRST_PROC#
PCB_ID6
1: HDMI
0: no HDMI
0917 Ken
0920 Ken
0928 JR
1203 Ruby
1031 Daniel12/3 R1.1
+3VS
GND
PCB_ID9
1: Zero_ODD
0: Non Zero ODD
U2001F
AT8
BMBUSY#/GPIO0
F13
TACH1/GPIO1
A14
TACH2/GPIO6
G15
TACH3/GPIO7
Y1
GPIO8
K13
LAN_PHY_PWR_CTRL/GPIO12
AB11
GPIO15
AN2
SATA4GP/GPIO16
C14
TACH0/GPIO17
BB4
SCLOCK/GPIO22
Y10
GPIO24
DSW
R11
GPIO27
AD11
GPIO28
AN6
GPIO34
AP1
GPIO35/NMI#
AT3
SATA2GP/GPIO36
AK1
SATA3GP/GPIO37
AT7
SLOAD/GPIO38
AM3
SDATAOUT0/GPIO39
AN4
SDATAOUT1/GPIO48
AK3
SATA5GP/GPIO49
U12
GPIO57
C16
TACH4/GPIO68
D13
TACH5/GPIO69
G13
TACH6/GPIO70
H15
TACH7/GPIO71
BE41
VSS25
BE5
VSS24
C45
VSS23
A5
VSS22
POINT
02V000 000013
USB3 Port 3 PCIE Port2 Mode (U SB3P3_PCIEP2_MODE)
USB3p3_tach6_gp70 pin is a ‘0’ , then Root Port 2 is
assigned to USB3 Port 3, else it is assigned to PCI Expres s.
USB3 Port 2 PCIE Port1 Mode (U SB3P2_PCIEP1_MODE)
USB3p2_tach7_gp71 pin is a ‘0’ , then Root Port 1is
assigned to USB3 Port 2, else it is assigned to PCI Expres s.
THRMTRIP#
3
+3VS 4,16 ,17,20,21 ,22,23,2 6,27,28,3 0,31,32 ,36,40,45 ,46,48,5 0,51,53,5 7,91,92
+3VSUS_O RG 20,21,22,24,2 6,27
+VCCDSW 22,2 7
PCB_ID14PCB_ID13
1: USB3.0
0. Enable KB_LED
0: non USB3.0
PCB_ID15
1: PS/2+SMBUS TP
0: PS/2 TP
+3VSUS_O RG
PCB_ID12PCB_ID11
1: S&M
1: eDP 1. Disabl e KB_LED
0: NoS&M
0: LVDS
+3VS
+VCCDSW
R1.1 2/19
AN10
TP14
AY1
H_PECI_ R
PECI
AT6
RCIN#
AV3
AV1
PM_THRMTRI P#
AU4
N10
VSS3
A2
VSS4
A41
VSS13
A43
VSS14
A44
VSS12
B1
VSS11
B2
VSS10
B44
VSS21
B45
VSS9
BA1
VSS1
BC1
VSS2
BD1
VSS8
BD2
VSS6
BD44
VSS7
BD45
VSS5
BE2
VSS20
BE3
VSS19
D1
VSS18
E1
VSS17
E45
VSS16
A4
VSS15
1 2
R25140Ohm @
1 2
R2516390Ohm 1%
1 2
GND
Intel is recommended that moth erboard designs implement a
pull-up resistor site on the THRMTRIP# signal to the
PCH 1.05V Core VR
0917 Ken
GND
R25661KOhm @
THRMTRIP#
A20GAT E 30
H_PECI 4
RCIN# 30
H_CPUPW RGD 4
H_THRMTRI P# 4,32
+V1.05VS _PCH_V CC
PCH_PLT RST_CP U 4
43Ohm
1 2
@
GND
R2515
12
C2501
47PF/50 V
close to EC
0920 Ken
H_PECI_ EC 30
2
+3VS
+3VS +3VS+3 VS +3VS
12
12
R2525
R2527
10KOhm
10KOhm
12
12
R2528
R2526
10KOhm
10KOhm
@
GND
GND
+3VS
+3VS
12
12
R2572
10KOhm
/HDMI
12
12
R2569
10KOhm
@
GND
GND
+3VS
12
R2588
10KOhm
@
12
R2587
10KOhm
@
GND
@
R2570
10KOhm
R2571
10KOhm
1
+3VS
12
12
R2553
10KOhm
@
12
12
R2554
10KOhm
GND
+3VS
12
R2568
10KOhm
@
12
R2567
10KOhm
@
GND
+3VS
12
R2584
10KOhm
12
R2583
10KOhm
@
GND
R2562
10KOhm
@
R2564
10KOhm
12
@
12
@
R2582
10KOhm
R2579
10KOhm
12
12
R2560
R2561
10KOhm
10KOhm
/U3_2
@
12
12
R2563
R2565
10KOhm
10KOhm
/U3_1
@
GNDGND GND
+3VS+3 VS +3V S
12
12
R2581
R2576
10KOhm
10KOhm
/UMA
@
12
12
R2574
R2573
10KOhm
10KOhm
/PX
@
GNDGND GND
+3VS
12
R2593
10KOhm
/SMBus
12
R2594
1KOhm
/PS2
GND
PCB_ID 0
PCB_ID 1
PCB_ID 2
PCB_ID 3
PCB_ID 4
PCB_ID 5
PCB_ID 6
PCB_ID 7
PCB_ID 8
PCB_ID 9
PCB_ID 10
PCB_ID 11
PCB_ID 12
PCB_ID 14
PCB_ID 15
PCB_ID 8 23
PCB_ID 9 23
PCB_ID 10 23
PCB_ID 11 23
PCB_ID 12 21
PCB_ID 14 21
PCB_ID 15 21
R1.1 2/19
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Title :
Title :
Title :
PCH(6)_CPU,GPIO,MISC
PCH(6)_CPU,GPIO,MISC
PCH(6)_CPU,GPIO,MISC
Engineer:
Ruby Tsai
Engineer:
Ruby Tsai
Engineer:
BG1\COR E
BG1\COR E
BG1\COR E
Size Project Name
Size Project Name
Size Project Name
D
D
D
PT10SG
PT10SG
PT10SG
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
Ruby Tsai
25 1 04Tuesday, Feb ruary 26, 2013
25 1 04Tuesday, Feb ruary 26, 2013
25 1 04Tuesday, Feb ruary 26, 2013
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
5
4
3
2
1
+VCCA_DAC_1_2
12
12
C2613
0.1UF/16V
GND
+V3.3S_ADACBG
C2623 10UF/6.3V
12
12
C2615
1UF/6.3V
1UF/6.3V
12
C2622
0.1UF/16V
GND
GND
C2620
10UF/6.3V
@
12
C2614
10UF/6.3V
GNDGND
@
1 2
C2608
0Ohm
1 2
R2630
0Ohm
1 2
R2637
0Ohm
1 2
R2636
12
1UF/6.3V
C2607
C2612
LPT_PCH_M_EDS
Core
PCIe/DMI
VCCMPHY
CRT DAC
HVCMOS
USB3
SATA
P45
P43
M31
BB44
AN34
AN35
R30
R32
Y12
AJ30
AJ32
AJ26
AJ28
AK20
AK26
AK28
BE22
AK18
AN11
AK22
AM18
AM20
AM22
AP22
AR22
AT22
70mA
13mA
+3VS_VCC_GIO
VCCADAC1_ 5
VSS26
VCCADACBG 3_3
FDI
VCCVRM2
VCCIO1
VCCIO2
VCC3_3_R 30
VCC3_3_R 32
DCPSUS1
VCCSUS3_ 3_1
VCCSUS3_ 3_2
DCPSUS3_ 1
DCPSUS3_ 2
VCCIO3
VCCVRM3
VCCVRM4
VCCVRM5
VCCIO4
VCCVRM1
VCCIO9
VCCIO11
VCCIO10
VCCIO5
VCCIO6
VCCIO7
VCCIO8
AD20
AD22
AD24
AD26
AD28
AG18
AG20
AG22
AG24
AA24
AA26
AE18
AE20
AE22
AE24
AE26
AA18
U14
U18
U20
U22
U24
V18
V20
V22
V24
Y26
Y18
Y20
Y22
U2001G
VCC7
VCC8
VCC9
VCC11
VCC10
VCC12
VCC13
VCC1
VCC17
VCC2
VCC16
VCC15
VCC14
VCC6
VCC5
VCC4
VCC3
DCPSUSBYP
VCCASW 12
VCCASW 11
VCCASW 1
VCCASW 2
VCCASW 3
VCCASW 9
VCCASW 10
VCCASW 4
VCCASW 5
VCCASW 6
VCCASW 7
VCCASW 8
POINT
02V000000013
LPT_PCH_M_EDS
U2001J
AL34
VSS116
D D
C C
AL38
VSS115
AL8
VSS114
AM14
VSS113
AM24
VSS112
AM26
VSS111
AM28
VSS91
AM30
VSS90
AM32
VSS110
AM16
VSS118
AN36
VSS89
AN40
VSS88
AN42
VSS117
AN8
VSS109
AP13
VSS108
AP24
VSS87
AP31
VSS107
AP43
VSS86
AR2
VSS85
AK16
VSS84
AT10
VSS83
AT15
VSS82
AT17
VSS37
AT20
VSS36
AT26
VSS35
AT29
VSS38
AT36
VSS34
AT38
VSS80
D42
VSS33
AV13
VSS32
AV22
VSS119
AV24
VSS39
AV31
VSS28
AV33
VSS31
BB25
VSS29
AV40
VSS30
AV6
VSS106
AW2
VSS105
F43
VSS81
AY10
VSS104
AY15
VSS103
AY20
VSS102
AY26
VSS101
AY29
VSS100
AY7
VSS99
B11
VSS98
B15
VSS97
POINT
02V000000013
GND GND
VSS96
VSS95
VSS94
VSS93
VSS92
VSS40
VSS42
VSS41
VSS43
VSS45
VSS44
VSS48
VSS47
VSS46
VSS49
VSS50
VSS53
VSS52
VSS51
VSS55
VSS54
VSS56
VSS58
VSS57
VSS60
VSS59
VSS61
VSS62
VSS63
VSS65
VSS64
VSS66
VSS67
VSS68
VSS71
VSS70
VSS69
VSS73
VSS72
VSS74
VSS76
VSS75
VSS78
VSS77
VSS79
K39
L2
L44
M17
M22
N12
N35
N39
N6
P22
P24
P26
P28
P30
P32
R12
R14
R16
R2
R34
R38
R44
R8
T43
U10
U16
U28
U34
U38
U42
U6
V14
V16
V26
V43
W2
W44
Y14
Y16
Y24
Y28
Y34
Y36
Y40
Y8
+V1.05VS_PCH_VCC
GND
+V1.05VM_VCCASW
12
1 2
C2609 1UF/6.3V
12
C2625
22UF/6.3V
12
C2602
C2601
1UF/6.3V
10UF/6.3V
GNDGND GND GND
1 2
R2606 5.1Ohm
12
C2626
1UF/6.3V
12
GNDGNDGND
C2603
1UF/6.3V
12
C2627
1UF/6.3V
1.29A
12
C2604
1UF/6.3V
+PCH_VCCDSW
0.67A
0.01UF/50V
GND
+V1.5S_VCCAPLL_FDI
+V1.05S_VCC_EXP
C2610
1UF/6.3V
T2601
1
T2602
1
+V1.05S_VCC_EXP
+VCCAPLL_USB3
+VCCAPLL_EXP
1 2
C2619 10UF/6.3V
@
+VCCAPLL_SATA3
GND
12
GND
12
C2621
22UF/6.3V
@
GND
GND
12
1UF/6.3V
+3VSUS_ORG
+3VSUS_VCCPSUS
1kOhm/100Mhz
1 2
1 2
C2611
+1.5VS
+1.5VS
0Ohm
R2631
0Ohm
R2632
B2604
12
21
2/4 R1.1
1UF/6.3V
C2624
+1.5VS
+3VS
+VTT_PCH_VCCIO
+1.5VS
12
GND
C2616
10UF/6.3V
1 2
12
C2618
0.1UF/16V
12
GND
vx_r1206_h28
0Ohm
R2633
0Ohm
1 2
R2635
@
12
+3VS
R2634 0Ohm
+1.5VS
+1.05VS +V1.05VS_PCH_VCC
JP2601
1.29A
2
112
2MM_OPEN_5MIL
JP2602
2
112
B B
2MM_OPEN_5MIL
JP2603
112
2MM_OPEN_5MIL
2
0.67A
3.629
+V1.05VM_VCCASW
+VTT_PCH_VCCIO
+V1.05VM_VCCASW
+V1.05VS_PCH_VCC
+VTT_PCH_VCCIO
+1.05VS
+1.5VS
+VCCA_DAC_1_2
+V3.3S_ADACBG
+3VSUS_VCCPSUS
+V1.05VM_VCCASW 27
+V1.05VS_PCH_VCC 25
+VTT_PCH_VCCIO 27
+1.05VS 4,27,32,57,80,82
+1.5VS 20,21,22,24,27,53,57,84
+3VS
+3VS 4,16,17,20,21,22,23,25,27,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92
+VCCA_DAC_1_2
+V3.3S_ADACBG
+3VSUS_VCCPSUS 27
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Title :
Title :
Title :
PCH(7)_POWER,GND
PCH(7)_POWER,GND
PCH(7)_POWER,GND
Ruby Tsai
Ruby Tsai
Ruby Tsai
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
Rev
Rev
Rev
1.1
1.1
1.1
26 104Tuesday, February 26, 2013
26 104Tuesday, February 26, 2013
26 104Tuesday, February 26, 2013
of
of
of
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Name
Size Project Name
Size Project Name
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
5
LPT_PCH_M_EDS
U2001K
AA16
VSS136
AA20
VSS197
AA22
VSS196
AA28
AB12
AB34
AB38
AC44
AD14
AD16
AD18
AD30
AD32
AD40
AE16
AE28
AF38
AG16
AG26
AG28
AG44
AK14
AK24
AK43
AK45
AL12
BC22
BB42
AA4
AC2
AD6
AD8
AF8
AG2
AJ16
AJ18
AJ20
AJ22
AJ24
AJ34
AJ38
AL2
AB8
AJ6
AJ8
VSS195
VSS194
VSS193
VSS192
VSS146
VSS128
VSS145
VSS191
VSS190
VSS189
VSS204
VSS203
VSS202
VSS209
VSS208
VSS188
VSS187
VSS186
VSS185
VSS184
VSS183
VSS201
VSS200
VSS199
VSS198
VSS182
VSS148
VSS147
VSS150
VSS149
VSS181
VSS180
VSS179
VSS178
VSS177
VSS176
VSS175
VSS174
VSS173
VSS172
VSS206
VSS205
POINT
02V000000013
D D
C C
B B
VSS171
VSS170
VSS169
VSS168
VSS167
VSS166
VSS165
VSS164
VSS163
VSS162
VSS161
VSS160
VSS159
VSS129
VSS130
VSS131
VSS132
VSS144
VSS133
VSS143
VSS134
VSS142
VSS135
VSS121
VSS120
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS139
VSS140
VSS141
VSS138
VSS158
VSS137
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS207
+1.05VS
+3VS
+1.05VS
B19
B23
B27
B31
B35
B39
B7
BA40
BD11
BD15
BD19
AY36
AT43
BD31
BD35
BD39
BD7
D25
AV7
F15
F20
F29
F33
BC16
D4
G2
G38
G44
G8
H10
H13
H17
H22
H24
H26
H31
H36
H40
H7
K10
K15
K20
K29
K33
BC28
+1.05VS
+1.5VS
GNDGND
0Ohm
1 2
+1.05VS_VCC_SSCFF +3VS_VCC_FLEX0 +3VS_VCC_FLEX1
R2706
12
C2745
1UF/6.3V
GND GND
0Ohm
1 2
+3VS_VCC_FLEX23 +3V S_VCC_ASEPCI +VCCCLKF135
R2709
12
C2748
1UF/6.3V
GND
0Ohm
1 2
+1.05VS_VCCCLKF100 +1.05VS_VCCSSCF100
R2712
12
C2751
1UF/6.3V
GND
+3VSUS_ORG
1 2
R2726 0Ohm
C2714
0.1UF/16V
GND
+VCCAXCK_VRM
R2729
1 2
0Ohm
12
+1.05VS
C2742
10UF/6.3V
GND
+3VS
+3VS
+1.05VS
12
+VTT_PCH_VCCIO
0Ohm
1 2
R2707
0Ohm
1 2
R2710
0Ohm
1 2
R2713
4
1 2
R2704 0Ohm
1 2
R2727 0Ohm
+3VS
1 2
R2728 0Ohm
vx_r0402_small
0Ohm
1 2
R2705
12
C2743
10UF/6.3V@
12
C2746
1UF/6.3V
12
C2749
1UF/6.3V
GND
12
C2752
1UF/6.3V
GND
+3VSUS_VCCPUSB
C2705
0.1UF/16V
GND
+1.05VS_VCCAUSB
+3VS_VCCAUBG
1 2
C2741 0.1UF/16V
+1.05VS_VCCUSBCORE
1 2
C2759 0.1UF/16V
+1.05VS_VCC_AXCK_DCB
12
+1.05VS_VCC_SSCFF
C2744
1UF/6.3V
+3VS_VCC_FLEX0
+3VS_VCC_FLEX1
+3VS_VCC_FLEX23
GND
+3VS_VCC_ASEPCI
+VCCCLKF135
+1.05VS_VCC_SSCFF
+1.05VS_VCCCLKF100
+1.05VS_VCCSSCF100
+1.05VS_VCCCLKF100
+1.05VS_VCCSSCF100
+3VS
0Ohm
1 2
R2708
+1.05VS
0Ohm
1 2
R2711
3
12
GND
GND
GND
T2701
12
C2747
1UF/6.3V
GND
12
C2750
1UF/6.3V
GND
U2001H
R24
VCCSUS3_3_9
R26
VCCSUS3_3_3
R28
VCCSUS3_3_4
U26
VCCSUS3_3_5
M24
VSS27
U35
VCCUSBPLL
L24
VCC3_3_1
U30
VCCIO12
V28
VCCIO14
V30
VCCIO13
Y30
VCCIO16
1
Y35
DCPSUS2
AF34
VCCVRM7
AP45
VCC20
Y32
VCCCLK1
M29
VCCCLK3_3_1
L29
VCCCLK3_3_2
L26
VCCCLK3_3_3
M26
VCCCLK3_3_4
U32
VCCCLK3_3_5
V32
VCCCLK3_3_6
AD34
VCCCLK2
AA30
VCCCLK3
AA32
VCCCLK4
AD35
VCCCLK5
AG30
VCCCLK6
AG32
VCCCLK7
AD36
VCCCLK8
AE30
VCCCLK9
AE32
VCCCLK10
POINT
02V000000013
LPT_PCH_M_EDS
GPIO/LPC
USB
Azalia
RTC
CPU
ICC
SPI
Fuse
Thermal
GND
261mA
12
C2755
1UF/6.3V
+3VM_VCCPSPI
+3VSUS_ORG
20mA
Deep sleep mode: JP2703
Normal mode: JP2704
VCCSUS3_3_6
VCCSUS3_3_7
VCCDSW3_3
VCCSUSHDA
VCCSUS3_3_8
V_PROC_IO_1
V_PROC_IO_2
+3VSUS_VCCPSUS
R20
R22
A16
AA14
DCPSST
AE14
VCC3_3_2
AF12
VCC3_3_3
AG14
VCC3_3_4
U36
VCCIO15
A26
K8
A6
VCCRTC
P14
DCPRTC1
P16
DCPRTC2
AJ12
AJ14
AD12
VCCSPI
P18
VCC18
P20
VCC19
L17
VCCASW13
R18
VCCASW14
AW40
VCCVRM6
AK30
VCC3_3_5
AK32
VCC3_3_6
R2617 0Ohm
12
+3VS_VCCPCORE
+V1.05S_VCCAUX
+3VSUS_VCCPAZSUS
+VCCPRTCSUS
+VCCRTCEXT
+1.05VS_VCCPCPU
+3VM_VCCPSPI
+3VS_VCCPFUSE
+PCH_VCC_1_1_20
+PCH_VCC_1_1_21
+V1.5S_VCCATS
+3VS_VCCPTS
+VCCDSW
+VCCSST
+3VM_SPI
2
+VCCDSW
1 2
GND
12
GND
12
12
+VTT_PCH_VCCIO
0Ohm
1 2
R2716
1 2
0Ohm
R2717
C2717
0.1UF/16V
C2719
0.1UF/16V
R2722 0Ohm
R2723 0Ohm
R2724
R2725
C2721
0.1UF/16V
C27160.1UF/16 V
+3VSUS_ORG
C2722
0.1UF/16V
12
C2720
0.1UF/16V
1 2
1 2
1 2
0Ohm
1 2
0Ohm
+VCCPRTCSUS
GND
R2730
12
C2723
0.1UF/16V
0Ohm
1 2
12
C2701
0.01UF/50V
GND
12
C2760
1UF/6.3V
GND
12
C2754
1UF/6.3V
GND
+V1.05VM_VCCASW
+V1.05VM_VCCASW
+1.5VS
+3VS
12
C2753
1UF/6.3V
GND
+VCC_RTC
12
1 2
1 2
+3VS
C2715
0.1UF/16V
GND
@
R2731
0Ohm
0Ohm
Unstuff R2731, stuff R2732
Intel MOW WW09: renamed
VCCIO2PCH to RSVD
+VCCIO2PCH
R2732
+1.05VS
1 2
R2719 0Ohm
@
1 2
R2718 0Ohm
R2714 0Ohm
12
R1.1
+3VSUS_ORG +3VA
1
1 2
+3VSUS_ORG
12
C2718
0.1UF/16V
GND
GND
12
R2721
0Ohm
@
C2756
1UF/6.3V
+1.05VS+3VS
R2720
0Ohm
R1.10
1 2
1 2
0921Ken
+3VSUS
JP2704
@
2
112
1MM_OPEN_M1M2
https://t.me/schematicslaptop
A A
https://t.me/biosarchive
https://t.me/schematicslaptop
https://t.me/biosarchive
+V1.05VM_VCCASW
+3VSUS
+3VSUS_ORG
+1.5VS
+1.05VS
+VTT_PCH_VCCIO
+VCCAXCK_VRM
+3VSUS_VCCPSUS
+3VA
+VCC_RTC
+VCCIO2PCH
+V1.05VM_VCCASW 26
+3VSUS 22,23,28,30,33,37,53,81,92
+3VSUS_ORG 20,21,22 ,24,25,26
+1.5VS 20,21,22,24,26,53,57,84
+3VS
+3VS 4,16,17,20,21,22,2 3,25,26,28,30,31,32,36,40,45,46,48,50,51,53,57,91,92
+1.05VS 4,26,32,57,80,82
+VTT_PCH_VCCIO 26
+VCCAXCK_VRM 21
+3VSUS_VCCPSUS 26
+3VA 20,30,33,57,60,65 ,81,88,93
+VCC_RTC 20 ,22
+VCCIO2PCH 6
Title :
Title :
Title :
PCH(8)_POWER,GND
PCH(8)_POWER,GND
PCH(8)_POWER,GND
Ruby Tsai
Ruby Tsai
Ruby Tsai
Engineer:
Engineer:
PT10SG
PT10SG
PT10SG
Engineer:
1
Rev
Rev
Rev
1.1
1.1
1.1
of
of
of
27 104Tuesday, February 26, 2013
27 104Tuesday, February 26, 2013
27 104Tuesday, February 26, 2013
BG1\CORE
BG1\CORE
BG1\CORE
Size Project Nam e
Size Project Nam e
Size Project Nam e
Custom
Custom
Custom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
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