Toshiba DAKAR10F/FG (45W CPU), MP(A02) BUILD Schematic

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.

8

7 6 5 4 3 2 1

HSF Property:ROHS or Halogen-Free

E

D

DAKAR10F/FG

(45W CPU)

MP(A02) BUILD

2012.03.23

FF

E

D

C

B

A

21-OCT-2002

DATE CHANGE NO.

8

REV

7 6 5 4 3

DRAWER

DESIGN

CHECK

RESPONSIBLE

SIZE=
FILE NAME:
P/N

LOREN
LOREN
BRYAN
BRYAN

C

B

A

POWER

DATEDATEEE
EDISON
EDISON
BY
BY

2

2012.03.23

2012.03.23

2012.03.23

2012.03.23

VER:

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

DAKAR10F/FG MAIN BOARD

CODE

SIZE

C

CS

SHEET

DOC.NUMBER REV

1310A2491301-0-MTR

1310xxxxx-0-0

of

1

X01

701

2012.03.23

2012.03.23

2012.03.23

2012.03.23

XXX

8 7

6 5

TABLE OF CONTENTS

4

3 2 1

D

PAGE

1. COVER PAGE

2. INDEX

3. BLOCK DIAGRAM

4. POWER MAP

5. POWER CHARGER

6. POWER +V3LA/+V3A/+5A

7. POWER +V1.5/+V0.75

8. POWER +V1.8S

9. POWER VCCIO

10. POWER VCCSA

11. POWER VCORE

12. POWER VGFX

13. POWER VCORE_DGPU

14. ENABLE PIN

15. LOAD SWITCH-1

16. LOAD SWITCH-2

17. PCB SCREW

B

18. HALL SENSOR

19. LED

20. K/B & TP/B CONN

21. EC

22. LAN

23. RJ45 & TRANSFORMER

24. AUDIO CODEC

PAGE

26. CARDREADER

27. MINI1 WLAN/DEBUG CARD

28. MINI2 3G/LTE

29. SATA HDD/ODD CONN

30. USB 2.0 CONN

31. USB 3.0 CONTROLLER(REMOVE)

32. USB 3.0 CONN W/ S&C

33. USB 3.0 CONN

34. LCM CONN

35. CRT CONN

36. HDMI CONN

37. HDMI CEC

38. DDR3 DIMM0

39. DDR3 DIMM1

40. FAN & THERMAL SENSOR

41. CPU 1

42. CPU 2

43. CPU 3 DRAM

44. CPU 4 POWER

45. CPU 5 POWER

46. CPU 6 GND

47. PCH 1

48. PCH 2

49. PCH 3

PAGE

51. PCH 5 USB

52. PCH 6 MISC

53. PCH 7 POWER

54. PCH 8 POWER

55. PCH 9 GND

56. VGA 1

57. VGA 2

58. VGA 3

59. VGA 4

60. VGA 5

61. VGA 6

62. VRAM 1

63. VRAM 2

64. VRAM 3

65. VRAM 4

66. USB BOARD

67. PICK BUTTON BOARD(4 PIN)

68. POWER BUTTON BOARD

69. EMI

70. PICK BUTTON BOARD(8 PIN)

D

CC

B

50. PCH 4 AXG25. SPEAKER/HP JACK/MIC JACK

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

702

8 7

6 5

4

3 2 1

AMD

PEG

W/ POWER EXPRESS

THAMES LE \ THAMES XT \

SEYMOUR XTX

29X 29 MM

D

IVY BRIDGE \

SANDY BRIDGE

QC 45W

SOCKET-RPGA989

37.5 X 37.5 X 5 mm

FDI

DMI 2.0

DDR3 INTERFACE

DDR3 INTERFACE

DDR3@1.5/0.75V

(1333/1600 MHZ)
204-PIN SODIMM0

DDR3@1.5/0.75V

(1333/1600 MHZ)

204-PIN SODIMM1

D

INTERNAL MIC IN

AUDIO CODEC

EXT MIC IN
HEADPHONE

CC

HDMI

HDA

REA_ALC269Q_VB6

PCH

CRT

LCM

PANTHER POINT

USB2.0

25 X 25 X 2.3 mm

LVDS

SLEEP & CHARGE

USB_0: USB CONN
USB_2: USB CONN

USB_8: CARD READER
USB_9: MINICARD WLAN

USB_10:WEBCAM

B

RJ45

PCIE_1:LAN

PCIE

USB3.0

USB_1: USB3.0 CONN

B

ATHEROS_AR8161/8162

PCIE_2:WLAN

PCIE

USB2.0

SATA

SPI

USB_8:

SATA0:HDD
SATA2 ESATA

CARD READER

REA_RTS5129

SATA5: ODD

ENE-P2809A

THERMAL SENSOR

EC WINDBOND

NPCE885LA0DX

SPI

SPI FLASH 4MB

WINB_W25Q32BVSSIG

AA

BATTERY CHARGER &

DC/DC & IMVP 7

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

703

1

REV

X011310xxxxx-0-0

LI-ION BATTERY

6-Cell

8

7 6

KEYBOARD

TOUCH PAD

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

8 7

6 5

4

3 2 1

ADAPTOR

FUSE

65W-75W 8A 6036A0003401
90W 10A 6036A0002901

D

120W 12A 6036A0006001

BQ24725RGRR

CHARGER

EC_SMB2
CHG_EN
BATT_IN
ACPRES

+VBAT

TPS51123

POWER BUDGET 14.745 A
F 300K
OCP 10.52A R=140K
PEAK 9.23A AVG 1.809A
330UF_25MΩ // 49.1UF_6.648MΩ

BATTERY PACK

+V5A_+-5%

NMOS

POWER BUDGET 4.711A
PEAK2.592A

122.42UF_0.658MΩ

TSP51461

POWER BUDGET 6A
F 340K
OCP 6A
PEAK 6A AVG 1.262A

+V5S

INRUSH 0.55A

+V0.85S_+-0.5%

D

+V3LA_+-5%

+VCORE_+-0.5%

+VCORE_+-0.5%

TPS51650

POWER BUDGET 94A
F 280K
OCP 104.5A
PEAK 94A AVG 45.3A
1880UF_1.1MΩ // 2276UF_0.203MΩ

TPS51123

POWER BUDGET 12.186 A
F 375K

OCP 8.40A R=120K
PEAK 7.31A AVG1.7 A
3300UF_25MΩ //6.7UF_5.458MΩ

NMOS

POWER BUDGET 4.711A
PEAK2.592A

3.6UF_8.409MΩ PEAK2.592A

NMOS

POWER BUDGET 4.711A
PEAK2.592A

75.6UF_0.986MΩ

+V3A

INRUSH 0.984A

+V3S

INRUSH 1.06A

NMOS

POWER BUDGET 4.711A

5.9UF_9.497MΩ

RT8068

POWER BUDGET 4.711A
PEAK2.592A

56.12UF_1.505MΩ

+V3_LAN

INRUSH 0.464A

+V1.8S

INRUSH 0.6A

CC

+V3S_DGPU

VDD_CORE

TPS51728

POWER BUDGET 46A
F 340K
OCP 50A

B

PEAK 46A AVG 38.7A
560UF_25MΩ // 80UF_0.93MΩ

+V1.5_+-5%

TPS51216

+V0.75S

+V1.5S_DGPU

NMOS

POWER BUDGET 4.711A
PEAK2.592A

13UF_5.803MΩ

INRUSH 0.496A

B

CHANGING POINTS~~
TPS51211 IS NEW IC

+V1.8S IS NEW IC RT8068
VDD CORE IS NEW IC TPS51728
CHARGE IS NEW IC BQ24725
VCC CORE IS NEW IC TPS51650
VTT IS NEW IC TPS51219
V0.85 IS NEW IC TPS 51641
V3_V5 IS NEW IC TPS51123
POWER BUDGET ~~IC SPEC (MAX CURRENT )
PEAK CURRENT ~~RATIO OF INTERNAL PREDICTION
AVG CURRENT ~~TEST RESULT(MAX CURRENT)
INRUSH ~~L/S TURN NO

8

7 6

TPS51216

POWER BUDGET 33.033 A
F 340K
OCP 20.1A R=56.2K
PEAK 19.82A AVG8.802 A
330UF_15MΩ // 480UF_0.560MΩ

+V1.05_+-5%

TPS51219

POWER BUDGET 19.218 A
F 340K
OCP 13.2A R=115K
PEAK 11.53A AVG 6.704A
560UF_25MΩ // 359.9UF_0.213MΩ

5 4

NMOS

NMOS

NMOS

CHANGE by

+V1.5S

+V1.5_CPU

DATE

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

704

FUSE6000
65W-75W 8A(6036A0003401)
90W 10A(6036A0002901)

120W 12A(6036A0006001)

D

PVADPTR

C6014

2 1

CSC0805_DY

R6018

2 1

B

8 7

G1
G2

ACES_50315_0047N_002_4P

SSM3K7002FU_DY

1M_5%_2_DY

21

R6019

2 1

RSC_1206_DY

RSC_1206_DY

21E6

R6002

20.5K_1%_2

ACPRES

OUT

21E621E8

21

R6003

3.32K_1%_3

C6029

CSC0603_DY

2 1

21D221D3
37C356C8

21D221D337C656D8

8

CN6000

654

Q6002
3

R6021

Q6010

8
7
6

2200PF_50V_2

P3V3AL

HW_I_ADC

OUT

C6037

100PF_50V_2

NEAR EC

EC_SMB2_DATA

BI

EC_SMB2_CLK

BI

FUSE6000

TP30

C6031

21

1
2
3
4 5

21

1

1

2

2

3

3

4

TP60031TP60041TP6005

1

DS

G

1

21

2 1

3M_5%_2_DY

R6015

21

4.7K_5%_3

R6014

21

RSC_0603_DY

D

S

G

NMOS_4D3S

TPCA8065_H

C6030

21

LITTLEFUSE_R451012_12A_65V

C7601

1000PF_50V_2

2 1

TP30TP30

2

R6022

1
2
3
45

0.1UF_25V_3

R6006

21

21

R6013

10K_5%_3

2 1

RSC_0603_DY

21

R6004

4.3K_5%_2

C6036

NEAR IC

2 1

CSC0402_DY

R6016

SHORT_0402

R6017

21

100PF_50V_2

C6035

2 1

21

21

SHORT_0402

7 6

10PF_50V_2

2 1

S

G

TPCA8065_H

R6005

4.3K_5%_2

6 5

L7600

NFE31PT222Z1E9L

21

C7602

NMOS_4D3S

Q6011

4

3

8

D

7
6

3

D6002

DIODES_BAV99

2 1

TI_BQ24725ARGRR_QFN_20P

P3V3AL

C6034

CSC0402_DY

21

2 1

R6007

110K_5%_2

21

R6008

91K_5%_2

PVADPTR

21E621E8

C6021

0.1UF_25V_3

U6000

6

ACDET

7

IOUT

8

SDA

9

SCL

10

ILIM

C6032

0.1UF_16V_2

2 1

RSC_0603_DY

2 1

R6802

33K_5%_2_DY

RSC_0603_DY

HW_V_ADC

OUT

0.1UF_16V_2_DY

0.01_1%_6

R6000

C6020

C6800

NEAR EC

21
43

21

0.1UF_16V_2

PVADPTR

D6000

C6022

3

ACP

CMSRC

GND

SRP

13

2

ACN

PHASE

LODRV

15

14

1UF_10V_2

HIDRV

BTST

REGN

C6028

TML

VCC

2 1

0.1UF_25V_3

21
20

19
18
17
16

2 1

C6026

1UF_25V_3

R6020

4.7_5%_3

D6001

BAT54C_30V_0.2A

R6011

SHORT_0402

R6010

2 1

0_5%_2

R6009

2 1

514

ACOK

ACDRV

BATDRV

SRN

12

11

4.3K_5%_2

5 4

R6800

21

R6801

C

BAT54C_30V_0.2A

3
21

R6012

21

21

21

21

4

PVBAT

21

21

EC_SMB1_DATA

21D2
21D3

21

A2A1

10_5%_5

VRCHARGER_HG
VRCHARGER_PH

C6027

3

0.047UF_16V_2

C

A2A1

VRCHARGER_LG

21E621E8

BATT_IN

21D221D3

EC_SMB1_CLK

PVBAT

12

2 1

AON7410

NMOS_4D3S

G

21

AON7410

NMOS_4D3S

21

G

OUT
BI

BI

PAD6000

POWERPAD_2_0610

678

Q6000

D

S

3

214 5

678

Q6001

D

D6700

S

3

214 5

3 2 1

P3V3AL

R6054

21

1M_5%_2

33_5%_2

R6050

21
21

33_5%_2

R6051

D6701

EZJZ0V500AA_DY

C6001

470PF_50V_2 4.7UF_25V_5 4.7UF_25V_5

2 1

2 1

ETQP3W4R7WFN

21

R7600

RSC_0603_DY

2 1

C7600

SBR3U40P1_DY

CSC0402_DY

2 1

21

C6002

L6000

R6053

21

220K_1%_2

1K_5%_2

R6052

21

D6702

EZJZ0V500AA_DY

C6003

2 1

21

C6024

2 1

0.1UF_25V_3

0.02_1%_6

0.1UF_16V_2

21

EZJZ0V500AA_DY

R6001

21
43

C6023

21

PVPACK

2 1

C6050

1000PF_50V_2

D6703

C6004

CSC0805_DY

2 1

C6025

2 1

0.1UF_25V_3

FUSE6050

LITTLEFUSE_R451015_15A_65V

21

C6010

2 1

INVENTEC

TITLE

CODE

SIZE

CHANGE by

DATE

21-OCT-2002XXX

23

A3

21

CN6050

1

BATT+

2

BATT+

3

ID

4

B-I

5

TS

6

SMD

7

SMC

8

GND

9

GND

SYN_200045GR009G18TZR_9P

PVPACK

Q6012

8

D

7
6

TPCA8065_H

C6011

2 1

4.7UF_25V_5

MODEL,PROJECT,FUNCTION

Block Diagram

CS

SHEET

NMOS_4D3S

C6012

2 1

4.7UF_25V_5

DOC.NUMBER

1

S

2
3
45

G

C6013

4.7UF_25V_5

of

1

G
G
G
G

0.1UF_25V_3

2 1

CSC0805_DY

705

G1
G2
G3
G4

C6033

REV

X011310xxxxx-0-0

D

21

CC

B

AA

8 7

6 5

4

3 2 1

IN

IN

R6114

2.2_5%_3

21

VRP3V3A_LDO

14C7

14C7

C6121

1UF_6.3V_2

EN_5V

EN_3V

21

VRP3V3A_HG
VRP3V3A_PH
VRP3V3A_LG

2 1

R6160

2 1

140K_1%_2

R6110

2 1

120K_1%_2

25

TML

TRIP2

7 24

VO2 VO1

8

VREG3

9 22

VBST2

10 21

DRVH2
LL2
DRVL2

R6113

U6100

EN0

13

2 1

11 20

12 19

SKIP_3V_5V

IN

VRP5V0A_VIN

IN

RSC_0402_DY

5

VFB2

SKIPSEL

14

3

4

TONSEL

VREF

GND

VIN

16

15618

2 1

1

2

VFB1

TRIP1

VREG5

ENC

17

C6122

2VREF

5V_PG

C6123

0.22UF_6.3V_2

2 1

23

PGOOD

DRVH1

TI_TPS51123RGER_QFN_24P

VBST1

DRVL1

R6155

2.2_5%_3

VRP5V0A_HG
VRP5V0A_PH

LL1

VRP5V0A_LG

EN_3V_5V

VRP5V0A_LDO

C6120

1UF_25V_3

10UF_6.3V_3

2 1

21

OUT

OUT

C6155

IN

OUT

6C614C8

21

0.1UF_16V_2

VRP5V0A_PH

IN

678

AON7410

NMOS_4D3S

G

3

678

AON7702A

G

3

VRP5V0A_LG

214 5

214 5

OUT

VBATP

Q6150

D

S

Q6151

D

S

14D6

OUT

6D3

C6160

4.7UF_25V_5

2 1

R7615

RSC_0603_DY

2 1

C7615

CSC0402_DY

2 1

6B3 14D5

C6161

4.7UF_25V_5

2 1

L6150

ETQP3W3R3WFN

D

CC

21

+

C6150

150UF_6.3V

2 1

R6150

15.4K_1%_2

2 1

R6151

10K_1%_2

2 1

VRP5V0A

VO=(( R6150/R6151)+1)*2

OUT

14D6
14C8
14D4

B

14D7

D

PVBAT

14C7

PAD6110

12

POWERPAD_2_0610

VBATP

2 1

4.7UF_25V_5

2 1

21

R7610

RSC_0603_DY

C7610

CSC0402_DY

C6111

C6110

4.7UF_25V_5

OUT

VRP3V3A

R6100

6.8K_1%_2

2 1

R6101

10K_1%_2

2 1

+

2 1

14D6

B

ETQP3W3R3WFN

C6100

150UF_6.3V

L6100

VOUT=((R6100/R6101)+1)*2

6C3 14C8

OUT

678

Q6100

D

2 1

Q6101

14C6

2 1

14C8

2 1

S

D

S

214 5

214 5

NMOS_4D3S

AON7410

G

3

C6115

0.1UF_16V_2

678

OUT

AON7702A

G

3

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

706

8 7

6 5

4

3 2 1

PVBAT

P5V0A

D

P0V75S

21

1 2

PAD6210

D

POWERPAD_2_0610

678

C6216

2 1

2.2UF_6.3V_3

U6200

IN

DDR3L_SEL

R6200

14D1

14D1

EN_0V75

IN

EN_1V5

IN

21

17

S3

16

S5

6

VREF

10.2K_1%_2

8

REFIN

7

21

C6217

R6201

2 1

B

54.9K_1%_2

C6218

2 1

0.01UF_50V_2

0.1UF_16V_2

21

R6203

R6202

2 1

100K_5%_2

75K_1%_2

GND

19

MODE

18

TRIP

TI_TPS51216RUKR_QFN_20P

DRVH

DRVL

PGND

PGOOD

VDDQSNS

VLDOIN

VTTSNS

VTTGND

VTTREF

1512

VBSTV5IN

VRP1V5_HG

14

VRP1V5_PH

13

SW

VRP1V5_LG

11
10
20
9
2
3

VTT

1

4
5
21

TML

C6220

2 1

R6215

2.2_5%_3

P0V75M_VREF

C6221

2 1

10UF_6.3V_3

21

0.22UF_6.3V_2

C6215

0.1UF_16V_2

21

FDMC8884

FDMS0310AS

NMOS_4D3S

G

G

1V5_PG

3

678

3

Q6200

D

C6212

C6211

C6210

S S

2 1

4.7UF_25V_5

2 1

2 1

4.7UF_25V_5

4.7UF_25V_5

214 5

L6200

21

21

Q6201

D

R7620

PCMC104T_1R0MN

RSC_0603_DY

14C2

C7620

CSC0402_DY

2 1

214 5

OUT

43

21

1 2

PAD6220

VRP1V5

OUT

14C2

CC

+

C6200

2 1

POWERPAD1X1M

560UF_2.5V

B

VOUT=REFIN=1.8*(R6201/(R6200+R6201))

MODE=100KOHM:TRACKING DISCHARGE

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

707

8 7

6 5

4

3 2 1

D

D

P3V3S

CC

C6971

2 1

R6970

10_5%_2

2 1

RICHTEK_RT8068AZQW_WDFN_10P

C6972

1UF_10V_2

10UF_6.3V_3

B

2 1

U6970

11

TML

10 1

LX

PVIN

9

LX

PVIN

8

LX

SVIN

7

PGOOD

NC

6 5

EN

FB

2
3
4

100K_5%_2

R6971

1V8S_PG

EN_1V8

21

PAN_ELL5PR2R2N

IN

OUT

L6970

14B1

21

C6970

R6973

C6974

2 1

2 1

20.5K_1%_2

CSC0402_DY

C6975

2 1

2 1

10UF_6.3V_3

VRP1V8S

10UF_6.3V_3

OUT

14A2

B

R6972

10K_1%_2

2 1

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

708

8 7

6 5

4

3 2 1

D

14B7

EN_VCCP

IN

PVBAT

D

21

1 2

R6303

2 1

100K_5%_2

OUT

R6307

0_5%_2_DY

VCCP_PG

21

1
2
3
4

TI_TPS51219RTER_QFN_16P

C6319

2 1

0.01UF_50V_2

U6300

VREF

REFIN

GSNS

VSNS

21

P5V0A

C6316

C6315

0.1UF_16V_2

2 1

2.2UF_6.3V_3

21

R6315

14

PGOOD

TRIP

13

EN

MODE

GND

PGND

2.2_5%_3

BST

SW

DH

DL

V5

VRP1VO_VCCP_PH

12

VRP1VO_VCCP_HG

11

VRP1V0_VCCP_LG

10
9

7

17

16815

PWPD

COMP

6

5

21

R6302

678

FDMC8884

Q6300

D

NMOS_4D3S

C6310

G

S S

3

214 5

678

FDMS0310AS

Q6301

D

G

3

214 5

2 1

4.7UF_25V_5

C7630

14A814B6

2 1

IN
IN
IN

0.01UF_50V_2

VCCIO_SEL
VSS_SENSE_VCCIO
VCC_SENSE_VCCIO

46B4

44A3

R6306

C6318

2 1

2.2UF_6.3V_3

B

44A3

10K_1%_2

2 1

C6320

R6308

2 1

11.3K_1%_2

52.3K_1%_2

PAD6310

POWERPAD_2_0610

CC

C6312

C6311

21

R7630

2 1

2 1

2 1

4.7UF_25V_5

4.7UF_25V_5

L6300

21

21

43

43

CYN_PCMB063T_R68MS_4P

RSC_0603_DY

C6300

C6301

2 1

22UF_6.3V_5

VRP1V05S

+

2 1

560UF_2.5V

OUT

14A8

B

CSC0402_DY

VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

709

8 7

6 5

4

3 2 1

D

C6522

0.01UF_50V_2

2 1

VCCSA_SENSE

EN_SA

VCCSA_VID0

21

VCCSA_VID1

21

C6515

0.1UF_16V_2

45A2

IN

L6500

21

21

43

21

14B5

IN

45A2

IN

45A2

IN

CYN_PCMB063T_R33MS_4P

R7650

RSC_0603_DY

2 1

C7650

CSC0402_DY

2 1

43

C6500

22UF_6.3V_5

2 1

C6501

22UF_6.3V_5 22UF_6.3V_5_DY

2 1

C6502

2 1

22UF_6.3V_5

VRPVCCSA

C6503

2 1

OUT

14A6

C6521

0.22UF_6.3V_2

R6520

5.11K_1%_2

25
24
23
22
21
20
19

21

TML

VIN
VIN
PGND
PGND
PGND

R6521

21

1

2

3

GND

VREF

COMP

U6500

V5FILT

V5DRV

PGOOD

18

16

RSC_0402_DY

5

4

6

TI_TPS51461RGER_QFN_24P

VOUT

SLEW

MODE

SWVIN
SW
SW
SW
SW

BST

VID0

VID1

EN

151417

13

7
8
9
10
11
12

VRPVSA_PH

R6524

SHORT_0402

R6525

SHORT_0402

C6524

2 1

1UF_6.3V_2

C6520

21

3300PF_50V_2

P5V0A

2 1

C6510

22UF_6.3V_5

2 1

C6511

2 1

0.1UF_16V_2

B

C6523

2 1

1UF_6.3V_2

D

CC

B

SA_PG

OUT

14A6 21B6

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7010

D

B

R6620
R6621
R6622
R6626

R6711
R6712
R6719
R6723
R6635
R6636
R6714
R6716
R6721
R6725
R6726

R6722
R6720
R6713
R6715

VREF_CPU

R6711

100K_1%_2

2 1

R6712

24K_1%_2

2 1

21D3

8 7

DIS.

UMA/PX

3+0

71.5K 71.5K

42.2K
100K

4.7K
75KR6627
100K

24K
DNP
DNP
DNP DNP
DNP
DNP
DNP
DNP
DNP

0
0R6724
0
0
0
0

R6628

RSC_0402_DY

2+13+2

44.2K

42.2K

90.9K

100K

39K

3.3KDNP

DNP

56K

200K

DNP

30K

DNP

0

DNP
DNP

0

0

DNP

0

0

DNP
DNP

0

0

0
0

0

DNP DNP

DNP

0

DNP

DNP

DNP

0

DNP

0

DNP

0 DNP

DNP

P3V3A

11C8 11D4
11B7
11A4

IN

11A7

C6633

2.2UF_6.3V_3

2 1

2 1

R6629

20K_1%_2

GFX_VSS_SENSE

IN
IN

R6630

0_5%_2

2 1

R6631

RSC_0402_DY

GFX_VCC_SENSE

VR_ON

45C3

2 1

EN_PVCORE

IN

2 1

8

2+0

44.2K

90.9K
39K
DNP
DNP
DNP
DNP

0
0
0
0
0
0
0
0

DNP
DNP
DNP
DNP

11D6 11D7

OUT

2.2UF_6.3V_3

40B4
49B7

R6713

R6715

0_5%_2_DY

OUT

VREF_CPU

C6634

11A4

11A344C2

44C2

11A344C2

0_5%_2
0_5%_2

R6714

11C7

11C8 11B7

IN

VREF_CPU

R6626

4.7K_1%_2

C6632

47PF_50V_2

R6625

15.4K_1%_2

2 1

R6627

75K_1%_2

2 1

VR_ON

IN

CORE_PG

OUT

2 1

21C341D6

11A4

21
21

2 1

IN
OUT
BI
OUT

OUT

11D7
11D6
11C8
11A4
11A7
11D4

R6716

0_5%_2_DY

2 1

VR_SVID_CLK
VR_SVID_ALERT#
VR_SVID_DATA

CPU_PROCHOT#

AXG_PG

VREF_CPU

IN

7.5K_1%_2

11A411B711C811D411D611D7

C6726

47PF_50V_2

R6718

IN

7 6

11A411A711D411D7

13
14
15
16
17
18
19
20

21

22
23
24

VREF_CPU

6 5

2 1

1

36

CPWM3

OUT

100K_1%_2

24K_1%_2

R6618

100K_5%_NTC

OUT

2.2UF_10V_3

CTHERM

GND

V5

CDH1

CBST1

CSW1

CDL1

V5DRV

PGND

CDL2

CSW2

CBST2

CDH2

VBAT

CPWM3

OUT

12D7

VREF_CPU

21

GSKIP#

R6622

R6623

C6629

21

21

C6631

0.1UF_16V_2_DY

2 1

15.4K_1%_2

V5_CPU

2 1

49

V5_CPU

48
47

R6601

46

2.2_5%_3

45
44
43
42
41
40

R6606

39
38

R6616

37

21

10K_5%_3

PVBAT

11A7 11B7 11C8 11D4 11D6 11D7

IN

12B7

OUT

R6620

VREF_CPU

IN

12D5

21

21

44B3

IN

VSSSENSE

12

CGFB

GOCP-R

VREF

V3R3

VR_ON

CPGOOD

VCLK

ALERT#

VDIO

VR_HOT#

SLEW

GPGOOD

GF_IMAX

GGFB

25

IN

44B3

IN

CPU_CSN3

VCCSENSE

9

10

11

CCOMP

CVFB

CCSN3

U6600

TI_TPS51650RSLR_QFN_48P

GCOMP

GCSN1

GVFB

282729

26

P3V3A

21

21

R6719
R6721

R6723
R6725

21

0_5%_2_DY

21

0_5%_2_DY

21

0_5%_2_DY

21

0_5%_2_DY

2 1

71.5K_1%_2

42.2K_1%_2

IN

RSC_0402_DY

CPU_CSP3

8

CCSP3

GCSP1

0_5%_2

0_5%_2

2 1

R6720

R6724

21

RSC_0402_DY

R6621

21

P3V3A

R6635

11C3

11C3

RSC_0402_DY

R6636

21

IN

IN

CPU_CSN2

CPU_CSP2

7

6

CCSP2

CCSN2

GCSN2

GCSP2

30

31

0_5%_2

0_5%_2

2 1

2 1

R6726

R6722

R6624

21

11D3

11D3

IN

IN

CPU_CSN1

CPU_CSP1

5

4

CCSN1

CCSP1

GTHERM

GSKIP#

323334

2 1

2

3

COCP-R

CF-IMAX

GPWM1

GPWM2

35

GPWM1

GPWM2

OUT

12B7

12A7

R6731

RSC_0402_DY

R6619

21

21

R6617

10_5%_3

IN

4

PVBAT

POWERPAD_2_0610

VREF_CPU

21

P5V0A

21

C6630

2 1

11D5

C6622

0.1UF_16V_2

P5V0A

C6624

0.1UF_16V_22.2_5%_3

PAD6610

1 2

C6699

68UF_25V

IN

4.7UF_10V_3

21

21

11D7

21

+

C6610

2 1

2 1

678

NMOS_4D3S

G

3
678

FDMS0306AS

G

3

678

FDMC7696FDMC7696

NMOS_4D3S

G

3
678

FDMS0306AS

G

3

P3V3A

R6730

2 1

R6728

15.4K_1%_2

GPU_CSN2

GPU_CSP2

GPU_CSN1

GPU_CSP1

IN

IN

IN

21

21

12B5

12A5

12C5

12C5

R6729

100K_5%_NTC

IN

2 1

100K_5%_2

C6727

0.1UF_16V_2_DY

11C740B449B7

11B7

OUT

OUT

CORE_PG

AXG_PG

R6732

R6634

2 1

2K_5%_2

2 1

5 4

3 2 1

C6611

4.7UF_25V_5

11B711A711A4

PVBAT_CPU

Q6610

D

S

214 5

Q6611

D

S

214 5

PVBAT_CPU

Q6620

D

S

214 5

Q6621

D

S

214 5

2 1

4.7UF_25V_5

11C8 11D6

2 1

IN

IN

2 1

4.7UF_25V_5

11D5

11D5

R7661

RSC_0603_DY

2 1

C7661

CSC0402_DY

2 1

11D5

11D6

11D1 11D3 12D5

R7662

RSC_0603_DY

2 1

C7662

CSC0402_DY

2 1

4.7UF_25V_5

OUT

OUT

2 1

11D111B3

OUT

OUT

2 1

4.7UF_25V_5

CPU_CSN1

CPU_CSP1

12D5

R6602

17.8K_1%_2

CPU_CSN2

CPU_CSP2

R6607

17.8K_1%_2

2 1

4.7UF_25V_5

21

100K_5%_NTC

21

100K_5%_NTC

4.7UF_25V_5

R6603

2 1

4.7UF_25V_5

0.022UF_16V_2

R6605

240K_1%_2

21

ETQP4LR36AFM

L6610

0.022UF_16V_2

R6610

240K_1%_2

R6608

21

ETQP4LR36AFM

L6620

2 1

C6623

C6625

4.7UF_25V_5

21

21

R6604

28.7K_1%_2

43
21

21

21

R6609

28.7K_1%_2

43
21

C6619

C6618

C6617

C6616

C6615

C6614

C6613

C6612

P1V05S

C6635

R6633

2K_5%_2

11C7
44C2

11C744C2

CHANGE by

IN

BI

VR_SVID_CLK

VR_SVID_DATA

R6632

130_1%_2

54.9_1%_2

2 1

DATE

2 1

2 1

0.1UF_16V_2

INVENTEC

SIZE

21-OCT-2002XXX

23

A3

C6621

C6620

2 1

2 1

4.7UF_25V_5

4.7UF_25V_5

21

1

+

3

2

21

1

C6602

+

3

2

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

CS

SHEET

PVBAT_CPU

2 1

4.7UF_25V_5

C6600

470UF_2V

of

1

PVCORE

2

7011

OUT

C6601

1

470UF_2V

+

3

PVCORE

1

470UF_2V470UF_2V

+

3

2

C6603

REV

X011310xxxxx-0-0

D

CC

B

AA

8 7

R6611

21

2.2_5%_3 0.1UF_16V_2

D

11B5

IN

P5V0A

CPWM3

U6630

3

PWM

4 5

GND DRVL

TI_TPS51601DRBR_SON_8P

6 5

C6626

21

9

PAD

81

DRVHBST

72

SWSKIP#

6

VDD

P5V0A

4

OUT

OUT

11D111B3

CPU_CSN3

CPU_CSP3

11D3

R6612

21

R6613

100K_5%_NTC17.8K_1%_2

C6628

0.022UF_16V_2

R6615

240K_1%_2

21

ETQP4LR36AFM

L6630

21

21

R6614

28.7K_1%_2

43
21

21

11D6

11D6

PVBAT_CPU

678

FDMC7696

FDMS0306AS

Q6630

D

NMOS_4D3S

G

S

3

214 5

678

Q6631

D

IN

R7663

RSC_0603_DY

3 2 1

PVCORE

D

2 1

G

C6627

2 1

1UF_6.3V_2

21

U6710

PWM
GND DRVL

C6720

0.1UF_16V_2

9

PAD

81

DRVHBST

72

SWSKIP#

6

VDD

21

P5V0A

C6721

2 1

1UF_6.3V_2

R6701

2.2_5%_3

11A4

11B5

GSKIP#

IN

GPWM1

IN

3
4 5

TI_TPS51601DRBR_SON_8P

B

S

3

214 5

PVBAT_AXG

678

FDMC7696

Q6710

D

NMOS_4D3S

G

S

3

214 5

678

Q6711

D S

G

S

3

214 5

C7663

CSC0402_DY

2 1

11A6

11A6

IN

R7671

RSC_0603_DY

2 1

C7671

CSC0402_DY

2 1

11A5

OUT

OUT

12A5 12C1

OUT

GPU_CSN1

GPU_CSP1

R6702

17.8K_1%_2

GPU_CSN2

21

100K_5%_NTC

0.022UF_16V_2

R6705

169K_1%_2

R6703

21

ETQP4LR36AFM

L6710

C6722

28.7K_1%_2

43
21

PVBAT

12

PAD6710

POWERPAD_2_0610

21

21

R6704

21

PVAXG

1

+

3

2

C6710

C6700

470UF_2V

2 1

C6716

C6715

C6714

C6713

C6712

C6711

2 1

2 1

2 1

2 1

4.7UF_25V_5

4.7UF_25V_5

4.7UF_25V_5

4.7UF_25V_5

2 1

2 1

4.7UF_25V_5

4.7UF_25V_5

PVBAT_AXG

OUT

12A5 12C5

CC

C6717

2 1

2 1

4.7UF_25V_5

4.7UF_25V_5

B

OUT

12C5

GPU_CSP2

R6707

17.8K_1%_2

21

100K_5%_NTC

11A6

R6706

PVBAT_AXG

678

C6723

21

21

FDMC7696

Q6720

D

NMOS_4D3S

12C1

IN

2.2_5%_3 0.1UF_16V_2

P5V0A

11B5

8

GPWM2

IN

7 6

U6720

3

PWM

4 5

GND DRVL

9

PAD

81

DRVHBST

72

SWSKIP#

6

VDD

TI_TPS51601DRBR_SON_8P

P5V0A

C6724

2 1

G

S

3

214 5

678

FDMS0306ASFDMS0306AS

Q6721

D

R7672

RSC_0603_DY

2 1

G

3

1UF_6.3V_2

214 5

C7672

CSC0402_DY

2 1

5 4

0.022UF_16V_2

R6710

169K_1%_2

R6708

21

ETQP4LR36AFM

L6720

C6725

28.7K_1%_2

43
21

21

21

R6709

PVAXG

21

AA

1

C6701

470UF_2V

+

2

CHANGE by

3

DATE

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

7012

1

REV

X011310xxxxx-0-0

8 7

6 5

4

3 2 1

13B216A1

16C4
16A8
13D2
16A1

49A1
21D6
14B8
13D2
14A6
14D2
45D3

13C3

16A816C4

21D645D3

13A214A6
14B814D2

49A1

IN

IN

IN

PVBAT

56F7
56C5

P5V0A

C6954

2 1

12

PAD6760

2 1

POWERPAD_2_0610

678

FDMS7692

FDMS0306AS

Q6750

D

NMOS_4D3S

G

S

3

214 5

678

Q6751

D

G

S

3

214 5

ANPEC_APL5930KAI_TRL_SOP_8P

1UF_10V_2

C6761

C6760

2 1

2 1

4.7UF_25V_5

PAN_ETQP4LR36WFC_4P

R7675

2 1

RSC_0603_DY

C7675

2 1

CSC0402_DY

P1V5S_DGPU

C6955

2 1

22UF_6.3V_5

U6950

5

VIN

6

VCNTL

7

POK

8

EN

9

VIN

4.7UF_25V_5

L6750

VOUT

VOUT

FB

GND

C6762

2 1

4.7UF_25V_5

1

+

C6750

3

2

2.7K_1%_2

C6950

2 1

10K_1%_2

VRPVCORE_DGPU

1

C6752

+

470UF_2V

470UF_2V

3

2

VRPVPCIE

C6951

2 1

1UF_10V_2

22UF_6.3V_5

OUT

OUT

13A2

13C2

21
43

R6750

2.2K_1%_2

2 1

R6751

10K_1%_2

2 1

4

C6952

3
2
1

R6950

2 1

2 1

68PF_50V_2

R6951

2 1

D

P5V0A

R6756

21

10_5%_2

C6757

C6754

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

OUT

IN

：

G1G0

0
1

DGPU_PWRGD

EN_DGPU

SEYMOUR XTX

VOUT

1.15

1.05
1

0.9

THAMES XT

VOUT
N/A

0.9

13B252C6

13D1

VGA TYPE

B

010
0
1
1

R6755

240K_5%_2

U6750

16

TON

9

VDDP

2

VDD

4

PGOOD

10

CS

R6758

13K_1%_2

15 5

2 1

EN_DEM D1

17

GND

REA_RT8208BGQW_WQFN_16P

THAMES LE

VOUT

RESISTOR VALUE

N/A
N/AN/A

11

0.9

21

13

BOOT

12

UGATE

11

PHASE

8

LGATE

7

G0

3

FB

14

G1

R6753

6

D0

R6754

1

VOUT

R6750(R1)
R6751(R2)

R6754(R3)

R6753(R4)

R6752

2.2_5%_3

21

VRPVCORE_DGPU_HG
VRPVCORE_DGPU_PH
VRPVCORE_DGPU_LG

PWRCNTL_0

PWRCNTL_1

21

10K_1%_2

21

16.5K_1%_2

IN

IN

P.S. R6750(R1)R6751(R2)R6753(R3)R6754(R4)

2.2 K
10 K

16.5 K

10 K

13B1

IN

C6753

0.1UF_16V_2

56D5 56F7

EN_VPCIE

21

DGPU_PWR_EN EN_DGPU

SLP_S3#_3R

IN

VRPVCORE_DGPU

DGPU_PWRGD

IN

DGPU_PWR_EN

SLP_S3#_3R

13A3

VRPVPCIE

IN

10K_5%_2

0_5%_2_DY

P3V3S_DGPU

100K_5%_2_DY

R7019

1K_5%_2

R7030

0_5%_2_DY

R7016

21

R7020

21

C7010

2 1

PVCORE_DGPU

PAD6750

1 2

POWERPAD_2_0610

PAD6751

1 2

POWERPAD_2_0610

R7017

10K_5%_2

2 1

P1V5S_DGPU

1

R7018

2

EN_VPCIE

21

21

C7011

2 1

1UF_6.3V_2

PAD6950

21

1 2

POWERPAD_2_0610

0.1UF_16V_2

21

21

OUT

PVPCIE

OUTIN

C6751

+

560UF_2.5V

2 1

OUT

13C8

D

CC

B

13A6

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7013

D

14D6

3V & 5V

EC_PW_ON#

15D4

IN

21C3

21F6
14C8

IN

15D6

VRP3V3A_LDO

6B614C6

IN

IN

6C36C6

IN

21F6

14D8

IN

15D6

VCCIO

8 7

3

Q7000

DS

1

G

C7000

SSM3K7002BFU

P5VAUXON

3

2

C

A2A1

2 1

0.047UF_16V_2

D7000

BAT54C_30V_0.2A_DY

2 1

R7000

21

RSC_0402_DY

VBATP

P5VAUXON

R7001

10K_5%_2

R7002

0_5%_3

R7003

0_5%_2

21

21

21

SKIP_3V_5VVRP5V0A

VRP5V0A_VIN

EN_3V_5V

EN_5V

EN_3V

OUT

OUT

OUT

OUT

OUT

6 5

6D6

IN

IN

IN

VRP5V0A

VRP3V3A

VRP5V0A_LDO

6C114C814D4

6C8

6B4

6D6

PAD6150

POWERPAD_2_0610

PAD6100

POWERPAD_2_0610

PAD6120

POWERPAD1X1M

1 2

1 2

1 2

21

21

21

P5V0A

P3V3AL

P5V0AL

C6151

++

330UF_6.3V_DY

2 1

C6101

330UF_6.3V_DY

2 1

IN

VRP5V0A_LG

6B3

P3V3_LDO

6B56C114D4

6B5

6B4

IN

POWERPAD1X1M

VRP3V3A_LDO

6B614C8

1 2

PAD6121

21

VCCSA

4

6C114C814D6

IN

DGPU

VRP5V0A

2 1

C7001

0.1UF_16V_2

C7002

0.1UF_16V_2

2 1

D7002

DIODES_BAV99

3

3

21

D7001

DIODES_BAV99

21

C7004

1UF_25V_3

2 1

3 2 1

DDR_P1V5

49A1

C7003

2 1

0.1UF_16V_2

P15V0A

21D6
14A6

13D2
14B8
45D3

49B3

IN

IN

7B314C2

7C1

SLP_S3#_3R

SLP_S5#_3R

1V5_PG

IN

IN

VRP1V5

47K_5%_2

R7012

P3V3S

21

R7013

R7010

0_5%_2

RSC_0402_DY

P1V8S

21

C7005

0.1UF_16V_2

2 1

21

C7006

CSC0402_DY

2 1

PAD6200

1 2

POWERPAD_2_0610

PAD6201

1 2

POWERPAD_2_0610

EN_0V75

1V5_PG

21

21

EN_1V5

P1V5

OUT

OUT

OUT

7C713A2

7C721D3

D

CC

49A1
21D6
14A6
13A2
13D2
14D2
45D3

IN

SLP_S3#_3R

B

R7021

47K_5%_2

EN_VCCP

21

OUT

9D6

C7020

2 1

0.1UF_16V_2

14A8

VCCP_PG

9C6

P3V3S

21

SA_PG SA_PG

SLP_S3#_3R

IN

14B6

R7022

9C614A8

VCCP_PG

IN

10K_5%_2

VCCP_PG

OUT

10A514A621B6

49A1
13A213D214B8
14D221D645D3

P1V05S

PAD6300

21

1 2

POWERPAD_2_0610

VRP1V05S

9B1

IN

8

PAD6301

1 2

POWERPAD_2_0610

21

7 6

10C1

IN

VRPVCCSA

R7040

21

0_5%_2

2 1

2

D7040

NC

BAT54_30V_0.2A

PAD6500

1 2

POWERPAD_2_0610

EN_SA

C7040

CSC0402_DY

10B4

OUTIN

P3V3S

R7041

10K_5%_2

2 1

13

OUTIN

PVSA

21

5 4

CHANGE by

DATE

P3V3S

R7050

10K_5%_2

EN_1V8

21

OUT

8B4

B

C7050

0.01UF_50V_2

2 1

P1V8S

VRP1V8S

8B2

IN

PAD6900

1 2

POWERPAD_2_0610

21

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7014

8 7

6 5

4

3 2 1

R7105

100K_5%_2

C7100

2200PF_50V_2

P3V3AL

1

2
5

Q7102

D

NMOS_4D1S

AO6402AL

S

G

4

POWERPAD_2_0610

36

PAD7100

1 2

Q7103

1

SSM3K7002BFU

P3V3A

21

R7106

200_5%_2

2 1

D

3

DS

G

2

CC

B

P3V3AL

PVBAT P3V3_LDO

R7491

510K_1%_2

D

56D6
40A8
40B1

THRM_SHUTDWN#

OUT

BAT54_30V_0.2A

D7490

2

NC

R7492

120K_1%_2

2 1

13

2 1

P15V0A

R7107

2 1

470K_5%_2

3

Q7104

16A7
15A4
15B4
49B1

SLP_S3_3R

IN

SSM3K7002BFU

DS

1

G

2

B

4

U7490

VDD

5 3

SENSE RESET#

GND

GND

TI_TPS3801_01_SC70_5P

2

1

C7101

2 1

2200PF_50V_2

P5VAUXON

OUT

14C8 14D8 21F6

P3V3AL

R7108

SHORT_0402

P5V0A

R7110

SHORT_0402

1

1

2
5

2
5

21

21

Q7105

D

NMOS_4D1S

AO6402AL

Q7107

D

NMOS_4D1S

AO6402AL

4

S

36

G

C7102

2 1

4

S

36

G

C7104

2 1

PAD7101

POWERPAD_2_0610

2 1

680PF_50V_2

PAD7102

POWERPAD_2_0610

2 1

12

CSC0402_DY

IN

EC_PW_ON#

14D821C3

P3V3S

12

C7103

2 1

22UF_6.3V_5

49B1

15B8
15A4
15B4
16A7

SLP_S3_3R

IN

P5V0S

C7105

2 1

49B1

22UF_6.3V_5

15B8
15A4
15B4
16A7

SLP_S3_3R

IN

R7104

100K_5%_2_DY

2 1

R7100

10K_5%_2

2 1

Q7106

1

SSM3K7002BFU

Q7108

1

SSM3K7002BFU

G

G

R7109

2 1

3

DS

2

R7111

3

2 1

DS

2

Q7101

1

G

SSM3K7002BFU

200_5%_2

200_5%_2

3

DS

2

P15V0A

2 1

2 1

21

P1V5S

C7107

2 1

REV

X011310xxxxx-0-0

AA

R7113

3

P0V75S

200_5%_2

2 1

Q7110

IN

SLP_S3_3R

15B415B8

22UF_6.3V_5

16A749B1

SSM3K7002BFU

1

DS

G

2

1

SSM3K7002BFU

CHANGE by

Q7111

R7114

200_5%_2

3

2 1

DS

G

2

DATE

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

7015

1

R7112

P1V5

8
7
6

8
7
6

21

Q7109

D

NMOS_4D3S

AM7330N

Q7112

D

NMOS_4D3S

AM7330N_DY

S

G

S

G

PAD7103

POWERPAD_2_0610

1
2
3
45

1
2
3
45

1 2

SHORT_0402

C7106

2 1

CSC0402_DY

8

7 6

5 4

8 7

6 5

4

3 2 1

1
2
3
45

1
2
3
45

2 1

4

36

2 1

0_5%_2_DY

1

G

1

G

SSM3K7002BFU

R7047

P1V5S_DGPU

R7115

200_5%_2

2 1

3

Q7115

DS

SSM3K7002BFU

2

P1V8S_DGPU

R7119

200_5%_2

2 1

3

Q7119

DS

SSM3K7002BFU

2

Q7019

1

G

21

P15V0A

R7034

1M_5%_2

DGPU_PWR_EN_15R

3

2 1

DS

2

POWER EXPRESS

DURING RESET

DGPU_PWR_EN#

DGPU_PWRGD

DGPU_HOLD_RST#

16B7 16D7

OUT

5 4

HIGH

LOW

13B213D216A116A8

IN

AFTER RESET

HIGH

DGPU_PWR_EN

LOW

CHANGE by

0 : DGPU POWER SWITCH TURNED ON

1 : POWER SWITCH TURNED OFF

0 : DGPU POWER IS NOT STABLE

1 : DGPU POWER IS STABLE

0 : KEEP DGPU IN RESET

1 : RESET IS RELEASED

P3V3S

R7031

10K_5%_2

3

R7039

0_5%_2

Q7002

SSM3K7002BFU

21

C7021

51B651C7

1

2 1

CSC0402_DY

IN

2 1

DS

G

2

DGPU_PWR_EN#

P3V3S P3V3S_DGPU

0_5%_2_DY

R7042

21

Q7003

S

C7023

2 1

CSC0402_DY

DIODES_DMP2305U_SOT23_3P

SD

G

G

D

C7024

2 1

CSC0402_DY

P3V3S

R7121

10K_5%_2

1

G

2 1
3

DS

Q7120

SSM3K7002BFU

DGPU_PWR_EN

2

INVENTEC

SIZE

DATE

21-OCT-2002XXX

23

A3

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

CS

SHEET

OUT

of

13B2 13D2 16A8
16C4

7016

1

REV

X011310xxxxx-0-0

D

CC

B

AA

P1V5

D

IN

16A616B7

IN

DGPU_PWR_EN_15R

DGPU_PWR_EN_3R

16A516B7

P1V8S

16A516D7

DGPU_PWR_EN_15R

IN

Q7121

Q7113

8

D

7
6

8
7
6

8
7
6

220K_5%_2

1

2
5

220K_5%_2

NMOS_4D3S

AM7330N

Q7114

D

NMOS_4D3S

AM7330N

D

NMOS_4D3S

AM7330N_DY

R7116

680PF_50V_2

R7038

Q7118

D

NMOS_4D1S

AO6402AL

R7120

680PF_50V_2

S

G

S

G

S

G

21

C7108

0_5%_6_DY

21

S

G

21

C7110

1
2
3
45

B

16A616C7

DGPU_PWR_EN_3R

IN

P3V3_LDO

16B7

IN

16C7

R7033

10K_5%_2

DGPU_PWR_EN_3R

3

Q7018

SSM3K7002BFU

IN

DGPU_PWR_EN

13B213D216A116C4

R7035

0_5%_2

21

C7022

2 1

2 1

DS

1

G

IN

SLP_S3_3R

2

CSC0402_DY

8

7 6

8 7

REFERENCE 0~49(PCB SCREW)

6 5

4

3 2 1

D

FIX1

1

FIX_MASK

FIX2

1

FIX_MASK

FIX3

1

FIX_MASK

FIX4

1

FIX_MASK

FIX5

1

FIX_MASK

FIX6

1

FIX_MASK

FIX7

1

FIX_MASK

FIX8

1

FIX_MASK

BOUNDARY SCAN TEST POINT

PVCORE

1

1

PVADPTR

1

PVBAT

TP1

TP30

TP2

TP30

TP8

TP30 TP30

1

PVCORE_DGPU

TP30

TP9

1

1

TP30

TP4

TP3

1

TP30

TP6

1

TP30

TP10

1

PVAXG

TP30

TP5

TP7

1

TP30

D

CC

S1

1

SCREW300_1000_1P

S2

1

SCREW300_1000_1P

S3

1

SCREW300_1000_1P

S5

1

B

SCREW300_1000_1P

S6

1

SCREW300_1000_1P

S7

1

SCREW300_1000_1P

S8

1

SCREW300_1000_1P

S18

1

SCREW220_700_1P

S20

1

SCREW540_1000_NP_1P

CPU

1

1

1

1

S10

S11

S12

S13

SCREW330_600_1P

SCREW330_600_1P

SCREW330_600_1P

SCREW330_600_1P

GPU

1

1

S14

S15

SCREW330_600_1P

SCREW330_600_1P

WLANPCB

ST16

1

STDPAD_1.15_6-TOP

4.2MM

3G

ST17

1

STDPAD_1.15_6-TOP

4.2MM

ST18

1

STDPAD_1.15_6-TOP

4.2MM

FAN

ST21

1

STDPAD_1.15_6.0_TOP

2MM

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7017

8 7

REFERENCE 50-99(HALL SENSOR)

6 5

4

3 2 1

D

P3V3AL

R50

U50

VDD

3

GND

MAG_MH248BESO_SOT23_3P

OUT

100K_5%_2

1

2 1

2

C50

1000PF_50V_2

2 1

LID_SW#_3

OUT

D50

SFI_SFI0402ML120C_LF_SMD_2P_DY

2 1

2 1

21D3

B

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7018

8 7

REFERENCE 100~199(LED)

6 5

4

3 2 1

D

POWER ON LED

D154 BRIGHT WHEN SYSTEM IS POWER ON
D154 BLINK WHEN SYSTEM GO TO SLEEP

D

P5V0A

21B6

IN

PWR_WLED#

TP100

1

TP30

D154

19_217_T1D_CP1Q2QY_3T

R160

21

21

220_5%_2

CC

WIFI/WIMAX/3G/LTE LED

21D6

WL_OLED#

IN

TP104

1

TP30

D156

HT_191UY

R155

21

150_5%_2

P3V3S

21

DC IN / BATTERY CHARGE LED

B

D152 BRIGHT:BOTH AC-ADAPTER IS PLUGGED IN AND BATTERY IS FULL CHARGED
D155 BRIGHT:WHILE CHARGING BATTERY FROM AC-ADAPTER

BLINK:LOW BATTERY

P5V0A

B

21B6

IN

DCIN_WLED#

TP102

1

TP30

D152

19_217_T1D_CP1Q2QY_3T

R152

21

21

220_5%_2

P3V3AL

21B6

IN

BAT_OLED#

TP103

1

TP30

D155

HT_191UY

R154

21

21

150_5%_2

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7019

8 7

6 5

4

3 2 1

REFERENCE 200~249(POWER CONN)
REFERENCE 250~299(KB/TP CONN)

D

21B6
21D6
21D6

IN
IN
IN

20D321B3

CAPS_LED#_3
SCROLL_LED#_3
NUM_LED#_3

21B3

IN

R250
R251
R252

SCAN_OUT<17..0>

OUT

SCAN_IN<7..0>

21
21
21

SCAN_OUT<16>

16

SCAN_OUT<17>

17

SCAN_OUT<4>

4

SCAN_OUT<2>

2

SCAN_OUT<13>

13

SCAN_OUT<15>

15

SCAN_OUT<1>

1

SCAN_OUT<0>

0

SCAN_OUT<11>

11

SCAN_OUT<9>

9

SCAN_OUT<5>

5

SCAN_OUT<6>

6

SCAN_OUT<10>

10

SCAN_OUT<14>

14

SCAN_OUT<8>

8

SCAN_OUT<12>

12

SCAN_OUT<7>

7

SCAN_OUT<3>

3

SCAN_IN<7>

7

SCAN_IN<2>

2

SCAN_IN<3>

3

SCAN_IN<4>

4

SCAN_IN<0>

0

SCAN_IN<5>

5

SCAN_IN<6>

6

SCAN_IN<1>

1

200_5%_2

200_5%_2_DY

200_5%_2

21

21

D258

SFI_SFI0402ML120C_LF_SMD_2P_DY SFI_SFI0402ML120C_LF_SMD_2P_DY

21

21

D259

R253

0_5%_2_DY

P3V3S

21

21

CN250

34

34

33

33

32

32

31

G

31

30

G

30

29

29

28

28

27

27

26

26

25

25

24

24

23

23

22

22

21

21

20

20

19

19

18

18

17

17

16

16

15

15

14

14

13

13

12

12

11

11

10

10

9

9

8

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

PTWO_196094_34021_3_34P

KEYBOARD CONN

D260

SFI_SFI0402ML120C_LF_SMD_2P_DY

21

G2
G1

D

IN

SCAN_IN<7..0>

SCAN_IN<0>

0

SCAN_IN<1>

1

SCAN_IN<2>

2

SCAN_IN<3>

3

SCAN_IN<4>

4

SCAN_IN<5>

5

SCAN_IN<6>

6

SCAN_IN<7>

7

SFI_SFI0402ML120C_LF_SMD_2P_DY

21D250

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21D251

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21D252

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21D253

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21D254

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21D255

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21D256

21

SFI_SFI0402ML120C_LF_SMD_2P_DY

21D257

21

CC

20C621B3

B

BI
BI

BI
BI

IM_CLK_5
IM_DAT_5

PCH_3S_SMCLK
PCH_3S_SMDATA

20A521D3
20A521D3

38C839C848A8
38C839C848A8

PHP_PESD5V2S2UT_SOT23_3P_DY

P5V0S P3V3S

1

2

D280

3

CN280

G1

G1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

G2

ACES_50503_0084N_001_8P

G2

P5V0S

CN281

1

1

20A721D3
20A721D3

IM_CLK_5

BI

IM_DAT_5

BI

2

2

3
4

G

3

G

4

ACES_50503_0044N_001_4P

G1
G2

21D3

PWR_SWIN#_3

OUT

21

21

D200

SFI_SFI0402ML120C_LF_SMD_2P_DY

CN200

1

1

2

2

ACES_50224_0020N_001_2P

3

G

4

G

POWER CONN

B

AA

TOUCHPAD CONN

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7020

8

7 6 5 4 3 2 1

REFERENCE 300~389(KBC)

2.2_5%_3

FOR ESD PROTECT

P3V3AL

FBM_11_160808_121T

E

HW_I_ADC

5B721E6

IN

HW_V_ADC

5D521E6

IN

BATT_IN

5D321E6

OUT

D

C

B

EC_SMB1

1.BATTERY

P3V3A

R313

P3V3A

OUT

OUT

EC_SPI_CS0#

IN

EC_SPI_SO

3.3K_5%_2

R330

R315

EC_SPI_CS1#

IN

EC_SPI_SO

3.3K_5%_2_DY

R331

21D647A6

21C621C8
47A6

47A6

21C621C8
47A6

P3V3AL_RP3V3AL

R318

21

C313

4.7UF_6.3V_3

2 1

L300

21

C314

AGND_KBC

C316

C317

0.1UF_16V_2

0.1UF_16V_2

2 1

2 1

EC_SMB2

1.CHARGE

2.GPU THERMAL

3.CEC

10K_5%_2

21

U300

1

/CS

2

DO_IO1

21

3

/WP_IO2

4

GND

WINB_W25Q32BVSSIG_SOIC_8P

10K_5%_2_DY

21

U302

1

/CS

2

DO_IO1

21

3

/WP_IO2

4

GND

WINB_W25Q32BVSSIG_SOIC_8P_DY

C300

2 1

50D7

2 1

C315

2 1

0.1UF_16V_2

10UF_6.3V_5_DY

/HOLD_IO3

/HOLD_IO3

DI_ID0

C301

0.1UF_16V_2

2 1

P3V3AL_EC

C305

0.1UF_16V_2

2 1

0.1UF_16V_2

EC_SMB3

8

VCC

7
6

CLK

5

DI_ID0

8

VCC

7
6

CLK

5

C302

2 1

R314

R319

0.1UF_16V_2

21

EC_SPI_CLK
EC_SPI_SI

C304

C303

0.1UF_16V_2

2 1

2 1

PCH_LCM_BKLTEN

IN

GM:3CELL OPEN
PM:6CELL STUFF

3.3K_5%_2

EC_SPI_CLK
EC_SPI_SI

21

3.3K_5%_2_DY

P3V3AL

R320

2

P5VAUXON VCC_POR#

P3V3S

CLOSE PIN4

C306

C312

0.1UF_16V_2

0.1UF_16V_2

2 1

2 1

10UF_6.3V_5_DY

14C814D815D6 21B6

D300

BAT54_30V_0.2A

100K_5%_2

NC

2 1

13

OUTIN

FF

P3V3AL_EC

0_5%_1

R301

LCM_BKLTENVGA_LCM_BKLTEN

21

0_5%_1

R302

21

GM: 100K

R344

PM: 10K

100K_5%_2

2 1

3 CELL ID

R303

10K_5%_2

P3V3AL

R346

2 1

100K_5%_2

21C847A6
21C747A6

21C847A6
21C747A6

P3V3A

47A6

21C7 21D6

IN

21C6 21C7

IN

C309

47A6

0.1UF_16V_2

2 1

R345

10K_5%_2_DY

2 1

OUT
OUT

IN

OUT

OUTIN

21

EC_SPI_CS0#
EC_SPI_CLK

EC_SPI_SO
EC_SPI_SI

21E656D6

10K_5%_2

HW_I_ADC

5B721E8

IN

HW_V_ADC

5D521E8

IN

BATT_IN

5D321E8

IN

EC_BKLTEN

34B5

OUT

LCM_BKLTEN

21E6

IN

ACPRES

5B8

IN

EC_CTL3

32A8

OUT

SLP_S3#_3R

13A213D214A614B814D245D349A1

IN

HDMI_HPD_EC

36B237B1

OUT

SCROLL_LED#_3

20C7

OUT

NUM_LED#_3

20C7

OUT

49A549A6

ACPRESENT

IN

EC_PWRSW#

IN

LOW_BAT#_3

49A8

OUT

WL_OLED#

19B4

OUT

USB_OC#_1

33C6

OUT

EC_MUTE#

24A2

OUT

WOL_AUX_ON#

22D7

OUT

EC_ILIM_SEL

32A8

OUT

EC_CTL2

32A8

OUT

33_5%_2

R342

33_5%_2

R340
R341

33_5%_2

R332

21
21

21

P3V3S

2 1

2 1

2 1

TP311

TP30

TP314

TP30

TP315

TP30

TP316

TP30

TP307

TP30

TP317

TP30

TP330

TP30

TP331

TP30

TP318

TP30

EC_SPI_CLK_R
EC_SPI_SO_R

EC_SPI_SI_R

R323

10_5%_2

C323

0.1UF_16V_2

U301

104

VREF

97

GPIO90/AD0

98

GPIO91/AD1

99

GPIO92/AD2

100

1

GPIO93/AD3

108

GPIO05/AD4

96

GPIO04/AD5

95

GPIO03/AD6

94

GPIO07/AD7

101

GPIO94/DA0

105

1

GPIO95/DA1

106

GPIO96/DA2

107

GPIO97/DA3

79

1

GPIO02

114

GPIO16

6

1

GPIO24 GPIO27/PSDAT2

109

GPIO30/F_WP#
GPIO34/CIRRXL

1

GPIO36

80

GPIO41/F_WP#

26

GPIO51/N2TCK

123

73

GPIO70

74

GPIO71

75

1

GPIO72

1

117

GPIO20/TA2/IOX_DIN_DIO

112

GP(I)O84/IOX_SCLK/XORTR#

110

GPO82/IOX_LDSH/TEST#

1

93

GPIO06/IOX_DOUT

91

1

GPIO81/F_WP#

90

F_CS0#

92

F_SCK

86

F_SDI_F_SDIO1

87

F_SDIO_F_SDIO0

44

VCORF

C310

1UF_6.3V_2

2 1

P3V3AL_R

19

VCC1

GND2

GND1

18

887646

VCC4

VCC3

VCC2

GND5

GND4

GND3

897845

116

P3V3AL_EC

115

VCC5

GND6

5

2 1

POWERPAD1X1M

102

AVCC

PAD319

P3V3S

4

VDD

GPIO11/CLKRUN#

GPIO46/SDA4B/CIRRXM/TRST#

AGND

103

12

7
2
3

1
128
127
126

125
8
9

1
29

TP30

124

121

122

27
25

11

10
7114
7215

70
69
67
68

119

120
24
28

17
20
21
23

82
84
83

BUF_PLT_RST#

CLK_KBPCI

LPC_3S_FRAME#

LPC_3S_AD<3>
LPC_3S_AD<2>
LPC_3S_AD<1>
LPC_3S_AD<0>
PCI_3S_SERIRQ

PCI_3S_CLKRUN#

TP324

RUNSCI0#_3
EC_3S_A20GATE

KBRST#

2 1

TP30

EN_PVCORE
USB_OC#_2
IM_DAT_5
IM_CLK_5

EC_SMB1_CLK
EC_SMB1_DATA
EC_SMB2_CLK
EC_SMB2_DATA
AOAC_ON#
WLON#
FLASH_OVERRIDE
LID_SW#_3

TP30
TP30
TP30
TP30

EC_PW_ON#
SB_USB_1
EC_CTL1

LRESET#/GPIOF7

LCLK/GPIOF5

LFRAME#/GPIOF6

LAD3/GPIOF4
LAD2/GPIOF3
LAD1/GPIOF2
LAD0/GPIOF1

SERIRQ/GPIOF0

GPIO65/SMI#

ECSCI#/GPIO54

GPIO10/LPCPD#

GPIO85/GA20

KBRST#/GPIO86

GPIO52/PSDAT3/RDY#

GPIO50/PSCLK3/TDO

GPIO26/PSCLK2
GPIO35/PSDAT1
GPIO37/PSCLK1

GPIO17/SCL1/N2TCKGPIO67/N2TMS

GPIO22/SDA1/N2TMS

GPIO73/SCL2

GPIO74/SDA2
GPIO23/SCL3A
GPIO31/SDA3A
GPIO47/SCL4A
GPIO53/SDA4A

GPIO42/SCL3B/TCK
GPIO43/SDA3B/TMS

GPIO44/SCL4B/TDI

GPIO75/SPI_SCK

GPIO77/SPI_DI

GPIO76/SPI_DO

WINB_NPCE885LA0DX_LQFP_128P

TP30

R300

10K_5%_2

TP306

TP326
TP303
TP304
TP305

1

1

1
1
1
1

IN

BI
BI
BI
BI
BI
BI
BI

OUT
OUT

TP325

P3V3AL

PWR_SWIN#_3

SB_USB_0
SLP_S5#_3R
H_PROCHOT_EC
SB_USB_2

OUT
OUT
OUT

27C3 27C7 28C3 51A8 57A6

51A7
27C3 47C3
27C3 47C3
27C3 47C3
27C3 47C3
27C3 47C3
27B7 47C2
49A5 49B3

51C7 52D6

20B3

OUT

RSMRST#

21D1 49B7 49C2

OUT

11A8

OUT

30A3

IN

20A5 20A7

BI

20A5 20A7

BI

5D3 21D2

BI

5D3 21D2

BI

5A7 21D2 37C6 56D8

BI

5A7 21D2 37C3 56C8

BI

21D2 27C2

BI

21D2 27B2

BI

47B7 47B8

OUT

18C4

IN

OUT

IN
OUT
OUT

14D8 15D4
33D8
32A8

32A8
14D2 49B3
21B1
30B6

P3V3S

E

R326

R312

10K_5%_2

2 1

2 1

10K_5%_2

52C2

OUT

52C2

OUT

EC_SMB1_CLK

5D321D3

BI

EC_SMB1_DATA

5D321D3

BI

EC_SMB2_CLK

5A721D337C656D8

BI

EC_SMB2_DATA

5A721D337C356C8

BI

AOAC_ON#

21D327C2

BI

WLON#

21D327B2

BI

RSMRST#

R333

10K_5%_2

2 1

R322

2 1

R321

2 1

R317

2 1

R316

2 1

R334

2 1

R335

OUT

3.3K_5%_2

3.3K_5%_2

1.8K_5%_2

1.8K_5%_2
10K_5%_2
10K_5%_2

21D3 49B7 49C2

P3V3AL

D

2 1

C

P3V3A

47A6

21C7 21D6

IN

21C6 21C7

IN

47A6

FAN_TACH1

C311

680PF_50V_2

2 1

C318

2 1

0.1UF_16V_2_DY

U301

31

1

21B6 40C8

IN

21B640C8

IN

SA_PG

10A514A6

IN

USB_OC#_0
PCH_PWROK
BAT_OLED#
DCIN_WLED#

FAN1_PWM
CAPS_LED#_3
PWR_WLED#

EC_32KHZ
LAN_RST#

VCC_POR#

R339

43_5%_2

TP320

TP321

TP322
TP323

EC_PECI

21

32A6

IN

49A649B7

OUT

19A7

OUT

19A7

OUT

40C6

OUT

20C7

OUT

19C7

OUT

49B3

IN

22B5

OUT

21F4

IN

H_PECI

41D552C2

BI

TP319

FAN_TACH1

P1V05S

TP30

TP30

TP30

TP30
TP30

GPIO56/TA1

63

GPIO14/TB1

64

GPIO01/TB2

32

1

GPIO15/A_PWM

118

GPIO21/B_PWM

62

GPIO13/C_PWM

65

GPIO32/D_PWM

22

1

GPIO45/E_PWM

81

GPIO66/G_PWM

66

GPIO33/H_PWM

16

GPIO40/F_PWM

111

1

GP(I)O83/SOUT_CR/TRIST#

113

1

GPIO87/CIRRXM/SIN_CR

77

GPIO00/EXTCLK

30

GPIO55/CLKOUT/IOX_DIN_DIO

85

VCC_POR#

13

PECI

12

VTT

WINB_NPCE885LA0DX_LQFP_128P

AGND_KBC

KBSOUT0/GPOB0/JENK#

KBSOUT1/GPIOB1/TCK
KBSOUT2/GPIOB2/TMS

KBSOUT3/GPIOB3/TDI

KBSOUT4/GPOB4/JEN0#

KBSOUT5/GPIOB5/TDO

KBSOUT6/GPIOB6/RDY#

KBSOUT7/GPIOB7
KBSOUT8/GPIOC0

KBSOUT9/GPOC1/SDP_VIS#
KBSOUT10_P80_CLK/GPIOC2
KBSOUT11_P80_DAT/GPIOC3

KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62

KBSOUT15/GPIO61/XOR_OUT

GPIO60/KBSOUT16
GPIO57/KBSOUT17

KBSIN0/GPIOA0/N2TCK
KBSIN1/GPIOA1/N2TMS

KBSIN2/GPIOA2
KBSIN3/GPIOA3
KBSIN4/GPIOA4
KBSIN5/GPIOA5
KBSIN6/GPIOA6
KBSIN7/GPIOA7

53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33

54
55
56
57
58
59
60
61

SCAN_OUT<0>
SCAN_OUT<1>
SCAN_OUT<2>
SCAN_OUT<3>
SCAN_OUT<4>
SCAN_OUT<5>
SCAN_OUT<6>
SCAN_OUT<7>
SCAN_OUT<8>
SCAN_OUT<9>
SCAN_OUT<10>
SCAN_OUT<11>
SCAN_OUT<12>
SCAN_OUT<13>
SCAN_OUT<14>
SCAN_OUT<15>
SCAN_OUT<16>
SCAN_OUT<17>

SCAN_IN<0>
SCAN_IN<1>
SCAN_IN<2>
SCAN_IN<3>
SCAN_IN<4>
SCAN_IN<5>
SCAN_IN<6>
SCAN_IN<7>

SCAN_OUT<17..0>

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17

SCAN_IN<7..0>

0

1

2

3

4

5

6

7

OUT

CPU_PROCHOT#

11C741D6

OUT

20D6

3

Q300

DS

G

SSM3K7002BFU

2

H_PROCHOT_EC

1

R324

100K_5%_2

21D3

IN

2 1

B

20C6 20D3

IN

A

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

1310xxxxx-0-0

CHANGE by

8

7 6 5 4 3

XXX 21-OCT-2002

DATE

2 1

C CS

SHEET

of

21 70

A

REV

X01

8 7

REFERENCE 400~499(LAN)

6 5

4

3 2 1

D

IN

L400

WOL_AUX_ON#

PDVDDL_LAN

21

C406

21D6

PVLX_LAN

LQM21PN2R2MC0D_DY

B

FOR SW MODE

P3V3A

C400

2 1

S

2 1

CSC0402_DY

C407

10UF_6.3V_3_DY

Q400

DIODES_DMP2305U_SOT23_3P

D

SD

G

C401

G

2 1

R400

21

C408

X400

33PF_50V_2

0.047UF_16V_2

RSC_0603_DY

2 1

1000PF_50V_2_DY

25MHZ

100K_5%_2

2 1

0.1UF_16V_2_DY

C409

2 1

R406

21

C410

2 1

POWERPAD_2_0610

21

33PF_50V_2

PAD400

1 2

PAVDDL_LAN

C412

2 1

P3V3A_LAN

21

C402

2 1

C413

2 1

1UF_6.3V_2

C403

2 1

4.7UF_6.3V_3

P3V3S

21

22A5

0.1UF_16V_2

LAN_X1

LAN_X2

R401

C404

2 1

1UF_6.3V_2

0.1UF_16V_2

48C7 48D7 48D8

CLKREQ_LAN#

OUT

30K_5%_2

PAVDDH_LAN

C414

2 1

OUT
OUT

C405

1UF_6.3V_2

23B8
23C6

23B8

2 1

C415

21B6

22A5

22B5
22B5

10UF_6.3V_5_DY

2 1

PDVDDL_LAN

C427

P3V3A_LAN

LAN_RST#

IN

PCIE_WAKE#

OUT

LAN_X1

IN

LAN_X2

IN

23D6
23C8

0.1UF_16V_2

23C8
23D6

23B8
23C6

23B8
23B8
23B8

C426

2 1

1UF_6.3V_2

R405

2.37K_1%_2

BI
BI
BI
BI
BI
BI
BI
BI

PVLX_LAN

2 1

FOR LDO MODE

0.1UF_16V_2

R403

2 1

10K_5%_2

R404

2 1

10K_5%_2_DY

402339

U400

LX

GND

1

VDD33
PERSTN
WAKEN
CLKREQN
ISOLATN
AVDDL_REG
XTLO
XTLI
AVDDH_REG
RBIAS

C416

LED_1

TRXP0

TRXN0

12

2
3
4

6
7
8

10

21

LAN_TRD0_DP
LAN_TRD0_DN
LAN_TRD1_DP
LAN_TRD1_DN
LAN_TRD2_DP
LAN_TRD2_DN
LAN_TRD3_DP
LAN_TRD3_DN

PAVDDL_LAN

0.1UF_16V_2 0.1UF_16V_2

C417:8161 STUFF 8162 OPEN

38541

37

LED_0

DVDDL_REG

TRXP1

AVDDL

141115

13916

2 1

C424

2 1

PAVDDL_LAN

PCIE_LAN_TX_DN
PCIE_LAN_TX_DP
CLK_PCIE_LAN_DP

353633

RX_P

RX_N

TRXN1

AVDD33

CLK_PCIE_LAN_DN

32

34

31

AVDDL

AVDDLTRXP3

TX_P

REFCLK_P

TX_N

REFCLK_N

NC

TESTMODE

SMDATA
SMCLK

PPS

LED_2

AVDDH

TRXN3

AVDDL

TRXN2

TRXP2

ATHEROS_AR8161_BL3A_R_QFN_40P

201918

17

1UF_6.3V_2_DY

C417

2 1

PAVDDVCO_LAN

C425

2 1

1UF_6.3V_2_DY

0.1UF_16V_2

C423

0.1UF_16V_2

2 1

30

PCIE_LAN_RX_C_DP

29

PCIE_LAN_RX_C_DN

28
27
26
25
24

22
21

C418

2 1

R402

0_5%_3

2 1

C421
C422

PAVDDH_LAN

C420

2 1

P3V3A_LAN

C419

0.1UF_16V_2

2 1

48D8

IN

48D8

IN

48C7

IN

48C7

IN

0.1UF_16V_2

21
21

0.1UF_16V_2

0.1UF_16V_2

PCIE_LAN_RX_DP
PCIE_LAN_RX_DN

OUT
OUT

48D8
48D8

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7022

8 7

REFERENCE 400~499(LAN)

6 5

4

3 2 1

23C223D3
23C223D3
23B223C3
23B223C2
23B223C2
23B223C3
23B223C2

D

IN
IN

IN
IN

LAN_TRD0_DN
LAN_TRD0_DP

LAN_TRD1_DN
LAN_TRD1_DP

22B523C8

P3V3AL

U460

1

I/O 1

2

GND

PANJIT_PJSRV05_4_DSSOT236P

IN
IN

LAN_TRD0_DP
LAN_TRD0_DN

22B523D6

22B523D6

6

I/O 4

5

VDD

43

I/O 3I/O 2

C460

2 1

0.1UF_16V_2

22B523C8

22B523B8
22B523B8

23B223C2

C479

C478

2 1

0.1UF_16V_2

LAN_TD_DP

IN

LAN_TD_DN

IN

LAN_RD_DP

IN

LAN_C_DP

IN

LAN_C_DN

IN

LAN_RD_DN

IN

LAN_D_DP

IN

LAN_D_DN

IN

2 1

0.1UF_16V_2

1

2
3
4

IN
IN
IN
IN

LAN_TRD1_DP
LAN_TRD1_DN
LAN_TRD2_DP
LAN_TRD2_DN

22B523C6

22B523C6

22B5

22B5

B

22B5

22B5

LAN_TRD3_DP

IN

LAN_TRD3_DN

IN

1
2

PANJIT_PJSRV05_4_DSSOT236P

U461

I/O 1
GND

P3V3AL

6

I/O 4

5

VDD

43

I/O 3I/O 2

C461

2 1

5
6
7
8

9
10
11
12

JACK470

1

TX+

2

TX-

3

RX+

4

P4

5

P5

6

RX-

7

P7

8

P8

SANTA_130456_051_8P

U471

2 15

TCT TCT

3

TX-

TD-

1

TX+

TD+

7

RCT

RCT

8

RX-

RD-

6

RX+

RD+

4

NC

NC

5

NC

NC

BOTH_TS21C_HF_SOP_16P

U470

TD+

TD1-

TDCT

TDCT

TD2+

TD2-

TD3+

TD3-

TDCT

TDCT

TD4+

TD4-

BOTH_NA0069RLF_SMD_24P

TX+

TX1-

TXTC

TXTC

TX2+

TX2-

TX3+

TX3-

TXTC

TXTC

TX4+

TX4-

G1

G

G2

G

D

R474

2 1

R475

75_5%_3

2 1

LAN_TD_DN
LAN_TD_DP

LAN_RD_DN
LAN_RD_DP

75_5%_3

OUT
OUT

OUT
OUT

2 1

RSC_0603_DY

2 1

RSC_0603_DY

23C2 23D5
23C2 23D5

23B2 23D5
23B2 23D5

R476

R477

R478

2 1

RSC_0402_DY

R479

2 1

RSC_0402_DY

LAN_C_DN

LAN_C_DP

LAN_D_DN

LAN_D_DP

LAN_TD_DP
LAN_TD_DN

LAN_RD_DP
LAN_RD_DN

LAN_C_DP
LAN_C_DN

OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT

23B2 23D5

23B2 23D5

23B2 23D5

23B2 23D5

23D3 23D5

23D3 23D5

23C3 23D5

23C3 23D5

23C2 23D5

23C2 23D5

CC

B

LAN_D_DP
LAN_D_DN

R470

75_5%_3

2 1

R473

R472

R471

75_5%_3

75_5%_3

75_5%_3

2 1

2 1

2 1

OUT
OUT

23C2 23D5

23C2 23D5

14
16
10
9
11
12
13

24
23
22
21
20
19
18
17
16
15
14
13

0.1UF_16V_2

C475

2 1

2 1

10PF_50V_2

1000PF_2000V_6

C477

2 1

CSC0402_DY

CHANGE by

DATE

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

21-OCT-2002XXX

23

7023

1

C480

2 1

C481

C470

2 1

2 1

0.1UF_16V_2

CSC0402_DY

C482

C471

2 1

2 1

0.1UF_16V_2

CSC0402_DY

C483

C472

2 1

CSC0402_DY

C473

2 1

2 1

0.1UF_16V_2

0.1UF_16V_2

CSC0402_DY

C474

2 1

1UF_6.3V_2

C476

8

7 6

5 4

REV

X011310xxxxx-0-0

AA

8 7

6 5

4

3 2 1

REFERENCE 500~549(AUDIO CODEC)

D

P5V0S

C532

2 1

10UF_6.3V_3_DY

B

8

BLM18PG121SN1(6014B0041601_0603)

R516

21

0_5%_3

C506

2 1

0.1UF_16V_2_DY

C529

2 1

4.7UF_6.3V_3

C514

2 1

CSC0402_DY

C515

2 1

CSC0402_DY

C516

2 1

CSC0402_DY

C517

2 1

CSC0402_DY

TIED UNDER OR NEAR CODEC

AGND_AUDIO

7 6

P5V0S_PVDD

C505

2 1

4.7UF_6.3V_3

25B8

OUT

25B8

OUT

25B8

OUT

25B8

OUT

C531

2 1

0.1UF_16V_2

PAD500

1 2

POWERPAD1X1M

C507

2 1

0.1UF_16V_2

SPK_OUT_L_P
SPK_OUT_L_N

SPK_OUT_R_N
SPK_OUT_R_P

21

AGND_AUDIO

P5V0S_AUDIO_AVDD

C536

2 1

4.7UF_6.3V_3

AGND_AUDIO

BI

34B3

BI

RESERVE FOR EMI

C500

2 1

0.1UF_16V_2

P3V3S

C508

2 1

MIC_IN_DATA

MIC_IN_CLK

C523

CSC0402_DY

AGND_AUDIO

2.2UF_6.3V_3

37

39
40

41

42
43
44
45
46
47
48

C509

2 1

1UF_6.3V_2

0.1UF_16V_2

R505

100_5%_2

2 1

C503

2.2UF_6.3V_3

C512

10UF_6.3V_3

2 1

C502

2 1

U500

AVSS2

AVDD2

PVDD1

SPK-L+

SPK-L-

PVSS1

PVSS2

SPK-R-

SPK-R+

PVDD2

EAPD

SPDIFO

MIC_IN_CLK_R

21

343635

33

CBP

CBN

CPVEE

HP-OUT-R

(THERMAL PAD 4X4 VIAS)

PD#

GPIO1/DMIC-CLK

GPIO0/DMIC-DATA

DVDD1

4

3

2

32

5

31

HP-OUT-L

MIC1-VREFO-L

DIGITAL

BIT-CLK

SDATA-OUT

6

29

30

MIC2-VREFO

MIC1-VREFO-R

SDATA-IN

DVSS2

8

719

C518

2 1

22PF_50V_2_DY

5 4

2 1

2710

28

VREF

LDO-CAP

ANALOG

SYNC

DVDD-IO

HDA_R_SDIN0
HDA_R_BITCLK

P3V3A

C510

C522

2 1

0.1UF_16V_2

CLOSE TO PIN27

C519

2.2UF_6.3V_3

2 1

C513

0.1UF_16V_2

2 1

AGND_AUDIO

263825

AVSS1

AVDD1

LINE1-R

LINE1-L

MIC1-R

MIC1-L

MONO-OUT

JDREF

Sense-B

MIC2-R

MIC2-L

LINE2-R

LINE2-L

Sense A

GND

PCBEEP

RESET#

REA_ALC269Q_VB6_CGT_QFN_48P

12

11

2 1

1UF_6.3V_2

C520

0.1UF_16V_2

22_5%_2

SHORT_0402

HP_R

HP_L
MIC_REF_L
MIC_REF_R

24
23
22
21
20
19
18
17
16
15
14
13
49

21

R502

21

R503

21

CHANGE by

25B3

OUT

25A3

OUT

25D3

OUT

25D3

OUT

MIC_R
MIC_L

R514

21

20K_1%_2

AGND_AUDIO

CLOSE TO PIN13

39.2K_1%_2

R507

47K_1%_2

HDA_3S_RST#
HDA_3S_SYNC

HDA_3S_SDIN0
HDA_3S_BITCLK

HDA_3S_SDOUT
EC_MUTE#

BI
BI

R500

20K_1%_2

R501

21

IN
IN

IN
IN

IN
IN

BLM18PG121SN1(6014B0041601_0603)

P5V0S_AUDIO_AVDD

25C2

25C2

MICS

21

21

HPS

PCSPKR_PCH_3

C521

2 1

100PF_50V_2

R506

4.7K_1%_2

47C7
47C7

47B7

47C7
47B7
21D6

DATE

21-OCT-2002XXX

23

IN

IN

21

P5V0S_AUDIO_AVDDP5V0S

R515

21

0_5%_3

C501

2 1

0.1UF_16V_2

AGND_AUDIO

25C5

25B2

47C8

IN

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

D

C504

2 1

4.7UF_6.3V_3

CC

B

AA

REV

of

X011310xxxxx-0-0

7024

1

8 7

REFERCE 600~649(JACK/MIC/SPEAKER)

6 5

AUDIO JACKS

4

3 2 1

D

21

MICPHONE

JACK600

SINGA_2SJ_T351_019_6P

TP30

5

TP607

MICS

4

1

3

1

6

TP30

2

1

1

1

TP30

G1

TP30

G2

TP606

AGND_AUDIO

CSC0402_DY

TP605

TP604

C600

OUT

24B2

C601

2 1

2 1

CSC0402_DY

R605

2.2K_5%_2

21

R604

2.2K_5%_2

R602

R603

21

1K_5%_2

21

1K_5%_2

MIC_REF_L
MIC_REF_R

C606

C607

IN
IN

2.2UF_6.3V_3

MIC_R

21

MIC_L

21

2.2UF_6.3V_3

24D3

24D3

D

24C2

BI

24C2

BI

CC

EMI CAPACITORS TO CLOSE TO JACK SIDE

AGND_AUDIO

D600

2

24B2

3

HPS

OUT

TP601
TP600

C611

C610

2 1

470PF_50V_2_DY

AGND_AUDIO

1

HEADPHONE

JACK601

5

TP603

TP30

4

1

1

TP30

1

TP30

2 1

470PF_50V_2_DY

3
6
2

TP30

1

1

G1

TP602

G2

SINGA_2SJ_T351_019_6P

AGND_AUDIO

B

PHP_PESD5V2S2UT_SOT23_3P_DY

AGND_AUDIO

NOTE:SPK TRACE SHOULD 30~40 MILS WIDTH

IN
IN
IN
IN

SPK_OUT_L_P
SPK_OUT_L_N
SPK_OUT_R_N
SPK_OUT_R_P

C602

2 1

24C7
24C7
24C7
24C7

INTERNAL SPEAKERS

CN600

4 G2

4
3
2
1

ACES_50224_0040N_001_4P

C603

2 1

470PF_50V_2_DY

470PF_50V_2_DY

C605

C604

2 1

2 1

470PF_50V_2_DY

470PF_50V_2_DY

C608

C609

2 1

2 1

470PF_50V_2_DY

470PF_50V_2_DY

G2

G1

3

G1

2
1

24D3

24D3

HP_R

IN
IN

HP_L

R601

120_5%_2

R600

120_5%_2

21
21

RESERVE FOR EMI

RESERVE FOR EMI

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7025

8 7

REFERNCE 900~999(CARDREADER)

6 5

4

3 2 1

D

SD_CMD

R901

SD_R_CLK SD_CLK

RESERVE FOR EMI

SD_CD#

17

161514

18

U900

SP10

SP11

SP12

SP13

XD_D7

TML

GPIO0

RREF

325

1

19
20

C901

SD_D3

21

SD_D2

BI

23

25

2 1

R900

21

CARD_REF

6.2K_1%_2

26B3

26B3

1UF_6.3V_2

B

SP9

SP8

DPDMCARD_3V3

3V3_IN

4

13

SP7

SP6

XD_CD#V18

SDREG

6

C904

1UF_6.3V_2

2 1

21

SHORT_0402

BI

12

SP5

SP4

SP3

SP2SP14

SP1

SD_D0

11

SD_D1

10
922

SD_WP

8
724

REA_RTS5129_QFN_24P

26B3

26B3

BI

26B3

BI

P3V3S_CR

C905

26B3

BIBI

26B3

BI

26B3

BI

2.2UF_6.3V_3

C906

0.1UF_16V_2

2 1

2 1

26C7
26D5

26C5

26C5
26C5
26C7
26C5
26B5

SD_D3

BI

SD_CMD

BI

SD_CLK

BI

SD_D0

BI

SD_D1

BI

SD_D2

BI

SD_CD#

BI

SD_WP

BI

CN900

1

CD-DAT3

2

CMD

3

VSS1

4

VDD

5

CLK

6

VSS2

7

DAT0

8

DAT1

9

DAT2

10

CARD_DETECT

11

WRIT_PROTECT

TAI_PSDAT0_09GLBS1ZZ4H1_11P

G1
G2

G1
G2

D

CC

B

P3V3S_CR
BI
BI

USB_CR_DN
USB_CR_DP

P3V3S

PAD900

1 2

POWERPAD_2_0610

4.7UF_6.3V_3

P3V3S_CARD

21

C900

2 1

C903

0.1UF_16V_2

2 1

C902

0.1UF_16V_2

2 1

AA

51B2

51B2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7026

8 7

REFERENCE 1300~1349(WLAN)

6 5

4

3 2 1

D

SUPPORT AOAC:OPEN SUPPORT AOAC:STUFF

D

P3V3S

4

S

36

3

Q1301

DS

SSM3K7002BFU

2

P3V3A

2 1

AOAC_ON#

1

G

C1307

CSC0402_DY

IN

WLON#

21D2 21D3

IN

CC

21D2 21D3

B

P1V5S

C1302

10UF_6.3V_3

2 1

BI
BI

IN
IN

IN
IN

IN

OUT
OUT

IN
IN

BI

IN

PCIE_WAKE#
BTIFON#

CLKREQ_WLAN#
CLK_PCIE_WLAN_DN

CLK_PCIE_WLAN_DP
BUF_PLT_RST#

CLK_PCI_DEBUG
PCIE_WLAN_RX_DN

PCIE_WLAN_RX_DP

PCIE_WLAN_TX_DN
PCIE_WLAN_TX_DP

BTIFON#
PCI_3S_SERIRQ

22B549A549B3

27B752B6
48B748D748D8

48B7
48B7

21E327C328C351A857A6
51A7

48D8
48D8

48D8
48D8

B

27C752B6

21E347C2

C1304

0.1UF_16V_2

2 1

R1300

0_5%_2

21

0_5%_2

R1301

21

C1303

RESERVE FOR EMI

0_5%_2

R1302

21

R1303

21

0_5%_2_DY

21

CSC0402_DY

1

3
5
7
9

11

13
15
17
19

21

23
25

29

31

33
35
37
39

41

43
45
47
49

51

CN1300

WAKE#
CH_DATA
CH_CLK
CLKREQ#
GND
REFCLK­REFCLK+
GND
LPC_DEBUG_RST#
LPC_PCI_CLK
GND
PERN0
PERP0

GND
PETN0
PETP0
GND
Reserved
Reserved
Reserved
Reserved
+V3AL
PWR_LED#
NUM_LED#
CAPS_LED#

LPC_FRAME#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

W_DISABLE#

PERST#

+3.3VAUX

SMB_CLK

SMB_DATA

USB_D­USB_D+

LED_WWAN#

LED_WLAN#

LED_WPAN#

2

3.3V

4

GND

6

1.5V

8
10
12
14
16
18

GND

20
22
24
26

GND

2827

1.5VGND

30
32
34

GND

36
38
40

GND

42
44
46
48

1.5V

50

GND

52

3.3V

G2G1

GG

C1305

0.1UF_16V_2

2 1

R1304

0_5%_5

2 1

C1301

10UF_6.3V_3

2 1

LPC_3S_FRAME#

LPC_3S_AD<3>
LPC_3S_AD<2>
LPC_3S_AD<1>
LPC_3S_AD<0>

BUF_PLT_RST#

PCH_3A_ALERT_CLK
PCH_3A_ALERT_DAT

USB_WLAN_DN
USB_WLAN_DP

Q1300

1
2
5

AM3423P_DY

C1306

CSC0402_DY

2 1

IN
IN
IN
IN
IN

IN

BI
BI

BI
BI

D

PMOS_4D1S

21E3 47C3
21E3 47C3
21E3 47C3
21E3 47C3
21E3 47C3

21E3 27C7
28C3 51A8
57A6

48D3
48D2

48D2 48D3

51B2
51B2

G

BELLW_80003_4021_52P

MINI CARD 1(WLAN)

8

7 6

5 4

CHANGE by

DATE

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7027

8 7

6 5

4

3 2 1

REFERENCE 1400~1499(3G)

D

47B3
47B3

47B3
47B3

SATA_MINICARD_RX_DP

BI

SATA_MINICARD_RX_DN

BI

SATA_MINICARD_TX_DN

BI

SATA_MINICARD_TX_DP

BI

CLOSE TO CONN SIDE

C1405

C1407

21

21

0.01UF_50V_2

C1406

0.01UF_50V_2

C1408

21

0.01UF_50V_2

0.01UF_50V_2

21

52D6

SATA_MINICARD_C_RX_DP
SATA_MINICARD_C_RX_DN

SATA_MINICARD_C_TX_DN
SATA_MINICARD_C_TX_DP

MSATA_DET

OUT

TP1402

P1V5S

C1410

2 1

0.1UF_16V_2

2 1

2 1

22UF_6.3V_5

0.1UF_16V_2

C1412

C1411

P3V3S

D

IN

C1400

22UF_6.3V_5

2 1

52D6

CC

28A4 28B6
28A6
28A4
28A4

3G_OFF#

21E3 27C3
27C7 51A8
57A6

51B2
51B2

C1402

0.1UF_16V_2

2 1

3

2

CN1400

1

WAKE#

3

CH_DATA

5

CH_CLK

7

CLKREQ#

9

GND

11

REFCLK-

13

REFCLK+

15

GND

17

LPC_DEBUG_RST#

19

LPC_PCI_CLK

21

GND

23

PERN0

25

PERP0

29

GND

31

PETN0

33

PETP0

35

GND

37

Reserved

39

Reserved

41

Reserved

43

Reserved

45

+V3AL

47

TP24

1

PWR_LED#

49

NUM_LED#

51

CAPS_LED#

LPC_FRAME#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

W_DISABLE#

PERST#

+3.3VAUX

SMB_CLK

SMB_DATA

USB_D­USB_D+

LED_WWAN#

LED_WLAN#

LED_WPAN#

2

3.3V

4

GND

6

1.5V

8
10
12
14
16
18

GND

20
22
24
26

GND

2827

1.5VGND

30
32
34

GND

36
38
40

GND

42
44
46
48

1.5V

50

GND

52

3.3V

G2G1

GG

UIM_PWR
UIM_DATA
UIM_CLK
UIM_RST

BUF_PLT_RST#

TP24

1

TP1400

TP24

1

TP1401

USB_3G_DN
USB_3G_DP

OUT

BI
BI

OUT

BI
BI

IN

2 1

Q1400

DS

1

G

SSM3K7002BFU

C1401

0.1UF_16V_2

3G_ON#

BELLW_80003_4021_52P

B

28A428D3

UIM_PWR

IN

U1400

1

VIO

3

VIO VIO

6

VIO

52

VBUSGND

4

P3V3S

B

NXP_IP4223CZ6_SOT457_6P_DY

CN1401

P5

28D3

UIM_DATA

BI BI

P6
P7

G2 G1

P1

VCC

GND

P2

VPP

RST

P3

I_O

CLK

G

G

TAI_PMPAT5_06GLBS7NI4H1_6P

C1403

UIM_PWR
UIM_RST
UIM_CLK

IN
IN

28B6 28D3
28C3

28C3

AA

C1404

2 1

2 1

4.7UF_6.3V_3

0.1UF_16V_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7028

8 7

REFERENCE 1700~1749(HDD)
REFERENCE 1750~1799(ODD)

6 5

4

3 2 1

SATA HDD

D

47C3
47C3

47C3
47C3

SATA_HDD_TX_DP

IN

SATA_HDD_TX_DN

IN

SATA_HDD_RX_DN

OUT

SATA_HDD_RX_DP

OUT

C1704
C1705
C1700

C1701

21
21

21
21

0.01UF_50V_2

0.01UF_50V_2

0.01UF_50V_2

0.01UF_50V_2

SATA_HDD_TX_C_DP
SATA_HDD_TX_C_DN

SATA_HDD_RX_C_DN
SATA_HDD_RX_C_DP

PLACE CLOSE TO CONNECTOR(<100MILS)

P5V0S

40MIL

C1702

C1703

C1706

2 1

22UF_6.3V_5

2 1

2 1

0.1UF_16V_2

22UF_6.3V_5

CN1700

1

GND

2

A+

3

A-

4

GND

5

B-

6

B+

7

GND

8

V3.3

9

V3.3

10

V3.3

11

GND

12

GND

13

GND

14

V5

15

V5

16

V5

17

GND

18

RESERVED

19

GND

20

V12

21

V12

22

V12

SANTA_194911_1_22P

D

G1

G1

G2

G2

CC

P5V0S

P3V3S

R1750

10K_5%_2_DY

2 1

B

52D2

SATA_ODD_PWREN

IN

1

SSM3K7002BFU_DY

Q1750

G

R1752

1M_5%_2_DY

2 1

3

DS

2

CSC0402_DY

R1751

100K_5%_2_DY

C1754

21

2 1

Q1751

TPC6111_DY

C1758

2 1

CSC0402_DY

4

36

S

G

R1754

PMOS_4D1S

5

0_5%_6

D

2 1

2

1

C1755

C1756

C1757

2 1

22UF_6.3V_5

2 1

2 1

22UF_6.3V_5

0.1UF_16V_2

B

CN1750

P6

GND

P5

GND

P4

MD

P3

+5V

P2

+5V

P1

DP

S7

GND

S6

B+

S5

B-

S4

GND

S3

A-

S2

A+

S1

G

GND

G

SYN_127382FR013G212ZR_13P

SATA ODD

G1
G2

AA

47B3
47B3

47B3
47B3

OUT
OUT

IN
IN

SATA_ODD_RX_DP
SATA_ODD_RX_DN

SATA_ODD_TX_DN
SATA_ODD_TX_DP

C1750

C1753

C1751

C1752

21

21

PLACE CLOSE TO CONNECTOR(<100MILS)

51B651C7

52B652D7

0.01UF_50V_2

21

0.01UF_50V_2

0.01UF_50V_2

21

0.01UF_50V_2

SATA_ODD_DA#

OUT

SATA_ODD_PRSNT#

OUT

SATA_ODD_RX_C_DP
SATA_ODD_RX_C_DN

SATA_ODD_TX_C_DN
SATA_ODD_TX_C_DP

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7029

8 7

REFERENCE 2000~2099(USB)

6 5

4

3 2 1

D

D

P5V0A_USB3

CN2002

1

51C2
51C2

BI
BI

USB_P2_DN
USB_P2_DP

1

2

2
3
4 G2

G1

G1

G2

3
4

ACES_50224_0040N_001_4P

CC

P5V0A

PAD2000

POWERPAD_2_0610

B

21D3

SB_USB_2

IN

1 2

P5V0A_USB_PW1

21

C2000

22UF_6.3V_5_DY

C2004

CSC0402_DY

2 1

2 1

C2001

1UF_6.3V_2

2 1

U2000

1

GND

2

IN

3

IN
EN

ROHM_BD82020FVJ_TSSOP_8P

8

OUT

7

OUT

6

OUT

54

OC#

R2001

10K_5%_2

22UF_6.3V_5

P3V3AL

2 1

C2002

2 1

USB_OC#_2

C2003

0.1UF_16V_2

OUT

2 1

21D3

P5V0A_USB3

R2000

RSC_0402_DY

2 1

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7030

8 7

REFERENCE 2400~2499

6 5

4

3 2 1

D

D

CC

REMOVE USB3.0 CONTROLLER IC

B

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7031

8 7

6 5

4

3 2 1

REFERENCE 2400~2499(USB3.0)

D

P5V0A_USB2

R2448

0_5%_5_DY

USB2.0 FROM SLEEP&CHARGE IC

BI
BI

R2459

R2460

USB_IC_DP
USB_IC_DN

21

0_5%_2

21

0_5%_2

32B8
51C2

USB2.0 FROM PCH

USB_P0_DN

BI

USB_P0_DP

BI

32A8
32A8

B

0_5%_2

R2458

21

USB_IC_DP
USB_IC_DN

R2456
R2457

5
6
7
8

21

0_5%_2

21

1

4

3 10

2 11

U2401

DP_OUT DP_IN

DM_OUT DM_IN

IN

ILIM_SEL

PWPD

FAULT#

OUT

NC

9

ILIM0

ILIM1

GND

TI_TPS2541A_QFN_16P

12

P5V0A_USB1

DSC
CTL1
CTL2
CTL3

BI
BI

IN

IN
IN
IN
IN

USB_P0_DN
USB_P0_DP

EC_ILIM_SEL

SB_USB_0
EC_CTL1
EC_CTL2
EC_CTL3

32C851C2

32C851C2

21D6

21D3
21C3
21D6
21E6

P5V0A

100K_5%_2_DY

32C7

BI

32C7

BI

R2446

R2447

USB_P0_R1_DN
USB_P0_R1_DP

51C6

BI

51C6

BI

C2442

0.1UF_16V_2

17
16
15
14

USB_OC#_0

13

21

0_5%_2

21

0_5%_2

USB3_PCH_TX1_DN

USB3_PCH_TX1_DP

P5V0A

P3V3AL

2 1

2 1

R2408

10K_5%_2

OUT

R2455
R2454

51C6
51C6

32B4
32B4

21B6

BI
BI

BI
BI

2 1

R2435

20K_1%_2

21

0_5%_2

21

0_5%_2

USB3_PCH_RX1_DN
USB3_PCH_RX1_DP

USB3_PCH_TX1C_DN
USB3_PCH_TX1C_DP

C2440

21

0.1UF_16V_2

C2441

21

0.1UF_16V_2

R2436

0_5%_2_DY

2 1

USB_P0_R_DN
USB_P0_R_DP

L2432

L2440

USB3_PCH_TX1C_DN

USB3_PCH_TX1C_DP

34
21

WCM_2012_900T

21
34

WCM_2012_900T

2 1

L2404

WCM_2012_900T

21
34

USB3_SSRX1_DN

USB3_SSRX1_DP
USB3_SSTX1_DN

USB3_SSTX1_DP

32B6

BI

32B6

BI

P5V0A_USB1

USB_P0_L_DN
USB_P0_L_DP

22UF_6.3V_5

CN2401

1

VBUS

2

D-

3

D+

4

PGND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

LOTES_AUSB0026_P002A_9P

G1

G

G2

G

G3

G

G4

G

C2426

C2427

0.1UF_16V_2 1000PF_50V_2

2 1

2 1

C2432

2 1

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7032

8 7

REFERENCE 2400~2499(USB3.0)

D

21C3

IN

SB_USB_1

47UF_6.3V_5

P5V0A

C2454

CURRENT LIMIT 2.5A

1
2
3

2 1

P5V0A_USB2

U2404

GND
IN
IN

ROHM_BD82024FVJ_TSSOP_8P

8

OUT

7

OUT

6

OUT

54

OC#EN

6 5

C2450

+

330UF_6.3V

2 1

P3V3AL

R2409

10K_5%_2

USB_OC#_1

2 1

OUT

21D6

USB2.0 FROM PCH

51C2
51C2

BI
BI

USB_P1_DN
USB_P1_DP

51C6
51C6

33B3
33B3

4

WCM_2012_900T

L2405

21
34

USB3_PCH_RX2_DN

BI

USB3_PCH_RX2_DP

BI

USB3_PCH_TX2C_DN

BI

USB3_PCH_TX2C_DP

BI

3 2 1

USB 3.0 CONNECTOR

P5V0A_USB2

2 1

CN2402

1

USB_P1_L_DN
USB_P1_L_DP

L2439

L2402

34
21

WCM_2012_900T

34
21

WCM_2012_900T

USB3_SSRX2_DN
USB3_SSRX2_DP

USB3_SSTX2_DN
USB3_SSTX2_DP

VBUS

2

D-

3

D+

4

PGND

5

SSRX-

6

SSRX+

7

GND

8

SSTX-

9

SSTX+

LOTES_AUSB0026_P002A_9P

G1

G

G2

G

G3

G

G4

G

C2452

0.1UF_16V_2

C2453

1000PF_50V_2

2 1

D

CC

51C6

51C6

USB3_PCH_TX2_DN

BI

USB3_PCH_TX2_DP

BI

C2445

21

0.1UF_16V_2

C2446

21

0.1UF_16V_2

B

USB3_PCH_TX2C_DN

USB3_PCH_TX2C_DP

33C4

BI

33C4

BI

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7033

8 7

REFFERENCE 3000~3049(LCM)

6 5

4

3 2 1

P3V3S

Q3000

S

DIODES_DMP2305U_SOT23_3P

0.01UF_50V_2

PCH_LCM_VDDEN#

R3001

C3000

2 1

21

D

R3011

R3012

21

21

0_5%_1

0_5%_1

LCM_VDDEN

SSM3K7002BFU

57B6

50D7

VGA_LCM_VDDEN

IN

PCH_LCM_VDDEN

IN

R3000

47K_5%_2

2 1

3

470K_5%_2

Q3001

DS

1

G

2

SD

G

G

D

PAD3003

1 2

POWERPAD_2_0610

C3003

2 1

680PF_50V_2

100_5%_2

SSM3K7002BFU

1

R3004

Q3002

G

P3V3S_LCMP3V3S_MOS_LCM

21

C3002

21

C3001

2 1

2 1

10UF_6.3V_3

0.1UF_16V_2

D

3

DS

2

GM:2.2K
PM:4.7K

(60130B4720ZT)

2.2K_5%_2

P3V3S

R300221R3005

2.2K_5%_2

P3V3S

C3004

56D6
56D6

50D7
50C7

57B6

50D7

50C6

B

50C6

50C6
50C6

50C6
50C6

50C6
50C6

PCH_LVDS_TXDL0_DN

IN

PCH_LVDS_TXDL0_DP

IN

PCH_LVDS_TXDL1_DN

IN

PCH_LVDS_TXDL1_DP

IN

PCH_LVDS_TXDL2_DN

IN

PCH_LVDS_TXDL2_DP

IN

PCH_LVDS_TXCL_DN

IN

PCH_LVDS_TXCL_DP

IN

R3019
R3020

R3021
R3022

R3023
R3024

R3025
R3026

21
21

21
21

21
21

21
21

0_5%_1
0_5%_1

0_5%_1
0_5%_1

0_5%_1
0_5%_1

0_5%_1
0_5%_1

VGA_INV_PWM_3

IN

PCH_INV_PWM_3

IN

EC_BKLTEN

IN

21E6

GM:OPEN
PM: 10K

VGA_LVDS_DDCCLK

BI

VGA_LVDS_DDCDATA

BI

PCH_LVDS_DDCCLK

BI

PCH_LVDS_DDCDATA

BI

0_5%_1

R3013

21

0_5%_1

R3014

21

R3035

10K_5%_2

2 1

100_5%_2

R3009

R3003

100_5%_2

1000PF_50V_2

R3015

21

0_5%_1

21

0_5%_1

R3016
R3017

21

0_5%_1

21

0_5%_1

R3018

21
21

R3006

100K_5%_2

C3006

2 1

CSC0402_DY

2 1

LVDS_DDCCLK
LVDS_DDCDATA

34A6
34A6

34A6
34A6

34A6
34A6

34A6
34A6

C3007

2 1

51B2
51B2

24A6
24A6

IN
IN

IN
IN

IN
IN

IN
IN

LVDS_TXDL0_DN
LVDS_TXDL0_DP

LVDS_TXDL1_DN
LVDS_TXDL1_DP

LVDS_TXDL2_DN
LVDS_TXDL2_DP

LVDS_TXCL_DN
LVDS_TXCL_DP

BI
BI

BI
BI

21

INV_PWM_3_R

EC_BKLTEN_R

USB_CAM_DN
USB_CAM_DP

MIC_IN_CLK
MIC_IN_DATA

R3010

100_5%_2

PVBAT

21

MIC_IN_DATA_R

2 1

0.1UF_16V_2

CN3000

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

16

16

17

17

18

18

19

19

20

20

21

21

22

22

23

23

24

24

25

25

26

26

27
28
29
30

G

27

G

28
29
30

ACES_50203_03001_001_30P

G1
G2

CC

B

P3V3S

C3010

57A6
57A6

57A6
57A6

57A6
57A6

57A6
57A6

VGA_LVDS_TXDL0_DN

IN

VGA_LVDS_TXDL0_DP

IN

VGA_LVDS_TXDL1_DN

IN

VGA_LVDS_TXDL1_DP

IN

VGA_LVDS_TXDL2_DN

IN

VGA_LVDS_TXDL2_DP

IN

VGA_LVDS_TXCL_DN

IN

VGA_LVDS_TXCL_DP

IN

R3027
R3028

R3029
R3030

R3031
R3032

R3033
R3034

21
21

21
21

21
21

21
21

0_5%_1
0_5%_1

0_5%_1
0_5%_1

0_5%_1
0_5%_1

0_5%_1
0_5%_1

LVDS_TXDL0_DN

LVDS_TXDL0_DP

LVDS_TXDL1_DN

LVDS_TXDL1_DP

LVDS_TXDL2_DN

LVDS_TXDL2_DP

LVDS_TXCL_DN
LVDS_TXCL_DP

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

34C3
34C3

34C3
34C3

34C3
34C3

34B3
34B3

C3009

2 1

2 1

0.1UF_25V_3

4.7UF_25V_5

C3011

2 1

0.1UF_16V_2
AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7034

8 7

REFERENCE 3050~3099(CRT)

56E2 56D3

50B7

56E2 56D3

D

50B7

56E2 56D3

50B7

IN
IN

IN
IN

IN
IN

VGA_CRTR
PCH_CRTR

VGA_CRTG
PCH_CRTG

VGA_CRTB
PCH_CRTB

R3064
R3065
R3066

R3067
R3068

R3069

21
21

21
21

21
21

0_5%_1
0_5%_1

0_5%_1
0_5%_1

0_5%_1
0_5%_1

CRTR

CRTG

CRTB

6 5

L3052

L3051

L3050

21

21

120NH,5%

21

120NH,5%

120NH,5%

CRTR_L

CRTG_L

CRTB_L

OUT

OUT

OUT

4

3 2 1

P5V0S

21

21

D3050

SS3040HE

35C335A7

35C335A7

35C335A7

P5V0S_CRT1

21

FUSE3050

SMD1812P110TF

D

R3054

2 1

150_1%_2

150_1%_2

2 1

150_1%_2

2 1

R3056

R3055

C3050

2 1

C3051

18PF_50V_2

2 1

C3052

R3050

P5V0S_CRTVDD

R3051

2.2K_5%_2

2 1

2 1

R3053

100_5%_2

R3052

100_5%_2

2 1

18PF_50V_2

35A3

35A3

18PF_50V_2

BI

BI

GM:2.2K
PM:2K

(60130B2020ZT)

CRT_DDCDATA_OUT

CRT_DDCCLK_OUT

2.2K_5%_2

35D4 35A7
35D4 35A7
35D4

21

35A3

IN

35A3

IN

21

IN
IN

35A7

IN

CRT_DDCDATA_R_OUT
CRT_HSYNC_R_OUT
CRT_VSYNC_R_OUT
CRT_DDCCLK_R_OUT

0.1UF_16V_2_DY

RESERVE CAP FOR EMI

B

CRT_VSYNC

OUT

CRT_HSYNC

OUT

CRT_DDCDATA

OUT

CRT_DDCCLK

OUT

CRT_VSYNC_R_OUT
CRT_HSYNC_R_OUT
CRT_DDCDATA_OUT

CRT_DDCCLK_OUT

OUT
OUT
OUT

OUT

CHANGE by

8

C3055

0.22UF_6.3V_2

P3V3S

2 1

P5V0S_CRTVDD

C3057

0.22UF_6.3V_2

2 1

35D4 35C3
35D4 35C3

35C3
35D4

IN
IN
IN

7 6

C3056

0.22UF_6.3V_2

CRTR_L
CRTG_L
CRTB_L

P5V0S

2 1

U3050

1 16

VCC-SYNC SYNC_OUT2

2

VCC-VIDEO

3

VIDEO_1

4

VIDEO_2

5

VIDEO_3

6

GND

7

VCC-DCC

TI_TPD7S019_15DBQR_SSOP_16P

GM:2.2K
PM:10K

(60130B1030ZT)

15

SYNC_IN2

14

SYNC_OUT1

13

SYNC_IN1

12

DCC_OUT2

11

DDC_IN2

10

DDC_IN1

98

DDC_OUT1BYP

P3V3S

R3060

2.2K_5%_2

CRT_VSYNC_OUT
CRT_VSYNC
CRT_HSYNC_OUT
CRT_HSYNC

CRT_DDCDATA
CRT_DDCCLK

R3061

2.2K_5%_2

2 1

2 1

IN
IN
IN

IN

5 4

35B4

35B4

35A4
35A4

R3062
R3063

21
21

35A4

35A4

35A4

35A4

30_5%_2
30_5%_2

R3070

R3071

R3072
R3073

R3074
R3075

R3076
R3077

35C3

35C3

35C5

35C5

0_5%_1

21

0_5%_1

21

0_5%_1

21
21

0_5%_1
0_5%_1

21

0_5%_1

21

0_5%_1

21

0_5%_1

21

VGA_CRT_DDCDATA
PCH_CRT_DDCDATA

VGA_CRT_DDCCLK
PCH_CRT_DDCCLK

P5V0S_CRT2

CRTR_L
CRTG_L
CRTB_L

TP3050

TP3051

C3053

2 1

VGA_CRT_VSYNC
PCH_CRT_VSYNC

VGA_CRT_HSYNC
PCH_CRT_HSYNC

DATE

21-OCT-2002XXX

23

TP24

1

TP24

1

C3054

0.1UF_16V_2_DY

2 1

IN
IN

IN
IN

IN
IN

IN
IN

CN3051

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12
13
14
15

SUYIN_070546HR015M25KZR_15P

50A6

50A6

56A3

50A6

56A3

50A6

G1

G1

12

G2

G2

13
14
15

56F756D3

56F756D3

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

1

CC

B

AA

REV

X011310xxxxx-0-0

7035

8 7

6 5

4

3 2 1

REFERENCE 3150~3199(HDMI)

50B3

50B3

56B3

D

56B3

36D6

B

PCH_HDMI_DDCDATA

BI

PCH_HDMI_DDCCLK

BI

VGA_HDMI_DDCDATA

BI

VGA_HDMI_DDCCLK

BI

GM: 2.2K
PM:10K

(60130B1030ZT)

2.2K_5%_2

BI BI

HDMI_DDCCLK

BI BI

36C5 36A2

36C5 36A2

36D5 36A2

36D5 36A2

36D5 36A2

36D5 36A2

36D5 36A2

36D5 36A2

8

R3178

P3V3S

2 1

IN

IN

IN

IN

IN

IN

IN

IN

R3174

21

0_5%_1

R3175

21

0_5%_1

R3176
R3177

21
21

0_5%_1
0_5%_1

HDMI_DDCDATA
HDMI_DDCCLK

P3V3S

R3179

2.2K_5%_2

2 1

SSM3K17FU

G

Q3151

G

S

DS

S

HDMI_TXC_C_DP

HDMI_TXC_C_DN

D

G

G

DS

GM:680_5%
PM:499_5%

(6013A0076801)

R3164

680_5%_2

R3163

680_5%_2

HDMI_TX0_C_DN

680_5%_2

HDMI_TX0_C_DP

680_5%_2

HDMI_TX1_C_DN

680_5%_2

HDMI_TX1_C_DP

680_5%_2

HDMI_TX2_C_DN

680_5%_2

HDMI_TX2_C_DP

680_5%_2

7 6

HDMI_CN_DDCDATAHDMI_DDCDATA

Q3150

SSM3K17FU

HDMI_CN_DDCCLK

D

21

21

R3162

21

R3161

21

R3160

21

R3159

21

R3158

21

R3157

21

Q3152

36C8

BI

36C8

BI

P3V3S

1

G

3

DS

SSM3K7002BFU

2

36C3

37C336C336D6

37D3

R3165

100K_5%_2

2 1

PLACE CLOSE TO CONNECTOR

WCM_2012HDMI_121T

WCM_2012HDMI_121T

WCM_2012HDMI_121T

WCM_2012HDMI_121T

D3155

SBR3U40P1

L3151

HDMI_TX2_R_DP

32

HDMI_TX2_R_DN

41

L3152

32

HDMI_TX1_R_DP

41

HDMI_TX1_R_DN

L3153

32

HDMI_TX0_R_DP

41

HDMI_TX0_R_DN

L3154

32

HDMI_TXC_R_DP

41

HDMI_TXC_R_DNHDMI_TXC_C_DN

P5V0AL_HDMI_VDD1

37D3 36C6
37C3 36C6

SMD1812P110TF

37C1

FUSE3150

OUT

37D6

21

HPDET_IC

HDMI_CEC

BI

HDMI_CN_DDCCLK

BI

HDMI_CN_DDCDATA

BI

P5V0AL_HDMI_VDD2

R3150

470K_5%_2

2 1

36A7 36A2
36A7 36A2

36A7

36A2

36A7

36A2

36A7

36A2
36A2

36B7

36B7 36A2
36B7 36A2

IN
IN

IN
IN

IN
IN

IN
IN

HDMI_TX2_C_DP
HDMI_TX2_C_DN

HDMI_TX1_C_DP
HDMI_TX1_C_DN

HDMI_TX0_C_DP
HDMI_TX0_C_DN

HDMI_TXC_C_DP

P5V0AL

40MIL

2 1

C3150

100PF_50V_2

2 1

CLOSE TO CONNECTOR

P3V3S

50B3

56C5

56F3

IN

56F3

IN

56F3

IN

56F3

IN

56F3

IN

56F3

IN

56F3

IN

56F3

IN

50B3

IN OUT

50B3

IN

50B3

IN

50B3

IN

50B3

IN

50B3

IN

50B3

IN

50B3

IN

PCH_HPDET

OUT

VGA_HPDET

OUT

VGA_HDMI_TX2_DN
VGA_HDMI_TX2_DP
VGA_HDMI_TX1_DN
VGA_HDMI_TX1_DP
VGA_HDMI_TX0_DN
VGA_HDMI_TX0_DP
VGA_HDMI_TXC_DN
VGA_HDMI_TXC_DP

PCH_HDMI_TX2_DN
PCH_HDMI_TX2_DP
PCH_HDMI_TX1_DN
PCH_HDMI_TX1_DP
PCH_HDMI_TX0_DN
PCH_HDMI_TX0_DP
PCH_HDMI_TXC_DN
PCH_HDMI_TXC_DP

R3180

R3181

C3152
C3154
C3156
C3158

C3160
C3162
C3164
C3166

21

21

0_5%_1

0_5%_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

HPDET

U3150

4

TC7SZ08FU

C3153
C3155
C3157
C3159

C3161
C3163
C3165
C3167

5

+

-

3

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21

0.1UF_6.3V_1

21
21
21
21

1
2

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

0.1UF_6.3V_1

CHANGE by

HDMI_HPD_EC
PLT_RST#

5 4

2

R3152

2.2K_5%_2

C3151

22PF_50V_2_DY

2 1

P5V0AL

13

D3150

NC

BAT54_30V_0.2A

2 1

TP3151

R3154

1K_5%_2

IN
IN

HDMI_TX2_C_DN
HDMI_TX2_C_DP
HDMI_TX1_C_DN
HDMI_TX1_C_DP
HDMI_TX0_C_DN
HDMI_TX0_C_DP
HDMI_TXC_C_DN
HDMI_TXC_C_DP

R3153

2.2K_5%_2

2 1

21

GM: 2.2K
PM:2K

(60130B2020ZT)

1
2
3
4
5
6
7
8
9

10

11

12
13

TP24

1

14
15
16
17
18
19

37B121D6

51A741C7

DATE

21-OCT-2002XXX

CN3150

TMDS Data2+
TMDS Data2 Shield
TMDS Data2­TMDS Data1+
TMDS Data1 Shield
TMDS Data1­TMDS Data0+
TMDS Data0 Shield
TMDS Data0­TMDS Clock+
TMDS Clock Shield
TMDS Clock­CEC
Reserved
DDC Clock
DDC Data
DDC/CEC GND
+5V Power
Hot Plug Detect

SYN_100042GR019M26DZL_19P

OUT
OUT
OUT
OUT
OUT
OUT
OUT

G1

G1

G2

G2

G3

G3

G4

G4

36D536A7

36D536A7

36D5
36A7

36A7
36D5

INVENTEC

36C5
36B7

TITLE

36B7
36C5

SIZE

A3

23

36D536A7

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

CS

SHEET

of

D

CC

B

AA

REV

X011310xxxxx-0-0

7036

1

8 7

6 5

4

3 2 1

P3V3AL

P3V3AL

13

NC

D3200

BAT54_30V_0.2A

37B3

HDMI_DDCCLK_CEC

BI

2

D

P3V3AL

R3204

27K_5%_2

1

5

2 1

NC

+

-

3

HDMI_CEC

2

3

Q3203

DS

G

SSM3K7002BFU

2

1

R3206

22K_5%_2

R3205

100K_5%_2

2 1

4.7K_5%_2

R3213

BI

CEC_OUT

21

2 1

36C3

P3V3AL

R3210

4.7K_5%_2

2 1

OUT

37A8

37A6

37D8

37C6

37B6

EC_SMB2_CLK EC_SMB2_DATA

BI

CEC_XOUT

OUT

CEC_XIN

IN

CEC_IN

IN

CEC_OUT

OUT

37B3

U3202

1 20

P3_5-SSCK-SCL-CMP1_2 P3_4-SCS#-SDA-CMP1_1

2

P3_7-CNTR0#-SSO-TXD1

3

RESET#

4

XOUT-P4_7

5

VSS-AVSS

6

XIN-P4_6

7

VCC-AVCC

8

MODE

9

P4_5-INT0#-RXD1

10 11

P1_7-CNTR00-INT10# P1_6-CLK0-SSI01

RENESAS_R5F211B4D61SP_LSSOP_20P

HDMI_DDCDATA_CEC

BI

37B6

CEC_IN

IN

68_5%_2

74LVC1G14GV

4

21

U3203

R3214

B

R3201

2.2K_5%_2

2 1

R3200

2.2K_5%_2

2 1

S

P3_3-TCIN-INT3#-SSI00-CMP1_0

P1_0-KI0#-AN8-CMP0_0

P1_1-KI1#-AN9-CMP0_1

P1_2-KI2#-AN10-CMP0_2

P1_3-KI3#-AN11-TZOUT

P1_5-RXD0-CNTR01-INT11#

S

P4_2-VREF

P1_4-TXD0

Q3201

G

SSM3K17FU

G

D

DS

P3V3AL

G

Q3200

SSM3K17FU

G

HDMI_CN_DDCDATA

D

DS

19

HDMI_DDCDATA_CEC

18

HDMI_DDCCLK_CEC

17
16
15
14
13
12

HDMI_CN_DDCCLK

36C3 36C6

BI

36C3 36C6

BI

P3V3AL

P3V3AL

C3200

2

2 1

HPDET_IC

0.1UF_16V_2

OUT

IN

21D6 36B2

36C4

R3215

21

0_5%_2_DY

R3208

R3209

4.7K_5%_2

4.7K_5%_2

2 1

BI

2 1

BI
BI

37C5
37D5

R3227

33_5%_2

21

PHP_74LVC1G17_SOT753_5P

4

U3200

1

5

NC

+

-

3

HDMI_HPD_EC

P3V3AL

D

CC

B

R3202

2 1

C3202

C3205

2 1

2 1

0.1UF_16V_2

1UF_6.3V_2

RSC_0402_DY

P3V3AL

R3211

47K_5%_2

37B6 37B6

CEC_XOUT CEC_XIN

2 1

8

R3212

47K_5%_2

2 1

INOUT

7 6

5 4

CHANGE by

DATE

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7037

8 7

REFERENCE 4100~4299(DDR)

M_A_A<15..0>

BI

43A8
43A8
43A8
43C5
43C5
43D4
43D4
43D4
43D4
43D4
43D4
43A8
43A8
43A8
38A6
38A6

43C5
43C5

43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5
43B5

M_A_BS0

IN

M_A_BS1

IN

M_A_BS2

IN

M_CS#0

IN

M_CS#1

IN

M_CLK_DDR0_DP

IN

M_CLK_DDR0_DN

IN

M_CLK_DDR1_DP

IN

M_CLK_DDR1_DN

IN

M_CKE0

IN

M_CKE1

IN

M_A_CAS#

IN

M_A_RAS#

IN

M_A_WE#

IN
OUT
OUT

PCH_3S_SMCLK

IN

PCH_3S_SMDATA

IN

IN

IN

M_A_DQS0_DP

IN

M_A_DQS1_DP

IN

M_A_DQS2_DP

IN

M_A_DQS3_DP

IN

M_A_DQS4_DP

IN

M_A_DQS5_DP

IN

M_A_DQS6_DP

IN

M_A_DQS7_DP

IN

M_A_DQS0_DN

IN

M_A_DQS1_DN

IN

M_A_DQS2_DN

IN

M_A_DQS3_DN

IN

M_A_DQS4_DN

IN

M_A_DQS5_DN

IN

M_A_DQS6_DN

IN

M_A_DQS7_DN

IN

D

B

43A4

48A8 39C8 20A7
48A8 39C8 20A7

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

SA0_DIM0
SA1_DIM0

M_ODT0
M_ODT1

M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>
M_A_A<6>
M_A_A<7>
M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>
M_A_A<14>
M_A_A<15>

98
97
96
95
92
91
90
86
89
85

107

84
83

119

80
78

109
108

79
114
121
101
103
102
104

73

74
115
110
113
197
201
202
200

116
120

11

28

46

63
136
153
170
187

12

29

47

64
137
154
171
188

10

27

45

62
135
152
169
186

CN4100

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15

BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA

ODT0
ODT1

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#

BELLW_80001_1021_204P

DQ10

DQ11

DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20

DQ21

DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30

DQ31

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40

DQ41

DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50

DQ51

DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60

DQ61

DQ62
DQ63

6 5

4

3 2 1

CHA

M_A_DQ<63..0>

5

M_A_DQ<0>

DQ0

7

M_A_DQ<1>

DQ1

15

M_A_DQ<2>

DQ2

17

M_A_DQ<3>

DQ3

4

M_A_DQ<4>

DQ4

6

M_A_DQ<5>

DQ5

16

M_A_DQ<6>

DQ6

18

M_A_DQ<7>

DQ7

21

M_A_DQ<8>

DQ8

23

M_A_DQ<9>

DQ9

33

M_A_DQ<10>

35

M_A_DQ<11>

22

M_A_DQ<12>

24

M_A_DQ<13>

34

M_A_DQ<14>

36

M_A_DQ<15>

39

M_A_DQ<16>

41

M_A_DQ<17>

51

M_A_DQ<18>

53

M_A_DQ<19>

40

M_A_DQ<20>

42

M_A_DQ<21>

50

M_A_DQ<22>

52

M_A_DQ<23>

57

M_A_DQ<24>

59

M_A_DQ<25>

67

M_A_DQ<26>

69

M_A_DQ<27>

56

M_A_DQ<28>

58

M_A_DQ<29>

68

M_A_DQ<30>

70

M_A_DQ<31>

129

M_A_DQ<32>

131

M_A_DQ<33>

141

M_A_DQ<34>

143

M_A_DQ<35>

130

M_A_DQ<36>

132

M_A_DQ<37>

140

M_A_DQ<38>

142

M_A_DQ<39>

147

M_A_DQ<40>

149

M_A_DQ<41>

157

M_A_DQ<42>

159

M_A_DQ<43>

146

M_A_DQ<44>

148

M_A_DQ<45>

158

M_A_DQ<46>

160

M_A_DQ<47>

163

M_A_DQ<48>

165

M_A_DQ<49>

175

M_A_DQ<50>

177

M_A_DQ<51>

164

M_A_DQ<52>

166

M_A_DQ<53>

174

M_A_DQ<54>

176

M_A_DQ<55>

181

M_A_DQ<56>

183

M_A_DQ<57>

191

M_A_DQ<58>

193

M_A_DQ<59>

180

M_A_DQ<60>

182

M_A_DQ<61>

192

M_A_DQ<62>

194

M_A_DQ<63>

0
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

P1V5

39C3 38C3

43D8

BI

LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN

C4100

+

330UF_2.5V_DY

2 1

C4101

1UF_6.3V_2

2 1

C4102

2 1

C4103

2 1

NOTE:PLACE C4100 ON COMMON PATH FOR BOTH DIMM'S

P3V3S

C4114

2.2UF_6.3V_3

C4115

0.1UF_16V_2

2 1

2 1

C4150

2.2UF_6.3V_3

P3V3S

R4104

10K_5%_2

PM_EXTTS#1_R

IN

2 1

C4104

1UF_6.3V_21UF_6.3V_21UF_6.3V_2

2 1

DIMM0_VREF_DQ

C4105

2 1

C4110

10UF_6.3V_3

2 1

C4106

2 1

C4109

10UF_6.3V_3

2 1

39C3 38B5
41A5 39C3

OUT
OUT

ALL VREF TRACES SHOULD HAVE 20 MIL TRACE WIDTH

C4116

0.1UF_16V_2

2 1

2 1

C4117

2.2UF_6.3V_3

DIMM0_VREF_CA

2 1

C4107

10UF_6.3V_310UF_6.3V_310UF_6.3V_3

2 1

C4108

10UF_6.3V_3

2 1

PM_EXTTS#1_R
DDR3_DRAMRST#

C4118

0.1UF_16V_2

2 1

75
76
81
82
87
88
93
94

99
100
105
106

111

112
117
118
123
124

199

77
122
125

198

30

1

126

2
3
8

9
13
14
19
20

26
31
32
37
38
43

CN4100

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

VDDSPD

NC1
NC2
NCTEST

EVENT#
RESET#

VREF_DQ
VREF_CA

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15

BELLW_80001_1021_204P

VSS16
VSS17
VSS18
VSS19
VSS20

VSS21

VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30

VSS31

VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40

VSS41

VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50

VSS51

VSS52

44
48
49
54
55
60
61
65
66
71
72

127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

1.5A

20325

VTT1

204

VTT2

G1

G1

G2

G2

PLACE THESE CAPS CLOSE TO VTT1 AND VTT2

D

CC

P0V75S

B

NOTE:
IF SA0_DIM0=1 , SA1_DIM0=0

SO-DIMMA SPD ADDRESS IS 0XA2
SO-DIMMA TS ADDRESS IS 0X32

IF SA0_DIM0=0 , SA1_DIM0=0
SO-DIMMA SPD ADDRESS IS 0XA0
SO-DIMMA TS ADDRESS IS 0X30

8

P3V3S

2 1

R4101

10K_5%_2_DY

2 1

SA0_DIM0

R4100

10K_5%_2_DY

SA1_DIM0

R4102

10K_5%_2

R4103

10K_5%_2

2 1

2 1

7 6

C4119

C4120

C4121

C4122

2 1

AA

R4118

1K_1%_21K_1%_2

R4117

1K_1%_2

P1V5

2 1

0_5%_2_DY

2 1

P1V5

P0V75M_VREF

R4132

R4133

1K_1%_2

2 1

38C8

IN

38C8

IN

R4145

0_5%_2_DY

DIMM0_VREF_CA

21

2 1

R4115

DIMM0_VREF_DQP0V75M_VREF

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

2 1

2 1

21

2 1

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

5 4

CHANGE by

DATE

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7038

8 7

REFERENCE 4100~4299(DDR)

6 5

4

3 2 1

BI

43A4
43A4
43A4
43C1
43C1
43D1
43D1
43D1
43D1
43D1
43D1
43A4
43A4

20A738C848A8

43C1
43C1

43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1
43B1

M_B_A<15..0>

M_B_BS0

IN

M_B_BS1

IN

M_B_BS2

IN

M_CS#2

IN

M_CS#3

IN

M_CLK_DDR2_DP

IN

M_CLK_DDR2_DN

IN

M_CLK_DDR3_DP

IN

M_CLK_DDR3_DN

IN

M_CKE2

IN

M_CKE3

IN

M_B_CAS#

IN

M_B_RAS#

IN

M_B_WE#

IN

PCH_3S_SMCLK

IN

PCH_3S_SMDATA

IN

M_ODT2

IN

M_ODT3

IN

M_B_DQS0_DP

IN

M_B_DQS1_DP

IN

M_B_DQS2_DP

IN

M_B_DQS3_DP

IN

M_B_DQS4_DP

IN

M_B_DQS5_DP

IN

M_B_DQS6_DP

IN

M_B_DQS7_DP

IN

M_B_DQS0_DN

IN

M_B_DQS1_DN

IN

M_B_DQS2_DN

IN

M_B_DQS3_DN

IN

M_B_DQS4_DN

IN

M_B_DQS5_DN

IN

M_B_DQS6_DN

IN

M_B_DQS7_DN

IN

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

M_B_A<0>
M_B_A<1>
M_B_A<2>
M_B_A<3>
M_B_A<4>
M_B_A<5>
M_B_A<6>
M_B_A<7>
M_B_A<8>
M_B_A<9>
M_B_A<10>
M_B_A<11>
M_B_A<12>
M_B_A<13>
M_B_A<14>
M_B_A<15>

CN4101

98

A0

97

A1

96

A2

95

A3

92

A4

91

A5

90

A6

86

A7

89

A8

85

A9

107

A10_AP

84

A11

83

A12

119

A13

80

A14

78

A15

109

BA0

108

BA1

79

BA2

114

S0#

121

S1#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

115

CAS#

110

RAS#

113

WE#

197

SA0

201

SA1

202

SCL

200

SDA

116

ODT0

120

ODT1

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS#0

27

DQS#1

45

DQS#2

62

DQS#3

135

DQS#4

152

DQS#5

169

DQS#6

186

DQS#7

BELLW_80001_5021_204P

M_B_DQ<63..0>

5

M_B_DQ<0>

DQ0

7

M_B_DQ<1>

DQ1

15

M_B_DQ<2>

DQ2

17

M_B_DQ<3>

DQ3

4

M_B_DQ<4>

DQ4

6

M_B_DQ<5>

DQ5

16

M_B_DQ<6>

DQ6

18

M_B_DQ<7>

DQ7

21

M_B_DQ<8>

DQ8

23

M_B_DQ<9>

DQ9

33

M_B_DQ<10>

DQ10

35

M_B_DQ<11>

DQ11

22

M_B_DQ<12>

DQ12

24

M_B_DQ<13>

DQ13

34

M_B_DQ<14>

DQ14

36

M_B_DQ<15>

DQ15

39

M_B_DQ<16>

DQ16

41

M_B_DQ<17>

DQ17

51

M_B_DQ<18>

DQ18

53

M_B_DQ<19>

DQ19

40

M_B_DQ<20>

DQ20

42

M_B_DQ<21>

DQ21

50

M_B_DQ<22>

DQ22

52

M_B_DQ<23>

DQ23

57

M_B_DQ<24>

DQ24

59

M_B_DQ<25>

DQ25

67

M_B_DQ<26>

DQ26

69

M_B_DQ<27>

DQ27

56

M_B_DQ<28>

DQ28

58

M_B_DQ<29>

DQ29

68

M_B_DQ<30>

DQ30

70

M_B_DQ<31>

DQ31

129

M_B_DQ<32>

DQ32

131

M_B_DQ<33>

DQ33

141

M_B_DQ<34>

DQ34

143

M_B_DQ<35>

DQ35

130

M_B_DQ<36>

DQ36

132

M_B_DQ<37>

DQ37

140

M_B_DQ<38>

DQ38

142

M_B_DQ<39>

DQ39

147

M_B_DQ<40>

DQ40

149

M_B_DQ<41>

DQ41

157

M_B_DQ<42>

DQ42

159

M_B_DQ<43>

DQ43

146

M_B_DQ<44>

DQ44

148

M_B_DQ<45>

DQ45

158

M_B_DQ<46>

DQ46

160

M_B_DQ<47>

DQ47

163

M_B_DQ<48>

DQ48

165

M_B_DQ<49>

DQ49

175

M_B_DQ<50>

DQ50

177

M_B_DQ<51>

DQ51

164

M_B_DQ<52>

DQ52

166

M_B_DQ<53>

DQ53

174

M_B_DQ<54>

DQ54

176

M_B_DQ<55>

DQ55

181

M_B_DQ<56>

DQ56

183

M_B_DQ<57>

DQ57

191

M_B_DQ<58>

DQ58

193

M_B_DQ<59>

DQ59

180

M_B_DQ<60>

DQ60

182

M_B_DQ<61>

DQ61

192

M_B_DQ<62>

DQ62

194

M_B_DQ<63>

DQ63

0

1

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

BI

43A1

D

43A4

OUT
OUT

SA0_DIM1
SA1_DIM1

39A7
39A6

B

43D4

P1V5

1UF_6.3V_2

2 1

C4138

2.2UF_6.3V_3

CHB

LAYOUT NOTE: PLACE CAPS NEAR SO-DIMM0 POWER PIN

C4124

C4125

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

2 1

P3V3S

C4137

0.1UF_16V_2

2 1

2 1

2.2UF_6.3V_3

C4126

2 1

C4151

C4127

2 1

DIMM1_VREF_DQ

ALL VREF TRACES SHOULD HAVE 20 MIL TRACE WIDTH

C4139

0.1UF_16V_2

2 1

2 1

C4128

10UF_6.3V_3

2 1

C4133

2 1

2.2UF_6.3V_3

C4129

10UF_6.3V_3

2 1

C4132

10UF_6.3V_310UF_6.3V_3

2 1

38B538C3

OUT

38C341A5

OUT

DIMM1_VREF_CA

C4140

2 1

C4130

10UF_6.3V_3

2 1

C4131

10UF_6.3V_3

2 1

PM_EXTTS#1_R
DDR3_DRAMRST#

C4141

0.1UF_16V_2

2 1

CN4101

75

VDD1

76

VDD2

81

VDD3

82

VDD4

87

VDD5

88

VDD6

93

VDD7

94

VDD8

99

VDD9

100

VDD10

105

VDD11

106

VDD12

111

VDD13

112

VDD14

117

VDD15

118

VDD16

123

VDD17

124

VDD18

199

VDDSPD

77

NC1

122

NC2

125

NCTEST

198

EVENT#

30

RESET#

1

VREF_DQ

126

VREF_CA

2

VSS1

3

VSS2

8

VSS3

9

VSS4

13

VSS5

14

VSS6

19

VSS7

20

VSS8

25

VSS9

26

VSS10

31

VSS11

32

VSS12

37

VSS13

38

VSS14

43

VSS15

BELLW_80001_5021_204P

VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52

44
48
49
54
55
60
61
65
66
71
72

127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196

1.5A

203

VTT1

204

VTT2

G1

G1

G2

G2

PLACE THESE CAPS CLOSE TO VTT1 AND VTT2

D

CC

P0V75S

B

NOTE:
SO-DIMMB SPD ADDRESS IS 0XA4
SO-DIMMB TS ADDRESS IS 0X34

IN

8

7 6

R4105

R4107

10K_5%_2

P3V3S

2 1

2 1

R4106

10K_5%_210K_5%_2_DY

2 1

SA1_DIM1SA0_DIM1

R4108

10K_5%_2_DY

2 1

R4122

1K_1%_2

2 1

39C839C8

IN

R4121

1K_1%_2

2 1

R4166

0_5%_2_DY

21

R4134

1K_1%_2

R4135

1K_1%_2

2 1

0_5%_2_DY

2 1

CHANGE by

5 4

DIMM1_VREF_CA P1V5 P0V75M_VREF

R4167

DIMM1_VREF_DQP0V75M_VREFP1V5

C4145

C4144

C4143

C4142

21

1UF_6.3V_2

2 1

1UF_6.3V_2 1UF_6.3V_2

2 1

2 1

1UF_6.3V_2

2 1

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DATE

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7039

8 7

REFERENCE 4300~4349(FAN)
REFERENCE 4411~4449(THERMAL )

D

21B6

IN

FAN_TACH1

6 5

4

3 2 1

P5V0S

PAD4300

1 2

POWERPAD_2_0610

L4300

KC_FBM_11_160808_101_T_2P_DY

P3V3S

R4300

10K_5%_2

2 1

TP4300

1

TP30

21B6

C4305

IN

C4300

2 1

220pF_50V_2

21

2 1

CSC0402_DY

P5V0S_FAN

21

FAN1_PWM

C4301

C4307

2 1

22UF_6.3V_5_DY

2 1

P3V3S

C4302

2 1

4.7UF_6.3V_3

0.1UF_16V_2

CN4300

1

1

2

2

3
4

G1

3

G2

GG4

ACES_50273_0047N_001_4P

D

CC

R4306

10K_5%_2

2 1

TP4301

1

TP30

FAN CN

B

56D6 40B1

P5V0AL

15D8

OUT

R4445

100K_5%_2

THRM_SHUTDWN#

C4441

2 1

2 1

0.1UF_16V_2

1
2
3
4

U4441

VCC

GND

OT1

OT2

ENE_P2809A2_SOT23_8P

THERMAL SHOUTDOWN

GM THERMAL SHOUTDOWN CPU SIDE AT 68.6 C
GM THERMAL SHOUTDOWN VGA SIDE AT 63.4 C

PM THERMAL SHOUTDOWN CPU SIDE AT 71.9 C
PM THERMAL SHOUTDOWN VGA SIDE AT 80.2 C

8

7 6

TMSNS1

RHYST1

TMSNS2

RHYST2

8
7
6
5

R4443

39K_1%_2

21

R4442
R4443
R4446
R4441

P5V0AL

R4442

2 1

R4444

2 1

R4441

75K_1%_2

100K_1%_NTC 48.7K_1%_2

21

48.7K
39K
59K
75K

P5V0AL

R4447

10F

C4306

2 1

CSC0402_DY

B

IN

R4413

330_5%_2

CORE_PG

21

Q4412

B

MMBT4401

B

2 1

C E

E C

R4414

2M_5%_2

C4412

CSC0402_DY

2 1

Q4411

1

G

SSM3K7002BFU

THRM_SHUTDWN#

3

DS

2

OUT

15D8 40A8 56D6

AA

11A411C749B7

R4446

59K_1%_2

2 1

2 1

100K_1%_NTC

41D552C1

PM_THRMTRIP#

IN

10FG

43.2K

30.1K

32.4K

18.2K

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

7040

1

REV

X011310xxxxx-0-0

8 7

6 5

4

3 2 1

REFERENCE 4500~4699(CPU)

P1V8S

21

R4500

2.2K_5%_2

R4502

2.2K_5%_2_DY

2 1

OUT

H_SNB_IVB#

41D5

D

PLACE CLOSE TO CPT AND NVRAM CONNECTOR

PROCESS STRAP SETTING
SANDY BRIDGE ONLY

SANDY BRIDGE/IVY BRIDGE

R4501

1K_5%_2

NV_CLE

21

STUFF R4502
STUFF R4500/R4501

OUT

52B2

11C721C3

DMI&FDI TERMINATIONVOLTAGE
NV_CLE (DEFAULT)

SET TOVSS WHEN LOW
SET TOVCC WHEN HIGH

IN

IN

PM_DRAM_PWRGD

PLT_RST#

49B7

36B251A7

B

S3 CIRCUIT: DRAM_RST# TO MEMORY SHOULD BE HIGH DURING S3

P1V5P3V3A

OUT

P1V05S

R4503

62_5%_2

2 1

2 1

P1V5S

2 1

C4500

CSC0402_DY

CPU_PROCHOT#

R4505

200_5%_2

R4506

130_1%_2

R4507

1.5K_5%_2

41D8

OUT

21A652C2

OUT

R4504

56_5%_2

40A4

OUT

52C1

49A3

BI

52C2

IN

PM_DRAM_PWRGD_R

21

21

R4508

750_1%_2

2 1

H_SNB_IVB#

TP4500

TP24

TP4501

TP24

H_PECI

CPU_PROCHOT#_R

21

PM_THRMTRIP#

LOW IN C6/C7

H_PM_SYNC

H_CPUPWRGD

R4509

10K_5%_2

CN4500

A28

C26

PROC_SELECT#

AN34

1

1

AL33

AN33

AL32

AN32

AM34

AP33

AR33

SKTOCC#

CATERR#

PECI

PROCHOT#

THERMTRIP#

PM_SYNC

UNCOREPWRGOOD

V8

SM_DRAMPWROK

RESET#

MISC

CLOCKS

MISCDDR3

JTAG & BPM

PWR MANAGEMENT THERMAL

BCLK

BCLK#

DPLL_REF_CLK

DPLL_REF_CLK#

SM_DRAMRST#

SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]

PRDY#
PREQ#

TRST#

DBR#

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]

TCK

TMS

TDI

TDO

CLK_DMI_PCH_DP

A27

CLK_DMI_PCH_DN

A16
A15

CPU_DRAMRST#

R8

AK1

SM_RCOMP0

A5

SM_RCOMP1

A4

SM_RCOMP2

TP30

AP29

TP30

AP27

TP30

AR26

TP30

AR27

TP30

AP30

TP30

AR28
AP26

TP30

TP30

AL35

AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32

R4510
R4511

21
21

OUT

R4512
R4513
R4514

1

TP4502

1

TP4503

1

TP4504

1

TP4505

1

TP4506

1

TP4507

1

TP4508

1

TP4509

CAD NOTE: ALL DDR_COMP SIGNALS SHOULD BE ROUTED SUCH TAHT

- MAX LENGTH = 500 MILS

- TRACE WIDTH = 15MILS AND

- MB TRACE IMPEDANCE < 68 MOHMS
(WORST CASE RESISTANCE)

IN
IN

1K_5%_2
1K_5%_2

41A5

21

140_1%_2

21

25.5_1%_2

21

200_1%_2

H_PRDY#
H_PREQ#

H_TCK
H_TMS
H_TRST#

H_TDI
H_TDO

SYS_RESET#

48B3
48B3

P1V05S

OUT

IN
IN

IN
IN

IN

OUT

OUT

41B2
41B2
41B2

41B2

D

41B2

CC

49B8

P1V05S

2 1

LOTES_ACA_ZIF_069_P01_989P

41C1
41C1
41C1

41C1
41C1

H_TMS
H_TDI
H_PREQ#

H_TCK
H_TRST#

R4516
R4517
R1418

R4519
R4520

IN
IN
IN

IN
IN

21
21
21

21
21

51_5%_2
51_5%_2
51_5%_2_DY

51_5%_2
51_5%_2

B

45D6
45D8

48D3

DRAMRST_CNTRL

OUT

DRAMRST_CNTRL_PCH

IN

8

R4601

1K_5%_2

2 1

R4600

21

SHORT_0402

0.047UF_16V_2

C4620

SSM3K7002BFU

2 1

7 6

R4602

1K_5%_2

2 1

3

Q4600

DS

1

G

R4603

1K_5%_2

2

R4604

4.99K_1%_2

DDR3_DRAMRST#

21

CPU_DRAMRST#

OUT

IN

38C3 39C3

41D2

AA

2 1

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

5 4

CHANGE by

DATE

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7041

8 7

6 5

4

3 2 1

REFERENCE 4500~4699(CPU)

D

49C3

IN

49C3

P1V05S

R4521

B

CAD NOTE: DP_COMPIO AND ICOMPO SIGNALS
SHOULD BE SHORTED NEAR BALLS AND ROUTED WITH

- TYPICAL IMPEDANCE < 25 MOHMS

24.9_1%_2

2 1

IN

49C3

IN

49C3

IN

49C3

IN

P1V0S_VCCP_EDP_COMPIO

49D6
49D6
49D6
49C6

49C6
49C6
49C6
49C6

49D6
49D6
49D6
49D6

49D6
49D6
49D6
49D6

49D3
49D3
49D3
49D3
49D3
49D3
49D3
49D3

49D3
49D3
49D3
49D3
49C3
49C3
49C3
49C3

FDI_FSYNC0
FDI_FSYNC1

FDI_INT
FDI_LSYNC0

FDI_LSYNC1

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

DMI_TX0_DN
DMI_TX1_DN
DMI_TX2_DN
DMI_TX3_DN

DMI_TX0_DP
DMI_TX1_DP
DMI_TX2_DP
DMI_TX3_DP

DMI_RX0_DN
DMI_RX1_DN
DMI_RX2_DN
DMI_RX3_DN

DMI_RX0_DP
DMI_RX1_DP
DMI_RX2_DP
DMI_RX3_DP

FDI_TX0_DN
FDI_TX1_DN
FDI_TX2_DN
FDI_TX3_DN
FDI_TX4_DN
FDI_TX5_DN
FDI_TX6_DN
FDI_TX7_DN

FDI_TX0_DP
FDI_TX1_DP
FDI_TX2_DP
FDI_TX3_DP
FDI_TX4_DP
FDI_TX5_DP
FDI_TX6_DP
FDI_TX7_DP

CN4500

B27

DMI_RX#[0]

B25

DMI_RX#[1]

A25

DMI_RX#[2]

B24

DMI_RX#[3]

B28

DMI_RX[0]

B26

DMI_RX[1]

A24

DMI_RX[2]

B23

DMI_RX[3]

G21

DMI_TX#[0]

E22

DMI_TX#[1]

F21

DMI_TX#[2]

D21

DMI_TX#[3]

G22

DMI_TX[0]

D22

DMI_TX[1]

F20

DMI_TX[2]

C21

DMI_TX[3]

A21

FDI0_TX#[0]

H19

FDI0_TX#[1]

E19

FDI0_TX#[2]

F18

FDI0_TX#[3]

B21

FDI1_TX#[0]

C20

FDI1_TX#[1]

D18

FDI1_TX#[2]

E17

FDI1_TX#[3]

A22

FDI0_TX[0]

G19

FDI0_TX[1]

E20

FDI0_TX[2]

G18

FDI0_TX[3]

B20

FDI1_TX[0]

C19

FDI1_TX[1]

D19

FDI1_TX[2]

F17

FDI1_TX[3]

J18

FDI0_FSYNC

J17

FDI1_FSYNC

H20

FDI_INT

J19

FDI0_LSYNC

H17

FDI1_LSYNC

A18

eDP_COMPIO

A17

eDP_ICOMPO

B16

eDP_HPD

C15

eDP_AUX

D15

eDP_AUX#

C17

eDP_TX[0]

F16

eDP_TX[1]

C16

eDP_TX[2]

G15

eDP_TX[3]

C18

eDP_TX#[0]

E16

eDP_TX#[1]

D16

eDP_TX#[2]

F15

eDP_TX#[3]

LOTES_ACA_ZIF_069_P01_989P

P1V05S

R4522

P1V0S_VCCP_PEG_ICOMPI

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]

DMI

PCI EXPRESS* - GRAPHICS

Intel(R) FDI

eDP

PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]

PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]

PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]

PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]

PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]

PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]

PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]

PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]

J22
J21
H22

K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32

J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32

M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25

M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25

PEG_C_RX15_DN
PEG_C_RX14_DN
PEG_C_RX13_DN
PEG_C_RX12_DN
PEG_C_RX11_DN
PEG_C_RX10_DN
PEG_C_RX9_DN
PEG_C_RX8_DN
PEG_C_RX7_DN
PEG_C_RX6_DN
PEG_C_RX5_DN
PEG_C_RX4_DN
PEG_C_RX3_DN
PEG_C_RX2_DN
PEG_C_RX1_DN
PEG_C_RX0_DN

PEG_C_RX15_DP
PEG_C_RX14_DP
PEG_C_RX13_DP
PEG_C_RX12_DP
PEG_C_RX11_DP
PEG_C_RX10_DP
PEG_C_RX9_DP
PEG_C_RX8_DP
PEG_C_RX7_DP
PEG_C_RX6_DP
PEG_C_RX5_DP
PEG_C_RX4_DP
PEG_C_RX3_DP
PEG_C_RX2_DP
PEG_C_RX1_DP
PEG_C_RX0_DP

PEG_TX15_DN
PEG_TX14_DN
PEG_TX13_DN
PEG_TX12_DN
PEG_TX11_DN
PEG_TX10_DN
PEG_TX9_DN
PEG_TX8_DN
PEG_TX7_DN
PEG_TX6_DN
PEG_TX5_DN
PEG_TX4_DN
PEG_TX3_DN
PEG_TX2_DN
PEG_TX1_DN
PEG_TX0_DN

PEG_TX15_DP
PEG_TX14_DP
PEG_TX13_DP
PEG_TX12_DP
PEG_TX11_DP
PEG_TX10_DP
PEG_TX9_DP
PEG_TX8_DP
PEG_TX7_DP
PEG_TX6_DP
PEG_TX5_DP
PEG_TX4_DP
PEG_TX3_DP
PEG_TX2_DP
PEG_TX1_DP
PEG_TX0_DP

24.9_1%_2

2 1

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CAD NOTE: PEG_ICOMPI AND RCOMPO SIGNALS
SHOULD BE SHORTED AND ROUTED WITH

- MAX LENGTH = 500 MILS

- TYPICAL IMPEDANCE = 43 MOHMS

PEG_ICOMPO SIGNALS SHOULD BE ROUTED WITH

- MAX LENGTH = 500 MILS

- TYPICAL IMPEDANCE = 14.5 MOHMS

57B1
57B1
57B1
57B1
57B1
57C1
57C1
57C1
57C1
57C1
57C1
57D1
57D1
57D1
57D1
57D1

57B1
57B1
57B1
57B1
57B1
57C1
57C1
57C1
57C1
57C1
57D1
57D1
57D1
57D1
57D1
57D1

42B3
42B3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42C3
42D3
42D3
42D3

42A3
42A3
42A3
42A3
42A3
42A3
42B3
42B3
42B3
42B3
42B3
42B3
42B3
42B3
42B3
42B3

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42B4

42C4

42C4

42C4

42A4

42A4

42A4

42A4 57D6

42A4 57D6

42A4 57D6

42A4 57C6

42B4 57C6

42B4 57C6

42B4 57C6

42B4

42B4 57B6

42B4 57B6

42B4 57B6

42B4 57B6

42B4

PEG_TX0_DN PEG_C_TX0_DN

IN

PEG_TX1_DN PEG_C_TX1_DN

IN

PEG_TX2_DN PEG_C_TX2_DN

IN

PEG_TX3_DN PEG_C_TX3_DN

IN

PEG_TX4_DN PEG_C_TX4_DN

IN

PEG_TX5_DN PEG_C_TX5_DN

IN

PEG_TX6_DN PEG_C_TX6_DN

IN

PEG_TX7_DN PEG_C_TX7_DN

IN

PEG_TX8_DN PEG_C_TX8_DN

IN

PEG_TX9_DN PEG_C_TX9_DN

IN

PEG_TX10_DN PEG_C_TX10_DN

IN

PEG_TX11_DN PEG_C_TX11_DN

IN

PEG_TX12_DN PEG_C_TX12_DN

IN

PEG_TX13_DN PEG_C_TX13_DN

IN

PEG_TX14_DN PEG_C_TX14_DN

IN

PEG_TX15_DN PEG_C_TX15_DN

IN

PEG_TX0_DP PEG_C_TX0_DP

IN

PEG_TX1_DP

IN

PEG_TX2_DP PEG_C_TX2_DP

IN

PEG_TX3_DP

IN

PEG_TX4_DP

IN

PEG_TX5_DP

IN

PEG_TX6_DP

IN

PEG_TX7_DP

IN

PEG_TX8_DP

IN

PEG_TX9_DP

IN

PEG_TX10_DP

IN

PEG_TX11_DP

IN

PEG_TX12_DP

IN

PEG_TX13_DP

IN

PEG_TX14_DP

IN

PEG_TX15_DP PEG_C_TX15_DP

IN

CLOSE TO CPU

C4580
C4581
C4582
C4583
C4584
C4585
C4586
C4587
C4588
C4589
C4590
C4591
C4592
C4593
C4594
C4595
C4596
C4597
C4598
C4599
C4600
C4601
C4602
C4603
C4604
C4605
C4606
C4607
C4608
C4609
C4610
C4611

21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

0.22UF_6.3V_2

PEG_C_TX1_DP

PEG_C_TX3_DP
PEG_C_TX4_DP
PEG_C_TX5_DP
PEG_C_TX6_DP
PEG_C_TX7_DP
PEG_C_TX8_DP
PEG_C_TX9_DP
PEG_C_TX10_DP
PEG_C_TX11_DP
PEG_C_TX12_DP
PEG_C_TX13_DP
PEG_C_TX14_DP

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

57D6

57D6

57D6

57D6

57D6

57C6

57C6

57C6

57C6

57C6

57C6

57B6

57B6

57B6

57B6

57B6

57D6

57D6

57D6

57C6

57B6

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7042

8 7

REFERENCE 4500~4699(CPU)

6 5

4

3 2 1

SOCKET,CPU,989P,TIN,3.0MM,STR,SMD,TR

CN4500

BI

38D8

M_B_DQ<63..0>

39D8

OUT

39D8

OUT

39C8

OUT

39C8

OUT

39C8

OUT

39C8

OUT

M_B_DQ<0>

0

M_B_DQ<1>

1

M_B_DQ<2>

2

M_B_DQ<3>

3

M_B_DQ<4>

4

M_B_DQ<5>

5

M_B_DQ<6>

6

M_B_DQ<7>

7

M_B_DQ<8>

8

M_B_DQ<9>

9

M_B_DQ<10>

10

M_B_DQ<11>

11

M_B_DQ<12>

12

M_B_DQ<13>

13

M_B_DQ<14>

14

M_B_DQ<15>

15

M_B_DQ<16>

16

M_B_DQ<17>

17

M_B_DQ<18>

18

M_B_DQ<19>

19

M_B_DQ<20>

20

M_B_DQ<21>

21

M_B_DQ<22>

22

M_B_DQ<23>

23

M_B_DQ<24>

24

M_B_DQ<25>

25

M_B_DQ<26>

26

M_B_DQ<27>

27

M_B_DQ<28>

28

M_B_DQ<29>

29

M_B_DQ<30>

30

M_B_DQ<31>

31

M_B_DQ<32>

32

M_B_DQ<33>

33

M_B_DQ<34>

34

M_B_DQ<35>

35

M_B_DQ<36>

36

M_B_DQ<37>

37

M_B_DQ<38>

38

M_B_DQ<39>

39

M_B_DQ<40>

40

M_B_DQ<41>

41

M_B_DQ<42>

42

M_B_DQ<43>

43

M_B_DQ<44>

44

M_B_DQ<45>

45

M_B_DQ<46>

46

M_B_DQ<47>

47

M_B_DQ<48>

48

M_B_DQ<49>

49

M_B_DQ<50>

50

M_B_DQ<51>

51

M_B_DQ<52>

52

M_B_DQ<53>

53

M_B_DQ<54>

54

M_B_DQ<55>

55

M_B_DQ<56>

56

M_B_DQ<57>

57

M_B_DQ<58>

58

M_B_DQ<59>

59

M_B_DQ<60>

60

M_B_DQ<61>

61

M_B_DQ<62>

62

M_B_DQ<63>

63

M_B_BS0
M_B_BS1
M_B_BS2

M_B_CAS#
M_B_RAS#
M_B_WE#

38D8
38C8

38C8
38C8

38B8
38B8
38B8
38B8
38B8
38B8
38B8
38B8

38B8
38B8
38B8
38B8
38B8
38B8
38B8
38B8

OUT
OUT
OUT

OUT
OUT
OUT

39D5

38C8
38C8
38C8

38C8
38C8
38C8

OUT

38D5

D

B

M_A_DQ<63..0>

BI

38D8
38D8
38D8

38C8
38C8
38C8

OUT
OUT
OUT

OUT
OUT
OUT

M_A_DQ<0>

0

M_A_DQ<1>

1

M_A_DQ<2>

2

M_A_DQ<3>

3

M_A_DQ<4>

4

M_A_DQ<5>

5

M_A_DQ<6>

6

M_A_DQ<7>

7

M_A_DQ<8>

8

M_A_DQ<9>

9

M_A_DQ<10>

10

M_A_DQ<11>

11

M_A_DQ<12>

12

M_A_DQ<13>

13

M_A_DQ<14>

14

M_A_DQ<15>

15

M_A_DQ<16>

16

M_A_DQ<17>

17

M_A_DQ<18>

18

M_A_DQ<19>

19

M_A_DQ<20>

20

M_A_DQ<21>

21

M_A_DQ<22>

22

M_A_DQ<23>

23

M_A_DQ<24>

24

M_A_DQ<25>

25

M_A_DQ<26>

26

M_A_DQ<27>

27

M_A_DQ<28>

28

M_A_DQ<29>

29

M_A_DQ<30>

30

M_A_DQ<31>

31

M_A_DQ<32>

32

M_A_DQ<33>

33

M_A_DQ<34>

34

M_A_DQ<35>

35

M_A_DQ<36>

36

M_A_DQ<37>

37

M_A_DQ<38>

38

M_A_DQ<39>

39

M_A_DQ<40>

40

M_A_DQ<41>

41

M_A_DQ<42>

42

M_A_DQ<43>

43

M_A_DQ<44>

44

M_A_DQ<45>

45

M_A_DQ<46>

46

M_A_DQ<47>

47

M_A_DQ<48>

48

M_A_DQ<49>

49

M_A_DQ<50>

50

M_A_DQ<51>

51

M_A_DQ<52>

52

M_A_DQ<53>

53

M_A_DQ<54>

54

M_A_DQ<55>

55

M_A_DQ<56>

56

M_A_DQ<57>

57

M_A_DQ<58>

58

M_A_DQ<59>

59

M_A_DQ<60>

60

M_A_DQ<61>

61

M_A_DQ<62>

62

M_A_DQ<63>

63

M_A_BS0
M_A_BS1
M_A_BS2

M_A_CAS#
M_A_RAS#
M_A_WE#

AP11

AN11

AL12
AM12
AM11

AL11
AP12
AN12

AJ14

AH14

AL15

AK15

AL14

AK14

AJ15

AH15

AE10
AF10

G10

N10

M10

AG6
AG5
AK6
AK5
AH5
AH6

AK8
AK9

AH8
AH9

AE8
AD9
AF9

M_CLK_DDR0_DP

SA_CLK[0]

C5

SA_DQ[0]

D5

SA_DQ[1]

D3

SA_DQ[2]

D2

SA_DQ[3]

D6

SA_DQ[4]

C6

SA_DQ[5]

C2

SA_DQ[6]

C3

SA_DQ[7]

F10

SA_DQ[8]

F8

SA_DQ[9]
SA_DQ[10]

G9

SA_DQ[11]

F9

SA_DQ[12]

F7

SA_DQ[13]

G8

SA_DQ[14]

G7

SA_DQ[15]

K4

SA_DQ[16]

K5

SA_DQ[17]

K1

SA_DQ[18]

J1

SA_DQ[19]

J5

SA_DQ[20]

J4

SA_DQ[21]

J2

SA_DQ[22]

K2

SA_DQ[23]

M8

SA_DQ[24]
SA_DQ[25]

N8

SA_DQ[26]

N7

SA_DQ[27]
SA_DQ[28]

M9

SA_DQ[29]

N9

SA_DQ[30]

M7

SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]

AJ5

SA_DQ[38]

AJ6

SA_DQ[39]

AJ8

SA_DQ[40]
SA_DQ[41]

AJ9

SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]

AL9

SA_DQ[46]

AL8

SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]

SA_BS[0]
SA_BS[1]

V6

SA_BS[2]

SA_CAS#
SA_RAS#
SA_WE#

DDR SYSTEM MEMORY A

SA_CLK#[0]

SA_CKE[0]

SA_CLK[1]

SA_CLK#[1]

SA_CKE[1]

RSVD_TP[1]
RSVD_TP[2]
RSVD_TP[3]

RSVD_TP[4]
RSVD_TP[5]
RSVD_TP[6]

SA_CS#[0]

SA_CS#[1]
RSVD_TP[7]
RSVD_TP[8]

SA_ODT[0]

SA_ODT[1]
RSVD_TP[9]

RSVD_TP[10]

SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]

SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]

SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]

SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]

AB6
AA6
V9

AA5
AB5
V10

AB4
AA4
W9

AB3
AA3
W10

AK3
AL3
AG1
AH1

AH3
AG3
AG2
AH2

C4
G6
J3
M6
AL6
AM8
AR12
AM15

D4
F6
K3
N6
AL5
AM9
AR11
AM14

AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7

M_A_DQS0_DN
M_A_DQS1_DN
M_A_DQS2_DN
M_A_DQS3_DN
M_A_DQS4_DN
M_A_DQS5_DN
M_A_DQS6_DN
M_A_DQS7_DN

M_A_DQS0_DP
M_A_DQS1_DP
M_A_DQS2_DP
M_A_DQS3_DP
M_A_DQS4_DP
M_A_DQS5_DP
M_A_DQS6_DP
M_A_DQS7_DP

M_CLK_DDR0_DN

M_CKE0

M_CLK_DDR1_DP
M_CLK_DDR1_DN

M_CKE1

M_CS#0
M_CS#1

M_ODT0
M_ODT1

M_A_A<0>
M_A_A<1>
M_A_A<2>
M_A_A<3>
M_A_A<4>
M_A_A<5>
M_A_A<6>
M_A_A<7>
M_A_A<8>
M_A_A<9>
M_A_A<10>
M_A_A<11>
M_A_A<12>
M_A_A<13>
M_A_A<14>
M_A_A<15>

10

11

12
13
14
15

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

M_A_A<15..0>

0

1

2
3
4
5
6
7
8
9

AM5
AM6
AR3

AN3
AN2
AN1

AN9

AN8
AR6
AR5
AR9

AJ11

AH11

AR8

AJ12
AH12
AT11
AN14
AR14

AT14

AT12
AN15
AR15

AT15

AA10

CN4500

M_CLK_DDR2_DP

SB_CLK[0]

C9

SB_DQ[0]

A7

SB_DQ[1]

D10

SB_DQ[2]

C8

SB_DQ[3]

A9

SB_DQ[4]

A8

SB_DQ[5]

D9

SB_DQ[6]

D8

SB_DQ[7]

G4

SB_DQ[8]

F4

SB_DQ[9]

F1

SB_DQ[10]

G1

SB_DQ[11]

G5

SB_DQ[12]

F5

SB_DQ[13]

F2

SB_DQ[14]

G2

SB_DQ[15]

J7

SB_DQ[16]

J8

SB_DQ[17]

K10

SB_DQ[18]

K9

SB_DQ[19]

J9

SB_DQ[20]

J10

SB_DQ[21]

K8

SB_DQ[22]

K7

SB_DQ[23]

M5

SB_DQ[24]

N4

SB_DQ[25]

N2

SB_DQ[26]

N1

SB_DQ[27]

M4

SB_DQ[28]

N5

SB_DQ[29]

M2

SB_DQ[30]

M1

SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]

AP3

SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]

AP2

SB_DQ[39]

AP5

SB_DQ[40]
SB_DQ[41]

AT5

SB_DQ[42]

AT6

SB_DQ[43]

AP6

SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]

AT8

SB_DQ[50]

AT9

SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]

AA9

SB_BS[0]

AA7

SB_BS[1]

R6

SB_BS[2]

SB_CAS#

AB8

SB_RAS#

AB9

SB_WE#

DDR SYSTEM MEMORY B

SB_CLK#[0]

SB_CKE[0]

SB_CLK[1]

SB_CLK#[1]

SB_CKE[1]

RSVD_TP[11]
RSVD_TP[12]
RSVD_TP[13]

RSVD_TP[14]
RSVD_TP[15]
RSVD_TP[16]

SB_CS#[0]

SB_CS#[1]
RSVD_TP[17]
RSVD_TP[18]

SB_ODT[0]

SB_ODT[1]
RSVD_TP[19]
RSVD_TP[20]

SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]

SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]

SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]

SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]

AE2
AD2
R9

AE1
AD1
R10

AB2
AA2
T9

AA1
AB1
T10

AD3
AE3
AD6
AE6

AE4
AD4
AD5
AE5

D7
F3
K6
N3
AN5
AP9
AK12
AP15

C7
G3
J6
M3
AN6
AP8
AK11
AP14

AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4

M_CLK_DDR2_DN

M_CLK_DDR3_DP
M_CLK_DDR3_DN

M_CS#2
M_CS#3

M_ODT2
M_ODT3

M_B_DQS0_DN
M_B_DQS1_DN
M_B_DQS2_DN
M_B_DQS3_DN
M_B_DQS4_DN
M_B_DQS5_DN
M_B_DQS6_DN
M_B_DQS7_DN

M_B_DQS0_DP
M_B_DQS1_DP
M_B_DQS2_DP
M_B_DQS3_DP
M_B_DQS4_DP
M_B_DQS5_DP
M_B_DQS6_DP
M_B_DQS7_DP

M_B_A<0>
M_B_A<1>
M_B_A<2>
M_B_A<3>
M_B_A<4>
M_B_A<5>
M_B_A<6>
M_B_A<7>
M_B_A<8>
M_B_A<9>
M_B_A<10>
M_B_A<11>
M_B_A<12>
M_B_A<13>
M_B_A<14>
M_B_A<15>

M_CKE2

M_CKE3

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

0

1

2
3
4
5
6
7
8
9

10

11

12
13
14
15

39C8
39C8

39C8
39C8

M_B_A<15..0>

39B8
39B8
39B8
39B8
39B8
39B8
39B8
39B8

39B8
39B8
39B8
39B8
39B8
39B8
39B8
39B8

OUT
OUT
OUT

OUT
OUT
OUT

39C8
39C8
39C8

39C8
39C8
39C8

D

CC

B

OUT

AA

LOTES_ACA_ZIF_069_P01_989P

8

7 6

5 4

LOTES_ACA_ZIF_069_P01_989P

CHANGE by

DATE

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

7043

1

REV

X011310xxxxx-0-0

8

7 6 5 4 3 2 1

FF

POWER

CN4500

E

REFERENCE 4500~4699(CPU)

2 1

2 1

2 1

2 1

22UF_6.3V_5

C4517

22UF_6.3V_5

C4521

22UF_6.3V_5

C4525

C4513

22UF_6.3V_5

C4514

22UF_6.3V_5

C4510

22UF_6.3V_5 22UF_6.3V_5

2 1

22UF_6.3V_5 22UF_6.3V_5

2 1

C4511

C4515

C4512

2 1

C4516

2 1

D

C4518

22UF_6.3V_5

C4522

22UF_6.3V_5 22UF_6.3V_5

2 1

2 1

C4519

22UF_6.3V_5

C4523

C4520

22UF_6.3V_5

2 1

C4524

22UF_6.3V_5 22UF_6.3V_5

2 1

C

B

PVCORE

AG35

VCC1

AG34

VCC2

AG33

VCC3

AG32

VCC4

AG31

VCC5

AG30

VCC6

AG29

VCC7

2 1

2 1

2 1

2 1

AG28

VCC8

AG27

VCC9

AG26

VCC10

AF35

VCC11

AF34

VCC12

AF33

VCC13

AF32

VCC14

AF31

VCC15

AF30

VCC16

AF29

VCC17

AF28

VCC18

AF27

VCC19

AF26

VCC20

AD35

VCC21

AD34

VCC22

AD33

VCC23

AD32

VCC24

AD31

VCC25

AD30

VCC26

AD29

VCC27

AD28

VCC28

AD27

VCC29

AD26

VCC30

AC35

VCC31

AC34

VCC32

AC33

VCC33

AC32

VCC34

AC31

VCC35

AC30

VCC36

AC29

VCC37

AC28

VCC38

AC27

VCC39

AC26

VCC40

AA35

VCC41

AA34

VCC42

AA33

VCC43

AA32

VCC44

AA31

VCC45

AA30

VCC46

AA29

VCC47

AA28

VCC48

AA27

VCC49

AA26

VCC50

Y35

VCC51

Y34

VCC52

Y33

VCC53

Y32

VCC54

Y31

VCC55

Y30

VCC56

Y29

VCC57

Y28

VCC58

Y27

VCC59

Y26

VCC60

V35

VCC61

V34

VCC62

V33

VCC63

V32

VCC64

V31

VCC65

V30

VCC66

V29

VCC67

V28

VCC68

V27

VCC69

V26

VCC70

U35

VCC71

U34

VCC72

U33

VCC73

U32

VCC74

U31

VCC75

U30

VCC76

U29

VCC77

U28

VCC78

U27

VCC79

U26

VCC80

R35

VCC81

R34

VCC82

R33

VCC83

R32

VCC84

R31

VCC85

R30

VCC86

R29

VCC87

R28

VCC88

R27

VCC89

R26

VCC90

P35

VCC91

P34

VCC92

P33

VCC93

P32

VCC94

P31

VCC95

P30

VCC96

P29

VCC97

P28

VCC98

P27

VCC99

P26

VCC100

PEG AND DDR

CORE SUPPLY

SVID

SENSE LINES

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8

VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24

VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39

VCCIO40

SVID SIGNAL TO VR

VIDALERT#

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE
VSSIO_SENSE

AH13
AH10
AG10
AC10
Y10
U10
P10

C4531

L10

2 1

J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12

E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11

J23

22UF_6.3V_5

C4533

C4532

2 1

2 1

22UF_6.3V_5

22UF_6.3V_5

C4535

C4534

2 1

2 1

22UF_6.3V_5

22UF_6.3V_5

PLACE CLOSE TO CPU

R4528

130_1%_2

2 1

H_CPU_SVIDALRT#

AJ29

H_CPU_SVIDCLK VR_SVID_CLK

AJ30

H_CPU_SVIDDAT

AJ28

R4529
R4530
R4531

PVCORE

R4532

100_1%_2

VCCSENSE

2 1

2 1

VSSSENSE

R4533

100_1%_2

OUT
OUT

11D6
11D6

P1V05S

AJ35
AJ34

B10
A10

2 1

2 1

R4534

10_1%_2

R4535

10_1%_2

VCC_SENSE_VCCIO
VSS_SENSE_VCCIO

21

43_5%_2

21

SHORT_0402

21

SHORT_0402

OUT
OUT

P1V05S

9B7
9B7

C4536

2 1

2 1

R4527

75_5%_2

P1V05S

C4537

2 1

22UF_6.3V_5

VR_SVID_ALERT#
VR_SVID_DATA

C4542

2 1

22UF_6.3V_5

22UF_6.3V_5

OUT
OUT
OUT

C4541

2 1

22UF_6.3V_5

11C7
11A3 11C7
11A3 11C7

C4540

2 1

22UF_6.3V_5

E

D

C

B

A

LOTES_ACA_ZIF_069_P01_989P

CHANGE by

8

7 6 5 4 3

XXX 21-OCT-2002

DATE

2 1

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

DOC.NUMBER

1310xxxxx-0-0

CSC

SHEET

of

44

A

REV

X01

70

8 7

6 5

4

3 2 1

PROCESSOR DRIVEN VREF PATH WAS STUFFED BY DEFAULT:
ROUTE WITH MIN. TRACE WIDTH OF 10 MILS

IN

IN

2 1

P1V8S

MPZ1608S221AT

8

CPUDDR_WR_VREF1

DRAMRST_CNTRL

C4545

22UF_6.3V_522UF_6.3V_5

L4500

C4546

2 1

21

C4562

10UF_6.3V_3

2 1

C4547

2 1

46C4

D

41A845D6

PVAXG

C4651

2 1

B

R4570

21

0_5%_2_DY

2

G

3

D S

Q4501

AM2302N

1

C4563

1UF_6.3V_2

2 1

C4548

2 1

2 1

1.2A

C4564

1UF_6.3V_2

C4549

22UF_6.3V_522UF_6.3V_522UF_6.3V_522UF_6.3V_5

2 1

2 1

C4565

22UF_6.3V_5

P1V8S_VCCPLL

7 6

46C4

41A845D8

C4550

22UF_6.3V_5

2 1

CPUDDR_WR_VREF2

IN

DRAMRST_CNTRL

IN

AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23

AR21

AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23

AN21

AN20
AN18

AN17
AM24
AM23
AM21
AM20
AM18
AM17

AL24
AL23

AL21

AL20
AL18

AL17
AK24
AK23
AK21
AK20
AK18
AK17

AJ24

AJ23
AJ21

AJ20

AJ18

AJ17
AH24
AH23

AH21

AH20
AH18
AH17

B6
A6
A2

R4572

21

0_5%_2_DY

2

3

D S

Q4502

G

AM2302N

1

POWER

CN4500

VAXG1 VAXG_SENSE

DIMM1_VREF_DQDIMM0_VREF_DQ

VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54

VCCPLL1
VCCPLL2
VCCPLL3

LOTES_ACA_ZIF_069_P01_989P

GRAPHICS

1.8V RAIL

5 4

SENSE

DDR3 -1.5V RAILS

SA RAIL

MISC VREF

VSSAXG_SENSE

LINES

SM_VREF

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8

VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15

VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8

VCCSA_SENSE

FC_C22

VCCSA_VID1

R4538

SHORT_0402

GFX_VCC_SENSE

AK35

GFX_VSS_SENSE

AK34

P0V75M_VREF_H

AL1

PVAXG

2 1

2 1

R4539

10_1%_2

OUT
OUT

R4540

10_1%_2

14A614B814D221D649A1
13A2
13D2

11B8
11B8

IN

SLP_S3#_3R

NOTE : DDR_WR_VREF SHOULD HAVE 20/20 MIL WHEREVER POSSIBLE

5A

AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1

M27
M26
L26
J26
J25
J24
H26
H25

H23

C22
C24

C4567

10UF_6.3V_3 10UF_6.3V_3

2 1

PVSA

2 1

R4544

100_5%_2

2 1

R4556

1K_5%_2

2 1

C4568

2 1

C4574

10UF_6.3V_3

CHANGE by

C4569

10UF_6.3V_3

2 1

C4575

10UF_6.3V_3

2 1

VCCSA_SENSE

VCCSA_VID0
VCCSA_VID1

R4547

1K_5%_2

2 1

C4570

2 1

C4576

10UF_6.3V_3

2 1

OUT

OUT
OUT

PVSA

2 1

10C4

10B4
10B4

C4571

2 1

+

C4577

100UF_6.3V

DATE

P0V75M_VREF_HP0V75M_VREF

DS

G

1

2 1

2

Q4500

AM2302N

C4578

470PF_50V_2

R4541

100K_5%_2

2 1

D

3

21

CC

P1V5S

+

C4572

10UF_6.3V_310UF_6.3V_310UF_6.3V_3

2 1

C4573

220UF_2.5V

2 1

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7045

8 7

CN4500

AT35

VSS1

AT32

VSS2

AT29

VSS3

AT27

VSS4

AT25

VSS5

AT22

VSS6

AT19

VSS7

AT16

VSS8

AT13 AJ2

VSS9

AT10

VSS10

AT7

VSS11

AT4

VSS12

AT3

VSS13

AR25

D

B

AR22
AR19
AR16
AR13
AR10

AR7
AR4

AR2
AP34
AP31
AP28
AP25
AP22
AP19
AP16
AP13
AP10

AP7

AP4

AP1
AN30
AN27
AN25
AN22
AN19
AN16
AN13
AN10

AN7

AN4
AM29
AM25
AM22
AM19
AM16
AM13
AM10

AM7
AM4
AM3
AM2

AM1
AL34
AL31
AL28
AL25
AL22
AL19
AL16
AL13
AL10

AK33
AK30
AK27
AK25
AK22
AK19
AK16
AK13
AK10

AK7
AK4

AJ25

VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

AL7

VSS66

AL4

VSS67

AL2

VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80

VSS

LOTES_ACA_ZIF_069_P01_989P

VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160

AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3

AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH26
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2

PEG STATIC LAN REVERSAL

LOW EDP ENABLE

PCIE PORT BIFURCATION

PEG DEFER TRAINING

8

7 6

6 5

CN4500

T35

VSS161

T34

VSS162

T33

VSS163

T32

VSS164

T31

VSS165

T30

VSS166

T29

VSS167

T28

VSS168

T27

VSS169

T26

VSS170

P9

VSS171

P8

VSS172

P6

VSS173

P5

VSS174

P3

VSS175

P2

VSS176

N35

VSS177

N34

VSS178

N33

VSS179

N32

VSS180

N31

VSS181

N30

VSS182

N29

VSS183

N28

VSS184

N27

VSS185

N26

VSS186

M34

VSS187

L33

VSS188

L30

VSS189

L27

VSS190

L9

VSS191

L8

VSS192

L6

VSS193

L5

VSS194

L4

VSS195

L3

VSS196

L2

VSS197

L1

VSS198

K35

VSS199

K32

VSS200

K29

VSS201

K26

VSS202

J34

VSS203

J31

VSS204

H33

VSS205

H30

VSS206

H27

VSS207

H24

VSS208

H21

VSS209

H18

VSS210

H15

VSS211

H13

VSS212

H10

VSS213

H9

VSS214

H8

VSS215

H7

VSS216

H6

VSS217

H5

VSS218

H4

VSS219

H3

VSS220

H2

VSS221

H1

VSS222

G35

VSS223

G32

VSS224

G29

VSS225

G26

VSS226

G23

VSS227

G20

VSS228

G17

VSS229

G11

VSS230

F34

VSS231

F31

VSS232

F29

VSS233

VSS_1

LOTES_ACA_ZIF_069_P01_989P

IN

46D4

IN

46D4

IN

IN

46D4

IN

STRAP PIN

CFG<2>

CFG<4>

CFG<5>

CFG<6>

CFG<7>

F22

VSS234

F19

VSS235

E30

VSS236

E27

VSS237

E24

VSS238

E21

VSS239

E18

VSS240

E15

VSS241

E13

VSS242

E10

VSS243

E9

VSS244

E8

VSS245

E7

VSS246

E6

VSS247

E5

VSS248

E4

VSS249

E3

VSS250

E2

VSS251

E1

VSS252

D35

VSS253

D32

VSS254

D29

VSS255

D26

VSS256

D20

VSS257

D17

VSS258

C34

VSS259

C31

VSS260

C28

VSS261

C27

VSS262

C25

VSS263

C23

VSS264

C10

VSS265

C1

VSS266

B22

VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285

45D8

B19

45D6

B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3

PEG STATIC LANE REVERSAL

CFG(2)

LOW EDP ENABLE

R4550

21

1K_1%_2

R4551

21

1K_1%_2_DY

R4552

21

1K_1%_2_DY

R4553

21

1K_1%_2_DY

R4554

21

1K_1%_2_DY

5 4

CFG(4)
PEG DEFER TRAINING

CFG(7)

PCIE PORT BIFURCATION STRAPS

CFG[6:5]

4

3 2 1

CN4500

RSVD28

OUT
OUT

46A6

OUT
OUT

46A6

OUT

46A6

OUT

46A6

OUT

46A6

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CPUDDR_WR_VREF1

OUT

CPUDDR_WR_VREF2

OUT

9C7

OUT

CFG<0>
CFG<1>
CFG<2>
CFG<3>
CFG<4>
CFG<5>
CFG<6>
CFG<7>
CFG<8>
CFG<9>
CFG<10>
CFG<11>
CFG<12>
CFG<13>
CFG<14>
CFG<15>
CFG<16>
CFG<17>

VCCIO_SEL

AK28

CFG[0]

AK29

CFG[1]

AL26

CFG[2]

AL27

CFG[3]

AK26

CFG[4]

AL29

CFG[5]

AL30

CFG[6]

AM31

CFG[7]

AM32

CFG[8]

AM30

CFG[9]

AM28

CFG[10]

AM26

CFG[11]

AN28

CFG[12]

AN31

CFG[13]

AN26

CFG[14]

AM27

CFG[15]

AK31

CFG[16]

AN29

CFG[17]

AJ31

VAXG_VAL_SENSE

AH31

VSSAXG_VAL_SENSE

AJ33

VCC_VAL_SENSE

AH33

VSS_VAL_SENSE

AJ26

RSVD5

B4

RSVD6

D1

RSVD7

F25

RSVD8

F24

RSVD9

F23

RSVD10

D24

RSVD11

G25

RSVD12

G24

RSVD13

E23

RSVD14

D23

RSVD15

C30

RSVD16

A31

RSVD17

B30

RSVD18

B29

RSVD19

D30

RSVD20

B31

RSVD21

A30

RSVD22

C29

RSVD23

J20

RSVD24

B18

RSVD25

A19

21

VCCIO_SEL

J15

RSVD27

RESERVED

R4555

RSVD29
RSVD30
RSVD31
RSVD32

RSVD33
RSVD34
RSVD35

RSVD37
RSVD38
RSVD39
RSVD40

RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

RSVD46
RSVD47
RSVD48
RSVD49
RSVD50

RSVD51
RSVD52

VCC_DIE_SENSE

RSVD54
RSVD55

RSVD56
RSVD57
RSVD58

KEY

10K_5%_2_DY

LOTES_ACA_ZIF_069_P01_989P

1 : (DEFAULT) NORMAL OPERATION
0 : LANE REVERSED

1 : (DEFAULT) EDP DISABLED
0 : EDP ENABLED

1 : (DEFAULT) PEG TRAIN IMMEDIATELY FOLLOWING XXRESETB DE ASSERTION
0 : PEG WAIT FOR BIOS FOR TRAINING

11 : (DEFAULT) X16 - DEVICE 1 FUNCTION AND 2 DISABLED
10 : X8, X8 - DEVICE 1 FUNCTION 1 ENABLE ; FUNCTION 2 DISABLED
01 : RESERVED - (DEVICE 1 FUNCTION 1 DISABLED ; FUNCTION 2 ENABLED)
00 : X8,X4,X4 - DEVICE 1 FUNCTION 1 AND 2 ENABLED

CHANGE by

DATE

L7
AG7
AE7
AK2
W8

AT26
AM33
AJ27

T8
J16
H16
G16

AR35
AT34
AT33
AP35
AR34

B34
A33
A34
B35
C35

AJ32
AK32

D

CC

AH27

REMOVE

AN35

CLK_XDP_CLKGEN_DP

AM35

CLK_XDP_CLKGEN_DN

AT2
AT1
AR1

B

B1

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7046

8 7

REFERENCE 4700~4949(PCH)

P3V3AL

21

A2A1

P3V3_RTC

3

C

D4700

D

R4700

1K_5%_2

INTVRMEN-INTEGRATE (SUS 1.05V VRM ENABLE
1:ENABLE INTERNAL VRS
0:ENABLE EXTERNAL VRS

PCSPKR_PCH_3(NO REBOOT)
1 : NO REBOOT ENABLED
0 : (DEFAULT) NO REBOOT DISABLED

FLASH OVERRIDE
FLASH DESCRIPTOR SECURITY OVERIDE

1:ENABLE
0:DISABLE : (DEFAULT INTERNAL PULL-DOWN)

B

21D3
47B7

HDA_3S_SYNC_R(PLL ODVR VOLTAGE)
1 : VCC VRM = 1.6V

0 : VCC VRM = 1.8V(DEFAULT)

P3V3A

BAT54C_30V_0.2A

1

2 1

TP30

CN4700

+

-

LOTES_AAA_BAT_063_P02_A_2P

2 1

OUT

FLASH_OVERRIDE

OUT

OUT

PCSPKR_PCH_3

HDA_3S_SYNC_R

R4713

24B1

10K_5%_2_DY

8

TP4705

21

0_5%_2_DY

R4720

10K_5%_2_DY

R4714

1K_5%_2

PCH_GPIO13

21

R4706

21

P3V3_RTC

R4707

330K_5%_3

C4700

2 1

P3V3_RTC

2 1

21

BI
BI

OUT

IN

HDA_3S_BITCLK
HDA_3S_SYNC

HDA_3S_RST#

HDA_3S_SDIN0

24A2

24B2

24B2

24A2

STRAP

FLASH_OVERRIDE

21D3

IN

47B8

P3V3A

OUT

R4718

RSC_0402_DY

47B6

IN

7 6

20K_1%_2

20K_1%_2

R4705

1M_5%_2

2 1

1UF_6.3V_2

R4711

33_5%_2

HDA_3S_SDOUT

21

OUT

47D3

OUT

47D3

OUT

47D3

OUT

21C721D6

OUT

21C821D6

OUT

21C8

OUT

21C621C7

OUT

21C621C8

OUT

6 5

R4703

21

21

C4702

R4709

33_5%_2

21

R4712

33_5%_2

1UF_6.3V_2

2 1

R4715

1K_5%_2

R4716

C4701

2 1

1UF_6.3V_2

HDA_3S_BITCLK_R

21

HDA_3S_SYNC_R

HDA_3S_RST#_R

21

21

21

R4704

33_5%_2

47A7

TP30
TP30
TP30
TP30

PCH_GPIO13

IN

TP4720

TP4721
TP4722
TP4723

PCH_TCK
PCH_TMS
PCH_TDI
PCH_TDO

1
1
1
1

EC_SPI_CLK
EC_SPI_CS0#
EC_SPI_CS1#

EC_SPI_SI
EC_SPI_SO

21

R4734

RSC_0402_DY

RTCX2

R4708

10M_5%_2

2 1

RTCX1

U4700

A20

RTCX1

C20

RTCX2

D20

RTCRST#

G22

SRTCRST#

K22

INTRUDER#

C17

INTVRMEN

STRAPPING

N34

HDA_BCLK

L34

HDA_SYNC

T10

K34

E34
G34
C34
A34

A36

C36
N32

J3

H7

K5

H1

T3

Y14

T1

V4

U3

STRAPPING

SPKR

HDA_RST#

HDA_SDIN0

HDA_SDIN1

HDA_SDIN2

HDA_SDIN3

HDA_SDO

STRAPPING

HDA_DOCK_EN#/GPIO33

HDA_DOCK_RST#/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CLK

SPI_CS0#

SPI_CS1#

SPI_MOSI

SPI_MISO

ITL_BD82PPSM_QPJ4_FCBGA_989P

5 4

4

3 2 1

P3V3A

R4736

21

0_5%_2_DY

P1V05S

R4737

21

47A6
47B6
47A6

29D5
29D5

29D5
29D5

28C7
28C7

28C7
28C7

21

21

OUT
OUT
OUT

P3V3S

2 1

10K_5%_2

RSC_0402_DY

PCH_TDI
PCH_TMS
PCH_TDO

R4744

BI

P1V05S

P1V05S

R4751

2 1

21E3 27B7

R4750

10K_5%_210K_5%_2

R4738

RSC_0402_DY

2 1

R4739

RSC_0402_DY

2 1

P3V3S

2 1

R4752

10K_5%_2

2 1

R4740

RSC_0402_DY

2 1

R4741

RSC_0402_DY

2 1

R4742

RSC_0402_DY

2 1

R4743

RSC_0402_DY

2 1

D

CC

B

AA

C4703

21

18PF_50V_2

4

32

X4700

32.768KHZ

1

C4704

21

18PF_50V_2

LPC_3S_AD<0>

RTC

IHDA

JTAG

SPI

LPC

SATA

STRAPPING

FWH4/LFRAME#

LDRQ1#/GPIO23

SATA 6G

SATA3RCOMPO

SATA0GP/GPIO21

SATA1GP/GPIO19

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

LDRQ0#

SERIRQ

SATA0RXN
SATA0RXP
SATA0TXN

SATA0TXP

SATA1RXN
SATA1RXP
SATA1TXN

SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN

SATA2TXP

SATA3RXN
SATA3RXP
SATA3TXN

SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN

SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN

SATA5TXP

SATAICOMPO

SATAICOMPI

SATA3COMPI

SATA3RBIAS

SATALED#

C38

LPC_3S_AD<1>

A38

LPC_3S_AD<2>

B37

LPC_3S_AD<3>

C37

LPC_3S_FRAME#

D36
E36

K36

PCI_3S_SERIRQ

V5

SATA_HDD_RX_DN

AM3

SATA_HDD_RX_DP

AM1

SATA_HDD_TX_DN

AP7

SATA_HDD_TX_DP

AP5
AM10

AM8
AP11
AP10

SATA_MINICARD_RX_DN

AD7

SATA_MINICARD_RX_DP

AD5

SATA_MINICARD_TX_DN

AH5

SATA_MINICARD_TX_DP

AH4
AB8

AB10
AF3
AF1

Y7
Y5
AD3
AD1

SATA_ODD_RX_DN

Y3

SATA_ODD_RX_DP

Y1

SATA_ODD_TX_DN

AB3

SATA_ODD_TX_DP

AB1
Y11

P1V05S_SATARCOMPO

Y10

AB12

P1V05S_SATA3RCOMPO

AB13

R4749

AH1

21

750_1%_2

P3
V14
P1

OUT

BI
BI
BI
BI

21E3 27C3
21E3 27C3
21E3 27C3
21E3 27C3

21E3 27C3

OUT
OUT

IN

IN
OUT
OUT

IN
IN

IN

IN
OUT
OUT

29A7
29A7

29A7
29A7

R4747

37.4_1%_2

R4748

49.9_1%_2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CHANGE by

DATE

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7047

REFERENCE 4700~4949(PCH)

D

48D7
22C5
48C7

48D7
27C7
48B7

B

39C8
20A7
38C8

48D3

48D3

39C8
20A7
38C8

CLKREQ_LAN#

OUT

CLKREQ_WLAN#

OUT

CLOCK TERMINATION FOR FICM
STUFF FOR INTEGRATED CLK

48B3

IN

48B3

IN

48B3

IN

48B3

IN

48A3

IN

48B3

IN

48B3

IN

BI

PCH_3A_SMCLK

BI

PCH_3A_SMDATA

BI

PCH_3S_SMDATA

BI

8 7

IN

IN
OUT
OUT

IN

IN
OUT
OUT

R4784

2.2K_5%_2

PCIE_LAN_RX_DN
PCIE_LAN_RX_DP
PCIE_LAN_TX_DN
PCIE_LAN_TX_DP

PCIE_WLAN_RX_DN
PCIE_WLAN_RX_DP
PCIE_WLAN_TX_DN
PCIE_WLAN_TX_DP

R4775

21

10K_5%_2_DY

R4776

21

10K_5%_2_DY

P3V3S

2.2K_5%_2

R4785

R4786

2.2K_5%_2

2 1

2 1

R4777

10K_5%_2

R4778

10K_5%_2

R4779

10K_5%_2

R4780

10K_5%_2

R4781

10K_5%_2

R4782

10K_5%_2

R4783

10K_5%_2

P3V3A

2 1

22B1

22B1
22C2
22C2

27B7

27B7
27B7
27B7

CLKIN_DMI_PCH_DN

CLKIN_DMI_PCH_DP

CLKIN_BUF_DOT96_DN

CLKIN_BUF_DOT96_DP

CLKIN_PCH14

CLKIN_SATA1_DP

CLKIN_SATA1_DN

PCH_3S_SMCLK

8

C4724

0.1UF_16V_2

C4726

0.1UF_16V_2

48D8
22C5

OUT

48C7

48D8
27C7

OUT

48B7

21

21

21

21

21

21

21

21

0.1UF_16V_2

21

0.1UF_16V_2

CLKREQ_LAN#

CLKREQ_WLAN#

22C2
22C2

48D8
22C5
48D7

27C7
27C7

48D8
27C7
48D7

PCIE_LAN_TX_C_DN

C4725

PCIE_LAN_TX_C_DP

21

PCIE_WLAN_TX_C_DN

C4727

PCIE_WLAN_TX_C_DP

21

CLK_PCIE_LAN_DN

OUT

CLK_PCIE_LAN_DP

OUT

CLKREQ_LAN#

IN

CLK_PCIE_WLAN_DN

OUT

CLK_PCIE_WLAN_DP

OUT

CLKREQ_WLAN#

IN

P3V3A

10K_5%_2_DY

R4773

10K_5%_2

R4772

10K_5%_2

R4803

R4789

10K_5%_2_DY

R4790

10K_5%_2_DY

R4791

10K_5%_2_DY

R4792

10K_5%_2_DY

1

R4793

10K_5%_2_DY

R4794

10K_5%_2_DY

R4787

2.2K_5%_2

2 1

2

Q4700

G

DS

SSM3K7002BFU

3

3

Q4701

DS

G

SSM3K7002BFU

2

P5V0S

1

7 6

6 5

U4700

BG34

PERN1

BJ34

PERP1

AV32

PETN1

AU32

PETP1

BE34

PERN2

BF34

PERP2

BB32

PETN2

AY32

PETP2

BG36

PERN3

BJ36

PERP3

AV34

PETN3

AU34

PETP3

BF36

PERN4

BE36

PERP4

AY34

BB34
BG37

BH37

AY36

BB36

BJ38
BG38
AU36
AV36

BG40

BJ40

AY40
BB40

BE38
BC38

AW38

AY38

AB49
AB47

AA48
AA47

AB42
AB40

AK14
AK13

PETN4
PETP4

PERN5
PERP5
PETN5
PETP5

PERN6
PERP6
PETN6
PETP6

PERN7
PERP7
PETN7
PETP7

PERN8
PERP8
PETN8
PETP8

Y40

CLKOUT_PCIE0N

Y39

CLKOUT_PCIE0P

J2

PCIECLKRQ0#/GPIO73

CLKOUT_PCIE1N
CLKOUT_PCIE1P

M1

PCIECLKRQ1#/GPIO18

CLKOUT_PCIE2N
CLKOUT_PCIE2P

V10

PCIECLKRQ2#/GPIO20

Y37

CLKOUT_PCIE3N

Y36

CLKOUT_PCIE3P

A8

PCIECLKRQ3#/GPIO25

Y43

CLKOUT_PCIE4N

Y45

CLKOUT_PCIE4P

L12

PCIECLKRQ4#/GPIO26

V45

CLKOUT_PCIE5N

V46

CLKOUT_PCIE5P

L14

PCIECLKRQ5#/GPIO44

CLKOUT_PEG_B_N
CLKOUT_PEG_B_P

E6

PEG_B_CLKRQ#/GPIO56

V40

CLKOUT_PCIE6N

V42

CLKOUT_PCIE6P

T13

PCIECLKRQ6#/GPIO45

V38

CLKOUT_PCIE7N

V37

CLKOUT_PCIE7P

K12

PCIECLKRQ7#/GPIO46

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

ITL_BD82PPSM_QPJ4_FCBGA_989P

P3V3A

21

P3V3S

21

1

TP24

TP4706

1

TP24

TP4707

21

TP24
TP24

1
1

TP4703
TP4704

21

21

21

21

21

21

SMBUS

SML0ALERT#/GPIO60

SML1ALERT#/PCHHOT#/GPIO74

PCI-E*

Link

Controller

PEG_A_CLKRQ#/GPIO47

CLOCKS

CLKIN_PCILOOPBACK

CLKOUTFLEX0/GPIO64

CLKOUTFLEX1/GPIO65

CLKOUTFLEX2/GPIO66

CLKOUTFLEX3/GPIO67

FLEX CLOCKS

5 4

4

SMBALERT#/GPIO11

SMBCLK

SMBDATA

SML0CLK

SML0DATA

SML1CLK/GPIO58

SML1DATA/GPIO75

CL_CLK1

CL_DATA1

CL_RST1#

CLKOUT_PEG_A_N
CLKOUT_PEG_A_P

CLKOUT_DMI_N

CLKOUT_DMI_P

CLKOUT_DP_N
CLKOUT_DP_P

CLKIN_DMI_N
CLKIN_DMI_P

CLKIN_GND1_N
CLKIN_GND1_P

CLKIN_DOT_96N
CLKIN_DOT_96P

CLKIN_SATA_N
CLKIN_SATA_P

REFCLK14IN

XTAL25_IN

XTAL25_OUT

XCLK_RCOMP

E12

PCH_3A_SMCLK

H14

PCH_3A_SMDATA

C9

DRAMRST_CNTRL_PCH

A12

PCH_3A_ALERT_CLK

C8

PCH_3A_ALERT_DAT

G12

C13
E14
M16

M7

T11

P10

48C3

OUT

CLKREQ_GPU#

M10

CLK_PEG_REF_DN

AB37

CLK_PEG_REF_DP

AB38

CLK_DMI_PCH_DN

AV22

CLK_DMI_PCH_DP

AU22

AM12
AM13

CLKIN_DMI_PCH_DN

BF18

CLKIN_DMI_PCH_DP

BE18

BJ30
BG30

CLKIN_BUF_DOT96_DN

G24

CLKIN_BUF_DOT96_DP

E24

CLKIN_SATA1_DN

AK7

CLKIN_SATA1_DP

AK5

CLKIN_PCH14

K45

CLKIN_PCI_FB

H45

V47
V49

Y47

CLOSE TO PCH

1

K43

1

F47

1

H47
K49

3 2 1

SMB_ALERT#

OUT

48B2

P3V3A

R4795

21

10K_5%_2

SML1ALERT#
SML1_CLK
SML1_DATA

CLKREQ_GPU#

10K_5%_2

XTAL25_IN
XTAL25_OUT

R4802

21

90.9_1%_2

TP24

TP4700

TP24

TP4701

TP24

TP4702

CHANGE by

R4837

BI
BI

OUT
OUT
OUT

OUT
OUT

R4753

10K_5%_2

OUT

OUT
OUT

OUT
OUT

21

OUT
OUT

48A8

48A8

41A8

48D227B3

48D227B3

48D2

IN

48D2

48C2

P3V3A

21

48C3

57B6
57B6

41D2
41D2

48C8

IN

48C8

IN

48D3

48D3 27B3

48D3 27B3

48D3

48D3

33PF_50V_2

48C8

IN

48C8

IN

48B8

IN

48B8

IN

48B8

IN

51A7

IN

48B1
48C1

P1V05S

DATE

IN

IN

IN

BI

BI

BI

BI

C4728

21-OCT-2002XXX

23

SML1ALERT#

PCH_3A_ALERT_CLK

PCH_3A_ALERT_DAT

SML1_CLK

EC_SMB3_CLK

SML1_DATA

EC_SMB3_DATA

X4701

25MHZ

2 1

IN

SMB_ALERT#

48D3

INVENTEC

SIZE

A3

2

DS

3

2

Q4703

DS

3

XTAL25_OUT

R4801

1M_5%_2

2 1

XTAL25_IN

21

C4729

27PF_50V_2

2 1

PASSWORD_0805

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

CS

SHEET

P3V3A

R4796

21

10K_5%_2

R4797

21

2.2K_5%_2

R4798

21

2.2K_5%_2

R4799

21

2.2K_5%_2

R4800

21

2.2K_5%_2

P3V3A

Q4702

G

1

SSM3K7002FU_DY

G

1

SSM3K7002FU_DY

OUT

OUT

B500

21

of

7048

1

48A3

48A3

REV

X011310xxxxx-0-0

D

CC

B

AA

8 7

6 5

4

3 2 1

U4700

BC24

DMI0RXN

BE20

DMI1RXN

BG18

DMI2RXN

BG20

DMI3RXN

BE24

DMI0RXP

BC20

DMI1RXP

BJ18

DMI2RXP

BJ20

DMI3RXP

AW24

DMI0TXN

AW20

DMI1TXN

BB18

DMI2TXN

AV18

DMI3TXN

AY24

DMI0TXP

AY20

DMI1TXP

AY18

DMI2TXP

AU18

DMI3TXP

BJ24

DMI_ZCOMP

BG25

DMI_IRCOMP

BH21

DMI2RBIAS

C12

SUSACK#

SYS_RESET#

P12

SYS_PWROK

L22

PWROK

L10

APWROK

B13

DRAMPWROK

C21

RSMRST#

K16

SUSWARN#/SUSPWRDNACK/GPIO30

E20

PWRBTN#

H20

ACPRESENT/GPIO31

E10

BATLOW#/GPIO72

A10

RI#

ITL_BD82PPSM_QPJ4_FCBGA_989P

21D649A6

IN

49B7

IN

49A6

IN

22B527C749B3

IN

49A3

IN

21E349B3

IN

DMI

FDI

FDI_FSYNC0

FDI_FSYNC1

FDI_LSYNC0

FDI_LSYNC1

DSWVRMEN

STRAPPING

CLKRUN#/GPIO32

SUS_STAT#/GPIO61

SUSCLK/GPIO62

SLP_S5#/GPIO63

INT. PU 20K

INT. PD 20K

INT. PU 20K

ACPRESENT
SUS_PWR_ACK
PM_RI#
PCIE_WAKE#
PCH_GPIO29

PCI_3S_CLKRUN#

R4824
R4825
R4826
R4827
R4821

R4828

System Power Management

SLP_LAN#/GPIO29

21
21
21
21
21

21

5 4

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7

FDI_INT

DPWROK

WAKE#

SLP_S4#

SLP_S3#

SLP_A#

SLP_SUS#

PMSYNCH

10K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2

8.2K_5%_2

IN
IN
IN
IN

IN
IN
IN
IN

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

DMI_RX0_DN
DMI_RX1_DN
DMI_RX2_DN
DMI_RX3_DN

DMI_RX0_DP
DMI_RX1_DP
DMI_RX2_DP
DMI_RX3_DP

DMI_TX0_DN
DMI_TX1_DN
DMI_TX2_DN
DMI_TX3_DN

DMI_TX0_DP
DMI_TX1_DP
DMI_TX2_DP
DMI_TX3_DP

D

P1V05S

R4812

49.9_1%_2

42D7
42D7
42D7
42D7

42D7
42D7
42C7
42C7

42D7
42D7
42D7
42D7

42D7
42D7
42D7
42D7

2 1

R4814

21

21D649A5

49A5

IN

750_1%_2

R4816

21

0_5%_2_DY

ACPRESENT

IN

PM_RI#

IN

PCH_PWROK

R4823

10K_5%_2

P3V3S

R4815

10K_5%_2

10K_5%_2_DY

2

NC

2 1

11A411C740B4

21B649A6

P3V3A

41C7

49C2
21D1
21D3

R4820

49A5

2 1

13

2

D4707

NC

IN

SYS_RESET#

41C1

B

IN

D4706

BAT54_30V_0.2A

LOW_BAT#_3

21D6

IN

EC_PWRSW#

21D6

IN

IN

IN

OUT

IN

OUT

13

SUSACK#

CORE_PG
PCH_PWROK

PM_DRAM_PWRGD

RSMRST#

SUS_PWR_ACK

BAT54_30V_0.2A

P3V3A

R4822

21

8.2K_5%_2

21B649B7

2 1

8

7 6

BJ14
AY14
BE14
BH13
BC12
BJ12
BG10
BG9

BG14
BB14
BF14
BG13
BE12
BG12
BJ10
BH9

AW16
AV12
BC10
AV14
BB10

A18

E22

B9K3

N3

G8

N14

D10

H4

F4

G10

G16

AP14

K14

P3V3A

P3V3S

0_5%_2_DY

FDI_TX0_DN
FDI_TX1_DN
FDI_TX2_DN
FDI_TX3_DN
FDI_TX4_DN
FDI_TX5_DN
FDI_TX6_DN
FDI_TX7_DN

FDI_TX0_DP
FDI_TX1_DP
FDI_TX2_DP
FDI_TX3_DP
FDI_TX4_DP
FDI_TX5_DP
FDI_TX6_DP
FDI_TX7_DP

FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_LSYNC1

SHORT_0402

PCIE_WAKE#

PCI_3S_CLKRUN#

EC_32KHZ

SLP_S5#_3R

R4817

21

SLP_S3#_IC_3R

SLP_SUS#

H_PM_SYNC

PCH_GPIO29

R4831

CHANGE by

OUT
OUT
OUT
OUT
OUT

21

IN
IN
IN
IN
IN
IN
IN
IN

IN
IN
IN
IN
IN
IN
IN
IN

RSMRST#

IN

IN

OUT

OUT

OUT

BI

IN

DSWVRMEN - DEEP S4/S5 WELL ON-DIE VOLTAGE REGULATOR ENABLE
HIGH-ENABLED(DEFAULT)

42C7

LOW-DISABLED

42C7
42C7
42C7
42C7
42C7
42C7
42C7

42C7
42C7
42C7
42C7
42C7
42C7
42C7
42B7

42B7

42B7

42B7

42B7

42B7

IN

27C7

22B5 49A5

21E3

49A5

21B6

21D3

14D2

41C5

49A5

21D3

21D1 49B7

SSM3K7002FU_DY

P3V3A

5

U4704

+

1
2

-

TC7SZ08FU

3

STRAPPING

1

4

P3V3_LDO

2 1
3

Q4713

DS

G

2

SLP_S3#_3R

21

R4710

100K_5%_2

P3V3_RTC

R4829

330K_5%_2

2 1

R4830

330K_5%_2_DY

2 1

P3V3A

R4832

2 1

R4883

10K_5%_2_DY

SLP_S5_3R

OUT

Q4714

1

G

SSM3K7002BFU

13A2 13D2 14A6 14B8 14D2 21D6

OUT

45D3

1K_5%_2_DY

P3V3_LDO

R4834

10K_5%_2

SLP_S3_3R

2 1
3

DS

2

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

DATE

21-OCT-2002XXX

23

SHEET

D

CC

B

15B8
15A4

OUT

15B4
16A7

AA

REV

of

1

X011310xxxxx-0-0

7049

8 7

REFERENCE 4700~4949(PCH)

6 5

4

3 2 1

R4856

2.2K_5%_2

P3V3S

2 1

2 1

R4857

2.2K_5%_2

35D8
35D8
35D8

OUT
OUT
OUT

21E7
34D7

34B5

34C5
34C5

OUT
OUT

OUT
OUT

OUT

R4859

150_1%_2

R4860

150_1%_2

R4861

150_1%_2

PCH_LCM_BKLTEN
PCH_LCM_VDDEN

PCH_INV_PWM_3

PCH_LVDS_DDCCLK
PCH_LVDS_DDCDATA

34B8

21

21

21

35A2

34B8

34B8
34B8
34B8

34B8
34B8
34B8

35B2

OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

R4858

21

2.37K_1%_2

PCH_LVDS_TXCL_DN
PCH_LVDS_TXCL_DP

PCH_LVDS_TXDL0_DN
PCH_LVDS_TXDL1_DN
PCH_LVDS_TXDL2_DN

PCH_LVDS_TXDL0_DP
PCH_LVDS_TXDL1_DP
PCH_LVDS_TXDL2_DP

PCH_CRTB
PCH_CRTG
PCH_CRTR

PCH_CRT_DDCCLK

OUT

PCH_CRT_DDCDATA

OUT

PCH_CRT_HSYNC

OUT

PCH_CRT_VSYNC

OUT

R4862

1K_1%_2

CLOSE TO PCH

100K_5%_2

2 1

2 1

R4855

AF37
AF36

AE48
AE47

AK39
AK40

AN48
AM47

AK47
AJ48

AN47
AM49

AK49
AJ47

AF40
AF39

AH45
AH47

AF49
AF45

AH43
AH49

AF47
AF43

U4700

J47

L_BKLTEN

M45

L_VDD_EN

P45

L_BKLTCTL

T40

L_DDC_CLK

K47

L_DDC_DATA

T45

L_CTRL_CLK

P39

L_CTRL_DATA

WHEN ‘1’- LVDS IS DETECTED

LVD_IBG
LVD_VBG

LVD_VREFH
LVD_VREFL

LVDSA_CLK#
LVDSA_CLK

LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3

LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3

LVDSB_CLK#
LVDSB_CLK

LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

N48

CRT_BLUE

P49

CRT_GREEN

T49

CRT_RED

T39

CRT_DDC_CLK

M40

CRT_DDC_DATA

M47

CRT_HSYNC

M49

CRT_VSYNC

T43

DAC_IREF

T42

CRT_IRTN

ITL_BD82PPSM_QPJ4_FCBGA_989P

LVDS

CRT

D

SDVO_TVCLKINN
SDVO_TVCLKINP

SDVO_STALLN
SDVO_STALLP

SDVO_INTN
SDVO_INTP

SDVO_CTRLCLK
SDVO_CTRLDATA

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPC_CTRLCLK
DDPC_CTRLDATA

DDPC_AUXN
DDPC_AUXP

DDPC_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P

Digital Display Interface

DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPD_CTRLCLK
DDPD_CTRLDATA

DDPD_AUXN
DDPD_AUXP

DDPD_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

AP43
AP45

AM42
AM40

AP39
AP40

P38
M39

AT49
AT47
AT40

AV42
AV40
AV45
AV46
AU48
AU47
AV47
AV49

PCH_HDMI_DDCCLK

P46

PCH_HDMI_DDCDATA

P42

AP47
AP49

PCH_HPDET

AT38

PCH_HDMI_TX2_DN

AY47

PCH_HDMI_TX2_DP

AY49

PCH_HDMI_TX1_DN

AY43

PCH_HDMI_TX1_DP

AY45

PCH_HDMI_TX0_DN

BA47

PCH_HDMI_TX0_DP

BA48

PCH_HDMI_TXC_DN

BB47

PCH_HDMI_TXC_DP

BB49

M43
M36

AT45
AT43
BH41

BB43
BB45
BF44
BE44
BF42
BE42
BJ42
BG42

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

CC

36D8

BI

36D8

BI

36B5

IN

36A5
36A5
36A5
36A5
36A5
36A5
36A5
36A5

B

AA

D

PCH_LVDS_DDCDATA - LVDS DETECT
HIGH-LVDS ENABLED

LOW-LVDS DISABLED (DEFAULT)

B

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7050

8 7

REFERENCE 4700~4949(PCH)

GPIO51

BBS_BIT1

0

D

P3V3S

B

28C3 27C7 27C3 21E3

0 0

R4874
R4875
R4876
R4877
R4878

R4880
R4881
R4882

R4838
R4956
R4879

R4957

57A6

8

GPIO19

BBS_BIT0

01

21

8.2K_5%_2

21

8.2K_5%_2

21

8.2K_5%_2

21

8.2K_5%_2

21

8.2K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

BI

BOOT BIOS

DESTINATION
RESERVED(NAND)

1

SPI (DEFAULT)11

41C7 36B2

BUF_PLT_RST#

R4888

100K_5%_2

------

LPC

PCI_3S_INTA#
PCI_3S_INTB#
PCI_3S_INTC#
PCI_3S_INTD#
RUNSCI0#_3

DGPU_HOLD_RST#
PCI_3S_REQ2#
DGPU_PWR_EN#

SATA_ODD_DA#
PCI_3S_PIRQG#
PCI_3S_PIRQH#

PCI_3S_PIRQE#

LOW=A16 SWAP OVERRIDE
STP_A16OVR
TOP-BLOCK SWAP OVERRIDE

HIGH=DEFAULT

PLT_RST#

BI

P3V3A

U4705

4

21

TC7SZ08FU

51B6

BI
BI
BI
BI
IN

IN
IN
IN

IN
IN
IN

IN

51B6

51B6

51B6

52D621E3

57A651B6

51B6

51B616A3

51B6

29A5

51B6

51B6

51B6

R4885

1K_5%_2_DY

BBS STRAPING

ROUTE WITH 90 OHMS IMPEDANCE
TOTAL LENGTH NO LONGER THAN 11 INCHES

BBS_BIT1

STP_A16OVR

21

21

R4886

1K_5%_2_DY

P3V3A

21E3

5

+

-

3

48A3

27C7

1

2

MCAHINE ID 0: USB ID0

MACHINE ID 1: POWER EXPRESS (YES:1 NO:0)
MACHINE ID 2: UMA:1 / DIS.:0
MACHINE ID 3: MAINSTREAM:1 / ENTRY:0
MACHINE ID 4: HDMI:1 / NO HDMI:0
MACHINE ID 5: SLEEP&CHARGE&DOLBY:(YES1 / NO 0)

MACHINE ID 6: USB ID1

MACHINE ID 1_DB : 35W CPU ONLY :1 / 35W&45W CPU:0

USB ID0
USB ID1

CLK_KBPCI

OUT

CLKIN_PCI_FB

OUT

CLK_PCI_DEBUG

OUT

USB3.0 X2 / 2.0 X1

1
1

USB3.0 X1 / 2.0 X2

7 6

6 5

BI
BI

BI
BI

BI
BI

BI
BI

51D7

BI

51C7

BI

51C7

BI

51C7

BI

51C7

OUT

57A6

OUT

16A3

OUT

51C7

51B7

BI

29A5

BI

51C7

BI

51B7

BI

21

21

22_5%_2

21

22_5%_2

21

22_5%_2

C4800

CSC0402_DY

USB3_PCH_RX1_DN
USB3_PCH_RX2_DN

USB3_PCH_RX1_DP
USB3_PCH_RX2_DP

USB3_PCH_TX1_DN
USB3_PCH_TX2_DN

USB3_PCH_TX1_DP
USB3_PCH_TX2_DP

PCI_3S_INTA#
PCI_3S_INTB#
PCI_3S_INTC#
PCI_3S_INTD#

DGPU_HOLD_RST#
PCI_3S_REQ2#
DGPU_PWR_EN#

PCI_3S_PIRQE#
SATA_ODD_DA#
PCI_3S_PIRQG#
PCI_3S_PIRQH#

P3V3A_PME#

CLK_KBPCI_R
CLK_PCI_FB_R

TP4717

CLK_PCI_DEBUG_R

21

51A3 51A2
51A3 51A2
51A3 51A2

51A3 51A2
51A3 51A2

51A3 51A2

51C7

10K_5%_2_DY

R4889
R4890

R4891

32C6
33C4

32C6
33C4

32B7
33B5

32B7
33B5

51C7

R4887

USB2.0 X3

1
0

0
1

U4700

BG26

TP1

BJ26

TP2

BH25

TP3

BJ16

TP4

BG16

TP5

AH38

TP6

AH37

TP7

AK43

TP8

AK45

TP9

C18

TP10

N30

TP11

H3

TP12

AH12

TP13

AM4

TP14

AM5

TP15

Y13

TP16

K24

TP17

L24

TP18

AB46

TP24

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

1

TP19

AB45

TP20

B21

TP21

M20

TP22

AY16

TP23

BG46

TP24

BE28

USB3RN1

BC30

USB3RN2

BE32

USB3RN3

BJ32

USB3RN4

BC28

USB3RP1

BE30

USB3RP2

BF32

USB3RP3

BG32

USB3RP4

AV26

USB3TN1

BB26

USB3TN2

AU28

USB3TN3

AY30

USB3TN4

AU26

USB3TP1

AY26

USB3TP2

AV28

USB3TP3

AW30

USB3TP4

K40

PIRQA#

K38

PIRQB#

H38

PIRQC#

G38

PIRQD#

C46

REQ1#/GPIO50

C44

REQ2#/GPIO52

E40

REQ3#/GPIO54

D47

GNT1#/GPIO51

E42

GNT2#/GPIO53

F46

GNT3#/GPIO55

G42

PIRQE#/GPIO2

G40

PIRQF#/GPIO3

C42

PIRQG#/GPIO4

D44

PIRQH#/GPIO5

K10

PME#

C6

PLTRST#

H49
H43

J48

K42

H40

MACHINE_ID0
MACHINE_ID1
MACHINE_ID2
MACHINE_ID3
MACHINE_ID4
MACHINE_ID5
MACHINE_ID6
MACHINE_ID1_DB

RSVD

PCI

USED AS GPIO ONLY.
INT. PU 20K

INT. PU 20K

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4 OC7#/GPIO14

ITL_BD82PPSM_QPJ4_FCBGA_989P

R4892
R4893
R4894
R4895
R4896
R4897
R4898
R4899

NOTE:10K_5%(60130B1030ZT)

5 4

4

RSVD1

RSVD2
RSVD3
RSVD4

RSVD5
RSVD6

RSVD7
RSVD8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16
RSVD17
RSVD18

USB

RSVD19
RSVD20
RSVD21
RSVD22

RSVD23

RSVD24

RSVD25

RSVD26
RSVD27

RSVD28
RSVD29

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P

USBRBIAS#

USBRBIAS

OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43

OC5#/GPIO9

OC6#/GPIO10

TO BE USED AS GPIO

NVRAM

DEBUG PORT

P3V3A

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2

21

10K_5%_2_DY 10K_5%_2_DY

51A5 51A2

3 2 1

AY7
AV7
AU3
BG4

AT10
BC8

AU2
AT4
AT3
AT1
AY3
AT5
AV3
AV1
BB1
BA3
BB5
BB3
BB7
BE8
BD4
BF6

AV5

AV10
AT8
AY5

BA2
AT12

NOTE:

BF3

USB2.0/3.0 COMBO-USB2.0 PORT 0,1 MAPPEDUSB3.0 PORT 1,2

USB_P0_DN

51A2
51A5
51A2
51A5
51A2
51A5
51A2
51A5
51A2
51A5
51A2
51A5
51A2
51A5

C24
A24
C25
B25
C26
A26
K28
H28
E28
D28
C28
A28
C29
B29
N28
M28
L30
K30
G30
E30
C30
A30
L32
K32
G32
E32
C32
A32

C33

B33

MACHINE_ID0

A14

MACHINE_ID1

K20

MACHINE_ID2

B17

MACHINE_ID3

C16

MACHINE_ID4

L16

MACHINE_ID5

A16

MACHINE_ID6

D14

MACHINE_ID1_DB

C14

MACHINE_ID0

OUT

MACHINE_ID1

OUT

MACHINE_ID2

OUT

MACHINE_ID3

OUT

MACHINE_ID4

OUT

MACHINE_ID5

OUT

MACHINE_ID6

OUT

MACHINE_ID1_DB

OUT

USB_P0_DP
USB_P1_DN
USB_P1_DP
USB_P2_DN
USB_P2_DP

USB_CR_DN
USB_CR_DP
USB_WLAN_DN
USB_WLAN_DP
USB_CAM_DN
USB_CAM_DP
USB_3G_DN
USB_3G_DP

22.6_1%_3

CLOSE TO PCH

R4835

R4900
R4901
R4902
R4903
R4904
R4905
R4906
R4907

BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

21

IN
IN
IN
IN
IN
IN
IN
IN

NOTE:10K_5%(60130B1030ZT)

CHANGE by

32B8

P0.P1 RESERVER FOR USB3.0

32C8

32B8
32C8

33C5
33C5
30C5
30C5

26A8

CARD READER

26A8
27B3

WLAN

27B3
34B3

WEBCAM

34B3
28C3

3G

28C3

51A551A3
51A551A3
51A551A3
51A551A3
51A551A3
51A551A3
51A551A3
51A551A3

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

10K_5%_2_DY

21

21

10K_5%_2

DATE

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CSA3

SHEET

of

7051

1

REV

X011310xxxxx-0-0

D

CC

B

AA

8 7

P3V3A

21

R4928
R4908
R4909
R4910

D

R4911

21

1K_5%_2_DY

21
21

10K_5%_2_DY

21

10K_5%_2_DY

10K_5%_2

10K_5%_2

P3V3S

21

R4927
R4916
R4917
R4915
R4919
R4920
R4921

R4727

21
21
21
21
21
21

10K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2
10K_5%_2

21

10K_5%_2_DY

B

FDI_OVRVLTG(GPIO37)

LOW- TX,RXTERMINATED TO SAME VOLTAGE

(DC COUPLING MODE) DEFAULT

P3V3S

21

R4934
R4935

10K_5%_2

21

100K_5%_2_DY

PLL_ODVR_EN(PLL ON DIE VR ENABLE)(GPIO28)

HIGH-ENABLED (DEFAULT)

LOW-DISABLED

P3V3A

R4950

21

10K_5%_2

R4936

21

10K_5%_2_DY

STRAP

8

PCH_GPIO27
PCH_GPIO15
PCH_GPIO8
PCH_GPIO12
PCH_GPIO24

PCH_GPIO6
PCH_GPIO22
PCH_GPIO38
PCH_GPIO16

SATA_ODD_PRSNT#

PCH_GPIO39
PCH_GPIO48

PCH_GPIO22

PCH_GPIO37

PLL_ODVR_EN

OUT

52C6

OUT

52C6

OUT

52D6

OUT

52C6

OUT

52C6

OUT

OUT

52C6 52C7

OUT

52B6

OUT

52C6

OUT

29A5 52B6

OUT

52B6

OUT

52B6

OUT

52C6 52D7

OUT

P3V3S

52B6

52C6

IN

7 6

6 5

P3V3S

R4721

21

33K_5%_2_DY

MSATA_DET

IN

28C252D6

52D7

21E351C7

52D7

52D7

52D7

52D7

13B213C8

52C752D7

52D7

52D7

52A7

R4929
R4930
R4932

52B7

52D7

52C7

52C7

29A552D7

OUT

27B727C7

3G_ON#

IN

PCH_GPIO6

IN

RUNSCI0#_3

IN

PCH_GPIO8

OUT

PCH_GPIO12

OUT

PCH_GPIO15

OUT

PCH_GPIO16

OUT

DGPU_PWRGD

IN

PCH_GPIO22

OUT

PCH_GPIO24

OUT

PCH_GPIO27

IN

PLL_ODVR_EN

OUT

PCH_GPIO37

OUT

PCH_GPIO38

OUT

PCH_GPIO39

OUT

PCH_GPIO48

OUT

SATA_ODD_PRSNT#

BTIFON#

OUT

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2

STRAPPING

STRAPPING

STRAPPING

U4700

T7

BMBUSY#/GPIO0

A42

TACH1/GPIO1

H36

TACH2/GPIO6

E38

TACH3/GPIO7

C10

GPIO8

C4
G2

U2

D40

T5
E8

E16

P8
K1
K4
V8

M5

N2

M3

V13

V3
D6

A4

A45
A46

A5
A6
B3

B47

BD1

BD49

BE1

BE49

BF1

BF49

INT. PU 20K

LAN_PHY_PWR_CTRL/GPIO12

INT. PD 20K

GPIO15

STRAPPING

SATA4GP/GPIO16

INT. PU 20K

TACH0/GPIO17

SCLOCK/GPIO22

GPIO24

GPIO27

INT.PD 20K

GPIO28

INT. PU 20K

STP_PCI#/GPIO34

GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SLOAD/GPIO38

SDATAOUT0/GPIO39

SDATAOUT1/GPIO48

SATA5GP/GPIO49/TEMP_ALERT#

GPIO57

VSS_NCTF_1

VSS_NCTF_2

VSS_NCTF_3

VSS_NCTF_4

VSS_NCTF_5

VSS_NCTF_6

VSS_NCTF_7

VSS_NCTF_8

VSS_NCTF_9

VSS_NCTF_10

VSS_NCTF_11

VSS_NCTF_12

VSS_NCTF_13

VSS_NCTF_14

ITL_BD82PPSM_QPJ4_FCBGA_989P

GPIO

INT. PD 20K

STRAPPING

NCTF

5 4

4

3 2 1

REFERENCE 4700~4949(PCH)

40A4
41D5

D

CC

B

AA

CPU/MISC

TACH4/GPIO68

TACH5/GPIO69

TACH6/GPIO70

TACH7/GPIO71

INT. PU 20K

PROCPWRGD

STRAPPING

VSS_NCTF_15

VSS_NCTF_16

VSS_NCTF_17

VSS_NCTF_18

VSS_NCTF_19

VSS_NCTF_20

VSS_NCTF_21

VSS_NCTF_22

VSS_NCTF_23

VSS_NCTF_24

VSS_NCTF_25

VSS_NCTF_26

VSS_NCTF_27

VSS_NCTF_28

VSS_NCTF_29

VSS_NCTF_30

VSS_NCTF_31

VSS_NCTF_32

A20GATE

RCIN#

THRMTRIP#

INIT3_3V#

DF_TVS

TS_VSS1

TS_VSS2

TS_VSS3

TS_VSS4

SATA_ODD_PWREN

C40

B41

C41

A40

P4

AU16

PECI

P5

AY11

AY10

T14

AY1

AH8

AK11

AH10

AK10

P37

NC_1

R4724
R4725
R4726

PCH_PECI

THRMTRIP#_R

OUT

21

10K_5%_2

21

10K_5%_2_DY

21

10K_5%_2_DY

R4940

21

0_5%_2_DY

BOTH THESE SHOULD BE CLOSE TO PCH

FOLLOW EDS1.0

BG2
BG48
BH3
BH47
BJ4
BJ44A44
BJ45
BJ46
BJ5
BJ6
C2
C48
D1
D49
E1
E49
F1
F49

29B828C6

EC_3S_A20GATE
H_PECI
KBRST#
H_CPUPWRGD

R4941

390_5%_2

P3V3S

R4942

56_5%_2

21

P1V05S

2 1

NV_CLE

IN

OUT

IN

OUT

R4943

0_5%_2_DY

OUT

21E2

21A6 41D5

21D2

41C5

21

41D6

P1V05S

R4944

56_5%_2

2 1

PM_THRMTRIP#

IN

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CHANGE by

DATE

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7052

8 7

REFERENCE 4700~4949(PCH)

6 5

4

3 2 1

P1V05S

C4772

D

10UF_6.3V_3

C4773

1UF_6.3V_2

2 1

C4774

1UF_6.3V_2 1UF_6.3V_2

2 1

2 1

P1V05S

P1V05S

3A

C4776

10UF_6.3V_3

C4777

1UF_6.3V_2 1UF_6.3V_2 1UF_6.3V_2

2 1

C4778

2 1

C4779

2 1

P3V3S

B

C4781

0.1UF_16V_2

2 1

P1V05S

P1V05S

P1V05S

C4780

1UF_6.3V_2

2 1

P1V5S_VCCAFDI_VRM

0_5%_2_DY

C4775

2 1

R4946

1.3A

2 1

R4945

0_5%_2_DY

15MIL

21

P1V05S

20MIL

P1V05S_VCCAPLLEXP

21

15MIL

P1V05S_VCCAFDIPLL

20MIL
15MIL

U4700

AA23

VCCCORE[1]

AC23

VCCCORE[2]

AD21

VCCCORE[3]

AD23

VCCCORE[4]

AF21

VCCCORE[5]

AF23

VCCCORE[6]

AG21

VCCCORE[7]

AG23

VCCCORE[8]

AG24

VCCCORE[9]

AG26

VCCCORE[10]

AG27

VCCCORE[11]

AG29

VCCCORE[12]

AJ23

VCCCORE[13]

AJ26

VCCCORE[14]

AJ27

VCCCORE[15]

AJ29

VCCCORE[16]

AJ31

VCCCORE[17]

AN19

VCCIO[28]

BJ22

VCCAPLLEXP

AN16

VCCIO[15]

AN17

VCCIO[16]

AN21

VCCIO[17]

AN26

VCCIO[18]

AN27

VCCIO[19]

AP21

VCCIO[20]

AP23

VCCIO[21]

AP24

VCCIO[22]

AP26

VCCIO[23]

AT24

VCCIO[24]

AN33

VCCIO[25]

AN34

VCCIO[26]

BH29

VCC3_3[3] VCCDFTERM[2]

AP16

VCCVRM[2]

BG6

VccAFDIPLL

AP17

VCCIO[27]

AU20

VCCDMI[2]

ITL_BD82PPSM_QPJ4_FCBGA_989P

POWER

VCC CORE

VCCIO

FDI

CRT

LVDS

DMI HVCMOS

NAND / SPI

VCCADAC

VSSADAC

VCCALVDS

VSSALVDS

VCCTX_LVDS[1]

VCCTX_LVDS[2]

VCCTX_LVDS[3]

VCCTX_LVDS[4]

VCC3_3[6]

VCC3_3[7]

VCCVRM[3]

VCCDMI[1]

VCCCLKDMI

VCCDFTERM[1]

VCCDFTERM[3]

VCCDFTERM[4]

VCCSPI

U48

U47

AK36
AK37

AM37
AM38
AP36
AP37

15MIL

V33

V34

AT16

AT20

AB36

AG16

AG17

AJ16

AJ17

V1

15MIL

15MIL

15MIL

15MIL

15MIL

15MIL

15MIL

P3V3S_VCCADAC

P3V3S

R4931

0_5%_2

2 1

0_5%_2_DY

15MIL

C4785

R4937

0.01UF_50V_2

2 1

2 1

0_5%_2_DY

P1V5S_VCCAFDI_VRM

C4790

1UF_6.3V_2_DY

P3V3AL P3V3A

21

R4947

0_5%_2_DY

2 1

C4782

22UF_6.3V_5

2 1

R4933

0.1UF_16V_2

P1V05S

21

C4792

1UF_6.3V_2

21

21

2 1

C4788

0_5%_2

C4786

R4948

C4783

0.01UF_50V_2

2 1

21

C4784

0.1UF_16V_2

2 1

P1V8S_VCCTX_LVDS

C4787

22UF_6.3V_50.01UF_50V_2

2 1

C4789

21

1UF_6.3V_2

P1V8S

C4791

0.1UF_16V_2

2 1

L4700

FBM_11_160808_121T

L4701

FBM_11_160808_121T

P1V05S

P3V3S

21

D

P1V8S

21

P3V3S

CC

B

AA

P1V5S_VCCAFDI_VRM P1V5S

R4949

0_5%_3

21

CHANGE by

DATE

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7053

40MIL

8

7 6

5 4

D

B

P1V05S

C4842

0.1UF_16V_2

P1V05S

4.7UF_6.3V_3

8 7

P3V3S

C4801

0.1UF_16V_2

10UF_6.3V_3

2 1

L4706

21

FBM_11_160808_121T

22UF_6.3V_5_DY

L4707

0.1UF_16V_2

2 1

21

C4843

C4824

0.1UF_16V_2

22UF_6.3V_5_DY

2 1

2 1

0.1UF_16V_2

FBM_11_160808_121T

2 1

C4823

8

C4802

2 1

P1V05S

P1V05S

C4808

P1V05S_VCCADPLLA

C4812

C4813

1UF_6.3V_2

2 1

P1V05S_VCCADPLLB

C4815

C4816

1UF_6.3V_2

2 1

P1V05S

C4825

2 1

P3V3A

15MIL

20MIL

P1V05S

P1V05S

20MIL

1UF_6.3V_2_DY

1.1A

C4806

22UF_6.3V_5

C4809

1UF_6.3V_21UF_6.3V_2

C4814

C4817

C4826

0.1UF_16V_2

2 1

2 1

C4818

C4819

C4820

C4821

21

P3V3_RTC

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

2 1

0.1UF_16V_2

2 1

C4827

1UF_6.3V_2

2 1

2 1

10UF_6.3V_3

2 1

10UF_6.3V_3

2 1

C4822

1UF_6.3V_2_DY

7 6

6 5

P1V05S

R4865

0_5%_2_DY

C4803

2 1

0.1UF_16V_2

C4804

2 1

0.1UF_16V_2_DY

R4867

21

P1V05S_VCCAPLLDMI2

0_5%_2_DY

C4805

21

C4807

22UF_6.3V_5

2 1

C4810

1UF_6.3V_2

2 1

2 1

0.1UF_16V_2

P1V5S_VCCAFDI_VRM

15MIL

C4828

0.1UF_16V_2

2 1

21

P1V05S_VCCACLK

C4811

2 1

2 1

R4866

SHORT_0402

15MIL

15MIL

15MIL

20MIL

15MIL

10MIL

U4700

AD49

VCCACLK

21

T16

VCCDSW3_3

V12

DCPSUSBYP

T38

VCC3_3[5]

BH23

VCCAPLLDMI2

AL29

VCCIO[14]

AL24

DCPSUS[3]

AA19

VCCASW[1]

AA21

VCCASW[2]

AA24

VCCASW[3]

AA26

VCCASW[4]

AA27

VCCASW[5]

AA29

VCCASW[6]

AA31

VCCASW[7]

AC26

VCCASW[8]

AC27

VCCASW[9]

AC29

VCCASW[10]

AC31

VCCASW[11]

AD29

VCCASW[12]

AD31

VCCASW[13]

W21

VCCASW[14]

W23

VCCASW[15]

W24

VCCASW[16]

W26

VCCASW[17]

W29

VCCASW[18]

W31

VCCASW[19]

W33

VCCASW[20]

N16

DCPRTC

Y49

VCCVRM[4]

BD47

VCCADPLLA

BF47

VCCADPLLB

AF17

VCCIO[7]

AF33

VCCDIFFCLKN[1]

AF34

VCCDIFFCLKN[2]

AG34

VCCDIFFCLKN[3]

AG33

VCCSSC

V16

DCPSST

T17

DCPSUS[1]

V19

DCPSUS[2]

BJ8

V_PROC_IO

A22

VCCRTC

ITL_BD82PPSM_QPJ4_FCBGA_989P

POWER

Clock and Miscellaneous

CPU

RTC

USB

PCI/GPIO/LPCMISC

SATA

HDA

VCCIO[29]

VCCIO[30]

VCCIO[31]

VCCIO[32]

VCCIO[33]

VCCSUS3_3[7]

VCCSUS3_3[8]

VCCSUS3_3[9]

VCCSUS3_3[10]

VCCSUS3_3[6]

VCCIO[34]

V5REF_SUS

DCPSUS[4]

VCCSUS3_3[1]

V5REF

VCCSUS3_3[2]

VCCSUS3_3[3]

VCCSUS3_3[4]

VCCSUS3_3[5]

VCC3_3[1]

VCC3_3[8]

VCC3_3[4]

VCC3_3[2]

VCCIO[5]

VCCIO[12]

VCCIO[13]

VCCIO[6]

VCCAPLLSATA

VCCVRM[1]

VCCIO[2]

VCCIO[3]

VCCIO[4]

VCCASW[22]

VCCASW[23]

VCCASW[21]

VCCSUSHDA

5 4

4

3A

N26
P26
P28
T27
T29

T23
T24
V23
V24
P24

T26
M26

AN23
AN24

P34

N20
N22
P20
P22

AA16
W16
T34

10MIL

10MIL

20MIL

V5REF_SUS

2 1

10MIL

V5REF

C4836

C4837

3 2 1

C4830

0.1UF_16V_2

C4831

0.1UF_16V_2

C4832

1UF_6.3V_2_DY

C4835

1UF_6.3V_2

2 1

21

21

20MIL

21

21

C4829

1UF_6.3V_2

10MIL

10MIL

21

0.1UF_16V_2

0.1UF_16V_2

P1V05S

P3V3A

P3V3A

P1V05S

P3V3A

10MIL

P3V3A

P3V3S

P3V3S

REFERENCE 4700~4949(PCH)

2

D4708

R4869

C4833

D4709

R4870

21

21

2

NC NC

21

C4834

1UF_6.3V_2

BAT54_30V_0.2A

13

10_5%_5

0.1UF_16V_2

BAT54_30V_0.2A

13

10_5%_5

21

P3V3A

P5V0A

D

P3V3S

P5V0S

CC

P3V3S

AJ2
AF13

AH13
AH14

AF14
AK1

AF11

AC16
AC17
AD17

T21

V21

T19

P32

10MIL

P1V05S_VCCAPLLSATA

P3V3A

2 1

C4838

C4841

0.1UF_16V_2

C4839

1UF_6.3V_2

C4840

1UF_6.3V_2

20MIL

CHANGE by

20MIL

21

0.1UF_16V_2

21

21

L4708

0603_DY

P1V05S

20MIL

21

P1V05S

P1V05S

P1V5S_VCCAFDI_VRM

10MIL

20MIL

DATE

B

P1V05S

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7054

8 7

6 5

4

3 2 1

REFERENCE 4700~4949(PCH)

U4700

H5

VSS[0]

AA17

VSS[1]

AA2

VSS[2]

AA3

VSS[3]

AA33

VSS[4]

AA34

VSS[5]

AB11

VSS[6]

AB14

VSS[7]

AB39

VSS[8]

AB4

VSS[9]

AB43

VSS[10]

D

B

AC19
AC21

AC24
AC33
AC34
AC48
AD10
AD11
AD12
AD13
AD19
AD24
AD26
AD27
AD33
AD34
AD36
AD37
AD38
AD39

AD40
AD42
AD43
AD45
AD46

AF10

AF12
AD14
AD16

AF16

AF19

AF24

AF26

AF27

AF29
AF31

AF38

AF42

AF46

AG19
AG31

AG48
AH11

AH36
AH39
AH40
AH42
AH46

AJ19

AJ21

AJ24

AJ33

AJ34
AK12

AB5
AB7

AC2

AD4

AD8
AE2
AE3

AF4

AF5
AF7
AF8

AG2

AH3

AH7

AK3

VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]

ITL_BD82PPSM_QPJ4_FCBGA_989P

8

7 6

VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]

VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]

AK38
AK4
AK42
AK46
AK8
AL16
AL17
AL19
AL2
AL21
AL23
AL26
AL27
AL31
AL33
AL34
AL48
AM11
AM14
AM36
AM39
AM43
AM45
AM46
AM7
AN2
AN29
AN3
AN31
AP12
AP19
AP28
AP30
AP32
AP38
AP4
AP42
AP46
AP8
AR2
AR48
AT11
AT13
AT18
AT22
AT26
AT28
AT30
AT32
AT34
AT39
AT42
AT46
AT7
AU24
AU30
AV16
AV20
AV24
AV30
AV38
AV4
AV43
AV8
AW14
AW18
AW2
AW22
AW26
AW28
AW32
AW34
AW36
AW40
AW48
AV11
AY12
AY22
AY28

5 4

U4700

AY4

VSS[159]

AY42

VSS[160]

AY46

VSS[161]

AY8

VSS[162]

B11

VSS[163]

B15

VSS[164]

B19

VSS[165]

B23

VSS[166]

B27

VSS[167]

B31

VSS[168]

B35

VSS[169]

B39

VSS[170]

B7

VSS[171]

F45

VSS[172]

BB12

VSS[173]

BB16

VSS[174]

BB20

VSS[175]

BB22

VSS[176]

BB24

VSS[177]

BB28

VSS[178]

BB30

VSS[179]

BB38

VSS[180]

BB4

VSS[181]

BB46

VSS[182]

BC14

VSS[183]

BC18

VSS[184]

BC2

VSS[185]

BC22

VSS[186]

BC26

VSS[187]

BC32

VSS[188]

BC34

VSS[189]

BC36

VSS[190]

BC40

VSS[191]

BC42

VSS[192]

BC48

VSS[193]

BD46

VSS[194]

BD5

VSS[195]

BE22

VSS[196]

BE26

VSS[197]

BE40

VSS[198]

BF10

VSS[199]

BF12

VSS[200]

BF16

VSS[201]

BF20

VSS[202]

BF22

VSS[203]

BF24

VSS[204]

BF26

VSS[205]

BF28

VSS[206]

BD3

VSS[207]

BF30

VSS[208]

BF38

VSS[209]

BF40

VSS[210]

BF8

VSS[211]

BG17

VSS[212]

BG21

VSS[213]

BG33

VSS[214]

BG44

VSS[215]

BG8

VSS[216]

BH11

VSS[217]

BH15

VSS[218]

BH17

VSS[219]

BH19

VSS[220]

H10

VSS[221]

BH27

VSS[222]

BH31

VSS[223]

BH33

VSS[224]

BH35

VSS[225]

BH39

VSS[226]

BH43

VSS[227]

BH7

VSS[228]

D3

VSS[229]

D12

VSS[230]

D16

VSS[231]

D18

VSS[232]

D22

VSS[233]

D24

VSS[234]

D26

VSS[235]

D30

VSS[236]

D32

VSS[237]

D34

VSS[238]

D38

VSS[239]

D42

VSS[240]

D8

VSS[241]

E18

VSS[242]

E26

VSS[243]

G18

VSS[244]

G20

VSS[245]

G26

VSS[246]

G28

VSS[247]

G36

VSS[248]

G48

VSS[249]

H12

VSS[250]

H18

VSS[251]

H22

VSS[252]

H24

VSS[253]

H26

VSS[254]

H30

VSS[255]

H32

VSS[256]

H34

VSS[257]

F3

VSS[258]

ITL_BD82PPSM_QPJ4_FCBGA_989P

CHANGE by

VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[333]
VSS[334]
VSS[335]
VSS[337]
VSS[338]
VSS[340]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]

H46
K18
K26
K39
K46
K7
L18
L2
L20
L26
L28
L36
L48
M12
P16
M18
M22
M24
M30
M32
M34
M38
M4
M42
M46
M8
N18
P30
N47
P11
P18
T33
P40
P43
P47
P7
R2
R48
T12
T31
T37
T4
W34
T46
T47
T8
V11
V17
V26
V27
V29
V31
V36
V39
V43
V7
W17
W19
W2
W27
W48
Y12
Y38
Y4
Y42
Y46
Y8
BG29
N24
AJ3
AD47
B43
BE10
BG41
G14
H16
T36
BG22
BG24
C22
AP13
M14
AP3
AP1
BE16
BC16
BG28
BJ28

DATE

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7055

8

7 6 5 4 3 2 1

P3V3S_DGPU

R5016
R5010
R5011
R5028
R5037
R5014
R5030
R5031
R5027
R5056
R5017

2 1

21
21

21
21
21
21

21

21

21

21

10K_5%_2_DY
10K_5%_2_DY

10K_5%_2_DY
RSC_0402_DY
RSC_0402_DY

10K_5%_2
10K_5%_2
10K_5%_2

10K_5%_2_DY

10K_5%_2
10K_5%_2

GPIO0
GPIO1
GPIO2
GPIO5
GPIO9

GPIO11
VGA_CRT_HSYNC
VGA_CRT_VSYNC

GPIO22

PWRCNTL_0
PWRCNTL_1

56D5

OUT

56D5

OUT

56D5

OUT

56D5

OUT

56D5

OUT
OUT

GPIO11:MEMORY APERTURE SIZE 256M

35B2 56D3

OUT

35B2 56D3

OUT

56C5

OUT

13C6 56D5

OUT

13C6 56C5

OUT

PIN BASE STRAPS

TRANSMITTER POWER SAVING ENABLEGPIO_0

GPIO_1 PCIE TRANSMITTER DE-EMPHASIS 0 : DE-EMPHASIS DISABLED (DEFAULT)

GEN1/GEN2 ENABLE

GPIO_2
GPIO_8

MUST BE LOW DURING RESET

GPIO_21

E

GPIO_9

VGA DISABLE

GPIO_[11:13]

MEMORY APERTURE SIZE

ENABLE EXTERNAL BIOS ROM DEVICE

GPIO_22

HSYNC[1]

AUDIO[1:0]

VSYNC[0]

0 : 50% TX OUTPUT SWING (DEFAULT)
1 : FULL TX OUTPUT SWING

1 : DE-EMPHASIS ENABLED
0 : GEN1 (DEFAULT)

1 : GEN2

LEFT UNCONNECTED

0 : ENABLE (DEFAULT)

1 : DISABLE

GPIO_12

GPIO_13

0
0

0

0

0 : DISABLE (DEFAULT)

1 : ENABLE

00 : NO AUDIO FUNCTION

01 : AUDIO FOR DP ONLY

10 : AUDIO FOR DP AND HDMI IF DONGLE IS DETECTED
11 : AUDIO FOR BOTH DP AND HDMI

GPIO_11

0

0

1

0
1

0

1

1

D

P3V3S_DGPU

1

G

R5094

10K_5%_2

2 1

2

3

EC_SMB2_CLK

5A721D221D337C6

BI

5A721D221D337C3

C

BI

EC_SMB2_DATA

PVPCIE

SSM3K7002BFU

P3V3S_DGPU

3

SSM3K7002BFU

L5005

FBM_11_160808_121T

B

A

8

GPU_SIC

DS

Q5001

1

G

2

DS

Q5002

P1V8S_DGPU

FBM_11_160808_121T

21

C5016

10UF_6.3V_3

P1V8S_DGPU

R5095

10K_5%_2

2 1

GPU_SID

L5004

PVPCIE_DPLL_VDDC

2 1

BI

BI

P1V8S_DPLL_PVDD

21

C5013

10UF_6.3V_3

L5006

FBM_11_160808_121T

10UF_6.3V_3

56D5

56D5

2 1

2 1

21

C5019

7 6 5 4 3

MEMORY APERTURE SIZE

128M
256M

64M
32M

I=75MA TRACE WIDTH>=15MIL

C5011

2 1

1UF_6.3V_2

I=125MA TRACE WIDTH>=15MIL

1UF_6.3V_2

C5015

0.1UF_16V_2

2 1

2 1

C5014

P1V8S_TSVDD

15D840A840B1

P3V3S_DGPU

C5017

1UF_6.3V_2

2 1

P1V8S_DGPU

OUT

SSM3K7002BFU_DY

21

R5061

10K_5%_2

C5012

2 1

10K_5%_2_DY

THRM_SHUTDWN#

Q5000

10K_5%_2

R5005

10K_5%_2_DY

0.1UF_16V_2

C5018

2 1

21

R500821R500721R5006

10K_5%_2_DY

10K_5%_2_DY

34C5

BI

34C5

BI

56F7
56C7
56D7
56F7

21E7

OUT

56F7

56F7

3

DS

G

2

13C6

56F7

R501521R5063

56F7

10K_5%_2

2 1

2 1

P1V8S_DGPU

21

36B5

R5004

499_1%_2

21

R5003

249_1%_2

C5010

I=20MA TRACE WIDTH>=15MIL

0.1UF_16V_2

21

R5009

10K_5%_2_DY

MEM_ID0
MEM_ID1
MEM_ID2
MEM_ID3

VGA_LVDS_DDCCLK
VGA_LVDS_DDCDATA

IN
IN
IN
BI
BI
IN

VGA_LCM_BKLTEN

IN
IN

1

OUT

OUT

IN

1

TP15

TP30

1

TP16

TP30

21

R5060

10K_5%_2

IN

2 1

0.1UF_16V_2

R4

1M_5%_2

X5000

27MHZ

C5211

2 1

27PF_50V_2

GPIO0
GPIO1
GPIO2

GPU_SID
GPU_SIC

GPIO5

GPIO9
GPIO11

PWRCNTL_0

PWRCNTL_1
GPIO22

1
1

1

VGA_HPDET

P0V6S_VREFG

21

21

C5212

TP5000

TP30

MEM_ID3

0

0
0

0
0

U5001

AU24

TXCAP_DPA3P

AV23

TXCAM_DPA3N

AT25

MUTI GFX

AR8

DVPCNTL_MVP_0

AU8

DVPCNTL_MVP_1

AP8

DVPCNTL_0

AW8

DVPCNTL_1

AR3

DVPCNTL_2

AR1

DVPCLK

AU1

DVPDATA_0

AU3

DVPDATA_1

AW3

DVPDATA_2

AP6

DVPDATA_3

AW5

DVPDATA_4

AU5

DVPDATA_5

AR6

DVPDATA_6

AW6

DVPDATA_7

AU6

DVPDATA_8

AT7

DVPDATA_9

AV7

DVPDATA_10

AN7

DVPDATA_11

AV9

DVPDATA_12

AT9

DVPDATA_13

AR10

DVPDATA_14

AW10

DVPDATA_15

AU10

DVPDATA_16

AP10

DVPDATA_17

AV11

DVPDATA_18

AT11

DVPDATA_19

AR12

DVPDATA_20

AW12

DVPDATA_21

AU12

DVPDATA_22

AP12

DVPDATA_23

AJ21

SWAPLOCKA

AK21

SWAPLOCKB

AK26
AJ26

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16

AL16
AM16
AM14
AM13

AK14
AG30

AN14
AM17

AL13

AJ14

AK13

AN13
AM23

TP14

TP30

AN23

AK23

TP11

TP30

AL24
AM24

TP12

TP30

AJ19

AK19

AJ20

AK20

AJ24

AH26

AH24

AK24

AH13

AM32

AN32

AN31

AV33

AU34

AW34
AW35

2 1

27PF_50V_2

AF29
AG29

1

AK32

AL31

AJ32

AJ33

I2C

SCL
SDA

GENERAL PURPOSE I/O

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

HPD1

VREFG

DPLL_PVDD
DPLL_PVSS

PLL/CLOCK

DPLL_VDDC

XTALIN
XTALOUT

XO_IN

XO_IN2

DPLUS

THERMAL

DMINUS

TS_FDO

TS_A/NC

TSVDD
TSVSS

AMD_216_0833002_FCBGA_962P

DPA

DPB

DPC

DPD

DAC1

DAC2

DDC/AUX

TX0P_DPA2P
TX0M_DPA2N

TX1P_DPA1P
TX1M_DPA1N

TX2P_DPA0P
TX2M_DPA0N

TXCBP_DPB3P
TXCBM_DPB3N

TX3P_DPB2P
TX3M_DPB2N

TX4P_DPB1P
TX4M_DPB1N

TX5P_DPB0P
TX5M_DPB0N

TXCCP_DPC3P
TXCCM_DPC3N

TX0P_DPC2P
TX0M_DPC2N

TX1P_DPC1P
TX1M_DPC1N

TX2P_DPC0P
TX2M_DPC0N

TXCDP_DPD3P
TXCDM_DPD3N

TX3P_DPD2P
TX3M_DPD2N

TX4P_DPD1P
TX4M_DPD1N

TX5P_DPD0P
TX5M_DPD0N

COMP/NC

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

VDD2DI/NC
VSS2DI/NC

A2VDD/NC

A2VDDQ/NC

A2VSSQ/TSVSSQ

R2SET/NC

DDC1CLK

DDC1DATA

DDC2CLK

DDC2DATA

DDCCLK_AUX3P

DDCDATA_AUX3N

DDCCLK_AUX4P

DDCDATA_AUX4N

DDCCLK_AUX5P

DDCDATA_AUX5N

DDC6CLK

DDC6DATA

DDCCLK_AUX7P

DDCDATA_AUX7N

AR24
AU26

AV25
AT27

AR26
AR30

AT29
AV31

AU30
AR32

AT31
AT33

AU32
AU14

AV13
AT15

AR14
AU16

AV15
AT17

AR16
AU20

AT19
AT21

AR20
AU22

AV21
AT23

AR22

AD39

R

AD37

RB

AE36

G

AD35

GB

AF37

B

AE38

BB

AC36

HSYNC

AC38

VSYNC

AB34

RSET

AD34

AVDD

AE34

AVSSQ

AC33

VDD1DI

AC34

VSS1DI

AC30

R2/NC

AC31

R2B/NC

AD30

G2/NC

AD31

G2B/NC

AF30

B2/NC

AF31

B2B/NC

AC32

C/NC

AD32

Y/NC

AF32

AD29
AC29

AG31
AG32

AG33
AD33
AF33

AA29

AM26
AN26

AM27

AUX1P

AL27

AUX1N

AM19
AL19

AN20

AUX2P

AM20

AUX2N

AL30
AM30

AL29
AM29

AN21
AM21

AJ30
AJ31

AK30
AK29

THAMES (6019B0917601)

VGA_HDMI_TXC_DP
VGA_HDMI_TXC_DN

VGA_HDMI_TX0_DP
VGA_HDMI_TX0_DN

VGA_HDMI_TX1_DP
VGA_HDMI_TX1_DN

VGA_HDMI_TX2_DP
VGA_HDMI_TX2_DN

VGA_CRTR

VGA_CRTG

VGA_CRTB

VGA_CRT_HSYNC
VGA_CRT_VSYNC

R5000

21

499_1%_2

C5003

0.1UF_16V_2

VGA_HDMI_DDCCLK
VGA_HDMI_DDCDATA

VGA_CRT_DDCCLK
VGA_CRT_DDCDATA

I=100MA TRACE WIDTH>=15MIL

OUT

OUT

OUT

OUT
OUT

2 1

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

36A5

OUT

35D8 56E2

35D8 56E2

35D8 56E2

35B2 56F7
35B2 56F7

36D8

BI

36D8

BI

35A2

BI

35B2

BI

P1V8S_VDD1DI

C5002

1UF_6.3V_2

2 1

I=70MA TRACE WIDTH>=15MIL

L5001

2 1

FBM_11_160808_121T

C5004

10UF_6.3V_3

2 1

0
0
0
0
0
0
1
1
1
1
1
1
1

PLACE CLOSE TO ASIC

VGA_CRTR

35D856D3

IN

VGA_CRTG

35D856D3

IN

VGA_CRTB

35D856D3

IN

P1V8S_AVDD

C5000

C5001

0.1UF_16V_2

1UF_6.3V_2

2 1

2 1

P1V8S_DGPU

0

1
1
1
1

0
0
0

1 0
1

1 11 RESERVE

R5072
R5073
R5074

0
001
1
1
0
0
1
1
00
0
1
1

0
11

150_1%_2

21

150_1%_2

21

150_1%_2

21

2 1

FBM_11_160808_121T

C5005

10UF_6.3V_3

2 1

MEM_ID0MEM_ID1MEM_ID2

0

HYNIX1GDFR*4 512MB
HYNIX2GBFR*4 1GB
HYNIX2GDFR*41GB

1

RESERVE

0

HYNIX1GDFR*8 1GB

1

HYNIX2GBFR*8 2GB

0

HYNIX2GDFR*82GB

1

RESERVE

0

AMDC11*4 512MB

1

AMDA11*4 1GB

0

AMDB11*4 1GB

1

RESERVE

0

AMDC11*8 1HB

1

AMDA11*8 2GB

0

AMDB11*8 2GB

1

L5000

P1V8S_DGPU

FF

E

D

C

B

A

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CHANGE by

XXX 21-OCT-2002

SIZE

DATE

2 1

C CS

CODE

1310xxxxx-0-0

SHEET

of

56 70

REV

X01

D

U5001

LVDS CONTROL

B

LVTMDP

AMD_216_0833002_FCBGA_962P

8 7

DIGON

AK27
AJ27

AK35
AL36

AJ38
AK37

AH35
AJ36

AG38
AH37

AF35
AG36

VGA_LVDS_TXCL_DP

AP34

VGA_LVDS_TXCL_DN

AR34

VGA_LVDS_TXDL0_DP

AW37

VGA_LVDS_TXDL0_DN

AU35

VGA_LVDS_TXDL1_DP

AR37

VGA_LVDS_TXDL1_DN

AU39

VGA_LVDS_TXDL2_DP

AP35

VGA_LVDS_TXDL2_DN

AR35
AN36

AP37

VARY_BL

TXCLK_UP_DPF3P

TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

TXOUT_U3P

TXOUT_U3N

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P

TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P

TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P

TXOUT_L2N_DPE0N

TXOUT_L3P
TXOUT_L3N

8

VGA_INV_PWM_3

VGA_LCM_VDDEN

21

R5071

OUT
OUT

34B5
34D7

10K_5%_2

34A8

BI

34A8

BI

34A8

BI

34A8

BI

34A8

BI

34A8

BI
BI

BI

27C3 21E3

51A8 28C3 27C7

34A8

51C7 51B6

34A8

7 6

6 5

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

PEG_C_TX0_DP
PEG_C_TX0_DN

PEG_C_TX1_DP
PEG_C_TX1_DN

PEG_C_TX2_DP
PEG_C_TX2_DN

PEG_C_TX3_DP
PEG_C_TX3_DN

PEG_C_TX4_DP
PEG_C_TX4_DN

PEG_C_TX5_DP
PEG_C_TX5_DN

PEG_C_TX6_DP
PEG_C_TX6_DN

PEG_C_TX7_DP
PEG_C_TX7_DN

PEG_C_TX8_DP
PEG_C_TX8_DN

PEG_C_TX9_DP
PEG_C_TX9_DN

PEG_C_TX10_DP
PEG_C_TX10_DN

PEG_C_TX11_DP
PEG_C_TX11_DN

PEG_C_TX12_DP
PEG_C_TX12_DN

PEG_C_TX13_DP
PEG_C_TX13_DN

PEG_C_TX14_DP
PEG_C_TX14_DN

PEG_C_TX15_DP
PEG_C_TX15_DN

CLK_PEG_REF_DP
CLK_PEG_REF_DN

R5013

0_5%_2_DY

42B1
42D1

42B1
42D1

42B1
42D1

42B1
42C1

42B1
42C1

42B1
42C1

42B1
42C1

42B1
42C1

42B1
42C1

42B1
42C1

42A1
42C1

42A1
42C1

42A1
42C1

42A1
42C1

42A1
42B1

42A1
42B1

48C3
48C3

P3V3S_DGPU

5

U5005

BUF_PLT_RST#

IN

DGPU_HOLD_RST#

IN

1

2

+

-

TC7SZ08FU

3

U5001

AA38

PCIE_RX0P

Y37

PCIE_RX0N

Y35

PCIE_RX1P

W36

PCIE_RX1N

W38

PCIE_RX2P

V37

PCIE_RX2N

V35

PCIE_RX3P

U36

PCIE_RX3N

U38

PCIE_RX4P

T37

PCIE_RX4N

T35

PCIE_RX5P

R36

PCIE_RX5N

R38

PCIE_RX6P

P37

PCIE_RX6N

P35

PCIE_RX7P

N36

PCIE_RX7N

N38

PCIE_RX8P

M37

PCIE_RX8N

M35

PCIE_RX9P

L36

PCIE_RX9N

L38

PCIE_RX10P

K37

PCIE_RX10N

K35

PCIE_RX11P

J36

PCIE_RX11N

J38

PCIE_RX12P

H37

PCIE_RX12N

H35

PCIE_RX13P

G36

PCIE_RX13N

G38

PCIE_RX14P

F37

PCIE_RX14N

F35

PCIE_RX15P

E37

PCIE_RX15N

CLOCK

PCIE_REFCLKP
PCIE_REFCLKN

PERSTB

AMD_216_0833002_FCBGA_962P

R5039

1K_5%_2

21

4

21

DGPU_PERST

AB35
AA36

AH16

AA30

5 4

4

PCIE_TX0P
PCIE_TX0N

PCIE_TX1P
PCIE_TX1N

PCIE_TX2P
PCIE_TX2N

PCIE_TX3P
PCIE_TX3N

PCIE_TX4P
PCIE_TX4N

PCIE_TX5P
PCIE_TX5N

PCIE_TX6P
PCIE_TX6N

PCIE_TX7P
PCIE_TX7N

PCIE_TX8P

PCI EXPRESS INTERFACE

PCIE_TX8N

PCIE_TX9P
PCIE_TX9N

PCIE_TX10P

PCIE_TX10N

PCIE_TX11P

PCIE_TX11N

PCIE_TX12P

PCIE_TX12N

PCIE_TX13P

PCIE_TX13N

PCIE_TX14P

PCIE_TX14N

PCIE_TX15P

PCIE_TX15N

3 2 1

0.22UF_6.3V_2

Y33
Y32

W33
W32

U33
U32

U30
U29

T33
T32

T30
T29

P33
P32

P30
P29

N33
N32

N30
N29

L33
L32

L30
L29

K33
K32

J33
J32

K30
K29

H33
H32

PEG_RX1_DP
PEG_RX1_DN

PEG_RX3_DP
PEG_RX3_DN

PEG_RX4_DP
PEG_RX4_DN

PEG_RX5_DP
PEG_RX5_DN

PEG_RX6_DP

PEG_RX7_DN

PEG_RX8_DP

C5022
C5023

C5024
C5025

C5026
C5027

C5028
C5029

C5030
C5031

C5032
C5033

C5034
C5035

C5036
C5037

C5038
C5039

C5040
C5041

C5042
C5043

C5044
C5045

C5046
C5047

C5048
C5049

C5050
C5051

C5052
C5053

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

0.22UF_6.3V_2

21
21

0.22UF_6.3V_2

PEG_C_RX0_DPPEG_RX0_DP
PEG_C_RX0_DNPEG_RX0_DN

PEG_C_RX1_DP
PEG_C_RX1_DN

PEG_C_RX2_DPPEG_RX2_DP
PEG_C_RX2_DNPEG_RX2_DN

PEG_C_RX3_DP
PEG_C_RX3_DN

PEG_C_RX4_DP
PEG_C_RX4_DN

PEG_C_RX5_DP
PEG_C_RX5_DN

PEG_C_RX6_DP
PEG_C_RX6_DNPEG_RX6_DN

PEG_C_RX7_DPPEG_RX7_DP
PEG_C_RX7_DN

PEG_C_RX8_DP
PEG_C_RX8_DNPEG_RX8_DN

PEG_C_RX9_DPPEG_RX9_DP
PEG_C_RX9_DNPEG_RX9_DN

PEG_C_RX10_DPPEG_RX10_DP
PEG_C_RX10_DNPEG_RX10_DN

PEG_C_RX11_DPPEG_RX11_DP
PEG_C_RX11_DNPEG_RX11_DN

PEG_C_RX12_DPPEG_RX12_DP
PEG_C_RX12_DNPEG_RX12_DN

PEG_C_RX13_DPPEG_RX13_DP
PEG_C_RX13_DNPEG_RX13_DN

PEG_C_RX14_DPPEG_RX14_DP
PEG_C_RX14_DNPEG_RX14_DN

PEG_C_RX15_DPPEG_RX15_DP
PEG_C_RX15_DNPEG_RX15_DN

42C4

BI

42C4

BI

42C4

BI

42C4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

42C4

BI

42D4

BI

D

CC

B

PVPCIE

CALIBRATION

PCIE_CALRP

PCIE_CALRNPWRGOOD

GPU_PCIE_CALRP

Y30

GPU_PCIE_CALRN

Y29

R5035
R5034

21

1.27K_1%_2

21

2K_1%_2

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CHANGE by

DATE

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7057

8 7

6 5

4

3 2 1

D

P1V5S_DGPU

B

R5053

2 1

R5023

2 1

62D162D5
63D163D5

40.2_1%_2

C5205

100_1%_2

DQA<63..0>

BI

P1V5S_DGPU

R5052

2 1

R5045

2 1

P1V5S_DGPU

2 1

0.1UF_16V_2

40.2_1%_2100_1%_2

C5204

2 1

R5033
R5022
R5058

R5048
R5047
R5050

U5001

MEMORY INTERFACE A

GDDR5/DDR2/GDDR3

DDBIA0_0/QSA_0B/WDQSA_0

DDBIA0_1/QSA_1B/WDQSA_1

DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7

DDR2
GDDR5/GDDR3
DDR3

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9

MAA1_2/MAA_10

MAA1_3/MAA_11

MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0

MAA1_7/MAA_A15_BA1

WCKA0_0/DQMA_0

WCKA0B_0/DQMA_1

WCKA0_1/DQMA_2

WCKA0B_1/DQMA_3

WCKA1_0/DQMA_4

WCKA1B_0/DQMA_5

WCKA1_1/DQMA_6

WCKA1B_1/DQMA_7

EDCA0_0/QSA_0/RDQSA_0

EDCA0_1/QSA_1/RDQSA_1

EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

ADBIA0/ODTA0
ADBIA1/ODTA1

CLKA0

CLKA0B

CLKA1

CLKA1B

RASA0B
RASA1B

CASA0B
CASA1B

CSA0B_0
CSA0B_1

CSA1B_0
CSA1B_1

CKEA0
CKEA1

WEA0B
WEA1B

MAA0_8
MAA1_8

GDDR5

MAA<0>

G24

MAA<1>

J23

MAA<2>

H24

MAA<3>

J24

MAA<4>

H26

MAA<5>

J26

MAA<6>

H21

MAA<7>

G21

MAA<8>

H19

MAA<9>

H20

MAA<10>

L13

MAA<11>

G16

MAA<12>

J16

MAA_BA<2>

H16

MAA_BA<0>

J17

MAA_BA<1>

H17

DQMA<0>

A32

DQMA<1>

C32

DQMA<2>

D23

DQMA<3>

E22

DQMA<4>

C14

DQMA<5>

A14

DQMA<6>

E10

DQMA<7>

D9

DQSA0_DP

C34

DQSA1_DP

D29

DQSA2_DP

D25

DQSA3_DP

E20

DQSA4_DP

E16

DQSA5_DP

E12

DQSA6_DP

J10

DQSA7_DP

D7

DQSA0_DN

A34

DQSA1_DN

E30

DQSA2_DN

E26

DQSA3_DN

C20

DQSA4_DN

C16

DQSA5_DN

C12

DQSA6_DN

J11

DQSA7_DN

F8
J21

G19
H27

G27
J14

H14
K23

K19
K20

K17
K24

K27
M13

K16
K21

J20
K26

L15

H23
J19

ODTA0
ODTA1

CLKA0_DP
CLKA0_DN

CLKA1_DP
CLKA1_DN

RASA0#
RASA1#

CASA0#
CASA1#

CSA0#_0

CSA1#_0

CKEA0
CKEA1

WEA0#
WEA1#

MAA<13>

0
1
2
3
4
5
6
7
8

9
10
11
12

MAA<12..0>

62D4 62D7 63D4 63D8

OUT

62D4 62D7 63D4 63D8

OUT

62D4 62D7 63D4 63D8

OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

62C4 62C7

BI

63C4 63C8

BI

62B3 62D4 62D7

OUT

62B5 62C4

OUT

62C7
63B4 63D4 63D8

OUT

63B5 63C8 63D4

OUT

62C4 62C7

OUT

63C4 63C8

OUT

62C4 62C7

OUT

63C4 63C8

OUT

62C4 62C7

OUT

63C4 63C8

OUT

62C4 62C7

OUT

63C4 63C8

OUT

62C4 62C7

OUT

63C4 63C8

OUT

62D4 62D8

OUT

63D4 63D8

OUT

62C7
62C7
62C4
62C4
63C4
63C4
63C8
63C8

62C7
62C7
62C4
62C4
63C4
63C4
63C8
63C8

62C7
62C7
62C4
62C4
63C4
63C4
63C8
63C8

P1V5S_DGPU

R5020

R5021

BI

P1V5S_DGPU

R5001

R5002

40.2_1%_2

2 1

C5202

100_1%_2

2 1

DQB<63..0>

40.2_1%_2

2 1

100_1%_2

2 1

P3V3S_DGPU

2 1

0.1UF_16V_2

DDR2
GDDR3/GDDR5

DQA<0>

0

DQA<1>

1

DQA<2>

2

DQA<3>

3

DQA<4>

4

DQA<5>

5

DQA<6>

6

DQA<7>

7

DQA<8>

8

DQA<9>

9

DQA<10>

10

DQA<11>

11

DQA<12>

12

DQA<13>

13

DQA<14>

14

DQA<15>

15

DQA<16>

16

DQA<17>

17

DQA<18>

18

DQA<19>

19

DQA<20>

20

DQA<21>

21

DQA<22>

22

DQA<23>

23

DQA<24>

24

DQA<25>

25

DQA<26>

26

DQA<27>

27

DQA<28>

28

DQA<29>

29

DQA<30>

30

DQA<31>

31

DQA<32>

32

DQA<33>

33

DQA<34>

34

DQA<35>

35

DQA<36>

36

DQA<37>

37

DQA<38>

38

DQA<39>

39

DQA<40>

40

DQA<41>

41

DQA<42>

42

DQA<43>

43

DQA<44>

44

DQA<45>

45

DQA<46>

46

DQA<47>

47

DQA<48>

48

DQA<49>

49

DQA<50>

50

DQA<51>

51

DQA<52>

52

DQA<53>

53

DQA<54>

54 54

DQA<55>

55

DQA<56>

56

DQA<57>

57

DQA<58>

58

DQA<59>

59

DQA<60>

60

0.1UF_16V_2

DQA<61>

61

DQA<62>

62

DQA<63>

63

P1V05_REFDA_GPU
P1V05_REFSA_GPU

21
21

RSC_0402_DY

21
21

RSC_0402_DY

21
21

THAMES

R5022 OPEN
R5048 OPEN

SEYMOUR

R5022 STUFF
R5048 STUFF

243_1%_2
243_1%_2

243_1%_2
243_1%_2

AG12

AH12

C37
C35

G32
D33

D31
C30

C28

D27
C26

C24

C22

D21

D19
C18

D17

D15

D13

D11

C10
G13
H13

H11
G10

N12

M12
M27

DDR3

DQA0_0/DQA_0
DQA0_1/DQA_1

A35

DQA0_2/DQA_2

E34

DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5

F32

DQA0_6/DQA_6

E32

DQA0_7/DQA_7
DQA0_8/DQA_8

F30

DQA0_9/DQA_9
DQA0_10/DQA_10

A30

DQA0_11/DQA_11

F28

DQA0_12/DQA_12
DQA0_13/DQA_13

A28

DQA0_14/DQA_14

E28

DQA0_15/DQA_15
DQA0_16/DQA_16

F26

DQA0_17/DQA_17
DQA0_18/DQA_18

A26

DQA0_19/DQA_19

F24

DQA0_20/DQA_20
DQA0_21/DQA_21

A24

DQA0_22/DQA_22

E24

DQA0_23/DQA_23
DQA0_24/DQA_24

A22

DQA0_25/DQA_25

F22

DQA0_26/DQA_26
DQA0_27/DQA_27

A20

DQA0_28/DQA_28

F20

DQA0_29/DQA_29
DQA0_30/DQA_30

E18

DQA0_31/DQA_31
DQA1_0/DQA_32

A18

DQA1_1/DQA_33

F18

DQA1_2/DQA_34
DQA1_3/DQA_35

A16

DQA1_4/DQA_36

F16

DQA1_5/DQA_37
DQA1_6/DQA_38

E14

DQA1_7/DQA_39

F14

DQA1_8/DQA_40
DQA1_9/DQA_41

F12

DQA1_10/DQA_42

A12

DQA1_11/DQA_43
DQA1_12/DQA_44

F10

DQA1_13/DQA_45

A10

DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49

J13

DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52

G8

DQA1_21/DQA_53

K9

DQA1_22/DQA_54

K10

DQA1_23/DQA_55

G9

DQA1_24/DQA_56

A8

DQA1_25/DQA_57

C8

DQA1_26/DQA_58

E8

DQA1_27/DQA_59

A6

DQA1_28/DQA_60

C6

DQA1_29/DQA_61

E6

DQA1_30/DQA_62

A5

DQA1_31/DQA_63

L18

MVREFDA

L20

MVREFSA

L27

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

AMD_216_0833002_FCBGA_962P

C5201

2 1

0.1UF_16V_2

P1V05_REFDB_GPU

P1V05_REFSB_GPU

R5012

5.11K_1%_2_DY

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53

55
56
57
58
59
60
61
62
63

21

R5024

2 1

DQB<0>
DQB<1>
DQB<2>
DQB<3>
DQB<4>
DQB<5>
DQB<6>
DQB<7>
DQB<8>
DQB<9>
DQB<10>
DQB<11>
DQB<12>
DQB<13>
DQB<14>
DQB<15>
DQB<16>
DQB<17>
DQB<18>
DQB<19>
DQB<20>
DQB<21>
DQB<22>
DQB<23>
DQB<24>
DQB<25>
DQB<26>
DQB<27>
DQB<28>
DQB<29>
DQB<30>
DQB<31>
DQB<32>
DQB<33>
DQB<34>
DQB<35>
DQB<36>
DQB<37>
DQB<38>
DQB<39>
DQB<40>
DQB<41>
DQB<42>
DQB<43>
DQB<44>
DQB<45>
DQB<46>
DQB<47>
DQB<48>
DQB<49>
DQB<50>
DQB<51>
DQB<52>
DQB<53>
DQB<54>
DQB<55>
DQB<56>
DQB<57>
DQB<58>
DQB<59>
DQB<60>
DQB<61>
DQB<62>
DQB<63>

1

TP30

1K_5%_2

TP13

U5001

C5

DQB0_0/DQB_0

C3

DQB0_1/DQB_1

E3

DQB0_2/DQB_2

E1

DQB0_3/DQB_3

F1

DQB0_4/DQB_4

F3

DQB0_5/DQB_5

F5

DQB0_6/DQB_6

G4

DQB0_7/DQB_7

H5

DQB0_8/DQB_8

H6

DQB0_9/DQB_9

J4

DQB0_10/DQB_10

K6

DQB0_11/DQB_11

K5

DQB0_12/DQB_12

L4

DQB0_13/DQB_13

M6

DQB0_14/DQB_14

M1

DQB0_15/DQB_15

M3

DQB0_16/DQB_16

M5

DQB0_17/DQB_17

N4

DQB0_18/DQB_18

P6

DQB0_19/DQB_19

P5

DQB0_20/DQB_20

R4

DQB0_21/DQB_21

T6

DQB0_22/DQB_22

T1

DQB0_23/DQB_23

U4

DQB0_24/DQB_24

V6

DQB0_25/DQB_25

V1

DQB0_26/DQB_26

V3

DQB0_27/DQB_27

Y6

DQB0_28/DQB_28

Y1

DQB0_29/DQB_29

Y3

DQB0_30/DQB_30

Y5

DQB0_31/DQB_31

AA4

DQB1_0/DQB_32

AB6

DQB1_1/DQB_33

AB1

DQB1_2/DQB_34

AB3

DQB1_3/DQB_35

AD6

DQB1_4/DQB_36

AD1

DQB1_5/DQB_37

AD3

DQB1_6/DQB_38

AD5

DQB1_7/DQB_39

AF1

DQB1_8/DQB_40

AF3

DQB1_9/DQB_41

AF6

DQB1_10/DQB_42

AG4

DQB1_11/DQB_43

AH5

DQB1_12/DQB_44

AH6

DQB1_13/DQB_45

AJ4

DQB1_14/DQB_46

AK3

DQB1_15/DQB_47

AF8

DQB1_16/DQB_48

AF9

DQB1_17/DQB_49

AG8

DQB1_18/DQB_50

AG7

DQB1_19/DQB_51

AK9

DQB1_20/DQB_52

AL7

DQB1_21/DQB_53

AM8

DQB1_22/DQB_54

AM7

DQB1_23/DQB_55

AK1

DQB1_24/DQB_56

AL4

DQB1_25/DQB_57

AM6

DQB1_26/DQB_58

AM1

DQB1_27/DQB_59

AN4

DQB1_28/DQB_60

AP3

DQB1_29/DQB_61

AP1

DQB1_30/DQB_62

AP5

DQB1_31/DQB_63

Y12

MVREFDB

AA12

MVREFSB

AD28

TESTEN

AK10

CLKTESTA

AL10

CLKTESTB

AMD_216_0833002_FCBGA_962P

DDR2
GDDR3/GDDR5
DDR3

MEMORY INTERFACE B

GDDR5/DDR2/GDDR3

DDR2
GDDR5/GDDR3
DDR3

MAB0_0/MAB_0

MAB0_1/MAB_1

MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9

MAB1_2/MAB_10

MAB1_3/MAB_11

MAB1_4/MAB_12

MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0

WCKB0B_0/DQMB_1

WCKB0_1/DQMB_2

WCKB0B_1/DQMB_3

WCKB1_0/DQMB_4

WCKB1B_0/DQMB_5

WCKB1_1/DQMB_6

WCKB1B_1/DQMB_7

EDCB0_0/QSB_0/RDQSB_0

EDCB0_1/QSB_1/RDQSB_1

EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7

ADBIB0/ODTB0
ADBIB1/ODTB1

CLKB0

CLKB0B

CLKB1

CLKB1B

RASB0B
RASB1B

CASB0B
CASB1B

CSB0B_0

CSB0B_1

CSB1B_0

CSB1B_1

CKEB0

CKEB1

WEB0B
WEB1B

MAB0_8
MAB1_8

GDDR5

DRAM_RST

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7

MAB_BA<2>

AA8

MAB_BA<0>

Y8

MAB_BA<1>

AA9
H3

H1
T3
T5
AE4
AF5
AK6
AK5

DQSB0_DP

F6

DQSB1_DP

K3

DQSB2_DP

P3

DQSB3_DP

V5

DQSB4_DP

AB5

DQSB5_DP

AH1

DQSB6_DP

AJ9

DQSB7_DP

AM5

DQSB0_DN

G7

DQSB1_DN

K1

DQSB2_DN

P1

DQSB3_DN

W4

DQSB4_DN

AC4

DQSB5_DN

AH3

DQSB6_DN

AJ8

DQSB7_DN

AM3
T7

W7
L9

L8
AD8

AD7
T10

Y10
W10

AA10
P10

L10
AD10

AC10
U10

AA11
N10

AB11

T8
W8

AH11

R5025

2 1

MAB<0>
MAB<1>
MAB<2>
MAB<3>
MAB<4>
MAB<5>
MAB<6>
MAB<7>
MAB<8>
MAB<9>
MAB<10>
MAB<11>
MAB<12>

DQMB<0>
DQMB<1>
DQMB<2>
DQMB<3>
DQMB<4>
DQMB<5>
DQMB<6>
DQMB<7>

ODTB0
ODTB1

CLKB0_DP
CLKB0_DN

CLKB1_DP
CLKB1_DN

RASB0#
RASB1#

CASB0#
CASB1#

CSB0#_0

CSB1#_0

MAB<13>

R5029

10_5%_2

5.1K_1%_2

CKEB0
CKEB1

WEB0#
WEB1#

10
11
12

21

C5200

0
1
2
3
4
5
6
7
8
9

2 1

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT
OUT

OUT
OUT

OUT

R5032

51_5%_2

MAB<12..0>

OUT
OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI

120PF_50V_2

65D4
64D4

OUT

64D7
65D8

64D4 64D7 65D4
65D8

64D4 64D7
65D4 65D8

64D4
64D7 65D4 65D8

64C7
64C4
64C4
64C7
65C4
65C4
65C8
65C8

64C7
64C4
64C4
64C7
65C4
65C4
65C8
65C8

64C7
64C4
64C4
64C7
65C4
65C4
65C8
65C8

64C4 64C7
65C4 65C8

64B3 64D4 64D7
64B5 64C4 64C7

65B4 65D4 65D8
65B5 65C8 65D4

64C4 64C7
65C4 65C8

64C4 64C7
65C4 65C8

64C4 64C7

65C4 65C8

64C4 64C7
65C4 65C8

64C4 64C7
65C4 65C8

64D4 64D7 65D4 65D8

VM_RESET

21

OUT

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7058

8

7 6 5 4 3 2 1

FF

AD11
AG10

1UF_6.3V_2

AG26
AG27

AG23
AG24

AG13
AG15

AD12
AF11

AG11

AM10

AN10

AG28

AH29

U5001

AC7

VDDR1#1
VDDR1#2

AF7

VDDR1#3
VDDR1#4

AJ7

VDDR1#5

AK8

VDDR1#6

AL9

VDDR1#7

G11

VDDR1#8

G14

VDDR1#9

G17

VDDR1#10

G20

VDDR1#11

G23

VDDR1#12

G26

VDDR1#13

G29

VDDR1#14

H10

VDDR1#15

J7

VDDR1#16

J9

VDDR1#17

K11

VDDR1#18

K13

VDDR1#19

K8

VDDR1#20

L12

VDDR1#21

L16

VDDR1#22

L21

VDDR1#23

L23

VDDR1#24

L26

VDDR1#25

L7

VDDR1#26

M11

VDDR1#27

N11

VDDR1#28

P7

VDDR1#29

R11

VDDR1#30

U11

VDDR1#31

U7

VDDR1#32

Y11

VDDR1#33

Y7

VDDR1#34

AF26

VDD_CT#1

AF27

VDD_CT#2
VDD_CT#3
VDD_CT#4

AF23

VDDR3#1

AF24

VDDR3#2
VDDR3#3
VDDR3#4

AF13

VDDR4#4

AF15

VDDR4#5
VDDR4#7
VDDR4#8

VDDR4#1
VDDR4#2

AF12

VDDR4#3
VDDR4#6

M20

NC_VDDRHA

M21

NC_VSSRHA

V12

NC_VDDRHB

U12

NC_VSSRHB

H7

MPV18#1

H8

MPV18#2

SPV18

AN9

SPV10

SPVSS

AF28

FB_VDDC

FB_VDDCI

FB_GND

AMD_216_0833002_FCBGA_962P

MEM I/O

LEVEL
TRANSLATION

I/O

PLL

VOLTAGE
SENESE

PCIE

PCIE_VDDR/PCIE_PVDD

CORE

ISOLATED
CORE I/O

POWER

VDDC/BIF_VDDC#33

VDDC/BIF_VDDC#42

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9

PCIE_VDDC#10

PCIE_VDDC#11

PCIE_VDDC#12

VDDC#10

VDDC#11

VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20

VDDC#21

VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30

VDDC#31

VDDC#32

VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40

VDDC#41

VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50

VDDC#51

VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8

VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
VDDCI#15
VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

P1V8S_PCIE_VDDR

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

AA15

VDDC#1

AA17

VDDC#2

AA20

VDDC#3

AA22

VDDC#4

AA24

VDDC#5

AA27

VDDC#6

AB16

VDDC#7

AB18

VDDC#8

AB21

VDDC#9

AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28

PVCORE_DGPU

M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23

C5265

Y26
Y28

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

C5110

2 1

0.01UF_50V_2

C5120

C5119

2 1

2 1

0.1UF_16V_2

0.1UF_16V_2

C5129

C5143

C5147

C5159

C5166

C5266

2 1

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5188

2 1

1UF_6.3V_2

C5167

10UF_6.3V_3

2 1

1.8V_504MA

C5115

C5114

C5113

C5112

C5111

2 1

C5121

2 1

2 1

1UF_6.3V_21UF_6.3V_2

2 1

2 1

1UF_6.3V_2

10UF_6.3V_3

2 1

2 1

2 1

1UF_6.3V_2

0.1UF_16V_2

1UF_6.3V_2

C5130

C5144

C5148

C5160

1UF_6.3V_2

C5123

C5122

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5133

C5132

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5146

C5145

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5151

C5150

2 1

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5163

C5161

10UF_6.3V_3

10UF_6.3V_3

2 1

2 1

2 1

10UF_6.3V_3

C5192

C5191

C5190

C5189

2 1

C5168

2 1

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

C5169

10UF_6.3V_3

10UF_6.3V_3

2 1

10UF_6.3V_3

2 1

2 1

1UF_6.3V_2

PVPCIE

C5126

C5125

C5124

2 1

1UF_6.3V_2

C5134

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

C5152

2 1

1UF_6.3V_2

C5164

10UF_6.3V_3

2 1

10UF_6.3V_3

2 1

2 1

1UF_6.3V_2

C5136

C5135

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5154

C5153

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5165

10UF_6.3V_3

10UF_6.3V_3

2 1

PVCORE_DGPU

C5197

C5195

C5193

2 1

2 1

1UF_6.3V_2

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

L5013

21

BLM18PG600SN1D

PVCORE_DGPU

2 1

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

P1V8S_DGPU

E

D

C

B

P1V5S_DGPU

C5077

2 1

2 1

1UF_6.3V_2

C5080

2 1

1UF_6.3V_2

2 1

1UF_6.3V_2

C5082

C5081

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5084

C5083

2 1

1UF_6.3V_2

1UF_6.3V_2

C5086

C5085

2 1

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

C5079

C5078

E

C5088

C5087

C5089

10UF_6.3V_3

2 1

C5093

10UF_6.3V_3

2 1

P1V8S_DGPU

C5098

L5010

2 1

10UF_6.3V_3

C5094

2 1

2 1

1.8V_110MA

10UF_6.3V_3

2 1

P1V8S_DGPU

D

L5009

FBM_11_160808_121T

21

P3V3S_DGPU

FBM_11_160808_121T

P1V8S_DGPU

L5014

21

C

FBM_11_160808_121T

C5104

2 1

10UF_6.3V_3

C5105

2 1

P1V8S_MPV

C5107

2 1

1UF_6.3V_2

0.1UF_16V_2

PVPCIE

L5016

FBM_11_160808_121T

P1V8S_DGPU

FBM_11_160808_121T

PVPCIE_SPV10

21

L5015

B

C5090

10UF_6.3V_3

2 1

1UF_6.3V_2

21

21

C5091

10UF_6.3V_3

2 1

C5095

2 1

C5099

2 1

C5106

P1V8S_SPV18

C5206

C5209

C5092

10UF_6.3V_3

10UF_6.3V_3

2 1

P1V8S_VDDCT

C5097

C5096

2 1

2 1

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

0.1UF_16V_21UF_6.3V_2

C5101

C5100

2 1

2 1

1UF_6.3V_2

P1V8S_VDDR4

C5108

C5103

C5102

2 1

2 1

1UF_6.3V_2

C5207

2 1

2 1

10UF_6.3V_3

C5210

10UF_6.3V_3

2 1

2 1

2 1

1UF_6.3V_2

0.1UF_16V_2

0.1UF_16V_2

C5208

2 1

1UF_6.3V_2

0.1UF_16V_2

C5213

2 1

2 1

1UF_6.3V_2

0.1UF_16V_2

A

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

1310xxxxx-0-0

CHANGE by

8

7 6 5 4 3

XXX 21-OCT-2002

DATE

2 1

CSC

SHEET

of

59 70

A

REV

X01

8 7

6 5

4

3 2 1

AP20
AP21

AP13

AT13

AN17
AP16

AP17
AW14
AW16

AP22

AP23

AP14

AP15

AN19

AP18

AP19
AW20
AW22

AW18

AH34

AJ34

AL33

AM33

AN34

AP39

AR39

AU37

AF34

AG34

AK33

AK34

AF39
AH39
AK39

AL34
AM34

AM39

U5001

DP C/D POWER

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2

DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP E/F POWER

DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

DPEF_CALR

AMD_216_0833002_FCBGA_962P

DP A/B POWER

DPAB/DPA_VDD18#1

DPAB/DPA_VDD18#2

DPAB/DPA_VDD10#1

DPAB/DPA_VDD10#2

DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

DPAB/DPB_VDD18#1

DPAB/DPB_VDD18#2

DPAB/DPB_VDD10#1

DPAB/DPB_VDD10#2

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DP PLL POWER

DPAB_VDD18/DPA_PVDD

DP_VSSR/DPA_PVSS

DPAB_VDD18/DPB_PVDD

DP_VSSR/DPB_PVSS

DPCD_VDD18/DPC_PVDD

DP_VSSR/DPC_PVSS

DPCD_VDD18/DPD_PVDD

DP_VSSR/DPD_PVSS

DPEF_VDD18/DPE_PVDD

DP_VSSR/DPE_PVSS

DPEF_VDD18/DPF_PVDD

DP_VSSR/DPF_PVSS

DPAB_CALR

AN24
AP24

AP31
AP32

AN27
AP27
AP28
AW24
AW26

AP25
AP26

AN33
AP33

AN29
AP29
AP30
AW30
AW32

AW28

AU28
AV27

AV29
AR28

AU18
AV17

AV19
AR18

AM37
AN38

AL38
AM35

DPAB_VDD18

DPAB_VDD10

R5040

150_1%_2

DPAB_VDD18

DPCD_VDD18

DPEF_VDD18

C5220

2 1

DPAB_VDD18

C5223

2 1

21

L5017

21

BLM18PG600SN1D

C5221

C5222

2 1

2 1

10UF_6.3V_3

1UF_6.3V_2

0.1UF_16V_2

IN

L5018

PVPCIE

21

D

BLM18PG600SN1D

C5225

C5224

2 1

2 1

0.1UF_16V_2

IN

IN

IN

60C3

60C6

60B6

10UF_6.3V_3

1UF_6.3V_2

CC

B

AA

P1V8S_DGPU P1V8S_DGPU

L5019

21

BLM18PG600SN1D

D

C5227

C5226

2 1

10UF_6.3V_3

60B360C6 60B3 60C3

IN

C5228

2 1

1UF_6.3V_2

DPCD_VDD18

DPCD_VDD18

2 1

0.1UF_16V_21UF_6.3V_2

PVPCIE

BLM18PG600SN1D

P1V8S_DGPU

L5021

BLM18PG600SN1D

L5020

21

21

C5232

2 1

10UF_6.3V_3

DPCD_VDD10

C5229

2 1

10UF_6.3V_3

DPEF_VDD18

C5233

2 1

1UF_6.3V_2

C5230

C5231

2 1

2 1

0.1UF_16V_2

R5041

21

150_1%_2

C5234

2 1

0.1UF_16V_2

B

IN

DPEF_VDD18

60B360B6

PVPCIE

L5022

BLM18PG600SN1D

21

C5235

2 1

10UF_6.3V_3

DPEF_VDD10

C5236

2 1

1UF_6.3V_2

C5237

2 1

R5042

150_1%_2

0.1UF_16V_2

21

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7060

8

7 6 5 4 3 2 1

FF

U5001

AB39

PCIE_VSS#1

E39

PCIE_VSS#2

F34

PCIE_VSS#3

F39

PCIE_VSS#4

G33

PCIE_VSS#5

G34

PCIE_VSS#6

H31

PCIE_VSS#7

H34

PCIE_VSS#8

H39

PCIE_VSS#9

J31

PCIE_VSS#10

J34

PCIE_VSS#11

K31

PCIE_VSS#12

K34

PCIE_VSS#13

K39

PCIE_VSS#14

L31

PCIE_VSS#15

L34

E

D

C

B

M34
M39
N31
N34
P31
P34
P39
R34
T31

T34

T39
U31
U34
V34
V39

W31

W34

Y34
Y39

F15

F17

F19
F21

F23

F25

F27

F29
F31

F33

F7
F9
G2
G6
H9

J2

J27

J6
J8

K14

K7

L11

L17

L2
L22
L24

L6

M17
M22
M24
N16
N18

N2
N21
N23
N26

N6
R15
R17

R2
R20
R22
R24
R27

R6
T11

T13
T16
T18

T21

T23

T26
U15
U17

U2
U20
U22
U24
U27

U6
V11
V16
V18
V21
V23
V26

W2

W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

AMD_216_0833002_FCBGA_962P

PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

GND

GND/PX_EN#61

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3

GND#1

A37

GND#2

AA16

GND#3

AA18

GND#4

AA2

GND#5

AA21

GND#6

AA23

GND#7

AA26

GND#8

AA28

GND#9

AA6

GND#10

AB12

GND#11

AB15

GND#12

AB17

GND#13

AB20

GND#14

AB22

GND#15

AB24

GND#16

AB27

GND#17

AC11

GND#18

AC13

GND#19

AC16

GND#20

AC18

GND#21

AC2

GND#22

AC21

GND#23

AC23

GND#24

AC26

GND#25

AC28

GND#26

AC6

GND#27

AD15

GND#28

AD17

GND#29

AD20

GND#30

AD22

GND#31

AD24

GND#32

AD27

GND#33

AD9

GND#34

AE2

GND#35

AE6

GND#36

AF10

GND#37

AF16

GND#38

AF18

GND#39

AF21

GND#40

AG17

GND#41

AG2

GND#42

AG20

GND#43

AG22

GND#44

AG6

GND#45

AG9

GND#46

AH21

GND#47

AJ10

GND#48

AJ11

GND#49

AJ2

GND#50

AJ28

GND#51

AJ6

GND#52

AK11

GND#53

AK31

GND#54

AK7

GND#55

AL11

GND#56

AL14

GND#57

AL17

GND#58

AL2

GND#59

AL20

GND#60

AL21
AL23

GND#62

AL26

GND#63

AL32

GND#64

AL6

GND#65

AL8

GND#66

AM11

GND#67

AM31

GND#68

AM9

GND#69

AN11

GND#70

AN2

GND#71

AN30

GND#72

AN6

GND#73

AN8

GND#74

AP11

GND#75

AP7

GND#76

AP9

GND#77

AR5

GND#78

B11

GND#79

B13

GND#80

B15

GND#81

B17

GND#82

B19

GND#83

B21

GND#84

B23

GND#85

B25

GND#86

B27

GND#87

B29

GND#88

B31

GND#89

B33

GND#90

B7

GND#91

B9

GND#92

C1

GND#93

C39

GND#94

E35

GND#95

E5

GND#96

F11

GND#97

F13

GND#98

A39
AW1
AW39

PX_EN

IN

E

D

C

B

A

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

CODE

SIZE

CHANGE by

8

7 6 5 4 3

XXX 21-OCT-2002

DATE

2 1

C CS

DOC.NUMBER

1310xxxxx-0-0

SHEET

of

61 70

A

REV

X01

D

B

62D7

IN

P1V5S_DGPU

8 7

62A8
62A7 62B2

58A558D462D463D463D8

VRAM_VREFC_A<0>

IN

VRAM_VREFD_A<3>

IN

MAA<13..0>

BI

58D562D463D463D8
58D562D463D463D8
58D562D463D463D8

58C5
58C5

58D5
58D5

58C5
58C5

58B562B362D4
58B562B562C4
58B562C4

58C562C4
58B562C4
58B562C4
58B562C4
58A562C4

58A162C463C463C864C464C765C465C8

MAA_BA<0>

BI

MAA_BA<1>

BI

MAA_BA<2>

BI

CLKA0_DP

IN

CLKA0_DN

IN

CKEA0

IN

ODTA0

IN

CSA0#_0

IN

RASA0#

IN

CASA0#

IN

WEA0#

IN

DQSA0_DP
DQSA1_DP

BI BI

DQMA<0>
DQMA<1>

BI BI

DQSA0_DN

BI

DQSA1_DN

BI BI

IN

P1V5S_DGPU

21

R5500

VRAM_VREFC_A<0>

C5500

2 1

21

R5501

0.1uF_16V_2

VM_RESET

4.99K_1%_2

4.99K_1%_2

MAA<0>

0

MAA<1>

1

MAA<2>

2

MAA<3>

3

MAA<4>

4

MAA<5>

5

MAA<6>

6

MAA<7>

7

MAA<8>

8

MAA<9>

9

MAA<10>

10

MAA<11>

11

MAA<12>

12

MAA<13>

13

U5500

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

R5509

RESET

L9

21

ZQ_ZQ0

243_1%_2

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

NC_ZQ1

A1

NC

A11

NC

SAM_K4B1G1646D_HCF7_FBGA_100P

62D7

VRAM_VREFD_A<3>

IN

6 5

E4

DQA<3>

DQL0

F8

DQA<0>

DQL1

F3

DQA<4>

DQL2

F9

DQA<2>

DQL3

H4

DQA<6>

DQL4

H9

DQA<1>

DQL5

G3

DQA<5>

DQL6

H8

DQA<7>

DQL7

D8

DQA<12>

DQU0

C4

DQA<13>

DQU1

C9

DQA<9>

DQU2

C3

DQA<15>

DQU3

A8

DQA<10>

DQU4

A3

DQA<14>

DQU5

B9

DQA<8>

DQU6

A4

DQA<11>

DQU7

B3

VDD#B3

D10

VDD#D10

G8

VDD#G8

K3

VDD#K3

K9

VDD#K9

N2

VDD#N2

N10

VDD#N10

R2

VDD#R2

VDD#R10

VDDQ#A2
VDDQ#A9
VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2
VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4
VSS#E2
VSS#G9
VSS#J3
VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2
VSSQ#D9
VSSQ#E3
VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

R10
A2

A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

T1

NC

T11

NC

P1V5S_DGPU

58B562C4
62C7

P1V5S_DGPU

21

R5502

4.99K_1%_2

21

C5501

2 1

R5503

0.1uF_16V_2

4.99K_1%_2

4

58D8

BI

58D8

BI BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI

58D8

BI
BI

IN

P1V5S_DGPU

CLKA0_DN

58D8

THAMES: 40OHM
SEYMOUR: 56OHM

(60130B5600ZT)

R5540

40.2_1%_2

21

40.2_1%_2

R5541

62B4

58A558D462D863D463D8

CLKA0_DP

21

VRAM_VREFC_A<2>

IN

VRAM_VREFD_A<1>

IN

MAA<13..0>

BI

58D562D763D463D8

BI

58D562D763D463D8

BI

58D562D763D463D8

BI

58B562B362D7

IN

58B562B562C7

IN

58B562C7

IN

58C562C7

IN

58B562C7

IN

58B562C7

IN

58B562C7

IN

58A562C7

IN

58C5

BIBI

58C5

58D5

BIBI

58D5

58C5

BI

58C5

58A162C763C463C864C464C765C465C8

IN

58B5 62D4

IN

62D7

C5516

2 1

0.01UF_50V_2

VRAM_VREFC_A<2>

IN

C5502

2 1

3 2 1

U5501

MAA_BA<0>
MAA_BA<1>
MAA_BA<2>

CLKA0_DP
CLKA0_DN
CKEA0

ODTA0
CSA0#_0
RASA0#
CASA0#
WEA0#

DQSA3_DP
DQSA2_DP

DQMA<3>
DQMA<2>

DQSA3_DN
DQSA2_DN

VM_RESET

P1V5S_DGPU

MAA<0>

0

MAA<1>

1

MAA<2>

2

MAA<3>

3

MAA<4>

4

MAA<5>

5

MAA<6>

6

MAA<7>

7

MAA<8>

8

MAA<9>

9

MAA<10>

10

MAA<11>

11

MAA<12>

12

MAA<13>

13

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

R5508

RESET

L9

21

ZQ_ZQ0

243_1%_2

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

NC_ZQ1

A1

NC

A11

NC

SAM_K4B1G1646D_HCF7_FBGA_100P

DQU1

VDD#B3

VDD#D10

VDD#G8
VDD#K3
VDD#K9
VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2
VDDQ#A9
VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2

VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4
VSS#E2
VSS#G9

VSS#J3
VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2
VSSQ#D9
VSSQ#E3
VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0

DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E4

DQA<26>

F8

DQA<31>

F3

DQA<29>

F9

DQA<25>

H4

DQA<24>

H9

DQA<28>

G3

DQA<27>

H8

DQA<30>

D8

DQA<19>

C4

DQA<18>

C9

DQA<21>

C3

DQA<16>

A8

DQA<23>

A3

DQA<17>

B9

DQA<22>

A4

DQA<20>

B3
D10
G8
K3
K9
N2
N10
R2
R10

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

T1

NC

T11

NC

21

R5504

4.99K_1%_24.99K_1%_2

21

62D462D4

R5505

0.1uF_16V_2

VRAM_VREFD_A<1>

IN

C5503

2 1

P1V5S_DGPU

P1V5S_DGPU

21

R5506

21

R5507

0.1uF_16V_2

P1V5S_DGPU

BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

4.99K_1%_24.99K_1%_2

58D8
58D8
58D8
58D8
58D8
58D8
58D8
58D8

58D8
58D8
58D8
58D8
58D8
58D8
58D8

P1V5S_DGPU

58D8

D

CC

B

AA

C5520

2 1

C5521

1UF_6.3V_2

2 1

C5522

1UF_6.3V_2

2 1

C5523

1UF_6.3V_2

2 1

8

C5524

1UF_6.3V_2

2 1

7 6

C5525

1UF_6.3V_2

C5526

2 1

2.2UF_6.3V_2

C5527

10UF_6.3V_310UF_6.3V_3

2 1

2 1

C5528

2 1

C5529

1UF_6.3V_2

2 1

C5530

1UF_6.3V_2

2 1

C5531

1UF_6.3V_2

2 1

C5532

1UF_6.3V_2

CHANGE by

5 4

C5533

2 1

1UF_6.3V_2

C5534

10UF_6.3V_310UF_6.3V_3

2 1

DATE

2 1

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

7062

1

REV

X011310xxxxx-0-0

8 7

63A8
63A6

58A558D462D462D863D4

D

VRAM_VREFC_A<4>

IN

VRAM_VREFD_A<7>

IN

MAA<13..0>

BI

58D562D462D763D4

BI

58D562D462D763D4

BI

58D562D462D763D4

BI

58B563B463D4

IN

58B563B563D4

IN

58B563C4

IN

58B563C4

IN

58B563C4

IN

58B563C4

IN

58B563C4

IN

58A563C4

IN

58C5

BI

58C5

BI

58C5

BI

58C5

BI

58C5

BI

58C5

BI

58A162C462C763C464C464C7

IN

65C465C8

MAA_BA<0>
MAA_BA<1>
MAA_BA<2>

CLKA1_DP
CLKA1_DN
CKEA1

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

DQSA6_DP
DQSA7_DP

DQMA<6>
DQMA<7>

DQSA6_DN
DQSA7_DN

VM_RESET

MAA<0>

0

MAA<1>

1

MAA<2>

2

MAA<3>

3

MAA<4>

4

MAA<5>

5

MAA<6>

6

MAA<7>

7

MAA<8>

8

MAA<9>

9

MAA<10>

10

MAA<11>

11

MAA<12>

12

MAA<13>

13

R5519

243_1%_2

B

P1V5S_DGPU

21

63D8 63D8

IN

VRAM_VREFC_A<4>

P1V5S_DGPU

R5510

4.99K_1%_2

21

R5511

C5504

2 1

4.99K_1%_2

0.1uF_16V_2

U5502

M9

VREFCA
VREFDQ

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
A14
A15_BA3

BA0
BA1
BA2

CK
CK
CKE_CKE0

ODT
CS
RAS
CAS
WE

DQSL
DQSU

DML
DMU

DQSL
DQSU

RESET

ZQ_ZQ0

NC_ODT
NC_CSI
NC_CE1
NC_ZQ1

NC
NC

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

DQU0

DQU1

DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3

VDD#D10

VDD#G8
VDD#K3
VDD#K9
VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2
VDDQ#A9
VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2
VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4
VSS#E2
VSS#G9

VSS#J3
VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2
VSSQ#D9
VSSQ#E3
VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

NC
NC

H2
N4

P8
P4
N3
P9
P3
R9
R3
T9
R4
L8
R8
N8
T4
T8

M8
M3

N9

M4

J8

K8

K10

K2
L3

J4
K4
L4

F4
C8

E8
D4

G4

B8

T3
L9

21

J2
L2

J10

L10

A1

A11

SAM_K4B1G1646D_HCF7_FBGA_100P

IN

6 5

E4

DQA<54>

F8

DQA<51>

F3

DQA<53>

F9

DQA<49>

H4

DQA<52>

H9

DQA<50>

G3

DQA<55>

H8

DQA<48>

D8

DQA<62>

C4

DQA<60>

C9

DQA<58>

C3

DQA<61>

A8

DQA<59>

A3

DQA<57>

B9

DQA<56>

A4

DQA<63>

B3
D10
G8
K3
K9
N2
N10
R2
R10

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

T1
T11

P1V5S_DGPU

58B563C8
63D4

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

IN

P1V5S_DGPU

21

VRAM_VREFD_A<7>

R5512

21

C5505

R5513

2 1

0.1uF_16V_2

58D8
58D8
58D8
58D8
58D8
58D8
58D8
58D8

58D8
58D8
58D8
58D8
58D8
58D8
58D8

P1V5S_DGPU

4.99K_1%_2 4.99K_1%_2

4

VRAM_VREFC_A<6>

IN

VRAM_VREFD_A<5>

IN

MAA<13..0>

BI

58D562D462D763D8

BI

58D562D462D763D8

BI

58D562D462D763D8

BI

58B563B463D8

IN

58B563B563C8

IN

58B563C8

IN

58B563C8

IN

58B563C8

IN

58B563C8

IN

58B563C8

IN

58A563C8

IN

58C5

BI

58C5

BI

58D5

BI

58C5

BI

58C5

BI

58C5

BI

58A162C462C763C864C464C765C465C8

IN

58B5 63D4

IN

63D8

MAA_BA<0>
MAA_BA<1>
MAA_BA<2>

CLKA1_DP
CLKA1_DN
CKEA1

ODTA1
CSA1#_0
RASA1#
CASA1#
WEA1#

DQSA4_DP
DQSA5_DP

DQMA<4>
DQMA<5>

DQSA4_DN
DQSA5_DN

VM_RESET

58D8

THAMES: 40 OHM
SEYMOUR: 56 OHM

(60130B5600ZT)

R5542

R5543

21

40.2_1%_240.2_1%_2

63A4
63A3

58A558D462D462D863D8

CLKA1_DPCLKA1_DN

21

C5517

2 1

0.01UF_50V_2

P1V5S_DGPU P1V5S_DGPU

21

63D4 63D4

VRAM_VREFC_A<6>

IN

C5506

P1V5S_DGPU

R5514

21

R5515

2 1

0.1uF_16V_2

3 2 1

U5503

0
1
2
3
4
5
6
7
8
9
10
11
12
13

MAA<0>
MAA<1>
MAA<2>
MAA<3>
MAA<4>
MAA<5>
MAA<6>
MAA<7>
MAA<8>
MAA<9>
MAA<10>
MAA<11>
MAA<12>
MAA<13>

R5518

243_1%_2

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

21

ZQ_ZQ0

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

NC_ZQ1

A1

NC

A11

NC

DQL1

DQU0

DQU1

DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3

VDD#D10

VDD#G8
VDD#K3
VDD#K9
VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2
VDDQ#A9
VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2
VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4
VSS#E2

VSS#G9

VSS#J3
VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2
VSSQ#D9
VSSQ#E3
VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

E4

DQA<35>

DQL0

F8

DQA<38>

F3

DQA<33>

DQL2

F9

DQA<39>

DQL3

H4

DQA<32>

DQL4

H9

DQA<37>

DQL5

G3

DQA<34>

DQL6

H8

DQA<36>

DQL7

D8

DQA<44>

C4

DQA<43>

C9

DQA<47>

C3

DQA<42>

A8

DQA<46>

A3

DQA<40>

B9

DQA<45>

A4

DQA<41>

B3
D10
G8
K3
K9
N2
N10
R2
R10

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

T1

NC

T11

NC

P1V5S_DGPU

SAM_K4B1G1646D_HCF7_FBGA_100P

21

VRAM_VREFD_A<5>

IN

C5507

4.99K_1%_24.99K_1%_2

R5516

21

R5517

2 1

0.1uF_16V_2

4.99K_1%_24.99K_1%_2

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

58D8
58D8
58D8
58D8
58D8
58D8
58D8
58D8

58D8
58D8
58D8
58D8
58D8
58D8
58D8

P1V5S_DGPU

58D8

D

CC

B

AA

10UF_6.3V_3

2 1

1UF_6.3V_2

DATE

C5548

21-OCT-2002XXX

23

C5535

2 1

C5536

1UF_6.3V_2

2 1

8

C5537

1UF_6.3V_2

2 1

C5538

1UF_6.3V_2

2 1

C5539

1UF_6.3V_2

2 1

C5540

1UF_6.3V_2

2 1

7 6

C5541

10UF_6.3V_3 10UF_6.3V_3

2.2UF_6.3V_2

C5542

2 1

2 1

2 1

5 4

C5543

C5544

1UF_6.3V_2

2 1

C5545

1UF_6.3V_2

2 1

CHANGE by

C5546

1UF_6.3V_2

2 1

C5547

1UF_6.3V_2

2 1

C5549

10UF_6.3V_3

2 1

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

REV

of

X011310xxxxx-0-0

7063

1

D

B

64D7

IN

P1V5S_DGPU

8 7

64A8
64A7

58A158D164D465D465D8

VRAM_VREFC_B<0>

IN

VRAM_VREFD_B<3>

IN

MAB<13..0>

BI

58D164D465D465D8

BI

58D164D465D465D8

BI

58D164D465D465D8

BI

58B164B364D4

IN

58B164B564C4

IN

58B164C4

IN

58C164C4

IN

58B164C4

IN

58B164C4

IN

58B164C4

IN

58A164C4

IN

58C1

BI

58C1

BI

58D1

BI

58D1

BI

58C1

BI

58C1

BI

58A162C462C763C463C864C465C465C8

IN

DQSB3_DP
DQSB0_DP

DQMB<3>
DQMB<0>

DQSB3_DN
DQSB0_DN

P1V5S_DGPU

21

R5520

VRAM_VREFC_B<0>

C5508

2 1

21

R5521

0.1uF_16V_2

0
2

3
4
5
6
7
8
9

MAB_BA<0>
MAB_BA<1>
MAB_BA<2>

CLKB0_DP
CLKB0_DN
CKEB0

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

VM_RESET

4.99K_1%_2

4.99K_1%_2

MAB<0>
MAB<1>

1

MAB<2>
MAB<3>
MAB<4>
MAB<5>
MAB<6>
MAB<7>
MAB<8>
MAB<9>
MAB<10>

10

MAB<11>

11

MAB<12>

12

MAB<13>

13

U5504

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

R5529

RESET

L9

21

ZQ_ZQ0

243_1%_2

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

NC_ZQ1

A1

NC

A11

NC

SAM_K4B1G1646D_HCF7_FBGA_100P

64D7

VRAM_VREFD_B<3>

IN

6 5

E4

DQB<26>

DQL0

F8

DQB<24>

DQL1

F3

DQB<29>

DQL2

F9

DQB<31>

DQL3

H4

DQB<28>

DQL4

H9

DQB<25>

DQL5

G3

DQB<30>

DQL6

H8

DQB<27>

DQL7

D8

DQB<6>

DQU0

C4

DQB<3>

DQU1

C9

DQB<2>

DQU2

C3

DQB<7>

DQU3

A8

DQB<1>

DQU4

A3

DQB<4>

DQU5

B9

DQB<0>

DQU6

A4

DQB<5>

DQU7

B3

VDD#B3

D10

VDD#D10

G8

VDD#G8

K3

VDD#K3

K9

VDD#K9

N2

VDD#N2

N10

VDD#N10

R2

VDD#R2

VDD#R10

VDDQ#A2
VDDQ#A9
VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2
VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4
VSS#E2
VSS#G9
VSS#J3
VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2
VSSQ#D9
VSSQ#E3
VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

R10
A2

A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

T1

NC

T11

NC

P1V5S_DGPU

58B164C4
64C7

P1V5S_DGPU

21

R5522

21

C5509

2 1

R5523

0.1uF_16V_2

4.99K_1%_2 4.99K_1%_2

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

IN

58D4
58D4
58D4
58D4
58D4
58D4
58D4
58D4

58D4
58D4
58D4
58D4
58D4
58D4
58D4

P1V5S_DGPU

4

VRAM_VREFC_B<2>

IN

VRAM_VREFD_B<1>

IN

MAB<13..0>

BI

58D164D765D465D8

BI

58D164D765D465D8

BI

58D164D765D465D8

BI

58B164B364D7

IN

58B164B564C7

IN

58B164C7

IN

58C164C7

IN

58B164C7

IN

58B164C7

IN

58B164C7

IN

58A164C7

IN

58C1

BI

58C1

BI

58D1

BI

58D1

BI

58C1

BI

58C1

BI

58A162C462C763C463C864C765C465C8

IN

58B1 64D4

IN

64D7

MAB_BA<0>
MAB_BA<1>
MAB_BA<2>

CLKB0_DP
CLKB0_DN
CKEB0

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

DQSB1_DP
DQSB2_DP

DQMB<1>
DQMB<2>

DQSB1_DN
DQSB2_DN

58D4

THAMES: 40 OHM
SEYMOUR: 56 OHM

(60130B5600ZT)

R5544

40.2_1%_2

21

40.2_1%_2

R5545

64B4
64B2

58A158D164D765D465D8

CLKB0_DPCLKB0_DN

21

C5518

2 1

0.01UF_50V_2

64D4 64D4

VRAM_VREFC_B<2>

IN

C5510

2 1

0.1uF_16V_2

P1V5S_DGPU

3 2 1

U5505

MAB<0>

0

MAB<1>

1

MAB<2>

2

MAB<3>

3

MAB<4>

4

MAB<5>

5

MAB<6>

6

MAB<7>

7

MAB<8>

8

MAB<9>

9

MAB<10>

10

MAB<11>

11

MAB<12>

12

MAB<13>

13

VM_RESET

243_1%_2

P1V5S_DGPU

21

R5524

21

R5525

4.99K_1%_2 4.99K_1%_2

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

R5528

RESET

L9

21

ZQ_ZQ0

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

NC_ZQ1

A1

NC

A11

NC

SAM_K4B1G1646D_HCF7_FBGA_100P

IN

E4

DQB<10>

DQL0

F8

DQB<12>

DQL1

F3

DQB<9>

DQL2

F9

DQB<14>

DQL3

H4

DQB<13>

DQL4

H9

DQB<11>

DQL5

G3

DQB<8>

DQL6

H8

DQB<15>

DQL7

D8

DQB<20>

DQU0

C4

DQB<19>

DQU1

C9

DQB<23>

DQU2

C3

DQB<16>

DQU3

A8

DQB<21>

DQU4

A3

DQB<17>

DQU5

B9

DQB<22>

DQU6

A4

DQB<18>

DQU7

B3

VDD#B3

D10

VDD#D10

G8

VDD#G8

K3

VDD#K3

K9

VDD#K9

N2

VDD#N2

N10

VDD#N10

R2

VDD#R2

R10

VDD#R10

A2

VDDQ#A2

A9

VDDQ#A9

C2

VDDQ#C2

C10

VDDQ#C10

D3

VDDQ#D3

E10

VDDQ#E10

F2

VDDQ#F2

H3

VDDQ#H3

H10

VDDQ#H10

A10

VSS#A10

B4

VSS#B4

E2

VSS#E2

G9

VSS#G9

J3

VSS#J3

J9

VSS#J9

M2

VSS#M2

M10

VSS#M10

P2

VSS#P2

P10

VSS#P10

T2

VSS#T2

T10

VSS#T10

B2

VSSQ#B2

B10

VSSQ#B10

D2

VSSQ#D2

D9

VSSQ#D9

E3

VSSQ#E3

E9

VSSQ#E9

F10

VSSQ#F10

G2

VSSQ#G2

G10

VSSQ#G10

T1

NC

T11

NC

VRAM_VREFD_B<1>

C5511

2 1

0.1uF_16V_2

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

P1V5S_DGPU

P1V5S_DGPU

21

R5526

21

R5527

4.99K_1%_24.99K_1%_2

58D4
58D4
58D4
58D4
58D4
58D4
58D4
58D4

58D4
58D4
58D4
58D4
58D4
58D4
58D4

P1V5S_DGPU

D

CC

B

AA

C5550

2 1

C5551

1UF_6.3V_2

2 1

C5552

1UF_6.3V_2

2 1

C5553

1UF_6.3V_2

2 1

8

C5554

1UF_6.3V_2

2 1

7 6

C5555

1UF_6.3V_2

C5556

10UF_6.3V_3 10UF_6.3V_3

2 1

2.2UF_6.3V_2

C5557

2 1

2 1

C5558

2 1

C5559

1UF_6.3V_2

2 1

C5560

1UF_6.3V_2

2 1

C5561

1UF_6.3V_2

2 1

C5562

1UF_6.3V_2

CHANGE by

5 4

10UF_6.3V_3

2 1

1UF_6.3V_2

C5563

10UF_6.3V_3

2 1

C5564

DATE

2 1

21-OCT-2002XXX

23

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

of

7064

1

REV

X011310xxxxx-0-0

8 7

U5506

65A8
65A6

58A158D164D464D765D4

D

VRAM_VREFC_B<4>

IN

VRAM_VREFD_B<7>

IN

MAB<13..0>

BI

58D164D464D765D4

BI

58D164D464D765D4

BI

58D164D464D765D4

BI

58B165B465D4

IN

58B165B565D4

IN

58B165C4

IN

58B165C4

IN

58B165C4

IN

58B165C4

IN

58B165C4

IN

58A165C4

IN

58C1

BI

58C1

BI

58C1

BI

58C1

BI

58C1

BI

58C1

BI

58A162C462C763C463C864C4

IN

64C765C4

MAB_BA<0>
MAB_BA<1>
MAB_BA<2>

CLKB1_DP
CLKB1_DN
CKEB1

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

DQSB6_DP
DQSB7_DP

DQMB<6>
DQMB<7>

DQSB6_DN
DQSB7_DN

VM_RESET

0

1
2
3
4
5
6
7
8
9

10

11

12

13

MAB<0>
MAB<1>
MAB<2>
MAB<3>
MAB<4>
MAB<5>
MAB<6>
MAB<7>
MAB<8>
MAB<9>
MAB<10>
MAB<11>
MAB<12>
MAB<13>

R5539

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

21

ZQ_ZQ0

243_1%_2

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

A11

NC_ZQ1

A1

NC
NC

B

SAM_K4B1G1646D_HCF7_FBGA_100P

P1V5S_DGPU P1V5S_DGPU

21

VRAM_VREFC_B<4>

P1V5S_DGPU

R5530

4.99K_1%_24.99K_1%_2

21

R5531

C5512

2 1

0.1UF_16V_2

65D865D8

6 5

E4

DQB<55>

DQL0

F8

DQB<54>

DQL1

F3

DQB<51>

DQL2

F9

DQB<52>

DQL3

H4

DQB<48>

DQL4

H9

DQB<53>

DQL5

G3

DQB<49>

DQL6

H8

DQB<50>

DQL7

D8

DQB<59>

DQU0

C4

DQB<63>

DQU1

C9

DQB<62>

DQU2

C3

DQB<58>

DQU3

A8

DQB<60>

DQU4

A3

DQB<56>

DQU5

B9

DQB<61>

DQU6

A4

DQB<57>

DQU7

B3

VDD#B3

D10

VDD#D10

G8

VDD#G8

K3

VDD#K3

K9

VDD#K9

N2

VDD#N2

N10

VDD#N10

R2

VDD#R2

R10

VDD#R10

A2

VDDQ#A2

A9

VDDQ#A9

C2

VDDQ#C2

C10

VDDQ#C10

D3

VDDQ#D3

E10

VDDQ#E10

F2

VDDQ#F2

H3

VDDQ#H3

H10

VDDQ#H10

A10

VSS#A10

B4

VSS#B4

E2

VSS#E2

G9

VSS#G9

J3

VSS#J3

J9

VSS#J9

M2

VSS#M2

M10

VSS#M10

P2

VSS#P2

P10

VSS#P10

T2

VSS#T2

T10

VSS#T10

B2

VSSQ#B2

B10

VSSQ#B10

D2

VSSQ#D2

D9

VSSQ#D9

E3

VSSQ#E3

E9

VSSQ#E9

F10

VSSQ#F10

G2

VSSQ#G2

G10

VSSQ#G10

T1

NC

T11

NC

VRAM_VREFD_B<7>

ININ

58B165C8
65D4

C5513

2 1

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI

58D4

BI
BI

P1V5S_DGPU

58D4

P1V5S_DGPU

THAMES: 40 OHM
SEYMOUR: 56 OHM

(60130B5600ZT)

CLKB1_DN CLKB1_DP

IN

R5546

21

C5519

2 1

21

R5532

4.99K_1%_24.99K_1%_2

21

R5533

0.1UF_16V_2

R5547

21

40.2_1%_240.2_1%_2

0.01UF_50V_2

VRAM_VREFC_B<6>

IN

4

65A4

IN

65A3

IN

58A158D164D464D765D8

BI

58D164D464D765D8
58D164D464D765D8
58D164D464D765D8

58B165B465D8
58B165B565C8
58B165C8

58B165C8
58B165C8
58B165C8
58B165C8
58A165C8

58C1
58C1

58D1
58C1

58C1
58C1

58A162C462C763C463C864C464C765C8

P1V5S_DGPU

VRAM_VREFC_B<6>
VRAM_VREFD_B<5>

MAB<13..0>

MAB_BA<0>

BI

MAB_BA<1>

BI

MAB_BA<2>

BI

CLKB1_DP

IN

CLKB1_DN

IN

CKEB1

IN

ODTB1

IN

CSB1#_0

IN

RASB1#

IN

CASB1#

IN

WEB1#

IN

DQSB4_DP

BI

DQSB5_DP

BI

DQMB<4>

BI

DQMB<5>

BI

DQSB4_DN

BI

DQSB5_DN

BI

VM_RESET

IN

58B1 65D4

IN

65D8

P1V5S_DGPU P1V5S_DGPU

21

R5534

21

C5514

R5535

2 1

0.1UF_16V_2

3 2 1

U5507

0
1
2
3
4
5
6
7
8
9
10
11
12
13

MAB<0>
MAB<1>
MAB<2>
MAB<3>
MAB<4>
MAB<5>
MAB<6>
MAB<7>
MAB<8>
MAB<9>
MAB<10>
MAB<11>
MAB<12>
MAB<13>

R5538

243_1%_2

M9

VREFCA

H2

VREFDQ

N4

A0

P8

A1

P4

A2

N3

A3

P9

A4

P3

A5

R9

A6

R3

A7

T9

A8

R4

A9

L8

A10_AP

R8

A11

N8

A12

T4

A13

T8

A14

M8

A15_BA3

M3

BA0

N9

BA1

M4

BA2

J8

CK

K8

CK

K10

CKE_CKE0

K2

ODT

L3

CS

J4

RAS

K4

CAS

L4

WE

F4

DQSL

C8

DQSU

E8

DML

D4

DMU

G4

DQSL

B8

DQSU

T3

RESET

L9

21

ZQ_ZQ0

J2

NC_ODT

L2

NC_CSI

J10

NC_CE1

L10

NC_ZQ1

A1

NC

A11

NC

DQL1

DQU0

DQU1

DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD#B3

VDD#D10

VDD#G8
VDD#K3
VDD#K9
VDD#N2

VDD#N10

VDD#R2

VDD#R10

VDDQ#A2
VDDQ#A9
VDDQ#C2

VDDQ#C10

VDDQ#D3

VDDQ#E10

VDDQ#F2
VDDQ#H3

VDDQ#H10

VSS#A10

VSS#B4
VSS#E2

VSS#G9

VSS#J3
VSS#J9

VSS#M2

VSS#M10

VSS#P2

VSS#P10

VSS#T2

VSS#T10

VSSQ#B2

VSSQ#B10

VSSQ#D2
VSSQ#D9
VSSQ#E3
VSSQ#E9

VSSQ#F10

VSSQ#G2

VSSQ#G10

E4

DQB<39>

DQL0

F8

DQB<37>

F3

DQB<36>

DQL2

F9

DQB<38>

DQL3

H4

DQB<35>

DQL4

H9

DQB<32>

DQL5

G3

DQB<33>

DQL6

H8

DQB<34>

DQL7

D8

DQB<41>

C4

DQB<44>

C9

DQB<42>

C3

DQB<45>

A8

DQB<40>

A3

DQB<47>

B9

DQB<43>

A4

DQB<46>

B3
D10
G8
K3
K9
N2
N10
R2
R10

A2
A9
C2
C10
D3
E10
F2
H3
H10

A10
B4
E2
G9
J3
J9
M2
M10
P2
P10
T2
T10

B2
B10
D2
D9
E3
E9
F10
G2
G10

T1

NC

T11

NC

P1V5S_DGPU

SAM_K4B1G1646D_HCF7_FBGA_100P

21

4.99K_1%_24.99K_1%_2

65D465D4

VRAM_VREFD_B<5>

IN

C5515

R5536

4.99K_1%_24.99K_1%_2

21

R5537

2 1

0.1UF_16V_2

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

58D4
58D4
58D4
58D4
58D4
58D4
58D4
58D4

58D4
58D4
58D4
58D4
58D4
58D4
58D4

P1V5S_DGPU

58D4

D

CC

B

AA

C5573

10UF_6.3V_3

2.2UF_6.3V_2

C5571

C5565

2 1

C5566

1UF_6.3V_2

2 1

C5567

1UF_6.3V_2

2 1

8

C5568

1UF_6.3V_2

2 1

7 6

C5569

1UF_6.3V_2

2 1

C5570

1UF_6.3V_2

2 1

10UF_6.3V_3

2 1

C5572

2 1

5 4

2 1

C5574

1UF_6.3V_2

2 1

C5575

1UF_6.3V_2

2 1

CHANGE by

C5576

1UF_6.3V_2

2 1

C5577

1UF_6.3V_2

10UF_6.3V_3

2 1

1UF_6.3V_2

DATE

C5578

21-OCT-2002XXX

23

2 1

C5579

10UF_6.3V_3

2 1

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

REV

of

X011310xxxxx-0-0

7065

1

8 7

6 5

USB BOARD

4

3 2 1

D

D

P5V0A_USB3_DB

C9100

22UF_6.3V_5

DGND_USB3_DB

66B5
66B5

USB_P2_DN_DB

BI

USB_P2_DP_DB USB_L_P2_DP_DB

BI

L9100

34
21

WCM_2012_900T

P5V0A_USB3_DB

BI
BI

USB_P2_DN_DB
USB_P2_DP_DB

DGND_USB3_DB

B

66C6

66C6

2 1

USB_L_P2_DN_DB

DGND_USB3_DB

SMDPAD_1P_40X120
SMDPAD_1P_40X120
SMDPAD_1P_40X120
SMDPAD_1P_40X120

CN9100

1

VCC

G1

2

G2

DATA-

3

G3

DATA+

4 G4

GND G4

SUYIN_020173GR004M555ZL_4P

PAD9100

1

PAD9101

1

PAD9102

1

PAD9103

1

G1
G2
G3

DGND_USB3_DB

CC

B

S9100

1

SCREW240_800_1P

S9101

1

SCREW300_1000_1P

DGND_USB3_DB

FIX9100

1

FIX_MASK

FIX9101

1

FIX_MASK

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

XXX 21-OCT-2002

DATE

23

SHEET

of

66

1

REV

X011310xxxxx-0-0

70

8 7

TOUCH PAD BOARD 4 PIN

6 5

4

3 2 1

D

TOUCHPAD TO MODULE CONN

DGND_TP

R9201
R9202
R9203
R9204
R9205
R9206

R9207
R9208

21

0_5%_2

21

0_5%_2_DY

21

0_5%_2

21

0_5%_2_DY

21

0_5%_2

21

0_5%_2_DY

21

0_5%_2

21

0_5%_2_DY

BI
BI
BI
BI

IN
IN
IN

TP_IM_CLK_5
TP_IM_DAT_5
TP_IM_DAT_5
TP_IM_CLK_5
LEFT_TP

RIGHT_TP
LEFT_TP

67B767D467D7
67B767D467D7
67B767D467D7
67B767D467D7

67A267C7

67A2

67A267C7

P5V0S_TPB

CN9201

1

1

2

2

3

3

4

4

5

5

ACES_50592_0060N_001_6P

G16

G16

G2

G2

DGND_TP

TOUCHPAD TO MB CONN

P5V0S_TPB

SMDPAD1_28X118

67B767D7
67B767D7

TP_IM_CLK_5

BI

TP_IM_DAT_5

BI

DGND_TP

SMDPAD1_28X118
SMDPAD1_28X118
SMDPAD1_28X118

D

1

PAD9201

1

PAD9202

1

PAD9203

1

PAD9204

CC

4PIN IMR/METAL TEXTURE

R9201
R9202

V

V

R9203 V
R9204
R9205
R9206
R9207

B

R9208
R9213
R9214

8

V

V

V
V V
V

67D467D7
67D467D7

FIX9201

1

7 6

V

V

B

V

TP_IM_CLK_5

BI

TP_IM_DAT_5

BI

FIX_MASKFIX_MASKFIX_MASK

FIX9203

1

DGND_TP

FIX9202

1

R9213

2 1
2 1

R9214

FIX9204

1

S9201

1

SCREW230_800_1P

S9202

1

SCREW230_500_1P

S9203

1

SCREW230_800_1P

47K_5%_2
47K_5%_2

FIX9205

1

P5V0S_TPB

FIX9206

1

FIX_MASKFIX_MASKFIX_MASK

5 4

SW9201

4

A B

5
6

MISAKI_NTC017_DA1G_E160T_6P

MISAKI_NTC017_DA1G_E160T_6P

DGND_TP

DC

SW9202

4

A B

5
6

DC

1
2
3

1
2
3

CHANGE by

RIGHT_TP

LEFT_TP

1

2

D9201

PHP_PESD5V2S2UT_SOT23_3P_DY

3

DGND_TP

OUT

OUT

DATE

67C7

67C7

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7067

8 7

REFERENCE 9000~9999(SMALL BOARD)

6 5

4

3 2 1

D

D

POWER BUTTON

SW9000
4
5
6

MISAKI_NTC017_DA1G_E160T_6P

DGND_PWRSW_DB

A B

1
2
3

DC

D9000

1

2

3

PHP_PESD5V2S2UT_SOT23_3P

C9000

1000PF_50V_2_DY

2 1

B

FIX_MASKFIX_MASK

FIX9005

1

FIX9003

1

FIX_MASK

FIX9004

1

1

1

PAD9000

PAD9001

SMDPAD_1P_40X120

SMDPAD_1P_40X120

CC

B

S9000

1

SCREW220_800_1P

S9001

1

SCREW220_800_1P

DGND_PWRSW_DB

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7068

8 7

6 5

4

3 2 1

D

PVBAT P5V0S

C7501

0.1UF_16V_2_DY

C7502

0.1UF_16V_2_DY

C7503

0.1UF_16V_2_DY

C7504

0.1UF_16V_2_DY

C7505

0.1UF_16V_2_DY

21

21

21

21

21

PVCORE

C7506

0.1UF_16V_2

C7507

0.1UF_16V_2_DY

C7511

0.1UF_16V_2_DY

C7512

0.1UF_16V_2_DY

21

21

P3V3S

21

21

P1V5S_DGPU

P5V0A

P5V0A

0.1UF_16V_2_DY

0.1UF_16V_2_DY

P3V3S

C7515

21

0.1UF_16V_2

P5V0A

C7508

C7509

C7516

0.1UF_16V_2

C7517

0.1UF_16V_2

P5V0S_AUDIO_AVDDP1V5

21

P5V0S_AUDIO_AVDD

21

P3V3S

21

P1V5S_DGPU

21

P1V5S_DGPU

C7518

0.1UF_16V_2

PVCORE_DGPU

21

B

D

CC

B

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

DOC.NUMBER

CODE

SIZE

CS

A3

8

7 6

5 4

CHANGE by

DATE

21-OCT-2002XXX

23

SHEET

of

1

REV

X011310xxxxx-0-0

7069

8 7

6 5

4

3 2 1

TOUCH PAD BOARD 8 PIN

TOUCHPAD TO MODULE CONN

D

P3V3S_TPM

CN9303

G2

8

70B770D4
70B770D4

70C4
70C4

70B2
70B2

TP_IM_DAT_8

BI

TP_IM_CLK_8

BI

RIGHT_TP_8

IN

LEFT_TP_8

IN

TP_PCH_3S_SMCLK_8

BI

TP_PCH_3S_SMDATA_8

BI

8

7

7

6

6

5

5

4

4

3

3

2

2

1

1

ACES_50503_0084N_001_8P

DGND_DB

B

P3V3S_TPM

R9313

BI
BI

TP_IM_CLK_8
TP_IM_DAT_8

70D470D7
70D470D7

2 1
2 1

R9314

47K_5%_2
47K_5%_2

G2

G1

G1

DGND_DB

TOUCHPAD TO MB CONN

P3V3S_TPMP5V0S_DB

70B770D7
70B770D7

70C7
70C7

TP_IM_CLK_8

BI

TP_IM_DAT_8

BI

TP_PCH_3S_SMCLK_8

BI

TP_PCH_3S_SMDATA_8

BI

SW9301

4

A B

5
6

MISAKI_NTC017_DA1G_E160T_6P

MISAKI_NTC017_DA1G_E160T_6P

DGND_DB

DC

SW9302

4

A B

5
6

DC

DGND_DB

1
2
3

1
2
3

SMDPAD1_28X118
SMDPAD1_28X118
SMDPAD1_28X118
SMDPAD1_28X118
SMDPAD1_28X118
SMDPAD1_28X118
SMDPAD1_28X118
SMDPAD1_28X118

1

2

PHP_PESD5V2S2UT_SOT23_3P_DY

3

DGND_DB

RIGHT_TP_8

LEFT_TP_8

D9301

1
1
1
1
1
1
1
1

OUT

OUT

PAD9301
PAD9302
PAD9303
PAD9304
PAD9305
PAD9306
PAD9307
PAD9308

70C7

70C7

D

CC

B

FIX9305

FIX9301

1

FIX_MASK

8

FIX9302

1

FIX_MASK FIX_MASK

7 6

FIX9303

1

FIX9304

1

FIX_MASK FIX_MASK

SCREW230_800_1P

SCREW230_500_1P

SCREW230_800_1P

DGND_DB

1

FIX_MASK

S9301

1

S9302

1

S9303

1

FIX9306

1

AA

INVENTEC

TITLE

MODEL,PROJECT,FUNCTION

Block Diagram

5 4

CHANGE by

DATE

DOC.NUMBER

CODE

SIZE

CS

A3

SHEET

21-OCT-2002XXX

23

of

1

REV

X011310xxxxx-0-0

7070