Toshiba M100 Schematics
A
hexainf@hotmail.com
1 1
B
C
D
E
HAWAA
2 2
LA-3141
3 3
uFCPGA Yonah/ ATi-RC410MD(A12)/ ATi-SB450(A13)
REV 0.3 Schematic
2006-01-26 Rev.0.3
4 4
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Black Diagram
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Friday, January 27, 2006
D
Date: Sheet
E
of
143
A
B
C
D
E
HAWAA LA-3141 FUNCTION BLOCK DIAGRAM
4 4
CRT Conn.
PAGE 14
LCD Conn
PAGE 13
LVDS & TV-OUT Conn.
3 3
2 2
CARDBUS
ENE 1410
PAGE 21
1394
TSB43AB21
PAGE 26
CARD BUS
SOCKET
PAGE 22
PAGE 13
Mini Card
FOR WLAN
PAGE 23
PCI BUS
33MHz (3.3V)
LAN
RTL8100CL
PAGE 20
RJ-45
PAGE 20
PCI-E X 1
LPC BUS 33MHz (3.3V)
TPM
SLB 9635
PAGE 31
Mobile Yonah
uFCPGA-479 Pin
PAGE 4,5,6
FSB
533MHz/667MHz
ATI-RC410MD/E
VGA M10P Embeded
707 pin BGA
2.5GHz(1.2V)
Bandwidth 500MB
ATI-SB450
564 pin BGA
Embedded
Controller
ENE KB910
BIOS(1M)
& I/O PORT
PAGE 29 PAGE 30
A-Link Express x 4
PAGE 28
PAGE 7,8,9
PAGE 15,16,17,18,19
Scan KB
Thermal Sensor
ADM1032ARM
400/533/667MHz
(1.8V)
Memory Bus
Single channel
480MHz(5V)
SATA
3.3V,5V 1.5GHz(150MB/s)
Secondary
ATA-100 (5V)
AZALIA
24MHz(3.3V)
Clock Generator
ICS951413CGLFT
PAGE 4
SO-DIMM x 2(DDRII)
BANK 0,1,2,3
USB 2.0 Port *4
0,2,4,6
SATA HDD
IDE ODD
HD CODEC
ALC 861
PAGE 27
PAGE 17
PAGE 26
PAGE 24
MDC
Connector
PAGE 33
MOM
PAGE 41,42
PAGE 12
PAGE 10,11
Audio Amplifier
CPU VID
TPA0232
PAGE 25
PAGE 5
FANController
RTC Battery
DC/DC Interface
LID/Kill Switch
Power Buttom
DCIN&DETECTOR
BATT CONN/OTP
CHARGER
3V/5V/12V
DDR_1.8V/0.9VEP
1.8VCORE
1.5V/PROCHOT
CPU_CORE
PAGE 32
PAGE 15
PAGE 33
PAGE 31
PAGE 34
PAGE 35
PAGE 36
PAGE 37
PAGE 39
PAGE 38
PAGE 40
PAGE 40
1 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Black Diagram
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
D
Date: Sheet
E
243
of
A
hexainf@hotmail.com
Voltage Rails
B
C
D
E
Power Plan e Description
VIN
1 1
B+
+CPU_CORE
+CPUVID
+1.2VS 1.2VS for PCI-Express OFFON OFF
+0.9VS 0.9V switched power rail
+1.5VS
+1.8VS 1.8VS switched power rail OFFOFFON
+1.8VALW 1.8V always on power rail ON*ONON
+1.8V
+3VALW
+3VS
+5VS
+RTCVCC
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2V switched power rail for CPU AGTL Bus
Yonah
1.8V power rail
3.3V always on power rail
3.3V switched power rai l
5V always on power rail
5V switched power rail
RTC power
S1 S3 S5
ON
ON ONONON
ON OFF
ON OFF
ON OFF OFF
ON OFF OFF
ON ON
ON
ON
ON+5VALW
ON
ON
OFF
ON
OFF
ON
ON
OFF
OFF
OFF
ON*ON
OFF
ON*
OFF
ON
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID Table for AD channel
Vcc
Ra/Rc
Board ID
0
1
2 2
2
3
4
5
Note : ON* means that this power plane is ON only with AC power available, otherwise it i s OFF.
6
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
ENE 1410
LAN
3 3
EC SM Bus1 address
Device
Smart Battery
SB450 SM Bus address
Device
Clock Generator
(ICS951413BGLFT)
DDRII DIMM0
4 4
DDRII DIMM1
AD20
AD22
AD16 PIRQA01394
2 PIRQB
1PIRQG
EC SM Bus2 address
Address Address
Address
1101 001Xb
1010 0100b
1010 0110b
A4
A6
Device
ADM1032
1001 110X b0001 011X b
Board ID
0
1
2
3
4
5
6
7
BTN ID
0
1
2
3
4
5
6
7
SIGNAL
3.3V +/- 5%
100K +/- 5%
Rb / Rd
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC7
PCB Revision
BTN Status
1 Buttons
6 Buttons
0.1
0.2
HIGH
LOW
LOW
AD_BID
0.436 V
0.712 V
1.036 V
1.935 V
2.500 V
SLP_S5#STATE
HIGHHIGH
HIGH
HIGH
HIGH
LOWLOW
minV
0 V
+VALW
+V
+VSSLP_S 3#
Clock
ON
OFF
OFF
OFF
V
AD_BID
ONON
LOW
OFF
OFF
OFF
max
0 V
ON
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
typV
AD_BID
0 V
0.289 V0.250 V0.216 V
0.503 V
0.819 V
0.538 V
0.875 V
1.264 V1.185 V
1.650 V1.453 V
2.200 V
3.300 V
1.759 V
2.341 V
3.300 V
PCB RevisionSKU ID
0
1
2
3
4
5
─
SKU 1
SKU 2
SKU 3
SKU 4(JP)
SKU 5
6
7
BTO Function BOM structure
1394 1394@
Wireless LAN WLAN@
TV-OUT TVOUT@
TPM TPM@
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Notes List
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
D
Date: Sheet
E
of
343
5
4
3
2
1
H_A#[3..31]<7>
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
D D
H_REQ#[0..4]<7>
H_ADSTB#0<7>
H_RS#[0..2]<7>
R482 1K_0402_5%@
R484 51_0402_5%
H_ADSTB#1<7>
CLK_BCLK<12>
CLK_BCLK#<12>
H_ADS#<7>
H_BNR#<7>
H_BPRI#<7>
H_BR0#<7>
H_DEFER#<7>
H_DRDY#<7>
H_HIT#<7>
H_HITM#<7>
H_LOCK#<7>
H_RESET#<7,15>
H_TRDY#<7>
H_DBSY#<7>
H_DPSLP#<15>
H_DPRSTP#<40>
H_DPWR#<7>
H_PWRGOOD<15>
H_CPUSLP#<15>
12
12
C C
B B
B
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A A
For B-0 stepping engineering samples (ES) of Celeron M
processor need to pop this 51 ohm resistor.
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_BCLK
CLK_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_DBRESET#
H_DBSY#
H_DPSLP# H_BR0#
H_DPRSTP#
H_DPWR#
PROCHOT#
C
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
A
JCPU1A
J4
A3#
L4
A4#
M3
A5#
K5
A6#
M1
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L1
A13#
P4
A14#
P1
A15#
R1
A16#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U2
A23#
R4
A24#
T5
ADDR GROUP
A25#
T3
A26#
W3
A27#
W5
A28#
Y4
A29#
W2
A30#
Y1
A31#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L5
REQ4#
L2
ADSTB0#
V4
ADSTB1#
A22
BCLK0
AD4
AD3
AD1
AC4
C20
D24
AC2
AC1
D21
AC5
AA6
AB3
C26
D25
AB5
AB6
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
E1
B5
E5
D6
D7
A24
A25
C7
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
FOX_PZ47903-2741-42_YONAH
YONAH
MISC
DATA GROUP
LEGACY CPU
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24
A6
A5
C4
B3
C6
B4
R766 0_0402_5%
D5
A3
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_STPCLK#
H_SMI#
12
H_NMI
H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>
H_A20M# <15>
H_FERR# <15>
H_IGNNE# <15>
H_INIT# <15>
H_INTR <15>
H_NMI <15>
H_STPCLK# <15>
H_SMI# <15>
H_D#0H_A#3
E22
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
H_D#[0..63] <7>
+CPU_CORE
+1.05VS
12
R463
@
47K_0402_5%
1 2
C665
+1.05VS
H_THERMTRIP#
12
0.1U_0603_25V7K@
1 2
R466
56_0402_5%
R464
47K_0402_5%
2
3 1
MAINPWON <16,34,35,37>
Q53
MMBT3904_SOT23
A
+1.05VS
R468
470_0402_5%
H_DPRSTP#
R471 0_0402_5%
B
MMBT3904_SOT23
H_DSTBN#[0..3] <7>
H_DSTBP#[0..3] <7>
C666 180P_0402_50V8J@
1 2
C667 180P_0402_50V8J@
1 2
C668 180P_0402_50V8J@
1 2
C669 180P_0402_50V8J@
1 2
C670 180P_0402_50V8J@
1 2
C671 180P_0402_50V8J@
1 2
C672 180P_0402_50V8J@
1 2
C673 180P_0402_50V8J@
1 2
C674 180P_0402_50V8J@
1 2
C675 180P_0402_50V8J@
1 2
2005/11/01 2006/11/30
1 2
12
Q55
2
R472 470_0402_5%
3 1
1 2
Place Caps Close to CPU Socket
H_INIT#
H_A20M#
H_CPUSLP#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_IGNNE#
H_PWRGOOD
H_FERR#
H_DPSLP#
Compal Secret Data
Deciphered Date
R480 390_0402_5%@
R481 390_0402_5%@
R485 200_0402_5%
R486 390_0402_5%@
R487 390_0402_5%@
R489 390_0402_5%@
R491 390_0402_5%@
R492 390_0402_5%@
R493 332_0402_1%
R494 56_0402_5%
R495 200_0402_5%
2
DPRSLPVR <15,40>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
1 2
C664
2200P_0402_50V7K
EC_SMB_CK2<28>
EC_SMB_DA2<28>
+3VS
1
C663
0.1U_0402_16V4Z
1
2
75_0402_5%
PROCHOT#
H_THERMDA
H_THERMDC
+1.05VS
12
R469
2
3
8
7
U31
D+
ALERT#
D-
THERM#
SCLK
SDATA
ADM1032ARM_RM8
12
R470
56_0402_5%
2
2
VDD1
GND
B
+3VALW
C
E
1
6
4
5
12
R467
1K_0402_5%
1
Q54
PMBT3904_SOT23
3
H_PROCHOT# <16>
C
H_DPRSTP#
H_RESET#
ITP_TMS
ITP_TDI
ITP_TDO
H_IERR#
+1.05VS
ITP_DBRESET#
ITP_TRST#
ITP_TCK
Compal Electronics, Inc.
Title
Yonah(1/2)-GTLITP
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
R473 56_0402_5%@
R474 54.9_0402_1%@
R475 40.2_0402_1%
R476 150_0402_1%
R477 54.9_0402_1%@
R478 200_0402_5%
R479 56_0402_5%
R483 150_0402_1%
R488 680_0402_5%
R490 27.4_0402_1%
1 2
1
12
12
12
12
12
12
12
12
12
443
12
R465
+3VALW
of
10K_0402_5%@
+1.05VS
5
hexainf@hotmail.com
4
3
2
1
Length match within 25 mils
Layout close CPU
C676
10U_0805_10V6M
20mils
1
2
VCCSENSE
VSSSENSE
1
C677
2
0.01U_0402_16V7K
CPU_VID0<40>
CPU_VID1<40>
CPU_VID2<40>
CPU_VID3<40>
CPU_VID4<40>
CPU_VID5<40>
CPU_VID6<40>
CPU_BSEL0<12>
CPU_BSEL1<8,12>
CPU_BSEL2<12>
H_PSI#<40>
+GTL_REF0
+CPU_CORE
+1.05VS
H_PSI#
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
COMP0
COMP1
COMP2
COMP3
JCPU1B
AF7
VCCSENSE
AE7
VSSSENSE
B26
VCCA
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
YONAH
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
FOX_PZ47903-2741-42_YONAH
AD26
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
K21
M21
N21
R21
V21
W21
G21
AE6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
B22
B23
C21
R26
U26
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
B25
T6
R6
J21
T21
V6
U1
V1
E7
D2
F6
D3
C1
M4
N5
T2
V3
B2
C3
T22
AB26
VSS
AA25
VSS
AD25
VSS
AE26
VSS
AB23
VSS
AC24
VSS
AF24
VSS
AE23
VSS
AA22
VSS
AD22
VSS
AC21
VSS
AF21
VSS
AB19
VSS
AA19
VSS
AD19
VSS
AC19
VSS
AF19
VSS
AE19
VSS
AB16
VSS
AA16
VSS
AD16
VSS
AC16
VSS
AF16
VSS
AE16
VSS
AB13
VSS
AA14
VSS
AD13
VSS
AC14
VSS
AF13
VSS
AE14
VSS
AB11
VSS
AA11
VSS
AD11
VSS
AC11
VSS
AF11
VSS
AE11
VSS
AB8
VSS
AA8
VSS
AD8
VSS
AC8
VSS
AF8
VSS
AE8
VSS
AA5
VSS
AD5
VSS
AC6
VSS
AF6
VSS
AB4
VSS
AC3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
POWER, GROUNG, RESERVED SIGNALS AND NC
+CPU_CORE
D D
+1.05VS
R_A
12
+GTL_REF0
R498
1K_0402_1%
R_B
12
R499
2K_0402_1%
VCCSENSE<40>
VSSSENSE<40>
R496 100_0402_1%
1 2
R497 100_0402_1%
1 2
+1.5VS
Layout close CPU PIN AD26
0.5 inch (max)
C C
R500 27.4_0402_1%
1 2
R501 54.9_0402_1%
1 2
R502 27.4_0402_1%
1 2
R503 54.9_0402_1%
CPU_BSEL CPU_BSEL0 CPU_BSEL1
133
166
B B
00
0
1
CPU_BSEL2
1
1
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils
1 2
+CPU_CORE
JCPU1C
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
AD7
AC7
POWER, GROUND
VCC
AE9
VCC
AB7
VCC
AA7
VCC
VCC
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
FOX_PZ47903-2741-42_YONAH
YONAH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Yonah(2/2)-PWR/GND
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
of
543
5
Place these inside
socket cavity on L6
(North side
1
C678
22U_0805_6.3V6M
2
1
C688
22U_0805_6.3V6M
2
1
C698
22U_0805_6.3V6M
2
1
C704
22U_0805_6.3V6M
2
Secondary)
+CPU_CORE
D D
+CPU_CORE
+CPU_CORE
+CPU_CORE
C C
1
C679
22U_0805_6.3V6M
2
1
C689
22U_0805_6.3V6M
2
1
C699
22U_0805_6.3V6M
2
1
C705
22U_0805_6.3V6M
2
4
1
C680
22U_0805_6.3V6M
2
1
C690
22U_0805_6.3V6M
2
1
C700
22U_0805_6.3V6M
2
1
C706
22U_0805_6.3V6M
2
1
C681
22U_0805_6.3V6M
2
1
C691
22U_0805_6.3V6M
2
1
C701
22U_0805_6.3V6M
2
1
C707
22U_0805_6.3V6M
2
1
2
1
2
1
2
1
2
3
C682
22U_0805_6.3V6M
C692
22U_0805_6.3V6M
C702
22U_0805_6.3V6M
C708
22U_0805_6.3V6M
1
C683
22U_0805_6.3V6M
2
1
C693
22U_0805_6.3V6M
2
1
C703
22U_0805_6.3V6M
2
1
C709
22U_0805_6.3V6M
2
1
C684
22U_0805_6.3V6M
2
1
C694
22U_0805_6.3V6M
2
1
2
1
2
22uF 0805 X5R -> 85 degree C
C685
22U_0805_6.3V6M
C695
22U_0805_6.3V6M
2
1
2
1
2
C686
22U_0805_6.3V6M
C696
22U_0805_6.3V6M
1
C687
22U_0805_6.3V6M
2
1
C697
22U_0805_6.3V6M
2
1
High Frequence Decoupling
Near VCORE regulator.
+CPU_CORE
South Side S econdary
B B
+1.05VS
1
+
C716
2
A A
5
330U_D2E_2.5VM_R9
C710
@
1
+
2
330U_D_2VM
9mOhm
7343
PS CAP
1
+
C711
2
330U_D_2VM
1
C717
0.1U_0402_10V7K
2
C712
@
1
+
2
330U_D_2VM
1
+
C713
2
330U_V_2.5VM @
C714
1
+
2
330U_D_2VM
1
+
North Side Secondary
C715
2
330U_V_2.5VM
ESR <= 1.5m ohm
Capacitor > 1980uF
H=1.9mm H=1.9mm
1
C718
0.1U_0402_10V7K
2
4
1
C719
0.1U_0402_10V7K
2
1
C720
0.1U_0402_10V7K
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C721
0.1U_0402_10V7K
2
3
1
C722
0.1U_0402_10V7K
2
2005/11/01 2006/11/30
Compal Secret Data
Place these inside
socket cavity on L8
(North side
Secondary)
Deciphered Date
Compal Electronics, Inc.
Title
Yonah Bypass
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
643
of
A
hexainf@hotmail.com
H_A#[3..31]<4>
H_REQ#[0..4]<4>
H_RS#[0..2]<4>
U21A
H_A#3
G28
CPU_A3#
H_A#4
H26
CPU_A4#
H_A#5
G27
CPU_A5#
H_A#6
G30
CPU_A6#
H_A#7
G29
CPU_A7#
H_A#8
G26
CPU_A8#
H_A#9
H28
M28
K29
K30
M30
K27
M29
K26
N28
N25
N24
D25
E11
G22
J28
H25
K28
H29
J29
K24
K25
F29
G25
F26
F28
E29
H27
J26
L28
L29
L26
L25
L27
F25
F24
E23
E25
G24
F23
E27
C11
D23
G23
E26
F22
D26
E24
D11
B11
H22
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#
CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_LOCK#
CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#
CPU_TRDY#
CPU_HIT#
CPU_HITM#
CPU_COMP_N
CPU_COMP_P
CPU_VREF
RESERVED0
RESERVED1
CPU_DPWR#
PART 1 OF 6
ADDR. GROUP
0
ADDR. GROUP
1
CPU I/F
CONTROLMISC.
RC410MD
216CPP4AKA21HK_BGA707
R30
12
R234
12
+CPU_VREF
1
C123
2
A
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_RS#2
H_RS#1
H_RS#0
HSCOMP
HRCOMP
1 1
H_ADSTB#0<4>
2 2
3 3
4 4
+1.05VS
220P_0402_50V9J
H_ADSTB#1<4>
H_ADS#<4>
H_BNR#<4>
H_BPRI#<4>
H_DEFER#<4>
H_DRDY#<4>
H_DBSY#<4>
H_LOCK#<4>
H_RESET#<4,15>
H_TRDY#<4>
H_HIT#<4>
H_HITM#<4>
24.9_0402_1%
49.9_0402_1%
Place C close
to Ball H22
H_BR0#<4>
H_DPWR#<4>
DATA GROUP 0
CPU_DSTBN0#
CPU_DSTBP0#
DATA GROUP 1
CPU_DSTBN1#
CPU_DSTBP1#
DATA GROUP 2
CPU_DSTBN2#
CPU_DSTBP2#
DATA GROUP
3
CPU_DSTBN3#
CPU_DSTBP3#
B
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
CPU_VREF
Trace=12Mil
Space=15Mil
+CPU_VREF
B
H_D#[0..63] <4>
H_DINV#[0..3] <4>
H_DSTBN#[0..3] <4>
H_DSTBP#[0..3] <4>
H_D#0
E28
H_D#1
D28
H_D#2
D29
H_D#3
C29
H_D#4
D30
H_D#5
C30
H_D#6
B29
H_D#7
C28
H_D#8
C26
H_D#9
B25
H_D#10
B27
H_D#11
C25
H_D#12
A27
H_D#13
C24
H_D#14
A24
H_D#15
B26
H_DINV#0
C27
H_DSTBN#0
A28
H_DSTBP#0
B28
H_D#16
C19
H_D#17
C23
H_D#18
C20
H_D#19
C22
H_D#20
B22
H_D#21
B23
H_D#22
C21
H_D#23
B24
H_D#24
E21
H_D#25
B21
H_D#26
B20
H_D#27
G19
H_D#28
F21
H_D#29
B19
H_D#30
E20
H_D#31
D21
H_DINV#1
A21
H_DSTBN#1
D22
H_DSTBP#1
E22
H_D#32
C18
H_D#33
F19
H_D#34
E19
H_D#35
A18
H_D#36
D19
H_D#37
B18
H_D#38
C17
H_D#39
B17
H_D#40
E17
H_D#41
B16
H_D#42
C15
H_D#43
A15
H_D#44
B15
H_D#45
F16
H_D#46
G18
H_D#47
F18
H_DINV#2
C16
H_DSTBN#2
D18
H_DSTBP#2
E18
H_D#48
E16
H_D#49
D16
H_D#50
C14
H_D#51
B14
H_D#52
E15
H_D#53
D15
H_D#54
C13
H_D#55
E14
H_D#56
F13
H_D#57
B13
H_D#58
A12
H_D#59
C12
H_D#60
E12
H_D#61
D13
H_D#62
D12
H_D#63
B12
H_DINV#3
E13
H_DSTBN#3
F15
H_DSTBP#3
G15
+1.05VS
1
C121
2
1U_0402_6.3V4Z
12
R38
49.9_0402_1%
12
R37
100_0402_1%
+1.2VS
SB_A_RXN0
SB_A_RXP0
SB_A_RXN1
SB_A_RXP1
NB_A_RXN0
NB_A_RXP0
NB_A_RXN1
NB_A_RXP1
C
ATI recommendation R33, R34
Place R
Close to Ball
C753 0.1U_0402_10V7K
C754 0.1U_0402_10V7K
C755 0.1U_0402_10V7K
C756 0.1U_0402_10V7K
CLK_NB_ALINK#<12>
CLK_NB_ALINK<12>
SB_A_RXN[0..3]
SB_A_RXP[0..3]
NB_A_RXN[0..3]
NB_A_RXP[0..3]
1 2
1 2
1 2
1 2
12
12
12
12
R2910K_0402_1%
R348.25K_0402_1%
R3382.5_0402_1%
R28150_0402_1%
PCE_RXISET
PCE_TXISET
PCE_NCAL
PCE_PCAL
SB_A_RXN[0..3] <15>
SB_A_RXP[0..3] <15>
NB_A_RXN[0..3] <15>
NB_A_RXP[0..3] <15>
10 mils
10 mils
10 mils
10 mils
NB_A_TXN0
NB_A_TXP0
NB_A_TXP1
AJ12
AK13
AG12
AH12
AJ11
AJ10
AK10
AG10
AG9
AF10
AA4
AA5
AB3
AB4
AC5
AC6
AD4
AD5
AK9
AE9
J4
J5
L4
K4
L5
L6
M4
M5
P4
N4
P5
P6
R4
R5
T3
T4
U5
U6
V4
V5
W3
W4
Y5
Y6
L2
K2
U21C
GFX_RX0N
GFX_RX0P
GFX_RX1N
GFX_RX1P
GFX_RX2N
GFX_RX2P
GFX_RX3N
GFX_RX3P
GFX_RX4N
GFX_RX4P
GFX_RX5N
GFX_RX5P
GFX_RX6N
GFX_RX6P
GFX_RX7N
GFX_RX7P
GFX_RX8N
GFX_RX8P
GFX_RX9N
GFX_RX9P
GFX_RX10N
GFX_RX10P
GFX_RX11N
GFX_RX11P
GFX_RX12N
GFX_RX12P
GFX_RX13N
GFX_RX13P
GFX_RX14N
GFX_RX14P
GFX_RX15N
GFX_RX15P
PCE_ISET
PCE_TXISET
PCE_NCAL
PCE_PCAL
SB_TX0N
SB_TX0P
SB_TX1N
SB_TX1P
SB_RX0N
SB_RX0P
SB_RX1N
SB_RX1P
SB_CLKN
SB_CLKP
A-LINK EXPRESS I/F
216CPP4AKA21HK_BGA707
PCIE_WLAN_TX_P1
D
PART 3 OF 6
PCI EXPRESS I/F
PCI EXPRESS I/F
RC410MD
GPP_TX0N/SB_TX2N
GPP_TX0P/SB_TX2P
GPP_TX1N/SB_TX3N
GPP_TX1P/SB_TX3P
GPP_RX0N/SB_RX2N
GPP_RX0P/SB_RX2P
GPP_RX1N/SB_RX3N
GPP_RX1P/SB_RX3P
C758 0.1U_0402_10V7K
C757 0.1U_0402_10V7K
To SB A-PCIE Link
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
D
1 2
1 2
GFX_TX0N
GFX_TX0P
GFX_TX1N
GFX_TX1P
GFX_TX2N
GFX_TX2P
GFX_TX3N
GFX_TX3P
GFX_TX4N
GFX_TX4P
GFX_TX5N
GFX_TX5P
GFX_TX6N
GFX_TX6P
GFX_TX7N
GFX_TX7P
GFX_TX8N
GFX_TX8P
GFX_TX9N
GFX_TX9P
GFX_TX10N
GFX_TX10P
GFX_TX11N
GFX_TX11P
GFX_TX12N
GFX_TX12P
GFX_TX13N
GFX_TX13P
GFX_TX14N
GFX_TX14P
GFX_TX15N
GFX_TX15P
GFX_CLKN
GFX_CLKP
GPP_TX2N
GPP_TX2P
GPP_TX3N
GPP_TX3P
GPP_RX2N
GPP_RX2P
GPP_RX3N
GPP_RX3P
E
N2
N1
R2
P2
T1
R1
U2
T2
V1
V2
W2
W1
AA2
Y2
AB1
AA1
AC2
AB2
AD1
AD2
AE2
AE1
AG2
AF2
AH1
AG1
AJ2
AH2
AJ4
AJ3
AJ5
AK4
M1
M2
NB_A_TXN2
AJ9
NB_A_TXP2
AJ8
NB_A_TXN3
AF6
NB_A_TXP3
AE6
PCIE_WLAN_TX_N1
AK6
PCIE_WLAN_TX_P1NB_A_TXN1
AJ6
AF4
AE4
NB_A_RXN2
AG8
NB_A_RXP2
AF8
NB_A_RXN3
AG7
NB_A_RXP3
AG6
PCIE_WLAN_C_RX_N1
AJ7
PCIE_WLAN_C_RX_P1
AK7
AH4
AG4
PCIE_WLAN_C_TX_N1PCIE_WLAN_TX_N1
PCIE_WLAN_C_TX_P1
Title
RC410MD-FSB, PCIE,A-PCIE
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Date: Sheet
PCIE_WLAN_C_RX_N1 <23>
PCIE_WLAN_C_RX_P1 <23>
Compal Electronics, Inc.
Thursday, January 26, 2006
SB_A_RXN2
C8040.1U_0402_10V7K
12
SB_A_RXP2
C8050.1U_0402_10V7K
12
SB_A_RXN3
C8060.1U_0402_10V7K
12
SB_A_RXP3
C8070.1U_0402_10V7K
12
PCIE_WLAN_C_TX_N1 <23>
PCIE_WLAN_C_TX_P1 <23>
E
of
743
A
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]
1 1
+1.8V
R42
12
1
1K_0402_1%
1K_0402_1%
2 2
2
0.1U_0402_10V7K
12
R46
1
2
0.1U_0402_10V7K
MEM_VMO DE: 1. 8V: DDR2
+1.8V
R242
12
61.9_0603_1%
R237
12
3 3
C435
@
61.9_0603_1%
Place these R and C
close to relative Ball.
MEM_COMPN
MEM_COMPP
1
1
C450
@
2
2
0.47U_0603_10V7K
C172
+DDR_VREF
C174
MEM_CAP1
MEM_CAP2
0.47U_0603_10V7K
DDR_DQ[0..63] <10,11>
DDR_DQS[0..7] <10,11>
DDR_DQS#[0..7] <10,11>
DDR_DM[0..7] <10,11>
DDR_SMA[0..17] <10,11>
DDR_SRAS#<10,11>
DDR_SCAS#<10,11>
DDR_SWE#<10,11>
EMC_DDR_CLK0#<10>
EMC_DDR_CLK0<10>
EMC_DDR_CLK1#<10>
EMC_DDR_CLK1<10>
EMC_DDR_CLK3#<11>
EMC_DDR_CLK3<11>
EMC_DDR_CLK4#<11>
EMC_DDR_CLK4<11>
DDR_SCKE0<10>
DDR_SCKE1<10>
DDR_SCKE2<10,11>
DDR_SCKE3<10,11>
DDR_SCS#0<10>
DDR_SCS#1<10>
DDR_SCS#2<10,11>
DDR_SCS#3<10,11>
DDR_ODT0<10>
DDR_ODT1<10,11>
DDR_ODT2<10>
DDR_ODT3<10,11>
+1.8V
DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_SMA13
DDR_SMA14
DDR_SMA15
DDR_SMA16
DDR_SMA17
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
DDR_ODT0
DDR_ODT1
DDR_ODT2
DDR_ODT3
R43 1K_0402_5%
1 2
MEM_CAP1
MEM_CAP2
MEM_COMPP
MEM_COMPN
+DDR_VREF
10mil
10mil
10mil
10mil
20mil
DDR_DQS#0
DDR_DQS0
DDR_DQS#1
DDR_DQS1
DDR_DQS#2
DDR_DQS2
DDR_DQS#3
DDR_DQS3
DDR_DQS#4
DDR_DQS4
DDR_DQS#5
DDR_DQS5
DDR_DQS#6
DDR_DQS6
DDR_DQS#7
DDR_DQS7
AK27
AJ27
AH26
AJ26
AH25
AJ25
AH24
AH23
AJ24
AJ23
AH27
AH22
AJ22
AF28
AJ21
AG27
AJ28
AH21
AJ29
AG28
AH30
AC26
AC25
AF16
AE16
AC24
AC23
AG17
AF17
W29
W28
AH20
AJ20
AE24
AE21
AH29
AG29
AH28
AF29
AG30
AE28
AC30
AD28
AJ14
AJ15
AE29
AB27
AH17
AJ18
AF15
AE14
AE22
AF22
AF26
AE25
W26
W27
AB30
AB29
V29
V30
Y30
N30
R25
P25
R30
R29
U21B
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_A16
MEM_A17
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CK0N
MEM_CK0P
MEM_CK1N
MEM_CK1P
MEM_CK2N
MEM_CK2P
MEM_CK3N
MEM_CK3P
MEM_CK4N
MEM_CK4P
MEM_CK5N
MEM_CK5P
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MEM_ODT0
MEM_ODT1
MEM_ODT2/RSV2
MEM_ODT3/RSV3
MEM_VMODE
MEM_CAP1
MEM_CAP2
MEM_COMPP
MEM_COMPN
MEM_VREF
MEM_DQS0N
MEM_DQS0P
MEM_DQS1N
MEM_DQS1P
MEM_DQS2N
MEM_DQS2P
MEM_DQS3N
MEM_DQS3P
MEM_DQS4N
MEM_DQS4P
MEM_DQS5N
MEM_DQS5P
MEM_DQS6N
MEM_DQS6P
MEM_DQS7N
MEM_DQS7P
NB STRAPING PINS
FSB SPEED
BM_REQ#
4 4
EMC_NB_CRT_VSYNC
EMC_NB_CRT_HSYNC
BM_REQ# EMC_NB_CRT_HSYNC EMC_NB_CRT_VSYNC
166MHZ
133MHZ
0
0
R223 4.7K_0402_5%@
1 2
R222 4.7K_0402_5%
1 2
R228
1 2
4.7K_0402_5%
R20
4.7K_0402_5%
MMBT3904_SOT23
A
1
0
+3VS
12
R227
4.7K_0402_5%
12
Q35
3 1
R229
2
4.7K_0402_5%
+3VS
1
1
12
+1.05VS
+3VS
12
R749
4.7K_0402_5%
B
PART 2 OF
6
ADDRESS
MEMORY I/F
RC410MD
DATA CLKMISC
216CPP4AKA21HK_BGA707
CPU_BSEL1 <5,12>
B
DATA
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
STRP_DATA
NB_DDC_CLK
MMBT3904_SOT23
C
DDR_DQ0
AJ16
DDR_DQ1
AH16
DDR_DQ2
AJ19
DDR_DQ3
AH19
DDR_DQ4
AH15
DDR_DQ5
AK16
DDR_DQ6
AH18
DDR_DQ7
AK19
DDR_DQ8
AF13
DDR_DQ9
AF14
DDR_DQ10
AE19
DDR_DQ11
AF19
DDR_DQ12
AE13
DDR_DQ13
AG13
DDR_DQ14
AF18
DDR_DQ15
AE17
DDR_DQ16
AF20
DDR_DQ17
AF21
DDR_DQ18
AG23
DDR_DQ19
AF24
DDR_DQ20
AG19
DDR_DQ21
AG20
DDR_DQ22
AG22
DDR_DQ23
AF23
DDR_DQ24
AD25
DDR_DQ25
AG25
AE27
AD27
AE23
AD24
AE26
AD26
AA25
Y26
W24
U25
AA26
Y25
V26
W25
AC28
AC29
AA29
Y29
AD30
AD29
AA30
Y28
U27
T27
N26
M27
U26
T26
P27
P26
U29
T29
P29
N29
U28
T28
P28
N27
AJ17
AG15
AE20
AF25
Y27
AB28
R26
R28
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46
DDR_DQ47
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63
DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM6
DDR_DM7
1 2
4.7K_0402_5%
1 2
4.7K_0402_5%@
Q5
2
3 1
R225
R220
1 2
2K_0402_1%
EMC_CLK_NB_14M<12>
+3VS
+3VS
R11
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
NB_LUMA<13>
NB_CRMA<13>
1 2
R27 75_0402_1%
EMC_NB_CRT_R<14>
EMC_NB_CRT_G<14>
EMC_NB_CRT_B<14>
EMC_NB_CRT_HSYNC<14>
EMC_NB_CRT_VSYNC<14>
1 2
R232 715_0402_1%
NB_DDC_CLK<14>
NB_DDC_DATA<14>
EMC_CLK_NB_BCLK<12>
EMC_CLK_NB_BCLK#<12>
NB_EDID_CLK<13>
NB_EDID_DATA<13>
R230
1 2
Low: Normal Mode(Fixed)
High: Test Mode
R219
1 2
4.7K_0402_5%
R226
1 2
4.7K_0402_5%
R23
1 2
4.7K_0402_5%@
STRP_DATA: DEBUG STRAP
DEFAULT: 1
0: MEMORY CHANNEL STRAPING
1: EEPROM STRAPING
NB_DDC_CLK: CPU VCC SEL
DEFAULT: 1 1: DESKTOP CPU 0: MOBILE CPU
SB_PWRGD# <17>
2005/11/01 2006/11/30
NB_COMPS
NB_DDC_CLK
NB_DDC_DATA
C422
12
15P_0402_50V8D@
R218 0_0402_5%
1 2
R217 10K_0402_5%
NB_EDID_CLK
NB_EDID_DATA
NB_DVI_DDCDATA
STRP_DATA
TESTMODE
1.8K_0402_5%
NB_EDID_CLK
NB_EDID_DATA
NB_DVI_DDCDATA
Compal Secret Data
RSET
15mil
12
NB_14M
U21D
F9
D9
E9
F10
E10
D10
C3
B3
B10
B2
C2
G1
F1
G2
J1
K1
D2
C1
H3
D1
C4
AH13
AJ13
R22
1 2
4.7K_0402_5%
Deciphered Date
Y
C
COMP
RED
GREEN
BLUE
DACHSYNC
DACVSYNC
RSET
DACSCL
DACSDA
OSCIN
OSCOUT
TVCLKIN
CPU_CLKP
CPU_CLKN
I2C_CLK
I2C_DATA
DDC_DATA
STRP_DATA
TESTMODE
THERMALDIODE_P
THERMALDIODE_N
D
CRT & TV
I/F
CLK. GEN.
216CPP4AKA21HK_BGA707
LVDS_ENBKL
LVDS_ENVDD
D
PART 4 OF 6
RC410MD
SUS_STAT#
NB_PWRGD
E
EMC_NB_TZOUT0-
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
LVDS
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
LVDS_BLON
LVDS_DIGON
LVDS_BLEN
SYSRESET#
SUS_STAT#
POWERGOOD
1
2
Title
Size Document Number Re v
Custom
Date: Sheet
B4
EMC_NB_TZOUT0+
A4
EMC_NB_TZOUT1-
B5
EMC_NB_TZOUT1+
C6
EMC_NB_TZOUT2-
B6
EMC_NB_TZOUT2+
A6
B7
A7
EMC_NB_TZCLK-
F7
TXCLK_UN
TXCLK_UP
TXCLK_LN
TXCLK_LP
BMREQ#
TMDS_HPD
+1.8V
+3VALW
A
B
4
A
5
B
EMC_NB_TZCLK+
F8
EMC_NB_TXOUT0-
E5
EMC_NB_TXOUT0+
F5
EMC_NB_TXOUT1-
D5
EMC_NB_TXOUT1+
C5
EMC_NB_TXOUT2-
E6
EMC_NB_TXOUT2+
D6
E7
E8
EMC_NB_TXCLK-
G6
EMC_NB_TXCLK+
F6
LVDS_ENBKL
G3
LVDS_ENVDD
E2
F2
NB_RST#
A3
SUS_STAT#
AH14
NB_PWRGD
E3
BM_REQ#
H2
J2
12
R236
220K_0402_5%
D21
1 2
2 1
CH751H-40_SC76
D20
2 1
CH751H-40_SC76
14
U5A
P
3
O
G
SN74LVC08APW_TSSOP14
7
+3VALW
14
U5B
P
6
O
G
SN74LVC08APW_TSSOP14
7
R216
10K_0402_5%
Compal Electronics, Inc.
RC410MD-DDR/DISP/MISC
HAWAA(LA3141) 0.3
Thursday, January 26, 2006
R21 4.7K_0402_5%@
1 2
1 2
R224
NB_RST#
ENBKL <28>
NB_ENVDD <13>
E
EMC_NB_TZOUT0- <13>
EMC_NB_TZOUT0+ <13>
EMC_NB_TZOUT1- <13>
EMC_NB_TZOUT1+ <13>
EMC_NB_TZOUT2- <13>
EMC_NB_TZOUT2+ <13>
EMC_NB_TZCLK- <13>
EMC_NB_TZCLK+ <13>
EMC_NB_TXOUT0- <13>
EMC_NB_TXOUT0+ <13>
EMC_NB_TXOUT1- <13>
EMC_NB_TXOUT1+ <13>
EMC_NB_TXOUT2- <13>
EMC_NB_TXOUT2+ <13>
EMC_NB_TXCLK- <13>
EMC_NB_TXCLK+ <13>
4.7K_0402_5%@
NB_RST# <15>
NB_PW RGD <17>
BM_REQ# <15>
NB_SUS_STAT# <16>
843
of
A
hexainf@hotmail.com
1 2
C65 10U_0805_10V4Z
1 2
C64 10U_0805_10V4Z
1 2
C75 1U_0402_6.3V4Z
1 2
C107 1U_0402_6.3V4Z
1 2
C88 1U_0402_6.3V4Z
1 2
C90 1U_0402_6.3V4Z
1 2
C104 1U_0402_6.3V4Z
1 1
1 2
C73 1U_0402_6.3V4Z
1 2
C74 1U_0402_6.3V4Z
1 2
C105 1U_0402_6.3V4Z
1 2
C36 1U_0402_6.3V4Z
1 2
C55 1U_0402_6.3V4Z
1 2
C89 1U_0402_6.3V4Z
1 2
C71 1U_0402_6.3V4Z
1 2
C106 1U_0402_6.3V4Z
1 2
C49 1U_0402_6.3V4Z
1 2
C50 1U_0402_6.3V4Z
1 2
C79 10U_0805_10V4Z
1 2
C118 10U_0805_10V4Z
1 2
C80 1U_0402_6.3V4Z
2 2
1 2
C100 1U_0402_6.3V4Z
1 2
C131 1U_0402_6.3V4Z
1 2
C91 1U_0402_6.3V4Z
1 2
C69 1U_0402_6.3V4Z
1 2
C133 1U_0402_6.3V4Z
1 2
C150 1U_0402_6.3V4Z
1 2
C151 1U_0402_6.3V4Z
1 2
C92 1U_0402_6.3V4Z
1 2
C95 1U_0402_6.3V4Z
1 2
C99 1U_0402_6.3V4Z
1 2
C144 1U_0402_6.3V4Z
1 2
C59 1U_0402_6.3V4Z
3 3
+1.8VS
L8
1 2
CHB1608U301_0603
+1.8VS +AVDDDI
L43
1 2
CHB1608U301_0603
C48
4 4
C54
1
2
0.1U_0402_16V4Z
+1.2VS
+1.2VS
5A
+1.05VS
+1.05VS
5A
+AVDD
+AVDDQ
+AVDDDI
1
1
2
+CPVDD
C53
C766
1
2
0.1U_0402_16V4Z
C57
C46
+MPVDD
2
2
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
2
1
C768
C767
2
1
2
H=1.9mm
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
2
A
C30
10U_0805_10V4Z
+LPVDD
1
C33
1U_0402_6.3V4Z
2
C47
1
2
0.1U_0402_16V4Z
U21E
M13
M15
M17
M19
N12
N14
N16
N18
P13
P15
P17
P19
R12
R14
R16
R18
T13
T15
T17
T19
U12
U14
U16
U18
V13
V15
V17
V19
W12
W14
W16
W18
A10
F11
F12
F17
G11
G12
G13
G14
G16
G17
G20
H11
H12
H13
H14
H16
H17
H19
H23
H24
L23
L24
N23
P23
P24
C9
B8
D8
H21
AB26
1
+
C650
2
22U_0805_6.3V6M
220U_D2_4VM@
L6
1 2
CHB2012U170_0805
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
AVDD
AVDDQ
AVDDDI
CPVDD
MPVDD
ATI recommend 2.2uF
1
C29
2
+1.8VS
CORE PWR
216CPP4AKA21HK_BGA707
1
C44
0.1U_0402_16V4Z
2
+1.8VS
1
+
2
B
PART 5 OF
6
MEM I/F PWR
POWER
RC410MD
CPU I/F
+AVDD
L5
1 2
1
C32
1U_0402_6.3V4Z
2
C289
470U_D2_2.5VM
B
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDD_18
VDD_18
VDD_18
VDD_18
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_18
VDDA_18
PWR
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDR3
VDDR3
LPVDD
LVDDR18D
LVDDR18A
LVDDR18A
PLLVDD
CHB2012U170_0805
+CPVDD
1
C138
2
10U_0805_10V4Z
C137
AB23
AB24
AC13
AC16
AC19
AC21
AC22
AD13
AD16
AD19
AD21
AD22
AD23
AK21
AK24
AK28
T23
T24
V23
V24
Y23
Y24
0.1A
AB22
AB9
J22
J9
AB7
AC7
AC8
AD9
H4
H5
J6
K6
L7
L8
M7
M8
P7
P8
T7
T8
W7
W8
0.75A
AB8
AC10
AC9
AD10
AE11
AF11
AG11
U7
U8
Y7
Y8
0.1A
G4
G5
J8
C7
H7
H8
H10
+3VS
1
2
+1.8V
2A
+VDDA_12
2.25A
RC_VDDA_18
+VDDQ
+LPVDD
ATI recommend separ ate pure power
+PLLVDD
1
10U_0805_10V4Z
2
L11
1 2
CHB1608U301_0603
1
C114
0.1U_0402_16V4Z
2
1U_0402_6.3V4Z
1 2
C87 0.1U_0402_16V4Z
1 2
C103 0.1U_0402_16V4Z
1 2
C149 0.1U_0402_16V4Z
RC_VDD_18
C70 0.1U_0402_16V4Z
C56 1U_0402_6.3V4Z
C68 1U_0402_6.3V4Z
C63 1U_0402_6.3V4Z
C62 1U_0402_6.3V4Z
C51 1U_0402_6.3V4Z
C45 10U_0805_10V4Z
20mils
20mils
C648
L4
1 2
CHB1608U301_0603
1 2
C134 1U_0402_6.3V4Z
1 2
C135 1U_0402_6.3V4Z
1 2
C58 1U_0402_6.3V4Z
1 2
C67 1U_0402_6.3V4Z
1 2
C31 10U_0805_10V4Z
1 2
C28 10U_0805_10V4Z
L7
1 2
CHB1608U301_0603
1 2
1 2
1 2
1 2
1 2
1 2
1 2
20mils
0.1U_0402_16V4Z
1
C649
2
+1.8VS
1
C158
2
1U_0402_6.3V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
1 2
1
C37
0.1U_0402_16V4Z
2
10U_0805_10V4Z
C
+1.8V
+1.8VS
+VDDA_12
C23 10U_0805_10V4Z
C417 10U_0805_10V4Z
+1.8VS
+1.2VS
C61 10U_0805_10V4Z
C418 10U_0805_10V4Z
C66 10U_0805_10V4Z
L37
CHB2012U170_0805
1
C641
2
D
1 2
C115 10U_0805_10V4Z
1 2
C72 10U_0805_10V4Z
1 2
C119 10U_0805_10V4Z
1 2
C93 10U_0805_10V4Z
1 2
C166 1U_0402_6.3V4Z
1 2
C76 1U_0402_6.3V4Z
1 2
C124 1U_0402_6.3V4Z
1 2
C152 1U_0402_6.3V4Z
1 2
C132 1U_0402_6.3V4Z
1 2
C117 1U_0402_6.3V4Z
1 2
C122 1U_0402_6.3V4Z
1 2
C139 1U_0402_6.3V4Z
1 2
C110 1U_0402_6.3V4Z
1 2
C86 1U_0402_6.3V4Z
1 2
C77 1U_0402_6.3V4Z
1 2
C130 1U_0402_6.3V4Z
1 2
C129 1U_0402_6.3V4Z
1 2
C141 1U_0402_6.3V4Z
1 2
C140 1U_0402_6.3V4Z
1 2
1 2
1 2
C22 1U_0402_6.3V4Z
1 2
C25 1U_0402_6.3V4Z
1 2
C85 1U_0402_6.3V4Z
1 2
C43 1U_0402_6.3V4Z
1 2
C84 1U_0402_6.3V4Z
1 2
C102 1U_0402_6.3V4Z
1 2
C41 1U_0402_6.3V4Z
1 2
C42 1U_0402_6.3V4Z
1 2
C78 1U_0402_6.3V4Z
1 2
C40 1U_0402_6.3V4Z
1 2
1 2
1 2
+
1 2
470U_D2_2.5VM
C414
@
+
1 2
470U_D2_2.5VM
C15
+3VS+VDDQ
+VDDA_12
L58
1 2
CHB2012U170_0805
Place L close to B a ll AB26
Place C between Ball AB26,AA27
L12
1 2
CHB1608U301_0603
1
1
C175
C159
0.1U_0402_16V4Z
2
2
1U_0402_6.3V4Z
2005/11/01 2006/11/30
Compal Secret Data
+1.2VS
+1.8VS+MPVDD
1U_0402_6.3V4Z
Deciphered Date
D
AA23
AA24
AA28
AC11
AC12
AC14
AC15
AC17
AC18
AC20
AC27
AD11
AD12
AD14
AD15
AD17
AD18
AD20
AE30
AF12
AF27
AG14
AG16
AG18
AG21
AG24
AG26
AH11
AJ30
AK12
AK15
AK18
AK2
AK22
AK25
AK29
B30
D14
D17
D20
D24
D27
G10
H15
H18
K23
M12
M14
M16
M18
M23
M24
M26
N13
N15
N17
N19
P12
P14
P16
P18
C60
A13
A16
A19
A22
A25
A29
AJ1
D3
D4
F27
F30
J23
J24
J27
J30
U21F
A2
A9
B1
F3
F4
J3
K8
+PLLVDD
1
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E
R13
VSS
R15
VSS
R17
VSS
R19
VSS
R23
VSS
R24
VSS
R27
VSS
T12
VSS
T14
VSS
T16
VSS
T18
VSS
T30
VSS
PART 6 OF 6
GOUNDRC410MD
216CPP4AKA21HK_BGA707
L10
1 2
1
C81
1U_0402_6.3V4Z
2
CHB1608U301_0603
1
C82
10U_0805_10V4Z
2
Compal Electronics, Inc.
Title
RC410MB PWR/GND
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
AVSSN
AVSSQ
AVSSDI
LPVSS
LVSSR
LVSSR
LVSSR
PLLVSS
CPVSS
MPVSS
+1.8VS
1
C116
10U_0805_10V4Z
2
E
U13
U15
U17
U19
U23
U24
V12
V14
V16
V18
V27
V28
W13
W15
W17
W19
W23
W30
AA3
AA7
AA8
AB5
AB6
AC3
AD3
AD7
AD8
AE8
AF3
AF5
AF7
AF9
AG5
AH10
AH3
AH5
AH6
AH7
AH8
AH9
K5
L3
M3
N5
N6
N7
N8
P3
R3
R7
R8
T5
T6
U3
V3
V7
V8
W5
W6
Y3
C10
B9
C8
J7
G7
G8
G9
H9
H20
AA27
of
943
A
+1.8V
1 1
C143 0.1U_0402_16V4Z
C111 0.1U_0402_16V4Z
1
1
+
C148
@
470U_D2_2.5VM
2
2
+0.9VS
2 2
C445 0.1U_0402_16V4Z
C447 0.1U_0402_16V4Z
1
1
2
2
Layout Note:
Every four par allel termination resistors with two caps,
one is conne cted to ground, the other one is connected
between +1 .8V and +0.9VS. Need to place each parallel
resistor with one cap to GND and one cap between
+1.8V and +0.9VS
3 3
4 4
DDR_SCKE2<8,11>
DDR_SCS#3<8,11>
DDR_ODT3<8,11>
A
C154 0.1U_0402_16V4Z
1
1
2
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to V_DDR_MCH_REF
C443 0.1U_0402_16V4Z
C444 0.1U_0402_16V4Z
1
2
DDR_SCKE2
DDR_SMA17
DDR_SMA12
DDR_SCKE1
DDR_SMA9
DDR_SMA8
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SMA15
DDR_SWE#
DDR_SCAS#
DDR_SCS#3
DDR_ODT3
DDR_SCS#0
1
2
56_1206_8P4R_5%
56_1206_8P4R_5%
56_1206_8P4R_5%
56_1206_8P4R_5%
C439 0.1U_0402_16V4Z
1
2
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
C101 0.1U_0402_16V4Z
1
2
C438 0.1U_0402_16V4Z
1
2
RP11
RP12
RP13
RP14
B
Layout Note:
Place near JDIM1
C162 0.1U_0402_16V4Z
C163 0.1U_0402_16V4Z
1
1
2
2
C437 0.1U_0402_16V4Z
C436 0.1U_0402_16V4Z
1
2
B
1
2
+0.9VS
1
2
C795 0.01U_0402_16V7K@
C796 0.01U_0402_16V7K@
C797 0.01U_0402_16V7K@
C798 0.01U_0402_16V7K@
C799 0.01U_0402_16V7K@
C800 0.01U_0402_16V7K@
C801 0.01U_0402_16V7K@
C802 0.01U_0402_16V7K@
C803 0.01U_0402_16V7K@
C96 0.1U_0402_16V4Z
1
2
C161 0.1U_0402_16V4Z
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
56_0402_5%
1
2
+1.8V
R40
C156 0.1U_0402_16V4Z
C113 0.1U_0402_16V4Z
1
2
C145 0.1U_0402_16V4Z
1
2
C94 0.1U_0402_16V4Z
1
1
2
2
RP1
56_1206_8P4R_5%
RP2
56_1206_8P4R_5%
RP3
56_1206_8P4R_5%
RP4
56_1206_8P4R_5%
DDR_ODT0
C83 0.1U_0402_16V4Z
C
C642 0.1U_0402_16V4Z
1
2
45
DDR_SMA14
36
DDR_SCKE0
27
DDR_SMA11
18
DDR_SMA7
45
DDR_SMA6
36
DDR_SMA4DDR_SMA5
27
DDR_SMA2
18
DDR_SMA0
45
DDR_SMA16
36
DDR_SRAS#
27
18
45
36
27
18
C
C136 0.1U_0402_16V4Z
1
2
DDR_SCKE3
DDR_SCS#2
DDR_ODT1
DDR_SMA13
DDR_SCS#1
DDR_ODT2
D
+1.8V
12
R13
1K_0402_1%
+DDR_VREF1
12
C644 0.1U_0402_16V4Z
C643 0.1U_0402_16V4Z
1
1
2
2
C120 0.1U_0402_16V4Z
C108 0.1U_0402_16V4Z
1
2
1
1
2
2
DDR_SCKE3 <8,11>
DDR_SCS#2 <8,11>
DDR_ODT1 <8,11>
R14
1K_0402_1%
C147 0.1U_0402_16V4Z
C176
1
1
2
2
22U_0805_6.3V6M
C177
22U_0805_6.3V6M
2
C19
0.1U_0402_16V4Z
1
C18 0.1U_0402_16V4Z
1
2
DDR_SCKE0<8>
DDR_SWE#<8,11>
DDR_SCAS#<8,11>
DDR_SCS#1<8>
DDR_ODT2<8>
SB_SMDATA<11,12,16,23>
SB_SMCLK<11,12,16,23>
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
+1.8V +1.8V
+DDR_VREF1
Trace=20mil
JP16
1
C185
1
2
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
QUASAR CA0228-200N22
DDR_DQ8
DDR_DQ10
DDR_DQS#1
DDR_DQS1
DDR_DQ14
DDR_DQ11
DDR_DQ5
DDR_DQ0
DDR_DQS#0
DDR_DQS0
DDR_DQ7 DDR_DQ3
DDR_DQ2 DDR_DQ6
DDR_DQ16
DDR_DQ20
DDR_DQS#2
DDR_DQS2
DDR_DQ23
DDR_DQ22
DDR_DQ25
DDR_DQ28
DDR_DM3
DDR_DQ31
DDR_DQ30
DDR_SCKE0
DDR_SMA17
DDR_SMA12
DDR_SMA9 DDR_SMA7
DDR_SMA8
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SMA15
DDR_SWE#
DDR_SCAS#
DDR_SCS#1
DDR_ODT2
DDR_DQ36
DDR_DQ32
DDR_DQS#4
DDR_DQS4
DDR_DQ39
DDR_DQ34
DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ46
DDR_DQ53
DDR_DQS#6
DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ57
DDR_DM7 DDR_DQS#7
DDR_DQ58
DDR_DQ62
+3VS
C187 0.1U_0402_16V4Z
2.2U_0805_10V6K
1
2
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DIMMA
F
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
CK0
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
DDR_SCKE1
80
82
84
DDR_SMA14
86
88
DDR_SMA11
90
A11
92
A7
A6
A4
A2
A0
BA1
S0#
NC
CK1
SA1
DDR_SMA6
94
96
DDR_SMA4
98
DDR_SMA2
100
DDR_SMA0
102
104
DDR_SMA16
106
DDR_SRAS#
108
DDR_SCS#0
110
112
DDR_ODT0
114
DDR_SMA13
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Reverse
Compal Secret Data
2005/11/01 2006/11/30
E
Deciphered Date
F
DDR_DQ15
DDR_DQ12
DDR_DM1
DDR_DQ13
DDR_DQ9
DDR_DQ1
DDR_DQ4
DDR_DM0
EMC_DDR_CLK1
EMC_DDR_CLK1#
DDR_DQ17
DDR_DQ21
DDR_DM2
DDR_DQ19
DDR_DQ18
DDR_DQ29
DDR_DQ24
DDR_DQS#3
DDR_DQS3
DDR_DQ26
DDR_DQ27
DDR_DQ37
DDR_DQ33
DDR_DM4
DDR_DQ35
DDR_DQ38
DDR_DQ44
DDR_DQ40
DDR_DQS#5
DDR_DQS5
DDR_DQ47DDR_DQ42
DDR_DQ43
DDR_DQ49
DDR_DQ52DDR_DQ48
EMC_DDR_CLK0
EMC_DDR_CLK0#
DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ56DDR_DQ60
DDR_DQ61
DDR_DQS7
DDR_DQ63
DDR_DQ59
+3VS
G
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]
EMC_DDR_CLK1 <8>
EMC_DDR_CLK1# <8>
DDR_SCKE1 <8>
DDR_SRAS# <8,11>
DDR_SCS#0 <8>
DDR_ODT0 <8>
EMC_DDR_CLK0 <8>
EMC_DDR_CLK0# <8>
Title
DDRII-SODIMM2
Size Document Number Rev
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
G
DDR_DQ[0..63] <8,11>
DDR_DQS[0..7] <8,11>
DDR_DQS#[0..7] <8,11>
DDR_DM[0..7] <8,11>
DDR_SMA[0..17] <8,11>
H
of
10 43
H
A
hexainf@hotmail.com
B
C
D
E
+1.8V +1.8V
+DDR_VREF2
Trace=20mil
JP15
1
VREF
3
C184
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
B
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
QUASA_CA0122-200N22_200P
DIMMB
Reverse
DDR_DQ[0..63]<8,10>
1 1
2 2
3 3
4 4
DDR_DQS[0..7]<8,10>
DDR_DQS#[0..7]<8,10>
DDR_DM[0..7]<8,10>
DDR_SMA[0..17]<8,10>
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]
A
DDR_SCKE2<8,10>
DDR_SWE#<8,10>
DDR_SCAS#<8,10>
DDR_SCS#3<8,10>
DDR_ODT3<8,10>
SB_SMDATA<10,12,16,23>
SB_SMCLK<10,12,16,23>
DDR_DQ8
DDR_DQ10
DDR_DQS#1
DDR_DQS1
DDR_DQ14
DDR_DQ11
DDR_DQ5
DDR_DQ0
DDR_DQS#0
DDR_DQS0
DDR_DQ7 DDR_DQ3
DDR_DQ2 DDR_DQ6
DDR_DQ16
DDR_DQ20
DDR_DQS#2
DDR_DQS2 DDR_DM2
DDR_DQ23
DDR_DQ22
DDR_DQ25
DDR_DQ28
DDR_DM3
DDR_DQ31
DDR_DQ30
DDR_SCKE2
DDR_SMA17
DDR_SMA12
DDR_SMA9
DDR_SMA8
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SMA15
DDR_SWE#
DDR_SCAS#
DDR_SCS#3
DDR_ODT3
DDR_DQ36
DDR_DQ32
DDR_DQS#4
DDR_DQS4
DDR_DQ39
DDR_DQ34
DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ53
DDR_DQ48
DDR_DQS#6
DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ60
DDR_DQ57
DDR_DM7
DDR_DQ58
DDR_DQ62
+3VS
2.2U_0805_10V6K
0.1U_0402_16V4Z
C186
1
1
2
2
DQ4
DQ5
DM0
DQ6
DQ7
DQ12
DQ13
DM1
CK0#
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
DQ36
DQ37
DM4
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DM6
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
SAO
VSS
VSS
VSS
VSS
VSS
VSS
CK0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A11
BA1
S0#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
VSS
VSS
VSS
VSS
VSS
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_DQ15
DDR_DQ12
DDR_DM1
DDR_DQ13
DDR_DQ9
DDR_DQ1
DDR_DQ4
DDR_DM0
EMC_DDR_CLK4
EMC_DDR_CLK4#
DDR_DQ17
DDR_DQ21
DDR_DQ19
DDR_DQ18
DDR_DQ29
DDR_DQ24
DDR_DQS#3
DDR_DQS3
DDR_DQ26
DDR_DQ27
DDR_SCKE3
DDR_SMA14
DDR_SMA11
DDR_SMA7
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SMA16
DDR_SRAS#
DDR_SCS#2
DDR_ODT1
DDR_SMA13
DDR_DQ37
DDR_DQ33
DDR_DM4
DDR_DQ35
DDR_DQ38
DDR_DQ44
DDR_DQ40
DDR_DQS#5
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ49
DDR_DQ52
EMC_DDR_CLK3
EMC_DDR_CLK3#
DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ56
DDR_DQ61
DDR_DQS#7
DDR_DQS7
DDR_DQ63
DDR_DQ59
EMC_DDR_CLK4 <8>
EMC_DDR_CLK4# <8>
DDR_SCKE3 <8,10>
DDR_SRAS# <8,10>
DDR_SCS#2 <8,10>
DDR_ODT1 <8,10>
EMC_DDR_CLK3 <8>
EMC_DDR_CLK3# <8>
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+1.8V
C52
470U_D2_2.5VM
+1.8V
C97 0.1U_ 0402_16V4Z
C112 0. 1 U_ 0402_16V4Z
1
1
2
C941 0 . 1 U_0402_16V4Z
1
2
1
2
C942 0 . 1 U_0402_16V4Z
1
2
Compal Secret Data
+
2
2005/11/01 2006/11/30
Layout Note:
Place near JDIM1
C165 0. 1 U_ 0402_16V4Z
1
1
2
2
C943 0 . 1 U_0402_16V4Z
1
1
2
2
+DDR_VREF2
Deciphered Date
C98 0.1U_ 0402_16V4Z
C125 0. 1 U_ 0402_16V4Z
C157 0. 1 U_ 0402_16V4Z
1
2
C944 0 . 1 U_0402_16V4Z
C945 0 . 1 U_0402_16V4Z
1
2
12
R15
1K_0402_1%
12
R16
1K_0402_1%
D
C155 0. 1 U_ 0402_16V4Z
C142 0. 1 U_ 0402_16V4Z
1
1
2
+1.8V
2
1
C21
0.1U_0402_16V4Z
2
1
C20
0.1U_0402_16V4Z
2
1
2
C164 0. 1 U_ 0402_16V4Z
C109 0. 1 U_ 0402_16V4Z
1
2
Title
Size Document Number Re v
Custom
Date: Sheet
C645 0. 1 U_ 0402_16V4Z
1
1
2
2
Compal Electronics, Inc.
DDR-II SODIMM1
HAWAA(LA3141) 0.3
Thursday, January 26, 2006
C647 0. 1 U_ 0402_16V4Z
C646 0. 1 U_ 0402_16V4Z
1
1
2
2
of
E
11 43
A
1 1
+3VS
KC FBM-L1 1-201209-221LMAT_0805
+3VS
+3VS
2 2
3 3
Clock Generator
L16
1 2
L14
1 2
CHB1608U301_0603
L33
1 2
CHB1608U301_0603
4.7U_0805_10V4Z
CLK_EN#<40>
R281
CLK_OK<16,17>
1 2
10K_0402_5%
+CLK_VDD1
+CLK_VDD1
10U_0805_10V4Z
C203
10U_0805_10V4Z
C497
R696 0_0402_5%@
2
G
1
C221
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
12
13
D
Q40
S
2N7002_SOT23
0.1U_0402_16V4Z
1
C188
2
1
C189
2
1
C484
2
1
1
C486
2
2
0.1U_0402_16V4Z
1
C190
0.1U_0402_16V4Z
2
22P_0402_50V8J
22P_0402_50V8J
+CLK_VDD1
CPU_STP#<15>
0.1U_0402_16V4Z
1
C458
C485
2
C501
C500
B
0.1U_0402_16V4Z
1
C456
2
+3VS
EMC_XTALIN_CLK
12
Y3
14.31818MHZ_20P_6X1430004201
SB_SMCLK<10,11,16,23>
SB_SMDATA<10,11,16,23>
EMC_XTALOUT_CLK
C
1- PLACE ALL THE SERIES TERMINATION RESISTORS
AS CLOSE TO CLOCK GEN AS POSSIBLE
2- ROUTE ALL CPUCLK/#, NBCLK/#, ITPCLK/#
AND SCR/# ,AS DIFFERENT PAIR RULE
3- PUT DECO UPLI NG CAPS CLOSE TO CLO CK GEN
POWER PIN
1 2
L13 CHB1608U301_0603
2
2
C182
C457
1
1
10U_0805_10V4Z
R269 4.7K_0402_5%@
R255 0_0402_5%
0.1U_0402_16V4Z
12
R277
1M_0402_5%@
12
12
12
R260
475_0402_1%
45
51
32
35
14
21
3
56
39
44
49
31
36
26
20
15
5
55
38
1
2
6
48
7
8
37
U23
VDDCPU
VDDPCI
VDDATI
VDDSRC
VDDSRC
VDDSRC
VDD48
VDDREF
VDDA
GNDCPU
GNDPCI
GNDATI
GNDSRC
GNDSRC
GNDSRC
GNDSRC
GND
GND
GNDA
XIN
XOUT
VTT_PWRGD#/PD
CPU_STOP#
SCLK
SDATA
IREF
ICS951413CGLFT_TSSOP56
CPUCLKT2_ITP
CPUCLKC2_ITP
CK410#/PCICLK0
USB_48MHZ
TEST_SEL/REF2
ICS951413
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
SRCCLKT0
SRCCLKC0
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
SRCCLKT3
SRCCLKC3
SRCCLKT4
SRCCLKC4
SRCCLKT5
SRCCLKC5
SRCCLKT6
SRCCLKC6
SRCCLKT7
SRCCLKC7
CLKREQA#
CLKREQB#
FS_C
FS_B/REF1
FS_A/REF0
47
46
43
42
41
40
34
33
30
29
27
28
24
25
22
23
18
19
16
17
12
13
10
11
50
4
9
53
54
52
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
SRCCLKT0
SRCCLKC0
SRCCLKT3
SRCCLKC3
SRCCLKT5
SRCCLKC5
10K_0402_5%
48M_SB
FS_C
FS_B/REF1
FS_A/REF0
TEST_SEL/REF2
R283
R771 47_0402_5%
R267 33_0402_5%
FS_C FS_B FS_A CPU SRC PCI REF USB
10
00
0
1
133.33 100.00 33.33 14.318 48.000
1
166.66 100.00 33.33 14.318 48.000
11
100.00 33.33 14.318 48.000100.00
R270 33_0402_5%
1 2
R271 33_0402_5%
1 2
R272 33_0402_5%
1 2
R273 33_0402_5%
1 2
R261 33_0402_5%
1 2
R263 33_0402_5%
1 2
R285 33_0402_5%
1 2
R278 33_0402_5%
1 2
R677 33_0402_5%
1 2
R678 33_0402_5%
1 2
R679 49.9_0402_1%
1 2
R680 49.9_0402_1%
1 2
12
R254 4.7K_0402_5%
1 2
1 2
R268 4.7K_0402_5%@
1 2
1 2
D
R256
R257
R258
1 2
1 2
49.9_0402_1%
R284 10K_0402_5%
R694
R282 4.7K_0402_5%
R253 4.7K_0402_5%
R251 4.7K_0402_5%
R266
33_0402_5%
1 2
R252
33_0402_5%
1 2
1 2
49.9_0402_1%
49.9_0402_1%
CLK_PCIE_MCARD <23>
CLK_PCIE_MCARD# <23>
12
12
0_0402_5%@
+CLK_VDD1
1 2
1 2
1 2
R259
1 2
49.9_0402_1%
12
12
49.9_0402_1%
R286
R279
MINI_CLKREQ#
EMC_CLK_NB_BCLK <8>
EMC_CLK_NB_BCLK# <8>
CLK_BCLK <4>
CLK_BCLK# <4>
12
12
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
R262
R264
+CLK_VDD1
+CLK_VDD1
MINI_CLKREQ# <23>
CPU_BSEL2 <5>
CPU_BSEL1 <5,8>
CPU_BSEL0 <5>
EMC_CLK_SB_14M <16>
EMC_CLK_NB_14M <8>
CLK_14M_SIO <29>
E
CLK_SB_ALINK <15>
CLK_SB_ALINK# <15>
CLK_NB_ALINK <7>
CLK_NB_ALINK# <7>
1
C931
10P_0402_50V8J
2
CLK_48M_SB <16>
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
ClockGen ICS 951413
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
D
Date: Sheet
E
12 43
of
A
hexainf@hotmail.com
B
C
D
E
TV-OUT CONNECTOR
1 1
NB_LUMA<8>
NB_CRMA<8>
75_0603_1%
2 2
3 3
R57
12
12
0.1U_0402_16V4Z@
+LCDVDD
Reduce LUMA_1 and CRMA_1 length
As short as possible
NB_LUMA
NB_CRMA
R59
75_0603_1%
1
C202
1
2
TVOUT@
82P_0402_50V8J
2
C213
TVOUT@
82P_0402_50V8J
LCD/PANEL BD. Conn.
+3VS
BKOFF#<28>
1
C406
L40 KC F B M-L11-201209-221LMAT_0805
1 2
2
1 2
L38 KC FBM-L11-201209-221LMAT_0805
EMC_NB_TXOUT2+<8>
EMC_NB_TXOUT1+<8>
EMC_NB_TXOUT0+<8>
1. Y ground
1
D8
22P_0402_50V8J
C204
@
1 2
1 2
L15 CHB1608B121_0603
TVOUT@
22P_0402_50V8J
C224
@
1 2
1 2
L17 CHB1608B121_0603
TVOUT@
1 2
R209 10K_0402_5%
D19 CH751H-40_SC76
KC FBM-L11-201209-221LMAT_0805
B+ B+
EMC_NB_TXCLK+<8>
EMC_NB_TXCLK-<8>
EMC_NB_TXOUT2-<8>
EMC_NB_TXOUT1-<8>
EMC_NB_TXOUT0-<8>
DISPOFF#
21
L39
1 2
+LCDVDD_C
EMC_NB_TXCLK+
EMC_NB_TXCLK-
EMC_NB_TXOUT2+
EMC_NB_TXOUT2EMC_NB_TXOUT1EMC_NB_TXOUT1+
EMC_NB_TXOUT0EMC_NB_TXOUT0+
1
2
2
3
DAN217_SC59@
LUMA_2
CRMA_2
C410
1 2
220P_0402_50V9J
ACES_88242-3000
1
2
C223
TVOUT@
82P_0402_50V8J
DISPOFF# DAC_BRIG
D7
DAN217_SC59@
C200
TVOUT@
82P_0402_50V8J
JP1
1
3
5
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
2
4
6
8
2. C ground
3. Y (luminance+sync)
4. C (crominance)
+3VS
JP18
ALLTO_C10877-104A1-L_4P
1
1
2
5
2
5
3
6
3
6
4
4
TVOUT@
KC FBM-L11-201209-221LMAT_0805
B+_LCDB+_LCD
INVT_PWM
NB_EDID_CLKNB_EDID_DATA
EMC_NB_TZCLKEMC_NB_TZCLK+
EMC_NB_TZOUT1EMC_NB_TZOUT1+
EMC_NB_TZOUT2+
EMC_NB_TZOUT2EMC_NB_TZOUT0+
EMC_NB_TZOUT0-
DAC_BRIG <28>
INVT_PWM <28>
NB_EDID_CLK <8>NB_EDID_DATA<8>
EMC_NB_TZCLK- <8>
EMC_NB_TZCLK+ <8>
EMC_NB_TZOUT1- <8>
EMC_NB_TZOUT1+ <8>
EMC_NB_TZOUT2+ <8>
EMC_NB_TZOUT2- <8>
EMC_NB_TZOUT0+ <8>
EMC_NB_TZOUT0- <8>
PANEL +LCDVDD CTRL CKT
NB_ENVDD<8>
+LCDVDD
R10
470_0805_5%
2N7002_SOT23
+LCDVDD Width: 40mils
L42
12
NB_ENVDD
2
G
Q3
12
100K_0402_5%
0.047U_0402_16V7K
+3VS
12
13
D
S
+3VALW
Q2
G
2
R9
1
C13
2
1
C407
0.1U_0402_16V4Z@
2
S
AO3413_SOT23
D
1 3
12
R7
100_0402_5%
12
R8
100K_0402_5%
Q34
G
2
+3VS
80mil
S
AO3413_SOT23
D
1 3
80mil
1
C404
4.7U_0805_10V4Z
2
1
C411
4.7U_0805_10V4Z
2
+LCDVDD
1
C405
0.1U_0402_16V4Z
2
NB_EDID_CLK
NB_EDID_DATA
4 4
A
B
1 2
C408 47P_0402_50V8J
1 2
C409 47P_0402_50V8J
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Re v
Custom
Date: Sheet of
Compal Electronics, Inc.
TV-OUT, LVDS CONNECTOR
HAWAA(LA3141) 0.3
Thursday, January 26, 2006
E
13 43
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