Page 1
A
hexainf@hotmail.com
1 1
B
C
D
E
HAWAA
2 2
LA-3141
3 3
uFCPGA Yonah/ ATi-RC410MD(A12)/ ATi-SB450(A13)
REV 0.3 Schematic
2006-01-26 Rev.0.3
4 4
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Black Diagram
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Friday, January 27, 2006
D
Date: Sheet
E
of
143
Page 2
A
B
C
D
E
HAWAA LA-3141 FUNCTION BLOCK DIAGRAM
4 4
CRT Conn.
PAGE 14
LCD Conn
PAGE 13
LVDS & TV-OUT Conn.
3 3
2 2
CARDBUS
ENE 1410
PAGE 21
1394
TSB43AB21
PAGE 26
CARD BUS
SOCKET
PAGE 22
PAGE 13
Mini Card
FOR WLAN
PAGE 23
PCI BUS
33MHz (3.3V)
LAN
RTL8100CL
PAGE 20
RJ-45
PAGE 20
PCI-E X 1
LPC BUS 33MHz (3.3V)
TPM
SLB 9635
PAGE 31
Mobile Yonah
uFCPGA-479 Pin
PAGE 4,5,6
FSB
533MHz/667MHz
ATI-RC410MD/E
VGA M10P Embeded
707 pin BGA
2.5GHz(1.2V)
Bandwidth 500MB
ATI-SB450
564 pin BGA
Embedded
Controller
ENE KB910
BIOS(1M)
& I/O PORT
PAGE 29 PAGE 30
A-Link Express x 4
PAGE 28
PAGE 7,8,9
PAGE 15,16,17,18,19
Scan KB
Thermal Sensor
ADM1032ARM
400/533/667MHz
(1.8V)
Memory Bus
Single channel
480MHz(5V)
SATA
3.3V,5V 1.5GHz(150MB/s)
Secondary
ATA-100 (5V)
AZALIA
24MHz(3.3V)
Clock Generator
ICS951413CGLFT
PAGE 4
SO-DIMM x 2(DDRII)
BANK 0,1,2,3
USB 2.0 Port *4
0,2,4,6
SATA HDD
IDE ODD
HD CODEC
ALC 861
PAGE 27
PAGE 17
PAGE 26
PAGE 24
MDC
Connector
PAGE 33
MOM
PAGE 41,42
PAGE 12
PAGE 10,11
Audio Amplifier
CPU VID
TPA0232
PAGE 25
PAGE 5
FANController
RTC Battery
DC/DC Interface
LID/Kill Switch
Power Buttom
DCIN&DETECTOR
BATT CONN/OTP
CHARGER
3V/5V/12V
DDR_1.8V/0.9VEP
1.8VCORE
1.5V/PROCHOT
CPU_CORE
PAGE 32
PAGE 15
PAGE 33
PAGE 31
PAGE 34
PAGE 35
PAGE 36
PAGE 37
PAGE 39
PAGE 38
PAGE 40
PAGE 40
1 1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Black Diagram
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
D
Date: Sheet
E
243
of
Page 3
A
hexainf@hotmail.com
Voltage Rails
B
C
D
E
Power Plan e Description
VIN
1 1
B+
+CPU_CORE
+CPUVID
+1.2VS 1.2VS for PCI-Express OFFON OFF
+0.9VS 0.9V switched power rail
+1.5VS
+1.8VS 1.8VS switched power rail OFFOFFON
+1.8VALW 1.8V always on power rail ON*ONON
+1.8V
+3VALW
+3VS
+5VS
+RTCVCC
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.2V switched power rail for CPU AGTL Bus
Yonah
1.8V power rail
3.3V always on power rail
3.3V switched power rai l
5V always on power rail
5V switched power rail
RTC power
S1 S3 S5
ON
ON ONONON
ON OFF
ON OFF
ON OFF OFF
ON OFF OFF
ON ON
ON
ON
ON+5VALW
ON
ON
OFF
ON
OFF
ON
ON
OFF
OFF
OFF
ON*ON
OFF
ON*
OFF
ON
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
Board ID Table for AD channel
Vcc
Ra/Rc
Board ID
0
1
2 2
2
3
4
5
Note : ON* means that this power plane is ON only with AC power available, otherwise it i s OFF.
6
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
ENE 1410
LAN
3 3
EC SM Bus1 address
Device
Smart Battery
SB450 SM Bus address
Device
Clock Generator
(ICS951413BGLFT)
DDRII DIMM0
4 4
DDRII DIMM1
AD20
AD22
AD16 PIRQA01394
2 PIRQB
1PIRQG
EC SM Bus2 address
Address Address
Address
1101 001Xb
1010 0100b
1010 0110b
A4
A6
Device
ADM1032
1001 110X b0001 011X b
Board ID
0
1
2
3
4
5
6
7
BTN ID
0
1
2
3
4
5
6
7
SIGNAL
3.3V +/- 5%
100K +/- 5%
Rb / Rd
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC7
PCB Revision
BTN Status
1 Buttons
6 Buttons
0.1
0.2
HIGH
LOW
LOW
AD_BID
0.436 V
0.712 V
1.036 V
1.935 V
2.500 V
SLP_S5#STATE
HIGHHIGH
HIGH
HIGH
HIGH
LOWLOW
minV
0 V
+VALW
+V
+VSSLP_S 3#
Clock
ON
OFF
OFF
OFF
V
AD_BID
ONON
LOW
OFF
OFF
OFF
max
0 V
ON
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
typV
AD_BID
0 V
0.289 V0.250 V0.216 V
0.503 V
0.819 V
0.538 V
0.875 V
1.264 V1.185 V
1.650 V1.453 V
2.200 V
3.300 V
1.759 V
2.341 V
3.300 V
PCB RevisionSKU ID
0
1
2
3
4
5
─
SKU 1
SKU 2
SKU 3
SKU 4(JP)
SKU 5
6
7
BTO Function BOM structure
1394 1394@
Wireless LAN WLAN@
TV-OUT TVOUT@
TPM TPM@
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Notes List
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
D
Date: Sheet
E
of
343
Page 4
5
4
3
2
1
H_A#[3..31]<7>
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
D D
H_REQ#[0..4]<7>
H_ADSTB#0<7>
H_RS#[0..2]<7>
R482 1K_0402_5%@
R484 51_0402_5%
H_ADSTB#1<7>
CLK_BCLK<12>
CLK_BCLK#<12>
H_ADS#<7>
H_BNR#<7>
H_BPRI#<7>
H_BR0#<7>
H_DEFER#<7>
H_DRDY#<7>
H_HIT#<7>
H_HITM#<7>
H_LOCK#<7>
H_RESET#<7,15>
H_TRDY#<7>
H_DBSY#<7>
H_DPSLP#<15>
H_DPRSTP#<40>
H_DPWR#<7>
H_PWRGOOD<15>
H_CPUSLP#<15>
12
12
C C
B B
B
H_THERMDA, H_THERMDC routing together.
Trace width / Spacing = 10 / 10 mil
A A
For B-0 stepping engineering samples (ES) of Celeron M
processor need to pop this 51 ohm resistor.
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
H_ADSTB#1
CLK_BCLK
CLK_BCLK#
H_ADS#
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DRDY#
H_HIT#
H_HITM#
H_IERR#
H_LOCK#
H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
ITP_DBRESET#
H_DBSY#
H_DPSLP# H_BR0#
H_DPRSTP#
H_DPWR#
PROCHOT#
C
H_PWRGOOD
H_CPUSLP#
ITP_TCK
ITP_TDI
ITP_TDO
TEST1
TEST2
ITP_TMS
ITP_TRST#
H_THERMDA
H_THERMDC
H_THERMTRIP#
A
JCPU1A
J4
A3#
L4
A4#
M3
A5#
K5
A6#
M1
A7#
N2
A8#
J1
A9#
N3
A10#
P5
A11#
P2
A12#
L1
A13#
P4
A14#
P1
A15#
R1
A16#
Y2
A17#
U5
A18#
R3
A19#
W6
A20#
U4
A21#
Y5
A22#
U2
A23#
R4
A24#
T5
ADDR GROUP
A25#
T3
A26#
W3
A27#
W5
A28#
Y4
A29#
W2
A30#
Y1
A31#
K3
REQ0#
H2
REQ1#
K2
REQ2#
J3
REQ3#
L5
REQ4#
L2
ADSTB0#
V4
ADSTB1#
A22
BCLK0
AD4
AD3
AD1
AC4
C20
D24
AC2
AC1
D21
AC5
AA6
AB3
C26
D25
AB5
AB6
A21
H1
E2
G5
F1
H5
F21
G6
E4
D20
H4
B1
F3
F4
G3
G2
E1
B5
E5
D6
D7
A24
A25
C7
HOST CLK
BCLK1
ADS#
BNR#
BPRI#
BR0#
DEFER#
DRDY#
HIT#
CONTROL
HITM#
IERR#
LOCK#
RESET#
RS0#
RS1#
RS2#
TRDY#
BPM0#
BPM1#
BPM2#
BPM3#
DBR#
DBSY#
DPSLP#
DPRSTP#
DPWR#
PRDY#
PREQ#
PROCHOT#
PWRGOOD
SLP#
TCK
TDI
TDO
TEST1
TEST2
TMS
TRST#
THERMAL
THERMDA
DIODE
THERMDC
THERMTRIP#
FOX_PZ47903-2741-42_YONAH
YONAH
MISC
DATA GROUP
LEGACY CPU
D10#
D11#
D12#
D13#
D14#
D15#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
DINV0#
DINV1#
DINV2#
DINV3#
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
A20M#
FERR#
IGNNE#
INIT#
LINT0
LINT1
STPCLK#
SMI#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D8#
D9#
F24
E26
H22
F23
G25
E25
E23
K24
G24
J24
J23
H26
F26
K22
H25
N22
K25
P26
R23
L25
L22
L23
M23
P25
P22
P23
T24
R24
L26
T25
N24
AA23
AB24
V24
V26
W25
U23
U25
U22
AB25
W22
Y23
AA26
Y26
Y22
AC26
AA24
AC22
AC23
AB22
AA21
AB21
AC25
AD20
AE22
AF23
AD24
AE21
AD21
AE25
AF25
AF22
AF26
J26
M26
V23
AC20
H23
M24
W24
AD23
G22
N25
Y25
AE24
A6
A5
C4
B3
C6
B4
R766 0_0402_5%
D5
A3
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20H_A#23
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_A20M#
H_FERR#
H_IGNNE#
H_INIT#
H_INTR
H_STPCLK#
H_SMI#
12
H_NMI
H_DINV#0 <7>
H_DINV#1 <7>
H_DINV#2 <7>
H_DINV#3 <7>
H_A20M# <15>
H_FERR# <15>
H_IGNNE# <15>
H_INIT# <15>
H_INTR <15>
H_NMI <15>
H_STPCLK# <15>
H_SMI# <15>
H_D#0H_A#3
E22
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
H_D#[0..63] <7>
+CPU_CORE
+1.05VS
12
R463
@
47K_0402_5%
1 2
C665
+1.05VS
H_THERMTRIP#
12
0.1U_0603_25V7K@
1 2
R466
56_0402_5%
R464
47K_0402_5%
2
3 1
MAINPWON <16,34,35,37>
Q53
MMBT3904_SOT23
A
+1.05VS
R468
470_0402_5%
H_DPRSTP#
R471 0_0402_5%
B
MMBT3904_SOT23
H_DSTBN#[0..3] <7>
H_DSTBP#[0..3] <7>
C666 180P_0402_50V8J@
1 2
C667 180P_0402_50V8J@
1 2
C668 180P_0402_50V8J@
1 2
C669 180P_0402_50V8J@
1 2
C670 180P_0402_50V8J@
1 2
C671 180P_0402_50V8J@
1 2
C672 180P_0402_50V8J@
1 2
C673 180P_0402_50V8J@
1 2
C674 180P_0402_50V8J@
1 2
C675 180P_0402_50V8J@
1 2
2005/11/01 2006/11/30
1 2
12
Q55
2
R472 470_0402_5%
3 1
1 2
Place Caps Close to CPU Socket
H_INIT#
H_A20M#
H_CPUSLP#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
H_IGNNE#
H_PWRGOOD
H_FERR#
H_DPSLP#
Compal Secret Data
Deciphered Date
R480 390_0402_5%@
R481 390_0402_5%@
R485 200_0402_5%
R486 390_0402_5%@
R487 390_0402_5%@
R489 390_0402_5%@
R491 390_0402_5%@
R492 390_0402_5%@
R493 332_0402_1%
R494 56_0402_5%
R495 200_0402_5%
2
DPRSLPVR <15,40>
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
12
12
1 2
C664
2200P_0402_50V7K
EC_SMB_CK2<28>
EC_SMB_DA2<28>
+3VS
1
C663
0.1U_0402_16V4Z
1
2
75_0402_5%
PROCHOT#
H_THERMDA
H_THERMDC
+1.05VS
12
R469
2
3
8
7
U31
D+
ALERT#
D-
THERM#
SCLK
SDATA
ADM1032ARM_RM8
12
R470
56_0402_5%
2
2
VDD1
GND
B
+3VALW
C
E
1
6
4
5
12
R467
1K_0402_5%
1
Q54
PMBT3904_SOT23
3
H_PROCHOT# <16>
C
H_DPRSTP#
H_RESET#
ITP_TMS
ITP_TDI
ITP_TDO
H_IERR#
+1.05VS
ITP_DBRESET#
ITP_TRST#
ITP_TCK
Compal Electronics, Inc.
Title
Yonah(1/2)-GTLITP
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
R473 56_0402_5%@
R474 54.9_0402_1%@
R475 40.2_0402_1%
R476 150_0402_1%
R477 54.9_0402_1%@
R478 200_0402_5%
R479 56_0402_5%
R483 150_0402_1%
R488 680_0402_5%
R490 27.4_0402_1%
1 2
1
12
12
12
12
12
12
12
12
12
443
12
R465
+3VALW
of
10K_0402_5%@
+1.05VS
Page 5
5
hexainf@hotmail.com
4
3
2
1
Length match within 25 mils
Layout close CPU
C676
10U_0805_10V6M
20mils
1
2
VCCSENSE
VSSSENSE
1
C677
2
0.01U_0402_16V7K
CPU_VID0<40>
CPU_VID1<40>
CPU_VID2<40>
CPU_VID3<40>
CPU_VID4<40>
CPU_VID5<40>
CPU_VID6<40>
CPU_BSEL0<12>
CPU_BSEL1<8,12>
CPU_BSEL2<12>
H_PSI#<40>
+GTL_REF0
+CPU_CORE
+1.05VS
H_PSI#
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
COMP0
COMP1
COMP2
COMP3
JCPU1B
AF7
VCCSENSE
AE7
VSSSENSE
B26
VCCA
K6
VCCP
J6
VCCP
M6
VCCP
N6
VCCP
YONAH
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
PSI#
VID0
VID1
VID2
VID3
VID4
VID5
VID6
GTLREF
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
FOX_PZ47903-2741-42_YONAH
AD26
AB20
AA20
AF20
AE20
AB18
AB17
AA18
AA17
AD18
AD17
AC18
AC17
AF18
AF17
K21
M21
N21
R21
V21
W21
G21
AE6
AD6
AF5
AE5
AF4
AE3
AF2
AE2
B22
B23
C21
R26
U26
AF1
D22
C23
C24
AA1
AA4
AB2
AA3
B25
T6
R6
J21
T21
V6
U1
V1
E7
D2
F6
D3
C1
M4
N5
T2
V3
B2
C3
T22
AB26
VSS
AA25
VSS
AD25
VSS
AE26
VSS
AB23
VSS
AC24
VSS
AF24
VSS
AE23
VSS
AA22
VSS
AD22
VSS
AC21
VSS
AF21
VSS
AB19
VSS
AA19
VSS
AD19
VSS
AC19
VSS
AF19
VSS
AE19
VSS
AB16
VSS
AA16
VSS
AD16
VSS
AC16
VSS
AF16
VSS
AE16
VSS
AB13
VSS
AA14
VSS
AD13
VSS
AC14
VSS
AF13
VSS
AE14
VSS
AB11
VSS
AA11
VSS
AD11
VSS
AC11
VSS
AF11
VSS
AE11
VSS
AB8
VSS
AA8
VSS
AD8
VSS
AC8
VSS
AF8
VSS
AE8
VSS
AA5
VSS
AD5
VSS
AC6
VSS
AF6
VSS
AB4
VSS
AC3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF3
AE4
AB1
AA2
AD2
AE1
B6
C5
F5
E6
H6
J5
M5
L6
P6
R5
V5
U6
Y6
A4
D4
E3
H3
G4
K4
L3
P3
N4
T4
U3
Y3
W4
D1
C2
F2
G1
POWER, GROUNG, RESERVED SIGNALS AND NC
+CPU_CORE
D D
+1.05VS
R_A
12
+GTL_REF0
R498
1K_0402_1%
R_B
12
R499
2K_0402_1%
VCCSENSE<40>
VSSSENSE<40>
R496 100_0402_1%
1 2
R497 100_0402_1%
1 2
+1.5VS
Layout close CPU PIN AD26
0.5 inch (max)
C C
R500 27.4_0402_1%
1 2
R501 54.9_0402_1%
1 2
R502 27.4_0402_1%
1 2
R503 54.9_0402_1%
CPU_BSEL CPU_BSEL0 CPU_BSEL1
133
166
B B
00
0
1
CPU_BSEL2
1
1
TRACE CLOSELY CPU < 0.5'
COMP0, COMP2 layout : Width 18mils and Space 25mils
COMP1, COMP3 layout : Space 25mils
1 2
+CPU_CORE
JCPU1C
AE18
VCC
AE17
VCC
AB15
VCC
AA15
VCC
AD15
VCC
AC15
VCC
AF15
VCC
AE15
VCC
AB14
VCC
AA13
VCC
AD14
VCC
AC13
VCC
AF14
VCC
AE13
VCC
AB12
VCC
AA12
VCC
AD12
VCC
AC12
VCC
AF12
VCC
AE12
VCC
AB10
VCC
AB9
VCC
AA10
VCC
AA9
VCC
AD10
VCC
AD9
VCC
AC10
VCC
AC9
VCC
AF10
VCC
AF9
VCC
AE10
AD7
AC7
POWER, GROUND
VCC
AE9
VCC
AB7
VCC
AA7
VCC
VCC
VCC
B20
VCC
A20
VCC
F20
VCC
E20
VCC
B18
VCC
B17
VCC
A18
VCC
A17
VCC
D18
VCC
D17
VCC
C18
VCC
C17
VCC
F18
VCC
F17
VCC
E18
VCC
E17
VCC
B15
VCC
A15
VCC
D15
VCC
C15
VCC
F15
VCC
E15
VCC
B14
VCC
A13
VCC
D14
VCC
C13
VCC
F14
VCC
E13
VCC
B12
VCC
A12
VCC
D12
VCC
C12
VCC
F12
VCC
E12
VCC
B10
VCC
B9
VCC
A10
VCC
A9
VCC
D10
VCC
D9
VCC
C10
VCC
C9
VCC
F10
VCC
F9
VCC
E10
VCC
E9
VCC
B7
VCC
A7
VCC
F7
VCC
FOX_PZ47903-2741-42_YONAH
YONAH
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K1
J2
M2
N1
T1
R2
V2
W1
A26
D26
C25
F25
B24
A23
D23
E24
B21
C22
F22
E21
B19
A19
D19
C19
F19
E19
B16
A16
D16
C16
F16
E16
B13
A14
D13
C14
F13
E14
B11
A11
D11
C11
F11
E11
B8
A8
D8
C8
F8
E8
G26
K26
J25
M25
N26
T26
R25
V25
W26
H24
G23
K23
L24
P24
N23
T23
U24
Y24
W23
H21
J22
M22
L21
P21
R22
V22
U21
Y21
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Yonah(2/2)-PWR/GND
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
of
543
Page 6
5
Place these inside
socket cavity on L6
(North side
1
C678
22U_0805_6.3V6M
2
1
C688
22U_0805_6.3V6M
2
1
C698
22U_0805_6.3V6M
2
1
C704
22U_0805_6.3V6M
2
Secondary)
+CPU_CORE
D D
+CPU_CORE
+CPU_CORE
+CPU_CORE
C C
1
C679
22U_0805_6.3V6M
2
1
C689
22U_0805_6.3V6M
2
1
C699
22U_0805_6.3V6M
2
1
C705
22U_0805_6.3V6M
2
4
1
C680
22U_0805_6.3V6M
2
1
C690
22U_0805_6.3V6M
2
1
C700
22U_0805_6.3V6M
2
1
C706
22U_0805_6.3V6M
2
1
C681
22U_0805_6.3V6M
2
1
C691
22U_0805_6.3V6M
2
1
C701
22U_0805_6.3V6M
2
1
C707
22U_0805_6.3V6M
2
1
2
1
2
1
2
1
2
3
C682
22U_0805_6.3V6M
C692
22U_0805_6.3V6M
C702
22U_0805_6.3V6M
C708
22U_0805_6.3V6M
1
C683
22U_0805_6.3V6M
2
1
C693
22U_0805_6.3V6M
2
1
C703
22U_0805_6.3V6M
2
1
C709
22U_0805_6.3V6M
2
1
C684
22U_0805_6.3V6M
2
1
C694
22U_0805_6.3V6M
2
1
2
1
2
22uF 0805 X5R -> 85 degree C
C685
22U_0805_6.3V6M
C695
22U_0805_6.3V6M
2
1
2
1
2
C686
22U_0805_6.3V6M
C696
22U_0805_6.3V6M
1
C687
22U_0805_6.3V6M
2
1
C697
22U_0805_6.3V6M
2
1
High Frequence Decoupling
Near VCORE regulator.
+CPU_CORE
South Side S econdary
B B
+1.05VS
1
+
C716
2
A A
5
330U_D2E_2.5VM_R9
C710
@
1
+
2
330U_D_2VM
9mOhm
7343
PS CAP
1
+
C711
2
330U_D_2VM
1
C717
0.1U_0402_10V7K
2
C712
@
1
+
2
330U_D_2VM
1
+
C713
2
330U_V_2.5VM @
C714
1
+
2
330U_D_2VM
1
+
North Side Secondary
C715
2
330U_V_2.5VM
ESR <= 1.5m ohm
Capacitor > 1980uF
H=1.9mm H=1.9mm
1
C718
0.1U_0402_10V7K
2
4
1
C719
0.1U_0402_10V7K
2
1
C720
0.1U_0402_10V7K
2
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C721
0.1U_0402_10V7K
2
3
1
C722
0.1U_0402_10V7K
2
2005/11/01 2006/11/30
Compal Secret Data
Place these inside
socket cavity on L8
(North side
Secondary)
Deciphered Date
Compal Electronics, Inc.
Title
Yonah Bypass
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
643
of
Page 7
A
hexainf@hotmail.com
H_A#[3..31]<4>
H_REQ#[0..4]<4>
H_RS#[0..2]<4>
U21A
H_A#3
G28
CPU_A3#
H_A#4
H26
CPU_A4#
H_A#5
G27
CPU_A5#
H_A#6
G30
CPU_A6#
H_A#7
G29
CPU_A7#
H_A#8
G26
CPU_A8#
H_A#9
H28
M28
K29
K30
M30
K27
M29
K26
N28
N25
N24
D25
E11
G22
J28
H25
K28
H29
J29
K24
K25
F29
G25
F26
F28
E29
H27
J26
L28
L29
L26
L25
L27
F25
F24
E23
E25
G24
F23
E27
C11
D23
G23
E26
F22
D26
E24
D11
B11
H22
CPU_A9#
CPU_A10#
CPU_A11#
CPU_A12#
CPU_A13#
CPU_A14#
CPU_A15#
CPU_A16#
CPU_REQ0#
CPU_REQ1#
CPU_REQ2#
CPU_REQ3#
CPU_REQ4#
CPU_ADSTB0#
CPU_A17#
CPU_A18#
CPU_A19#
CPU_A20#
CPU_A21#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_A25#
CPU_A26#
CPU_A27#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_ADSTB1#
CPU_ADS#
CPU_BNR#
CPU_BPRI#
CPU_DEFER#
CPU_DRDY#
CPU_DBSY#
CPU_LOCK#
CPU_CPURSET#
CPU_RS2#
CPU_RS1#
CPU_RS0#
CPU_TRDY#
CPU_HIT#
CPU_HITM#
CPU_COMP_N
CPU_COMP_P
CPU_VREF
RESERVED0
RESERVED1
CPU_DPWR#
PART 1 OF 6
ADDR. GROUP
0
ADDR. GROUP
1
CPU I/F
CONTROLMISC.
RC410MD
216CPP4AKA21HK_BGA707
R30
12
R234
12
+CPU_VREF
1
C123
2
A
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_RS#2
H_RS#1
H_RS#0
HSCOMP
HRCOMP
1 1
H_ADSTB#0<4>
2 2
3 3
4 4
+1.05VS
220P_0402_50V9J
H_ADSTB#1<4>
H_ADS#<4>
H_BNR#<4>
H_BPRI#<4>
H_DEFER#<4>
H_DRDY#<4>
H_DBSY#<4>
H_LOCK#<4>
H_RESET#<4,15>
H_TRDY#<4>
H_HIT#<4>
H_HITM#<4>
24.9_0402_1%
49.9_0402_1%
Place C close
to Ball H22
H_BR0#<4>
H_DPWR#<4>
DATA GROUP 0
CPU_DSTBN0#
CPU_DSTBP0#
DATA GROUP 1
CPU_DSTBN1#
CPU_DSTBP1#
DATA GROUP 2
CPU_DSTBN2#
CPU_DSTBP2#
DATA GROUP
3
CPU_DSTBN3#
CPU_DSTBP3#
B
CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#
CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_DBI0#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_DBI1#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_DBI2#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#
CPU_DBI3#
CPU_VREF
Trace=12Mil
Space=15Mil
+CPU_VREF
B
H_D#[0..63] <4>
H_DINV#[0..3] <4>
H_DSTBN#[0..3] <4>
H_DSTBP#[0..3] <4>
H_D#0
E28
H_D#1
D28
H_D#2
D29
H_D#3
C29
H_D#4
D30
H_D#5
C30
H_D#6
B29
H_D#7
C28
H_D#8
C26
H_D#9
B25
H_D#10
B27
H_D#11
C25
H_D#12
A27
H_D#13
C24
H_D#14
A24
H_D#15
B26
H_DINV#0
C27
H_DSTBN#0
A28
H_DSTBP#0
B28
H_D#16
C19
H_D#17
C23
H_D#18
C20
H_D#19
C22
H_D#20
B22
H_D#21
B23
H_D#22
C21
H_D#23
B24
H_D#24
E21
H_D#25
B21
H_D#26
B20
H_D#27
G19
H_D#28
F21
H_D#29
B19
H_D#30
E20
H_D#31
D21
H_DINV#1
A21
H_DSTBN#1
D22
H_DSTBP#1
E22
H_D#32
C18
H_D#33
F19
H_D#34
E19
H_D#35
A18
H_D#36
D19
H_D#37
B18
H_D#38
C17
H_D#39
B17
H_D#40
E17
H_D#41
B16
H_D#42
C15
H_D#43
A15
H_D#44
B15
H_D#45
F16
H_D#46
G18
H_D#47
F18
H_DINV#2
C16
H_DSTBN#2
D18
H_DSTBP#2
E18
H_D#48
E16
H_D#49
D16
H_D#50
C14
H_D#51
B14
H_D#52
E15
H_D#53
D15
H_D#54
C13
H_D#55
E14
H_D#56
F13
H_D#57
B13
H_D#58
A12
H_D#59
C12
H_D#60
E12
H_D#61
D13
H_D#62
D12
H_D#63
B12
H_DINV#3
E13
H_DSTBN#3
F15
H_DSTBP#3
G15
+1.05VS
1
C121
2
1U_0402_6.3V4Z
12
R38
49.9_0402_1%
12
R37
100_0402_1%
+1.2VS
SB_A_RXN0
SB_A_RXP0
SB_A_RXN1
SB_A_RXP1
NB_A_RXN0
NB_A_RXP0
NB_A_RXN1
NB_A_RXP1
C
ATI recommendation R33, R34
Place R
Close to Ball
C753 0.1U_0402_10V7K
C754 0.1U_0402_10V7K
C755 0.1U_0402_10V7K
C756 0.1U_0402_10V7K
CLK_NB_ALINK#<12>
CLK_NB_ALINK<12>
SB_A_RXN[0..3]
SB_A_RXP[0..3]
NB_A_RXN[0..3]
NB_A_RXP[0..3]
1 2
1 2
1 2
1 2
12
12
12
12
R2910K_0402_1%
R348.25K_0402_1%
R3382.5_0402_1%
R28150_0402_1%
PCE_RXISET
PCE_TXISET
PCE_NCAL
PCE_PCAL
SB_A_RXN[0..3] <15>
SB_A_RXP[0..3] <15>
NB_A_RXN[0..3] <15>
NB_A_RXP[0..3] <15>
10 mils
10 mils
10 mils
10 mils
NB_A_TXN0
NB_A_TXP0
NB_A_TXP1
AJ12
AK13
AG12
AH12
AJ11
AJ10
AK10
AG10
AG9
AF10
AA4
AA5
AB3
AB4
AC5
AC6
AD4
AD5
AK9
AE9
J4
J5
L4
K4
L5
L6
M4
M5
P4
N4
P5
P6
R4
R5
T3
T4
U5
U6
V4
V5
W3
W4
Y5
Y6
L2
K2
U21C
GFX_RX0N
GFX_RX0P
GFX_RX1N
GFX_RX1P
GFX_RX2N
GFX_RX2P
GFX_RX3N
GFX_RX3P
GFX_RX4N
GFX_RX4P
GFX_RX5N
GFX_RX5P
GFX_RX6N
GFX_RX6P
GFX_RX7N
GFX_RX7P
GFX_RX8N
GFX_RX8P
GFX_RX9N
GFX_RX9P
GFX_RX10N
GFX_RX10P
GFX_RX11N
GFX_RX11P
GFX_RX12N
GFX_RX12P
GFX_RX13N
GFX_RX13P
GFX_RX14N
GFX_RX14P
GFX_RX15N
GFX_RX15P
PCE_ISET
PCE_TXISET
PCE_NCAL
PCE_PCAL
SB_TX0N
SB_TX0P
SB_TX1N
SB_TX1P
SB_RX0N
SB_RX0P
SB_RX1N
SB_RX1P
SB_CLKN
SB_CLKP
A-LINK EXPRESS I/F
216CPP4AKA21HK_BGA707
PCIE_WLAN_TX_P1
D
PART 3 OF 6
PCI EXPRESS I/F
PCI EXPRESS I/F
RC410MD
GPP_TX0N/SB_TX2N
GPP_TX0P/SB_TX2P
GPP_TX1N/SB_TX3N
GPP_TX1P/SB_TX3P
GPP_RX0N/SB_RX2N
GPP_RX0P/SB_RX2P
GPP_RX1N/SB_RX3N
GPP_RX1P/SB_RX3P
C758 0.1U_0402_10V7K
C757 0.1U_0402_10V7K
To SB A-PCIE Link
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
D
1 2
1 2
GFX_TX0N
GFX_TX0P
GFX_TX1N
GFX_TX1P
GFX_TX2N
GFX_TX2P
GFX_TX3N
GFX_TX3P
GFX_TX4N
GFX_TX4P
GFX_TX5N
GFX_TX5P
GFX_TX6N
GFX_TX6P
GFX_TX7N
GFX_TX7P
GFX_TX8N
GFX_TX8P
GFX_TX9N
GFX_TX9P
GFX_TX10N
GFX_TX10P
GFX_TX11N
GFX_TX11P
GFX_TX12N
GFX_TX12P
GFX_TX13N
GFX_TX13P
GFX_TX14N
GFX_TX14P
GFX_TX15N
GFX_TX15P
GFX_CLKN
GFX_CLKP
GPP_TX2N
GPP_TX2P
GPP_TX3N
GPP_TX3P
GPP_RX2N
GPP_RX2P
GPP_RX3N
GPP_RX3P
E
N2
N1
R2
P2
T1
R1
U2
T2
V1
V2
W2
W1
AA2
Y2
AB1
AA1
AC2
AB2
AD1
AD2
AE2
AE1
AG2
AF2
AH1
AG1
AJ2
AH2
AJ4
AJ3
AJ5
AK4
M1
M2
NB_A_TXN2
AJ9
NB_A_TXP2
AJ8
NB_A_TXN3
AF6
NB_A_TXP3
AE6
PCIE_WLAN_TX_N1
AK6
PCIE_WLAN_TX_P1NB_A_TXN1
AJ6
AF4
AE4
NB_A_RXN2
AG8
NB_A_RXP2
AF8
NB_A_RXN3
AG7
NB_A_RXP3
AG6
PCIE_WLAN_C_RX_N1
AJ7
PCIE_WLAN_C_RX_P1
AK7
AH4
AG4
PCIE_WLAN_C_TX_N1PCIE_WLAN_TX_N1
PCIE_WLAN_C_TX_P1
Title
RC410MD-FSB, PCIE,A-PCIE
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Date: Sheet
PCIE_WLAN_C_RX_N1 <23>
PCIE_WLAN_C_RX_P1 <23>
Compal Electronics, Inc.
Thursday, January 26, 2006
SB_A_RXN2
C8040.1U_0402_10V7K
12
SB_A_RXP2
C8050.1U_0402_10V7K
12
SB_A_RXN3
C8060.1U_0402_10V7K
12
SB_A_RXP3
C8070.1U_0402_10V7K
12
PCIE_WLAN_C_TX_N1 <23>
PCIE_WLAN_C_TX_P1 <23>
E
of
743
Page 8
A
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]
1 1
+1.8V
R42
12
1
1K_0402_1%
1K_0402_1%
2 2
2
0.1U_0402_10V7K
12
R46
1
2
0.1U_0402_10V7K
MEM_VMO DE: 1. 8V: DDR2
+1.8V
R242
12
61.9_0603_1%
R237
12
3 3
C435
@
61.9_0603_1%
Place these R and C
close to relative Ball.
MEM_COMPN
MEM_COMPP
1
1
C450
@
2
2
0.47U_0603_10V7K
C172
+DDR_VREF
C174
MEM_CAP1
MEM_CAP2
0.47U_0603_10V7K
DDR_DQ[0..63] <10,11>
DDR_DQS[0..7] <10,11>
DDR_DQS#[0..7] <10,11>
DDR_DM[0..7] <10,11>
DDR_SMA[0..17] <10,11>
DDR_SRAS#<10,11>
DDR_SCAS#<10,11>
DDR_SWE#<10,11>
EMC_DDR_CLK0#<10>
EMC_DDR_CLK0<10>
EMC_DDR_CLK1#<10>
EMC_DDR_CLK1<10>
EMC_DDR_CLK3#<11>
EMC_DDR_CLK3<11>
EMC_DDR_CLK4#<11>
EMC_DDR_CLK4<11>
DDR_SCKE0<10>
DDR_SCKE1<10>
DDR_SCKE2<10,11>
DDR_SCKE3<10,11>
DDR_SCS#0<10>
DDR_SCS#1<10>
DDR_SCS#2<10,11>
DDR_SCS#3<10,11>
DDR_ODT0<10>
DDR_ODT1<10,11>
DDR_ODT2<10>
DDR_ODT3<10,11>
+1.8V
DDR_SMA0
DDR_SMA1
DDR_SMA2
DDR_SMA3
DDR_SMA4
DDR_SMA5
DDR_SMA6
DDR_SMA7
DDR_SMA8
DDR_SMA9
DDR_SMA10
DDR_SMA11
DDR_SMA12
DDR_SMA13
DDR_SMA14
DDR_SMA15
DDR_SMA16
DDR_SMA17
DDR_SCS#0
DDR_SCS#1
DDR_SCS#2
DDR_SCS#3
DDR_ODT0
DDR_ODT1
DDR_ODT2
DDR_ODT3
R43 1K_0402_5%
1 2
MEM_CAP1
MEM_CAP2
MEM_COMPP
MEM_COMPN
+DDR_VREF
10mil
10mil
10mil
10mil
20mil
DDR_DQS#0
DDR_DQS0
DDR_DQS#1
DDR_DQS1
DDR_DQS#2
DDR_DQS2
DDR_DQS#3
DDR_DQS3
DDR_DQS#4
DDR_DQS4
DDR_DQS#5
DDR_DQS5
DDR_DQS#6
DDR_DQS6
DDR_DQS#7
DDR_DQS7
AK27
AJ27
AH26
AJ26
AH25
AJ25
AH24
AH23
AJ24
AJ23
AH27
AH22
AJ22
AF28
AJ21
AG27
AJ28
AH21
AJ29
AG28
AH30
AC26
AC25
AF16
AE16
AC24
AC23
AG17
AF17
W29
W28
AH20
AJ20
AE24
AE21
AH29
AG29
AH28
AF29
AG30
AE28
AC30
AD28
AJ14
AJ15
AE29
AB27
AH17
AJ18
AF15
AE14
AE22
AF22
AF26
AE25
W26
W27
AB30
AB29
V29
V30
Y30
N30
R25
P25
R30
R29
U21B
MEM_A0
MEM_A1
MEM_A2
MEM_A3
MEM_A4
MEM_A5
MEM_A6
MEM_A7
MEM_A8
MEM_A9
MEM_A10
MEM_A11
MEM_A12
MEM_A13
MEM_A14
MEM_A15
MEM_A16
MEM_A17
MEM_RAS#
MEM_CAS#
MEM_WE#
MEM_CK0N
MEM_CK0P
MEM_CK1N
MEM_CK1P
MEM_CK2N
MEM_CK2P
MEM_CK3N
MEM_CK3P
MEM_CK4N
MEM_CK4P
MEM_CK5N
MEM_CK5P
MEM_CKE0
MEM_CKE1
MEM_CKE2
MEM_CKE3
MEM_CS#0
MEM_CS#1
MEM_CS#2
MEM_CS#3
MEM_ODT0
MEM_ODT1
MEM_ODT2/RSV2
MEM_ODT3/RSV3
MEM_VMODE
MEM_CAP1
MEM_CAP2
MEM_COMPP
MEM_COMPN
MEM_VREF
MEM_DQS0N
MEM_DQS0P
MEM_DQS1N
MEM_DQS1P
MEM_DQS2N
MEM_DQS2P
MEM_DQS3N
MEM_DQS3P
MEM_DQS4N
MEM_DQS4P
MEM_DQS5N
MEM_DQS5P
MEM_DQS6N
MEM_DQS6P
MEM_DQS7N
MEM_DQS7P
NB STRAPING PINS
FSB SPEED
BM_REQ#
4 4
EMC_NB_CRT_VSYNC
EMC_NB_CRT_HSYNC
BM_REQ# EMC_NB_CRT_HSYNC EMC_NB_CRT_VSYNC
166MHZ
133MHZ
0
0
R223 4.7K_0402_5%@
1 2
R222 4.7K_0402_5%
1 2
R228
1 2
4.7K_0402_5%
R20
4.7K_0402_5%
MMBT3904_SOT23
A
1
0
+3VS
12
R227
4.7K_0402_5%
12
Q35
3 1
R229
2
4.7K_0402_5%
+3VS
1
1
12
+1.05VS
+3VS
12
R749
4.7K_0402_5%
B
PART 2 OF
6
ADDRESS
MEMORY I/F
RC410MD
DATA CLKMISC
216CPP4AKA21HK_BGA707
CPU_BSEL1 <5,12>
B
DATA
MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8
MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15
MEM_DQ16
MEM_DQ17
MEM_DQ18
MEM_DQ19
MEM_DQ20
MEM_DQ21
MEM_DQ22
MEM_DQ23
MEM_DQ24
MEM_DQ25
MEM_DQ26
MEM_DQ27
MEM_DQ28
MEM_DQ29
MEM_DQ30
MEM_DQ31
MEM_DQ32
MEM_DQ33
MEM_DQ34
MEM_DQ35
MEM_DQ36
MEM_DQ37
MEM_DQ38
MEM_DQ39
MEM_DQ40
MEM_DQ41
MEM_DQ42
MEM_DQ43
MEM_DQ44
MEM_DQ45
MEM_DQ46
MEM_DQ47
MEM_DQ48
MEM_DQ49
MEM_DQ50
MEM_DQ51
MEM_DQ52
MEM_DQ53
MEM_DQ54
MEM_DQ55
MEM_DQ56
MEM_DQ57
MEM_DQ58
MEM_DQ59
MEM_DQ60
MEM_DQ61
MEM_DQ62
MEM_DQ63
MEM_DM0
MEM_DM1
MEM_DM2
MEM_DM3
MEM_DM4
MEM_DM5
MEM_DM6
MEM_DM7
STRP_DATA
NB_DDC_CLK
MMBT3904_SOT23
C
DDR_DQ0
AJ16
DDR_DQ1
AH16
DDR_DQ2
AJ19
DDR_DQ3
AH19
DDR_DQ4
AH15
DDR_DQ5
AK16
DDR_DQ6
AH18
DDR_DQ7
AK19
DDR_DQ8
AF13
DDR_DQ9
AF14
DDR_DQ10
AE19
DDR_DQ11
AF19
DDR_DQ12
AE13
DDR_DQ13
AG13
DDR_DQ14
AF18
DDR_DQ15
AE17
DDR_DQ16
AF20
DDR_DQ17
AF21
DDR_DQ18
AG23
DDR_DQ19
AF24
DDR_DQ20
AG19
DDR_DQ21
AG20
DDR_DQ22
AG22
DDR_DQ23
AF23
DDR_DQ24
AD25
DDR_DQ25
AG25
AE27
AD27
AE23
AD24
AE26
AD26
AA25
Y26
W24
U25
AA26
Y25
V26
W25
AC28
AC29
AA29
Y29
AD30
AD29
AA30
Y28
U27
T27
N26
M27
U26
T26
P27
P26
U29
T29
P29
N29
U28
T28
P28
N27
AJ17
AG15
AE20
AF25
Y27
AB28
R26
R28
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31
DDR_DQ32
DDR_DQ33
DDR_DQ34
DDR_DQ35
DDR_DQ36
DDR_DQ37
DDR_DQ38
DDR_DQ39
DDR_DQ40
DDR_DQ41
DDR_DQ42
DDR_DQ43
DDR_DQ44
DDR_DQ45
DDR_DQ46
DDR_DQ47
DDR_DQ48
DDR_DQ49
DDR_DQ50
DDR_DQ51
DDR_DQ52
DDR_DQ53
DDR_DQ54
DDR_DQ55
DDR_DQ56
DDR_DQ57
DDR_DQ58
DDR_DQ59
DDR_DQ60
DDR_DQ61
DDR_DQ62
DDR_DQ63
DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3
DDR_DM4
DDR_DM5
DDR_DM6
DDR_DM7
1 2
4.7K_0402_5%
1 2
4.7K_0402_5%@
Q5
2
3 1
R225
R220
1 2
2K_0402_1%
EMC_CLK_NB_14M<12>
+3VS
+3VS
R11
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
NB_LUMA<13>
NB_CRMA<13>
1 2
R27 75_0402_1%
EMC_NB_CRT_R<14>
EMC_NB_CRT_G<14>
EMC_NB_CRT_B<14>
EMC_NB_CRT_HSYNC<14>
EMC_NB_CRT_VSYNC<14>
1 2
R232 715_0402_1%
NB_DDC_CLK<14>
NB_DDC_DATA<14>
EMC_CLK_NB_BCLK<12>
EMC_CLK_NB_BCLK#<12>
NB_EDID_CLK<13>
NB_EDID_DATA<13>
R230
1 2
Low: Normal Mode(Fixed)
High: Test Mode
R219
1 2
4.7K_0402_5%
R226
1 2
4.7K_0402_5%
R23
1 2
4.7K_0402_5%@
STRP_DATA: DEBUG STRAP
DEFAULT: 1
0: MEMORY CHANNEL STRAPING
1: EEPROM STRAPING
NB_DDC_CLK: CPU VCC SEL
DEFAULT: 1 1: DESKTOP CPU 0: MOBILE CPU
SB_PWRGD# <17>
2005/11/01 2006/11/30
NB_COMPS
NB_DDC_CLK
NB_DDC_DATA
C422
12
15P_0402_50V8D@
R218 0_0402_5%
1 2
R217 10K_0402_5%
NB_EDID_CLK
NB_EDID_DATA
NB_DVI_DDCDATA
STRP_DATA
TESTMODE
1.8K_0402_5%
NB_EDID_CLK
NB_EDID_DATA
NB_DVI_DDCDATA
Compal Secret Data
RSET
15mil
12
NB_14M
U21D
F9
D9
E9
F10
E10
D10
C3
B3
B10
B2
C2
G1
F1
G2
J1
K1
D2
C1
H3
D1
C4
AH13
AJ13
R22
1 2
4.7K_0402_5%
Deciphered Date
Y
C
COMP
RED
GREEN
BLUE
DACHSYNC
DACVSYNC
RSET
DACSCL
DACSDA
OSCIN
OSCOUT
TVCLKIN
CPU_CLKP
CPU_CLKN
I2C_CLK
I2C_DATA
DDC_DATA
STRP_DATA
TESTMODE
THERMALDIODE_P
THERMALDIODE_N
D
CRT & TV
I/F
CLK. GEN.
216CPP4AKA21HK_BGA707
LVDS_ENBKL
LVDS_ENVDD
D
PART 4 OF 6
RC410MD
SUS_STAT#
NB_PWRGD
E
EMC_NB_TZOUT0-
TXOUT_U0N
TXOUT_U0P
TXOUT_U1N
TXOUT_U1P
TXOUT_U2N
TXOUT_U2P
TXOUT_U3N
TXOUT_U3P
TXOUT_L0N
TXOUT_L0P
TXOUT_L1N
TXOUT_L1P
LVDS
TXOUT_L2N
TXOUT_L2P
TXOUT_L3N
TXOUT_L3P
LVDS_BLON
LVDS_DIGON
LVDS_BLEN
SYSRESET#
SUS_STAT#
POWERGOOD
1
2
Title
Size Document Number Re v
Custom
Date: Sheet
B4
EMC_NB_TZOUT0+
A4
EMC_NB_TZOUT1-
B5
EMC_NB_TZOUT1+
C6
EMC_NB_TZOUT2-
B6
EMC_NB_TZOUT2+
A6
B7
A7
EMC_NB_TZCLK-
F7
TXCLK_UN
TXCLK_UP
TXCLK_LN
TXCLK_LP
BMREQ#
TMDS_HPD
+1.8V
+3VALW
A
B
4
A
5
B
EMC_NB_TZCLK+
F8
EMC_NB_TXOUT0-
E5
EMC_NB_TXOUT0+
F5
EMC_NB_TXOUT1-
D5
EMC_NB_TXOUT1+
C5
EMC_NB_TXOUT2-
E6
EMC_NB_TXOUT2+
D6
E7
E8
EMC_NB_TXCLK-
G6
EMC_NB_TXCLK+
F6
LVDS_ENBKL
G3
LVDS_ENVDD
E2
F2
NB_RST#
A3
SUS_STAT#
AH14
NB_PWRGD
E3
BM_REQ#
H2
J2
12
R236
220K_0402_5%
D21
1 2
2 1
CH751H-40_SC76
D20
2 1
CH751H-40_SC76
14
U5A
P
3
O
G
SN74LVC08APW_TSSOP14
7
+3VALW
14
U5B
P
6
O
G
SN74LVC08APW_TSSOP14
7
R216
10K_0402_5%
Compal Electronics, Inc.
RC410MD-DDR/DISP/MISC
HAWAA(LA3141) 0.3
Thursday, January 26, 2006
R21 4.7K_0402_5%@
1 2
1 2
R224
NB_RST#
ENBKL <28>
NB_ENVDD <13>
E
EMC_NB_TZOUT0- <13>
EMC_NB_TZOUT0+ <13>
EMC_NB_TZOUT1- <13>
EMC_NB_TZOUT1+ <13>
EMC_NB_TZOUT2- <13>
EMC_NB_TZOUT2+ <13>
EMC_NB_TZCLK- <13>
EMC_NB_TZCLK+ <13>
EMC_NB_TXOUT0- <13>
EMC_NB_TXOUT0+ <13>
EMC_NB_TXOUT1- <13>
EMC_NB_TXOUT1+ <13>
EMC_NB_TXOUT2- <13>
EMC_NB_TXOUT2+ <13>
EMC_NB_TXCLK- <13>
EMC_NB_TXCLK+ <13>
4.7K_0402_5%@
NB_RST# <15>
NB_PW RGD <17>
BM_REQ# <15>
NB_SUS_STAT# <16>
843
of
Page 9
A
hexainf@hotmail.com
1 2
C65 10U_0805_10V4Z
1 2
C64 10U_0805_10V4Z
1 2
C75 1U_0402_6.3V4Z
1 2
C107 1U_0402_6.3V4Z
1 2
C88 1U_0402_6.3V4Z
1 2
C90 1U_0402_6.3V4Z
1 2
C104 1U_0402_6.3V4Z
1 1
1 2
C73 1U_0402_6.3V4Z
1 2
C74 1U_0402_6.3V4Z
1 2
C105 1U_0402_6.3V4Z
1 2
C36 1U_0402_6.3V4Z
1 2
C55 1U_0402_6.3V4Z
1 2
C89 1U_0402_6.3V4Z
1 2
C71 1U_0402_6.3V4Z
1 2
C106 1U_0402_6.3V4Z
1 2
C49 1U_0402_6.3V4Z
1 2
C50 1U_0402_6.3V4Z
1 2
C79 10U_0805_10V4Z
1 2
C118 10U_0805_10V4Z
1 2
C80 1U_0402_6.3V4Z
2 2
1 2
C100 1U_0402_6.3V4Z
1 2
C131 1U_0402_6.3V4Z
1 2
C91 1U_0402_6.3V4Z
1 2
C69 1U_0402_6.3V4Z
1 2
C133 1U_0402_6.3V4Z
1 2
C150 1U_0402_6.3V4Z
1 2
C151 1U_0402_6.3V4Z
1 2
C92 1U_0402_6.3V4Z
1 2
C95 1U_0402_6.3V4Z
1 2
C99 1U_0402_6.3V4Z
1 2
C144 1U_0402_6.3V4Z
1 2
C59 1U_0402_6.3V4Z
3 3
+1.8VS
L8
1 2
CHB1608U301_0603
+1.8VS +AVDDDI
L43
1 2
CHB1608U301_0603
C48
4 4
C54
1
2
0.1U_0402_16V4Z
+1.2VS
+1.2VS
5A
+1.05VS
+1.05VS
5A
+AVDD
+AVDDQ
+AVDDDI
1
1
2
+CPVDD
C53
C766
1
2
0.1U_0402_16V4Z
C57
C46
+MPVDD
2
2
1
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
2
1
C768
C767
2
1
2
H=1.9mm
1U_0402_6.3V4Z
1U_0402_6.3V4Z
0.1U_0402_16V4Z
1
2
A
C30
10U_0805_10V4Z
+LPVDD
1
C33
1U_0402_6.3V4Z
2
C47
1
2
0.1U_0402_16V4Z
U21E
M13
M15
M17
M19
N12
N14
N16
N18
P13
P15
P17
P19
R12
R14
R16
R18
T13
T15
T17
T19
U12
U14
U16
U18
V13
V15
V17
V19
W12
W14
W16
W18
A10
F11
F12
F17
G11
G12
G13
G14
G16
G17
G20
H11
H12
H13
H14
H16
H17
H19
H23
H24
L23
L24
N23
P23
P24
C9
B8
D8
H21
AB26
1
+
C650
2
22U_0805_6.3V6M
220U_D2_4VM@
L6
1 2
CHB2012U170_0805
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CORE
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
VDD_CPU
AVDD
AVDDQ
AVDDDI
CPVDD
MPVDD
ATI recommend 2.2uF
1
C29
2
+1.8VS
CORE PWR
216CPP4AKA21HK_BGA707
1
C44
0.1U_0402_16V4Z
2
+1.8VS
1
+
2
B
PART 5 OF
6
MEM I/F PWR
POWER
RC410MD
CPU I/F
+AVDD
L5
1 2
1
C32
1U_0402_6.3V4Z
2
C289
470U_D2_2.5VM
B
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDDR_MEM
VDD_18
VDD_18
VDD_18
VDD_18
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_12
VDDA_18
VDDA_18
PWR
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDA_18
VDDR3
VDDR3
LPVDD
LVDDR18D
LVDDR18A
LVDDR18A
PLLVDD
CHB2012U170_0805
+CPVDD
1
C138
2
10U_0805_10V4Z
C137
AB23
AB24
AC13
AC16
AC19
AC21
AC22
AD13
AD16
AD19
AD21
AD22
AD23
AK21
AK24
AK28
T23
T24
V23
V24
Y23
Y24
0.1A
AB22
AB9
J22
J9
AB7
AC7
AC8
AD9
H4
H5
J6
K6
L7
L8
M7
M8
P7
P8
T7
T8
W7
W8
0.75A
AB8
AC10
AC9
AD10
AE11
AF11
AG11
U7
U8
Y7
Y8
0.1A
G4
G5
J8
C7
H7
H8
H10
+3VS
1
2
+1.8V
2A
+VDDA_12
2.25A
RC_VDDA_18
+VDDQ
+LPVDD
ATI recommend separ ate pure power
+PLLVDD
1
10U_0805_10V4Z
2
L11
1 2
CHB1608U301_0603
1
C114
0.1U_0402_16V4Z
2
1U_0402_6.3V4Z
1 2
C87 0.1U_0402_16V4Z
1 2
C103 0.1U_0402_16V4Z
1 2
C149 0.1U_0402_16V4Z
RC_VDD_18
C70 0.1U_0402_16V4Z
C56 1U_0402_6.3V4Z
C68 1U_0402_6.3V4Z
C63 1U_0402_6.3V4Z
C62 1U_0402_6.3V4Z
C51 1U_0402_6.3V4Z
C45 10U_0805_10V4Z
20mils
20mils
C648
L4
1 2
CHB1608U301_0603
1 2
C134 1U_0402_6.3V4Z
1 2
C135 1U_0402_6.3V4Z
1 2
C58 1U_0402_6.3V4Z
1 2
C67 1U_0402_6.3V4Z
1 2
C31 10U_0805_10V4Z
1 2
C28 10U_0805_10V4Z
L7
1 2
CHB1608U301_0603
1 2
1 2
1 2
1 2
1 2
1 2
1 2
20mils
0.1U_0402_16V4Z
1
C649
2
+1.8VS
1
C158
2
1U_0402_6.3V4Z
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
1 2
1
C37
0.1U_0402_16V4Z
2
10U_0805_10V4Z
C
+1.8V
+1.8VS
+VDDA_12
C23 10U_0805_10V4Z
C417 10U_0805_10V4Z
+1.8VS
+1.2VS
C61 10U_0805_10V4Z
C418 10U_0805_10V4Z
C66 10U_0805_10V4Z
L37
CHB2012U170_0805
1
C641
2
D
1 2
C115 10U_0805_10V4Z
1 2
C72 10U_0805_10V4Z
1 2
C119 10U_0805_10V4Z
1 2
C93 10U_0805_10V4Z
1 2
C166 1U_0402_6.3V4Z
1 2
C76 1U_0402_6.3V4Z
1 2
C124 1U_0402_6.3V4Z
1 2
C152 1U_0402_6.3V4Z
1 2
C132 1U_0402_6.3V4Z
1 2
C117 1U_0402_6.3V4Z
1 2
C122 1U_0402_6.3V4Z
1 2
C139 1U_0402_6.3V4Z
1 2
C110 1U_0402_6.3V4Z
1 2
C86 1U_0402_6.3V4Z
1 2
C77 1U_0402_6.3V4Z
1 2
C130 1U_0402_6.3V4Z
1 2
C129 1U_0402_6.3V4Z
1 2
C141 1U_0402_6.3V4Z
1 2
C140 1U_0402_6.3V4Z
1 2
1 2
1 2
C22 1U_0402_6.3V4Z
1 2
C25 1U_0402_6.3V4Z
1 2
C85 1U_0402_6.3V4Z
1 2
C43 1U_0402_6.3V4Z
1 2
C84 1U_0402_6.3V4Z
1 2
C102 1U_0402_6.3V4Z
1 2
C41 1U_0402_6.3V4Z
1 2
C42 1U_0402_6.3V4Z
1 2
C78 1U_0402_6.3V4Z
1 2
C40 1U_0402_6.3V4Z
1 2
1 2
1 2
+
1 2
470U_D2_2.5VM
C414
@
+
1 2
470U_D2_2.5VM
C15
+3VS+VDDQ
+VDDA_12
L58
1 2
CHB2012U170_0805
Place L close to B a ll AB26
Place C between Ball AB26,AA27
L12
1 2
CHB1608U301_0603
1
1
C175
C159
0.1U_0402_16V4Z
2
2
1U_0402_6.3V4Z
2005/11/01 2006/11/30
Compal Secret Data
+1.2VS
+1.8VS+MPVDD
1U_0402_6.3V4Z
Deciphered Date
D
AA23
AA24
AA28
AC11
AC12
AC14
AC15
AC17
AC18
AC20
AC27
AD11
AD12
AD14
AD15
AD17
AD18
AD20
AE30
AF12
AF27
AG14
AG16
AG18
AG21
AG24
AG26
AH11
AJ30
AK12
AK15
AK18
AK2
AK22
AK25
AK29
B30
D14
D17
D20
D24
D27
G10
H15
H18
K23
M12
M14
M16
M18
M23
M24
M26
N13
N15
N17
N19
P12
P14
P16
P18
C60
A13
A16
A19
A22
A25
A29
AJ1
D3
D4
F27
F30
J23
J24
J27
J30
U21F
A2
A9
B1
F3
F4
J3
K8
+PLLVDD
1
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E
R13
VSS
R15
VSS
R17
VSS
R19
VSS
R23
VSS
R24
VSS
R27
VSS
T12
VSS
T14
VSS
T16
VSS
T18
VSS
T30
VSS
PART 6 OF 6
GOUNDRC410MD
216CPP4AKA21HK_BGA707
L10
1 2
1
C81
1U_0402_6.3V4Z
2
CHB1608U301_0603
1
C82
10U_0805_10V4Z
2
Compal Electronics, Inc.
Title
RC410MB PWR/GND
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
AVSSN
AVSSQ
AVSSDI
LPVSS
LVSSR
LVSSR
LVSSR
PLLVSS
CPVSS
MPVSS
+1.8VS
1
C116
10U_0805_10V4Z
2
E
U13
U15
U17
U19
U23
U24
V12
V14
V16
V18
V27
V28
W13
W15
W17
W19
W23
W30
AA3
AA7
AA8
AB5
AB6
AC3
AD3
AD7
AD8
AE8
AF3
AF5
AF7
AF9
AG5
AH10
AH3
AH5
AH6
AH7
AH8
AH9
K5
L3
M3
N5
N6
N7
N8
P3
R3
R7
R8
T5
T6
U3
V3
V7
V8
W5
W6
Y3
C10
B9
C8
J7
G7
G8
G9
H9
H20
AA27
of
943
Page 10
A
+1.8V
1 1
C143 0.1U_0402_16V4Z
C111 0.1U_0402_16V4Z
1
1
+
C148
@
470U_D2_2.5VM
2
2
+0.9VS
2 2
C445 0.1U_0402_16V4Z
C447 0.1U_0402_16V4Z
1
1
2
2
Layout Note:
Every four par allel termination resistors with two caps,
one is conne cted to ground, the other one is connected
between +1 .8V and +0.9VS. Need to place each parallel
resistor with one cap to GND and one cap between
+1.8V and +0.9VS
3 3
4 4
DDR_SCKE2<8,11>
DDR_SCS#3<8,11>
DDR_ODT3<8,11>
A
C154 0.1U_0402_16V4Z
1
1
2
2
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to V_DDR_MCH_REF
C443 0.1U_0402_16V4Z
C444 0.1U_0402_16V4Z
1
2
DDR_SCKE2
DDR_SMA17
DDR_SMA12
DDR_SCKE1
DDR_SMA9
DDR_SMA8
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SMA15
DDR_SWE#
DDR_SCAS#
DDR_SCS#3
DDR_ODT3
DDR_SCS#0
1
2
56_1206_8P4R_5%
56_1206_8P4R_5%
56_1206_8P4R_5%
56_1206_8P4R_5%
C439 0.1U_0402_16V4Z
1
2
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
1 8
2 7
3 6
4 5
C101 0.1U_0402_16V4Z
1
2
C438 0.1U_0402_16V4Z
1
2
RP11
RP12
RP13
RP14
B
Layout Note:
Place near JDIM1
C162 0.1U_0402_16V4Z
C163 0.1U_0402_16V4Z
1
1
2
2
C437 0.1U_0402_16V4Z
C436 0.1U_0402_16V4Z
1
2
B
1
2
+0.9VS
1
2
C795 0.01U_0402_16V7K@
C796 0.01U_0402_16V7K@
C797 0.01U_0402_16V7K@
C798 0.01U_0402_16V7K@
C799 0.01U_0402_16V7K@
C800 0.01U_0402_16V7K@
C801 0.01U_0402_16V7K@
C802 0.01U_0402_16V7K@
C803 0.01U_0402_16V7K@
C96 0.1U_0402_16V4Z
1
2
C161 0.1U_0402_16V4Z
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
56_0402_5%
1
2
+1.8V
R40
C156 0.1U_0402_16V4Z
C113 0.1U_0402_16V4Z
1
2
C145 0.1U_0402_16V4Z
1
2
C94 0.1U_0402_16V4Z
1
1
2
2
RP1
56_1206_8P4R_5%
RP2
56_1206_8P4R_5%
RP3
56_1206_8P4R_5%
RP4
56_1206_8P4R_5%
DDR_ODT0
C83 0.1U_0402_16V4Z
C
C642 0.1U_0402_16V4Z
1
2
45
DDR_SMA14
36
DDR_SCKE0
27
DDR_SMA11
18
DDR_SMA7
45
DDR_SMA6
36
DDR_SMA4DDR_SMA5
27
DDR_SMA2
18
DDR_SMA0
45
DDR_SMA16
36
DDR_SRAS#
27
18
45
36
27
18
C
C136 0.1U_0402_16V4Z
1
2
DDR_SCKE3
DDR_SCS#2
DDR_ODT1
DDR_SMA13
DDR_SCS#1
DDR_ODT2
D
+1.8V
12
R13
1K_0402_1%
+DDR_VREF1
12
C644 0.1U_0402_16V4Z
C643 0.1U_0402_16V4Z
1
1
2
2
C120 0.1U_0402_16V4Z
C108 0.1U_0402_16V4Z
1
2
1
1
2
2
DDR_SCKE3 <8,11>
DDR_SCS#2 <8,11>
DDR_ODT1 <8,11>
R14
1K_0402_1%
C147 0.1U_0402_16V4Z
C176
1
1
2
2
22U_0805_6.3V6M
C177
22U_0805_6.3V6M
2
C19
0.1U_0402_16V4Z
1
C18 0.1U_0402_16V4Z
1
2
DDR_SCKE0<8>
DDR_SWE#<8,11>
DDR_SCAS#<8,11>
DDR_SCS#1<8>
DDR_ODT2<8>
SB_SMDATA<11,12,16,23>
SB_SMCLK<11,12,16,23>
Security Classification
Issued Date
THIS SHEET OF ENGI NEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORI ZED BY COMPAL ELECTRONICS, INC. NEITHER THI S SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
E
+1.8V +1.8V
+DDR_VREF1
Trace=20mil
JP16
1
C185
1
2
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
QUASAR CA0228-200N22
DDR_DQ8
DDR_DQ10
DDR_DQS#1
DDR_DQS1
DDR_DQ14
DDR_DQ11
DDR_DQ5
DDR_DQ0
DDR_DQS#0
DDR_DQS0
DDR_DQ7 DDR_DQ3
DDR_DQ2 DDR_DQ6
DDR_DQ16
DDR_DQ20
DDR_DQS#2
DDR_DQS2
DDR_DQ23
DDR_DQ22
DDR_DQ25
DDR_DQ28
DDR_DM3
DDR_DQ31
DDR_DQ30
DDR_SCKE0
DDR_SMA17
DDR_SMA12
DDR_SMA9 DDR_SMA7
DDR_SMA8
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SMA15
DDR_SWE#
DDR_SCAS#
DDR_SCS#1
DDR_ODT2
DDR_DQ36
DDR_DQ32
DDR_DQS#4
DDR_DQS4
DDR_DQ39
DDR_DQ34
DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ46
DDR_DQ53
DDR_DQS#6
DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ57
DDR_DM7 DDR_DQS#7
DDR_DQ58
DDR_DQ62
+3VS
C187 0.1U_0402_16V4Z
2.2U_0805_10V6K
1
2
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
DIMMA
F
DQ12
DQ13
CK0#
DQ14
DQ15
DQ20
DQ21
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
NC/A15
NC/A14
RAS#
ODT0
NC/A13
DQ36
DQ37
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
VSS
DM1
VSS
VSS
VSS
VSS
VSS
DM2
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VSS
VSS
DM4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DM6
VSS
VSS
VSS
VSS
VSS
SAO
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
CK0
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
DDR_SCKE1
80
82
84
DDR_SMA14
86
88
DDR_SMA11
90
A11
92
A7
A6
A4
A2
A0
BA1
S0#
NC
CK1
SA1
DDR_SMA6
94
96
DDR_SMA4
98
DDR_SMA2
100
DDR_SMA0
102
104
DDR_SMA16
106
DDR_SRAS#
108
DDR_SCS#0
110
112
DDR_ODT0
114
DDR_SMA13
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Reverse
Compal Secret Data
2005/11/01 2006/11/30
E
Deciphered Date
F
DDR_DQ15
DDR_DQ12
DDR_DM1
DDR_DQ13
DDR_DQ9
DDR_DQ1
DDR_DQ4
DDR_DM0
EMC_DDR_CLK1
EMC_DDR_CLK1#
DDR_DQ17
DDR_DQ21
DDR_DM2
DDR_DQ19
DDR_DQ18
DDR_DQ29
DDR_DQ24
DDR_DQS#3
DDR_DQS3
DDR_DQ26
DDR_DQ27
DDR_DQ37
DDR_DQ33
DDR_DM4
DDR_DQ35
DDR_DQ38
DDR_DQ44
DDR_DQ40
DDR_DQS#5
DDR_DQS5
DDR_DQ47DDR_DQ42
DDR_DQ43
DDR_DQ49
DDR_DQ52DDR_DQ48
EMC_DDR_CLK0
EMC_DDR_CLK0#
DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ56DDR_DQ60
DDR_DQ61
DDR_DQS7
DDR_DQ63
DDR_DQ59
+3VS
G
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]
EMC_DDR_CLK1 <8>
EMC_DDR_CLK1# <8>
DDR_SCKE1 <8>
DDR_SRAS# <8,11>
DDR_SCS#0 <8>
DDR_ODT0 <8>
EMC_DDR_CLK0 <8>
EMC_DDR_CLK0# <8>
Title
DDRII-SODIMM2
Size Document Number Rev
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
G
DDR_DQ[0..63] <8,11>
DDR_DQS[0..7] <8,11>
DDR_DQS#[0..7] <8,11>
DDR_DM[0..7] <8,11>
DDR_SMA[0..17] <8,11>
H
of
10 43
H
Page 11
A
hexainf@hotmail.com
B
C
D
E
+1.8V +1.8V
+DDR_VREF2
Trace=20mil
JP15
1
VREF
3
C184
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
B
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
QUASA_CA0122-200N22_200P
DIMMB
Reverse
DDR_DQ[0..63]<8,10>
1 1
2 2
3 3
4 4
DDR_DQS[0..7]<8,10>
DDR_DQS#[0..7]<8,10>
DDR_DM[0..7]<8,10>
DDR_SMA[0..17]<8,10>
DDR_DQ[0..63]
DDR_DQS[0..7]
DDR_DQS#[0..7]
DDR_DM[0..7]
DDR_SMA[0..17]
A
DDR_SCKE2<8,10>
DDR_SWE#<8,10>
DDR_SCAS#<8,10>
DDR_SCS#3<8,10>
DDR_ODT3<8,10>
SB_SMDATA<10,12,16,23>
SB_SMCLK<10,12,16,23>
DDR_DQ8
DDR_DQ10
DDR_DQS#1
DDR_DQS1
DDR_DQ14
DDR_DQ11
DDR_DQ5
DDR_DQ0
DDR_DQS#0
DDR_DQS0
DDR_DQ7 DDR_DQ3
DDR_DQ2 DDR_DQ6
DDR_DQ16
DDR_DQ20
DDR_DQS#2
DDR_DQS2 DDR_DM2
DDR_DQ23
DDR_DQ22
DDR_DQ25
DDR_DQ28
DDR_DM3
DDR_DQ31
DDR_DQ30
DDR_SCKE2
DDR_SMA17
DDR_SMA12
DDR_SMA9
DDR_SMA8
DDR_SMA5
DDR_SMA3
DDR_SMA1
DDR_SMA10
DDR_SMA15
DDR_SWE#
DDR_SCAS#
DDR_SCS#3
DDR_ODT3
DDR_DQ36
DDR_DQ32
DDR_DQS#4
DDR_DQS4
DDR_DQ39
DDR_DQ34
DDR_DQ41
DDR_DQ45
DDR_DM5
DDR_DQ42
DDR_DQ46
DDR_DQ53
DDR_DQ48
DDR_DQS#6
DDR_DQS6
DDR_DQ50
DDR_DQ55
DDR_DQ60
DDR_DQ57
DDR_DM7
DDR_DQ58
DDR_DQ62
+3VS
2.2U_0805_10V6K
0.1U_0402_16V4Z
C186
1
1
2
2
DQ4
DQ5
DM0
DQ6
DQ7
DQ12
DQ13
DM1
CK0#
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3#
DQS3
DQ30
DQ31
NC/CKE1
VDD
NC/A15
NC/A14
VDD
VDD
VDD
RAS#
VDD
ODT0
NC/A13
VDD
DQ36
DQ37
DM4
DQ38
DQ39
DQ44
DQ45
DQS5#
DQS5
DQ46
DQ47
DQ52
DQ53
CK1#
DM6
DQ54
DQ55
DQ60
DQ61
DQS7#
DQS7
DQ62
DQ63
SAO
VSS
VSS
VSS
VSS
VSS
VSS
CK0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A11
BA1
S0#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CK1
VSS
VSS
VSS
VSS
VSS
VSS
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
A7
94
A6
96
98
A4
100
A2
102
A0
104
106
108
110
112
114
116
118
120
NC
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDR_DQ15
DDR_DQ12
DDR_DM1
DDR_DQ13
DDR_DQ9
DDR_DQ1
DDR_DQ4
DDR_DM0
EMC_DDR_CLK4
EMC_DDR_CLK4#
DDR_DQ17
DDR_DQ21
DDR_DQ19
DDR_DQ18
DDR_DQ29
DDR_DQ24
DDR_DQS#3
DDR_DQS3
DDR_DQ26
DDR_DQ27
DDR_SCKE3
DDR_SMA14
DDR_SMA11
DDR_SMA7
DDR_SMA6
DDR_SMA4
DDR_SMA2
DDR_SMA0
DDR_SMA16
DDR_SRAS#
DDR_SCS#2
DDR_ODT1
DDR_SMA13
DDR_DQ37
DDR_DQ33
DDR_DM4
DDR_DQ35
DDR_DQ38
DDR_DQ44
DDR_DQ40
DDR_DQS#5
DDR_DQS5
DDR_DQ47
DDR_DQ43
DDR_DQ49
DDR_DQ52
EMC_DDR_CLK3
EMC_DDR_CLK3#
DDR_DM6
DDR_DQ54
DDR_DQ51
DDR_DQ56
DDR_DQ61
DDR_DQS#7
DDR_DQS7
DDR_DQ63
DDR_DQ59
EMC_DDR_CLK4 <8>
EMC_DDR_CLK4# <8>
DDR_SCKE3 <8,10>
DDR_SRAS# <8,10>
DDR_SCS#2 <8,10>
DDR_ODT1 <8,10>
EMC_DDR_CLK3 <8>
EMC_DDR_CLK3# <8>
+3VS
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
+1.8V
C52
470U_D2_2.5VM
+1.8V
C97 0.1U_ 0402_16V4Z
C112 0. 1 U_ 0402_16V4Z
1
1
2
C941 0 . 1 U_0402_16V4Z
1
2
1
2
C942 0 . 1 U_0402_16V4Z
1
2
Compal Secret Data
+
2
2005/11/01 2006/11/30
Layout Note:
Place near JDIM1
C165 0. 1 U_ 0402_16V4Z
1
1
2
2
C943 0 . 1 U_0402_16V4Z
1
1
2
2
+DDR_VREF2
Deciphered Date
C98 0.1U_ 0402_16V4Z
C125 0. 1 U_ 0402_16V4Z
C157 0. 1 U_ 0402_16V4Z
1
2
C944 0 . 1 U_0402_16V4Z
C945 0 . 1 U_0402_16V4Z
1
2
12
R15
1K_0402_1%
12
R16
1K_0402_1%
D
C155 0. 1 U_ 0402_16V4Z
C142 0. 1 U_ 0402_16V4Z
1
1
2
+1.8V
2
1
C21
0.1U_0402_16V4Z
2
1
C20
0.1U_0402_16V4Z
2
1
2
C164 0. 1 U_ 0402_16V4Z
C109 0. 1 U_ 0402_16V4Z
1
2
Title
Size Document Number Re v
Custom
Date: Sheet
C645 0. 1 U_ 0402_16V4Z
1
1
2
2
Compal Electronics, Inc.
DDR-II SODIMM1
HAWAA(LA3141) 0.3
Thursday, January 26, 2006
C647 0. 1 U_ 0402_16V4Z
C646 0. 1 U_ 0402_16V4Z
1
1
2
2
of
E
11 43
Page 12
A
1 1
+3VS
KC FBM-L1 1-201209-221LMAT_0805
+3VS
+3VS
2 2
3 3
Clock Generator
L16
1 2
L14
1 2
CHB1608U301_0603
L33
1 2
CHB1608U301_0603
4.7U_0805_10V4Z
CLK_EN#<40>
R281
CLK_OK<16,17>
1 2
10K_0402_5%
+CLK_VDD1
+CLK_VDD1
10U_0805_10V4Z
C203
10U_0805_10V4Z
C497
R696 0_0402_5%@
2
G
1
C221
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
0.1U_0402_16V4Z
1
2
12
13
D
Q40
S
2N7002_SOT23
0.1U_0402_16V4Z
1
C188
2
1
C189
2
1
C484
2
1
1
C486
2
2
0.1U_0402_16V4Z
1
C190
0.1U_0402_16V4Z
2
22P_0402_50V8J
22P_0402_50V8J
+CLK_VDD1
CPU_STP#<15>
0.1U_0402_16V4Z
1
C458
C485
2
C501
C500
B
0.1U_0402_16V4Z
1
C456
2
+3VS
EMC_XTALIN_CLK
12
Y3
14.31818MHZ_20P_6X1430004201
SB_SMCLK<10,11,16,23>
SB_SMDATA<10,11,16,23>
EMC_XTALOUT_CLK
C
1- PLACE ALL THE SERIES TERMINATION RESISTORS
AS CLOSE TO CLOCK GEN AS POSSIBLE
2- ROUTE ALL CPUCLK/#, NBCLK/#, ITPCLK/#
AND SCR/# ,AS DIFFERENT PAIR RULE
3- PUT DECO UPLI NG CAPS CLOSE TO CLO CK GEN
POWER PIN
1 2
L13 CHB1608U301_0603
2
2
C182
C457
1
1
10U_0805_10V4Z
R269 4.7K_0402_5%@
R255 0_0402_5%
0.1U_0402_16V4Z
12
R277
1M_0402_5%@
12
12
12
R260
475_0402_1%
45
51
32
35
14
21
3
56
39
44
49
31
36
26
20
15
5
55
38
1
2
6
48
7
8
37
U23
VDDCPU
VDDPCI
VDDATI
VDDSRC
VDDSRC
VDDSRC
VDD48
VDDREF
VDDA
GNDCPU
GNDPCI
GNDATI
GNDSRC
GNDSRC
GNDSRC
GNDSRC
GND
GND
GNDA
XIN
XOUT
VTT_PWRGD#/PD
CPU_STOP#
SCLK
SDATA
IREF
ICS951413CGLFT_TSSOP56
CPUCLKT2_ITP
CPUCLKC2_ITP
CK410#/PCICLK0
USB_48MHZ
TEST_SEL/REF2
ICS951413
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
SRCCLKT0
SRCCLKC0
ATIGCLKT0
ATIGCLKC0
ATIGCLKT1
ATIGCLKC1
SRCCLKT3
SRCCLKC3
SRCCLKT4
SRCCLKC4
SRCCLKT5
SRCCLKC5
SRCCLKT6
SRCCLKC6
SRCCLKT7
SRCCLKC7
CLKREQA#
CLKREQB#
FS_C
FS_B/REF1
FS_A/REF0
47
46
43
42
41
40
34
33
30
29
27
28
24
25
22
23
18
19
16
17
12
13
10
11
50
4
9
53
54
52
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
SRCCLKT0
SRCCLKC0
SRCCLKT3
SRCCLKC3
SRCCLKT5
SRCCLKC5
10K_0402_5%
48M_SB
FS_C
FS_B/REF1
FS_A/REF0
TEST_SEL/REF2
R283
R771 47_0402_5%
R267 33_0402_5%
FS_C FS_B FS_A CPU SRC PCI REF USB
10
00
0
1
133.33 100.00 33.33 14.318 48.000
1
166.66 100.00 33.33 14.318 48.000
11
100.00 33.33 14.318 48.000100.00
R270 33_0402_5%
1 2
R271 33_0402_5%
1 2
R272 33_0402_5%
1 2
R273 33_0402_5%
1 2
R261 33_0402_5%
1 2
R263 33_0402_5%
1 2
R285 33_0402_5%
1 2
R278 33_0402_5%
1 2
R677 33_0402_5%
1 2
R678 33_0402_5%
1 2
R679 49.9_0402_1%
1 2
R680 49.9_0402_1%
1 2
12
R254 4.7K_0402_5%
1 2
1 2
R268 4.7K_0402_5%@
1 2
1 2
D
R256
R257
R258
1 2
1 2
49.9_0402_1%
R284 10K_0402_5%
R694
R282 4.7K_0402_5%
R253 4.7K_0402_5%
R251 4.7K_0402_5%
R266
33_0402_5%
1 2
R252
33_0402_5%
1 2
1 2
49.9_0402_1%
49.9_0402_1%
CLK_PCIE_MCARD <23>
CLK_PCIE_MCARD# <23>
12
12
0_0402_5%@
+CLK_VDD1
1 2
1 2
1 2
R259
1 2
49.9_0402_1%
12
12
49.9_0402_1%
R286
R279
MINI_CLKREQ#
EMC_CLK_NB_BCLK <8>
EMC_CLK_NB_BCLK# <8>
CLK_BCLK <4>
CLK_BCLK# <4>
12
12
49.9_0402_1%
49.9_0402_1%
49.9_0402_1%
R262
R264
+CLK_VDD1
+CLK_VDD1
MINI_CLKREQ# <23>
CPU_BSEL2 <5>
CPU_BSEL1 <5,8>
CPU_BSEL0 <5>
EMC_CLK_SB_14M <16>
EMC_CLK_NB_14M <8>
CLK_14M_SIO <29>
E
CLK_SB_ALINK <15>
CLK_SB_ALINK# <15>
CLK_NB_ALINK <7>
CLK_NB_ALINK# <7>
1
C931
10P_0402_50V8J
2
CLK_48M_SB <16>
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
ClockGen ICS 951413
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
D
Date: Sheet
E
12 43
of
Page 13
A
hexainf@hotmail.com
B
C
D
E
TV-OUT CONNECTOR
1 1
NB_LUMA<8>
NB_CRMA<8>
75_0603_1%
2 2
3 3
R57
12
12
0.1U_0402_16V4Z@
+LCDVDD
Reduce LUMA_1 and CRMA_1 length
As short as possible
NB_LUMA
NB_CRMA
R59
75_0603_1%
1
C202
1
2
TVOUT@
82P_0402_50V8J
2
C213
TVOUT@
82P_0402_50V8J
LCD/PANEL BD. Conn.
+3VS
BKOFF#<28>
1
C406
L40 KC F B M-L11-201209-221LMAT_0805
1 2
2
1 2
L38 KC FBM-L11-201209-221LMAT_0805
EMC_NB_TXOUT2+<8>
EMC_NB_TXOUT1+<8>
EMC_NB_TXOUT0+<8>
1. Y ground
1
D8
22P_0402_50V8J
C204
@
1 2
1 2
L15 CHB1608B121_0603
TVOUT@
22P_0402_50V8J
C224
@
1 2
1 2
L17 CHB1608B121_0603
TVOUT@
1 2
R209 10K_0402_5%
D19 CH751H-40_SC76
KC FBM-L11-201209-221LMAT_0805
B+ B+
EMC_NB_TXCLK+<8>
EMC_NB_TXCLK-<8>
EMC_NB_TXOUT2-<8>
EMC_NB_TXOUT1-<8>
EMC_NB_TXOUT0-<8>
DISPOFF#
21
L39
1 2
+LCDVDD_C
EMC_NB_TXCLK+
EMC_NB_TXCLK-
EMC_NB_TXOUT2+
EMC_NB_TXOUT2ÂEMC_NB_TXOUT1ÂEMC_NB_TXOUT1+
EMC_NB_TXOUT0ÂEMC_NB_TXOUT0+
1
2
2
3
DAN217_SC59@
LUMA_2
CRMA_2
C410
1 2
220P_0402_50V9J
ACES_88242-3000
1
2
C223
TVOUT@
82P_0402_50V8J
DISPOFF# DAC_BRIG
D7
DAN217_SC59@
C200
TVOUT@
82P_0402_50V8J
JP1
1
3
5
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
2
4
6
8
2. C ground
3. Y (luminance+sync)
4. C (crominance)
+3VS
JP18
ALLTO_C10877-104A1-L_4P
1
1
2
5
2
5
3
6
3
6
4
4
TVOUT@
KC FBM-L11-201209-221LMAT_0805
B+_LCDB+_LCD
INVT_PWM
NB_EDID_CLKNB_EDID_DATA
EMC_NB_TZCLKÂEMC_NB_TZCLK+
EMC_NB_TZOUT1ÂEMC_NB_TZOUT1+
EMC_NB_TZOUT2+
EMC_NB_TZOUT2ÂEMC_NB_TZOUT0+
EMC_NB_TZOUT0-
DAC_BRIG <28>
INVT_PWM <28>
NB_EDID_CLK <8>NB_EDID_DATA<8>
EMC_NB_TZCLK- <8>
EMC_NB_TZCLK+ <8>
EMC_NB_TZOUT1- <8>
EMC_NB_TZOUT1+ <8>
EMC_NB_TZOUT2+ <8>
EMC_NB_TZOUT2- <8>
EMC_NB_TZOUT0+ <8>
EMC_NB_TZOUT0- <8>
PANEL +LCDVDD CTRL CKT
NB_ENVDD<8>
+LCDVDD
R10
470_0805_5%
2N7002_SOT23
+LCDVDD Width: 40mils
L42
12
NB_ENVDD
2
G
Q3
12
100K_0402_5%
0.047U_0402_16V7K
+3VS
12
13
D
S
+3VALW
Q2
G
2
R9
1
C13
2
1
C407
0.1U_0402_16V4Z@
2
S
AO3413_SOT23
D
1 3
12
R7
100_0402_5%
12
R8
100K_0402_5%
Q34
G
2
+3VS
80mil
S
AO3413_SOT23
D
1 3
80mil
1
C404
4.7U_0805_10V4Z
2
1
C411
4.7U_0805_10V4Z
2
+LCDVDD
1
C405
0.1U_0402_16V4Z
2
NB_EDID_CLK
NB_EDID_DATA
4 4
A
B
1 2
C408 47P_0402_50V8J
1 2
C409 47P_0402_50V8J
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
D
Title
Size Document Number Re v
Custom
Date: Sheet of
Compal Electronics, Inc.
TV-OUT, LVDS CONNECTOR
HAWAA(LA3141) 0.3
Thursday, January 26, 2006
E
13 43
Page 14
5
4
3
2
1
D D
EMC_NB_CRT_R<8>
EMC_NB_CRT_G<8>
EMC_NB_CRT_B<8>
C C
R1
75_0603_1%
EMC_NB_CRT_HSYNC<8>
SN74AHCT1G125GW_SOT353-5
EMC_NB_CRT_VSYNC<8>
B B
12
R2
C12
1 2
0.1U_0402_16V4Z
12
75_0603_1%
+CRT_VCC
U3
12
R3
6P_0402_50V8K
75_0603_1%
5
1
P
OE#
A2Y
G
3
0.1U_0402_16V4Z
4
C11
1
C10
2
6P_0402_50V8K
+CRT_VCC
1 2
1
C8
2
DVI_HSYNC_B
5
P
A2Y
G
3
1
OE#
CRT CONNECTOR
1
D2
DAN217_SC59@
2
L1
1 2
FCM2012C-800_0805
L2
1 2
FCM2012C-800_0805
L3
1 2
FCM2012C-800_0805
1
C5
6P_0402_50V8K
2
R4
1K_0402_5%
1 2
DVI_VSYNC_B
4
U2
SN74AHCT1G125GW_SOT353-5
1
C4
2
6P_0402_50V8K@
L29
1 2
CHB1608B121_0603
L30
1 2
CHB1608B121_0603
+5VS +R_CRT_VCC
+3VS
D4
2 1
CH491D_SC59
1A_6VDC_MINISMDC110
0.1U_0402_16V4Z
DVI_R
DVI_G
DVI_B
1
C402
2
220P_0402_50V9J
68P_0402_50V8K
1
D1
DAN217_SC59@
2
3
3
1
C6
6P_0402_50V8K@
2
1
C401
68P_0402_50V8K@
2
1
D3
DAN217_SC59@
2
3
1
C7
2
6P_0402_50V8K@
DVI_HSYNC
DVI_VSYNC
1
C403
68P_0402_50V8K@
2
C398
F1
21
1
2
+CRT_VCC
1
C400
2
1
C9
2
68P_0402_50V8K
CRT Conn.
JP14
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
TYCO_1470801-1
4.7K_0402_5%
R204
1 2
R207
1 2
4.7K_0402_5%
Q32
2N7002_SOT23
2N7002_SOT23
1 2
2.2K_0402_5%
2
1 3
D
Q33
R205
G
S
1 3
D
R206
2
+3VS+CRT_VCC +3VS+CRT_VCC +3VS
R208
1 2
1 2
4.7K_0402_5%
4.7K_0402_5%
G
S
NB_DDC_DATA <8>
NB_DDC_CLK <8>
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
CRT CONNECTOR
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
14 43
of
Page 15
PCI_PIRQD#
hexainf@hotmail.com
PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQG#
PCI_PIRQH#
PCI_PIRQE#
PCI_PIRQF#
PCI_REQ#1
PCI_REQ#0
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_REQ#5
PCI_GNT#0
PCI_GNT#1
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_IRDY#
LOCK#
PCI_PERR#
PCI_SERR#
PCI_DEVSEL#
PCI_GNT#5
PCI_GNT#4
PCI_GNT#3
PCI_GNT#2
12
R103
1 2
20M_0603_5%
4
OUT
NC3NC
5
PCI_REQ#6
PCI_GNT#6
+1.8VS
EMC_SB_32KHI
1
IN
2
5
NB_A_RXP0<7>
NB_A_RXN0<7>
NB_A_RXP1<7>
NB_A_RXN1<7>
NB_A_RXP2<7>
NB_A_RXN2<7>
NB_A_RXP3<7>
NB_A_RXN3<7>
SB_A_RXP0<7>
SB_A_RXN0<7>
SB_A_RXP1<7>
SB_A_RXN1<7>
SB_A_RXP2<7>
SB_A_RXN2<7>
SB_A_RXP3<7>
SB_A_RXN3<7>
CHB2012U170_0805
+PCIE_VDDR
18P_0402_50V8J
1
C287
2
L24
C313
1U_0402_6.3V4Z
C314
10U_0805_10V4Z
C312
0.1U_0402_10V7K
R102
20M_0603_5%
1 2
+1.8VS
L22
CHB2012U170_0805
1 2
NB_RST#<8>
CLK_SB_ALINK<12>
CLK_SB_ALINK#<12>
C759 0.01U _0402_16V7K
1 2
C760 0.01U _0402_16V7K
1 2
C761 0.01U _0402_16V7K
1 2
C762 0.01U _0402_16V7K
1 2
C808 0.01U _0402_16V7K
1 2
C809 0.01U _0402_16V7K
1 2
C810 0.01U _0402_16V7K
1 2
C811 0.01U _0402_16V7K
1 2
12
+PCIE_VDDR
80mA
+PCIE_VDDR
CPU_STP#<12>
H_DPSLP#<4>
PCI_PIRQA#<26>
PCI_PIRQB#<21>
PCI_PIRQG#<20>
H_PWRGOOD<4>
H_INTR<4>
H_NMI<4>
H_INIT#<4>
H_SMI#<4>
H_CPUSLP#<4>
H_IGNNE#<4>
H_A20M#<4>
H_FERR#<4>
H_STPCLK#<4>
DPRSLPVR<4,40>
BM_REQ#<8>
H_RESET#<4,7>
PCIE_PVDD
50mil trace width
1 2
1 2
1 2
Pull-high on CPU side
+3VS
8.2K_1206_8P4R_5%
45
36
27
18
RP23
8.2K_1206_8P4R_5%
45
D D
C C
R382 8.2K_0402_5%
R162 8.2K_0402_5%
B B
A A
36
27
18
RP22
RP25
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
8.2K_1206_8P4R_5%
45
36
27
18
RP10
RP8
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
RP9
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
RP24
1 8
2 7
3 6
4 5
8.2K_1206_8P4R_5%
1 2
1 2
C288 470U_D2_2.5VM
+
C285 10U_0805_10V4Z
1 2
C291 10U_0805_10V4Z
1 2
C552 0.1U_0402_16V4Z
1 2
C550 0.1U_0402_16V4Z
1 2
C537 0.1U_0402_16V4Z
1 2
C562 0.1U_0402_16V4Z
1 2
C559 0.1U_0402_16V4Z
1 2
C561 0.1U_0402_16V4Z
1 2
C558 0.1U_0402_16V4Z
1 2
C541 0.1U_0402_16V4Z
1 2
C531 0.1U_0402_16V4Z
1 2
EMC_SB_32KH0
Y1
18P_0402_50V8J
1
C286
2
32.768KHZ_12.5P_1TJS125DJ2A073
4
R163 8.2K_0402_5%
1 2
NB_RST#
SB_A_TXP0
SB_A_TXN0
SB_A_TXP1
SB_A_TXN1
SB_A_TXP2
SB_A_TXN2
SB_A_TXP3
SB_A_TXN3
SB_A_RXP0
SB_A_RXN0
SB_A_RXP1
SB_A_RXN1
SB_A_RXP2
SB_A_RXN2
SB_A_RXP3
SB_A_RXN3
R108 150_0402_1%
R110 150_0402_1%
1 2
1 2
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
EMC_SB_32KHI
EMC_SB_32KH0
H_PWRGD
H_A20M#
12
12
1 2
R343 4.12K_0603_1%
R167 0_0402_5%
R690 0_0402_5%
R336
1 2
10K_0402_5%
R317
1 2
0_0402_5%@
4
AH8
L27
M27
M30
N30
K30
L30
H30
J30
F30
G30
M29
N29
M28
N28
J29
K29
J28
K28
G27
H27
G28
R30
F26
R29
G26
P26
K26
L26
P28
N26
P27
H28
F29
H29
H26
F27
G29
L29
J26
L28
J27
N27
M26
K27
P29
P30
AJ8
AK7
AG5
AH5
AJ5
AH6
AJ6
AK6
AG7
AH7
B2
B1
C29
A28
C28
B29
D29
E4
B30
F28
E28
E29
D25
E27
D27
D28
U9A
A_RST#
PCIE_RCLKP
PCIE_RCLKN
PCIE_TX0P
PCIE_TX0N
PCIE_TX1P
PCIE_TX1N
PCIE_TX2P
PCIE_TX2N
PCIE_TX3P
PCIE_TX3N
PCIE_RX0P
PCIE_RX0N
PCIE_RX1P
PCIE_RX1N
PCIE_RX2P
PCIE_RX2N
PCIE_RX3P
PCIE_RX3N
PCIE_CALRP
PCIE_CALRN
PCIE_CALI
PCIE_PVDD
PCIE_VDDR_1
PCIE_VDDR_2
PCIE_VDDR_3
PCIE_VDDR_4
PCIE_VDDR_5
PCIE_VDDR_6
PCIE_VDDR_7
PCIE_VDDR_8
PCIE_VDDR_9
PCIE_VSS_1
PCIE_VSS_2
PCIE_VSS_3
PCIE_VSS_4
PCIE_VSS_5
PCIE_VSS_6
PCIE_VSS_7
PCIE_VSS_8
PCIE_VSS_9
PCIE_VSS_10
PCIE_VSS_11
PCIE_VSS_12
PCIE_VSS_13
PCIE_VSS_14
PCIE_VSS_15
CPU_STP#/DPSLP_3V#
DPSLP_OD#/GPIO37
INTA#
INTB#
INTC#
INTD#
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
X1
X2
CPU_PG
INTR/LINT0
NMI/LINT1
INIT#
SMI#
SLP#/LDT_STP#
IGNNE#
A20M#
FERR#
STPCLK#/ALLOW_LDTSTP
LDT_PG/SSMUXSEL/GPIO0
DPRSLPVR
BMREQ#
LDT_RST#
PCI EXPRESS INTERFACE
SB450
SB450 SB
Part 1 of 4
PCI CLKS
PCI INTERFACE
REQ3#/PDMA_REQ0#
REQ4#/PLL_BP33/PDMA_REQ1#
GNT3#/PLL_BP66/PDMA_GNT0#
GNT4#/PLL_BP50/PDMA_GNT1#
LPC
CPU XTAL
RTC_IRQ#/ACPWR_STRAP
RTC
PCI_AD[0..31]<19,20,21,23,26>
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK8
PCICLK9
PCICLK_FB
PCIRST#
AD0/ROMA18
AD1/ROMA17
AD2/ROMA16
AD3/ROMA15
AD4/ROMA14
AD5/ROMA13
AD6/ROMA12
AD7/ROMA11
AD8/ROMA9
AD9/ROMA8
AD10/ROMA7
AD11/ROMA6
AD12/ROMA5
AD13/ROMA4
AD14/ROMA3
AD15/ROMA2
AD16/ROMD0
AD17/ROMD1
AD18/ROMD2
AD19/ROMD3
AD20/ROMD4
AD21/ROMD5
AD22/ROMD6
AD23/ROMD7
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE0#/ROMA10
CBE1#/ROMA1
CBE2#/ROMWE#
CBE3#
FRAME#
DEVSEL#/ROMA0
IRDY#
TRDY#/ROMOE#
PAR/ROMA19
STOP#
PERR#
SERR#
REQ0#
REQ1#
REQ2#
REQ5#/GPIO13
REQ6#/GPIO31
GNT0#
GNT1#
GNT2#
GNT5#/GPIO14
GNT6#/GPIO32
CLKRUN#
LOCK#
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#
SERIRQ
RTCCLK
VBAT
RTC_GND
3
PCI_AD[0..31]
L4
L3
L2
L1
M4
M3
M2
M1
N4
N3
N2
AJ7
W3
Y2
W4
Y3
V1
Y4
V2
W2
AA4
V4
AA3
U1
AA2
U2
AA1
U3
T4
AC1
R2
AD4
R3
AD3
R4
AD2
P2
AE3
P3
AE2
P4
AF2
N1
AF1
V3
AB4
AC2
AE4
T3
AC4
AC3
T2
U4
T1
AB2
AB3
AF4
AF3
AG2
AG3
AH1
AH2
AH3
AJ2
AK2
AJ3
AK3
AG4
AH4
AJ4
AG1
AB1
AG25
AH25
AJ25
AH24
AG24
AH26
AG26
AK27
C2
F3
A2
A1
PCI_CLK0_R
PCI_CLK1_R
PCI_CLK2_R
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R
PCI_CLK6_R
PCI_CLK8_R
PCICLK9_R
PCICLKFB
PCI_PLTRST#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_STOP#
PCI_PERR#
PCI_SERR#
PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4
PCI_REQ#5
PCI_REQ#6
PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_GNT#5
PCI_GNT#6
PM_CLKRUN#
LOCK#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
LPC_DRQ1#
SERIRQ
RTC_CLK
+SB_VBAT
R340
1 2
R333
1 2
R118
1 2
R354
1 2
R344
1 2
R349
1 2
R816
1 2
R365
1 2
R363 39_0402_5%
1 2
R165 8.2K_0402_5%
1 2
+3VS +3VS
FBM-L11-160808-800LMT_0603
C890
1U_0402_6.3V4Z
PCI_C/BE#0 <20,21,23,26>
PCI_C/BE#1 <20,21,23,26>
PCI_C/BE#2 <20,21,23,26>
PCI_C/BE#3 <20,21,23,26>
PCI_FRAME# <20,21,23,26>
PCI_DEVSEL# <20,21,26>
PCI_IRDY# <20,21,26>
PCI_TRDY# <20,21,23,26>
PCI_PAR <20,21,26>
PCI_STOP# <20,21,26>
PCI_PER R# <20,21,26>
PCI_SER R# <20,21,26>
PCI_REQ#0 <26>
PCI_REQ#1 <20>
PCI_REQ#2 <21>
PCI_GNT#0 <26>
PCI_GNT#1 <20>
PCI_GNT#2 <21>
PM_CLKRUN# <20,21,26,28,31>
LPC_AD0 <28,29,31,32>
LPC_AD1 <28,29,31,32>
LPC_AD2 <28,29,31,32>
LPC_AD3 <28,29,31,32>
LPC_FRAME# <19,28,29,31,32>
LPC_DRQ1# <29,32>
SERIRQ <21,28,29,31,32>
RTC_CLK <19>
AUTO_ON# <19>
Consider
@
39_0402_5%
39_0402_5%
@
@
39_0402_5%
39_0402_5%
@
39_0402_5%
@
39_0402_5%
39_0402_5%
39_0402_5%
@
12
L56
SS_VDD
R755
1 2
10K_0402_5%
10K_0402_5%
1
2
CLK_PCI_MINI
CLK_PCI_CB
CLK_PCI3
CLK_PCI_LAN
CLK_PCI_LPC
CLK_PCI_1394
CLK_PCI_SIO
PCI_CLK7_R
R794
@
1 2
--connect
RTC_CLK to EC
100P_0402_50V8J@
12
R759
2
C563
12
R761
10K_0402_5%@
13
12
12
10K_0402_5%
C278
Close to SB
PIN A2
CLK_PCI_MINI <23>
CLK_PCI_CB <21>
PCI_CLK2_R <19>
CLK_PCI3 <31>
CLK_PCI_LAN <20>
CLK_PCI_LPC <28>
CLK_PCI_1394 <26>
CLK_PCI_SIO <29,32>
EMI 11/15 Modify
U46
8
DLY CNTRL
1
CLKIN
3
VDD
VDD
9
SSON
4
SS%
5
GND
GND
ASM3P623S00EF-16-TR_TSSOP16
+SB_VBAT
1
2
1U_0402_6.3V4Z
Layout Note:
1. Under BATT1 battery Body, no Trace and Via
2. BATT1 + - PIN keep out 80mil from other component ,trace and via
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
2
1
C932
10P_0402_50V8J@
2
CKO1 CLK_PCI_MINI
2
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUT6
CLKOUT7
CLKOUT8
6
7
10
11
14
15
16
PCI_PLTRST#
TC7SH08FU_SSOP5@
PCI_PAR
LPC_DRQ1#
LPC_DRQ0#
SERIRQ
LPC_AD2
LPC_AD1
LPC_AD0
LPC_AD3
PM_CLKRUN#
CKO2
CKO3
CKO4
CKO5
CKO6
CKO7
R693
R136 8.2K_0402_5%
RTC Battery
-
Place JOPEN1 close
to DDR-SODIMM
+VBAT_JOP
R87
1 2
470_0805_5%
W=20mils
1
JOPEN1
1
JUMP_43X39@
No short
2
2
Title
Size Document Number Re v
Date: Sheet
1
PCI_CLK7_R <19>
PCI_CLK3_R
PCI_CLK4_R
PCI_CLK5_R
PCI_CLK6_R
PCI_CLK8_R
R760 39_0402_5%
1 2
R752 39_0402_5%
1 2
R753 39_0402_5%
1 2
R754 39_0402_5%@
1 2
R756 39_0402_5%
1 2
R757 39_0402_5%
1 2
R758 39_0402_5%
1 2
+3VS
0.1U_0402_16V4Z@
C891
1 2
5
U35
1
P
B
4
Y
2
A
G
3
12
0_0402_5%
1 2
4 5
3 6
2 7
1 8
RP20 10K_1206_8P4R_5%
4 5
3 6
2 7
1 8
RP21 100K_1206_8P4R_5%
1 2
R151 4.7K_0402_5%
BATT1
R88
1 2
470_0805_5%
RTCBATT45@
+RTCVCC
1
2
+
+RTCBATT
12
3
C274
0.1U_0402_16V4Z
PCIRST# <17,2 0 , 2 1 ,23,26,28,29,31,32>
+3VS
+RTCBATT
D12
1
BAS40-04_SOT23
CLK_PCI_CB
CLK_PCI3
CLK_PCI_LAN
CLK_PCI_LPC
CLK_PCI_1394
CLK_PCI_SIO
2
+CHGRTC
PCI_CLK3_R <19>
PCI_CLK4_R <19>
PCI_CLK5_R <19>
PCI_CLK6_R <19>
PCI_CLK8_R <19>
Compal Electronics, Inc.
PCI_EXP/LPC/RTC
HAWAA(LA3141) 0.3
Thursday, January 26, 2006
1
of
15 43
Page 16
+3VALW
D D
R96 4.7K_0402_5%
R99 4.7K_0402_5%
R94 10K_0402_5%@
+3VS
R326 10K_0402_5%
R337 10K_0402_5%@
R90 10K_0402_5%
R385 10K_0402_5%
R384 10K_0402_5%
R98 1.5K_0402_5%
R325 1.5K_0402_5%
R795 10K_0402_5%@
R796 10K_0402_5%@
R797 10K_0402_5%
C C
R858 10K_0402_5%
R859 10K_0402_5%
R860 10K_0402_5%
R861 10K_0402_5%
M_RST
+3VALW
R817
R84
0.1U_0402_16V4Z
TC7SH08FU_SSOP5
+3VS
1 2
1 2
1
C267
0.1U_0402_10V7K
@
2
B B
@
0_0603_5%
A A
@
0_0603_5%
5
RP17
1 8
2 7
3 6
4 5
10K_1206_8P4R_5%
RP6
1 8
2 7
3 6
4 5
4.7K_1206_8P4R_5%
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
RP7
1 8
2 7
3 6
4 5
10K_1206_8P4R_5%
10K_1206_8P4R_5%
4 5
3 6
2 7
1 8
RP15
1 2
1 2
1 2
1 2
+3VALW
C892
12
U45
4
Y
R818
@
0_0603_5%
1 2
12
R74
10K_0402_5%@
X1 48MHZ_4P_FN4800002@
4
VDD
1
OE
5
MASTER_RST#
EC_THRM#
EC_PME#
PBTN_OUT#
EXTEVENT0#
PCIE_PME#
EC_FLASH#
PM_SLP_S5#
EC_SWI#
PM_SLP_S3#
AZ_RST
AGP_BUSY#
AGP_STP#
SIO_SMI#
SB_GA20
SB_KBRST#
SB_SMCLK
B
A
12
12
OUT
GND
1
2
R18533_0402_5%
R71533_0402_5%
AZ_RST
GPIO_M
3
2
SB_SMDATA
GPIO_M
MAINPWON_R
GPIO_M
AC_BITCLK
AZ_SDIN1_MOM
AC_SDIN2
AZ_SDIN0_MDC
GPIO12
GPIO11
AGP_STP#
GPIO8
GPIO46
GPIO40
GPIO45
AZ_RST_MDC# <32>
AZ_RST_MOM# <41>
EMC_OSCLIN
AZ_BITCLK_MDC<32>
AZ_SDOUT_MDC<32>
AZ_SYNC_MDC<32>
AZ_BITCLK_MOM<41>
AZ_SDOUT_MOM<41>
AZ_SYNC_MOM<41>
AZ_SDIN0_MDC<32>
AZ_SDIN1_MOM<41>
5
P
G
3
NB_SUS_STAT#<8>
MINI_WAKE#<23,28>
EMC_CLK_SB_14M<12>
AZ_BITCLK_HD<24>
AZ_SDOUT_HD<24>
AZ_SDIN3_HD<24>
AZ_SYNC_HD<24>
AZ_RST_HD#<24>
AC_SDOUT<19>
SPDIF_OUT<19>
4
EC_THRM#<28>
EC_SWI#<28>
PM_SLP_S3#<28>
PM_SLP_S5#<28>
PBTN_OUT#<28>
SB_PWRGD<17>
H_PROCHOT#<4>
R768 0_0402_5%@
SB_INT_FLASH_SEL<29>
R708 KC FBMA-11-100505-900T 0402
1 2
R709 33_0402_5%
R710 33_0402_5%
R711 33_0402_5%
R181 KC FBMA-11-100505-900T 0402
1 2
R183 33_0402_5%
R184 33_0402_5%
R712 KC FBMA-11-100505-900T 0402
1 2
R713 33_0402_5%
R714 33_0402_5%
12
R97
0_0402_5%
SIDERST#<17>
CLK_OK<12,17>
R743 10K_0402_5%
1 2
SPKR<24>
SB_SMCLK<10,11,12,23>
SB_SMDATA<10,11,12,23>
1 2
AZ_SDIN3_HD
1 2
1 2
1 2
1 2
1 2
1 2
AC_SDOUT
AZ_SDIN0_MDC
AZ_SDIN1_MOM
AC_SDIN2
SPDIF_OUT
4
EC_THRM#
EC_SWI#
EXTEVENT0#
PM_SLP_S3#
PM_SLP_S5#
PBTN_OUT#
R308 0_0402_5%
1 2
R319 10K_0402_5%
1 2
R314 10K_0402_5%
1 2
SB_GA20
SB_KBRST#
MAINPWON_R
EC_PME#
SIO_SMI#
MASTER_RST#
PCIE_PME#
EC_RSMRST#
12
1
C279
15P_0402_50V8D@
2
SB_INT_FLASH_SEL
AGP_STP#
AGP_BUSY#
SPKR
SB_SMCLK
SB_SMDATA
GPIO_M
GPIO8
GPIO11
GPIO12
R762 0_0402_5%
1 2
R763 0_0402_5%
1 2
SB_14M
AZ_BITCLK
AZ_SDOUT
AZ_SYNC
AZ_RST
GPIO46
AC_BITCLK
GPIO40
GPIO45
3
1 2
R772 0_0402_5%
1 2
U9B
C6
C4
D3
B4
E3
B3
C3
D4
F2
E2
AJ26
AJ27
D6
C5
A25
D8
D7
D2
D1
A23
B23
AK24
B25
C25
C23
D24
D23
A27
C24
A26
B26
B27
C26
C27
D26
J2
J3
D5
K2
A6
K3
G1
G2
H4
G3
G4
H1
H3
H2
SB450
SB_GA20
SB_KBRST#
MAINPWON_R
SB450 SB
TALERT#/TEMP_ALERT#/GPIO10
PCI_PME#/GEVENT4#
RI#/EXTEVNT0#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
TEST1
TEST0
GA20IN
KBRST#
SMBALERT#/THRMTRIP#/GEVENT2#
LPC_PME#/GEVENT3#
LPC_SMI#/EXTEVNT1#
VOLT_ALERT#/S3_STATE/GEVENT5#
SYS_RESET#/GPM7#
WAKE#/GEVENT8#
RSMRST#
14M_X1/OSC
14M_X2
SIO_CLK
ROM_CS#/GPIO1
GHI#/GPIO6
VGATE/GPIO7
GPIO4
GPIO5
FANOUT0/GPIO3
SPKR/GPIO2
SCL0/GPOC0#
SDA0/GPOC1#
DDC1_SCL/GPIO9
DDC1_SDA/GPIO8
DDC2_SCL/GPIO11
DDC2_SDA/GPIO12
AZ_BITCLK
AZ_SDOUT
BLINK/AZ_SDIN3/GPM6#
AZ_SYNC
USB_OC5#/AZ_RST#/GPM5#
48M_AZ/GPIO46
AC_BITCLK/GPIO38
AC_SDOUT/GPIO39
ACZ_SDIN0/GPIO42
ACZ_SDIN1/GPIO43
ACZ_SDIN2/GPIO44
AC_SYNC/GPIO40
AC_RST#/GPIO45
SPDIF_OUT/GPIO41
CLK / RST
D32
2 1
R393
1 2
0_0402_5%
2 1
D31
R392
1 2
0_0402_5%
CH751H-40_SC76
2 1
D11
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Part 4 of 4
USB_OC2#/FANOUT1/LLB#/GPM2#
USB_OC6#/FAN_ALERT#/GEVENT6#
USB_OC7#/CASE_ALERT#/GEVENT7#
ACPI / WAKE UP EVENTS
USB INTERFACE
GPIOAC97
AZALIA
USB PWR
CH751H-40_SC76@
CH751H-40_SC76@
GATEA20
KBRST#
2005/11/01 2006/11/30
48M_X1/USBCLK
48M_X2
USB_RCOMP
USB_VREFOUT
USB_ATEST1
USB_ATEST0
USB_OC0#/GPM0#
USB_OC1#/GPM1#
USB_OC3#/GPM3#
USB_OC4#/GPM4#
USB_HSDP7+
USB_HSDP7+
USB_HSDP6+
USB_HSDM6-
USB_HSDP5+
USB_HSDM5-
USB_HSDP4+
USB_HSDM4-
USB_HSDP3+
USB_HSDM3-
USB_HSDP2+
USB_HSDM2-
USB_HSDP1+
USB_HSDM1-
USB_HSDP0+
USB_HSDM0-
AVDDTX_0
AVDDTX_1
AVDDTX_2
AVDDTX_3
AVDDRX_0
AVDDRX_1
AVDDRX_2
AVDDRX_3
AVDDC
AVSSC
AVSS_USB_1
AVSS_USB_2
AVSS_USB_3
AVSS_USB_4
AVSS_USB_5
AVSS_USB_6
AVSS_USB_7
AVSS_USB_8
AVSS_USB_9
AVSS_USB_10
AVSS_USB_11
AVSS_USB_12
AVSS_USB_13
AVSS_USB_14
AVSS_USB_15
AVSS_USB_16
AVSS_USB_17
AVSS_USB_18
AVSS_USB_19
AVSS_USB_20
AVSS_USB_21
AVSS_USB_22
AVSS_USB_23
AVSS_USB_24
GATEA20 <28>
KBRST# <28>
MAINPWON <4,34,35,37>
Compal Secret Data
R95 0_0402_5% @
R100 10K_0402_5%@
A15
R307 10K_0402_5%
B15
USB_RCOMP
C15
D16
C16
D15
B8
C8
C7
B7
B6
B5
A5
A11
B11
A10
B10
A14
B14
A13
B13
A18
B18
A17
B17
A21
B21
A20
B20
C21
C18
D13
D10
D20
D17
C14
C11
A16
B16
A9
A12
A19
A22
B9
B12
B19
B22
C9
C10
C12
C13
C17
C19
C20
C22
D9
D11
D12
D14
D18
D19
D21
D22
EC_SCI#
EC_FLASH#
USB_OC2#
EC_LID_OUT#
USB_OC4#
USB_OC6#
EC_SMI#
+AVDDTX
+AVDDRX
+AVDDC
Deciphered Date
1 2
1 2
R318 11.3K_0603_1%
USBP6+
USBP6-
USBP4+
USBP4-
USBP2+
USBP2-
USBP1+
USBP1-
USBP0+
USBP0-
2
CLK_48M_SB
EMC_OSCLIN
1 2
USBP6+ <27>
USBP6- <27>
USBP4+ <27>
USBP4- <27>
USBP2+ <27>
USBP2- <27>
USBP1+ <23>
USBP1- <23>
USBP0+ <27>
USBP0- <27>
EC_RSMRST#<28>
EC_SCI# <28>
EC_FLASH# <29>
EC_LID_OUT# <28>
EC_SMI# <28>
CLK_48M_SB <12>
EC_SCI#
EC_LID_OUT#
USB_OC2#
EC_SMI#
USB_OC4#
USB_OC6#
+AVDDTX
+AVDDRX
+AVDDC
R764 10K_0402_5%
R765 10K_0402_5%
L18 FBM-10-201209-260-T_0805
1 2
C268 10U _0805_10V4Z
1 2
C281 1 U _ 0402_6.3V 4Z
1 2
C512 0 . 1 U_0402_16V 4Z
1 2
C513 0 . 1 U_0402_16V 4Z
1 2
C514 0 . 1 U_0402_16V 4Z
1 2
L19 FBM-10-201209-260-T_0805
1 2
C270 10U _0805_10V4Z
1 2
C283 1 U _ 0402_6.3V 4Z
1 2
C521 0 . 1 U_0402_16V 4Z
1 2
C510 0 . 1 U_0402_16V 4Z
1 2
C511 0 . 1 U_0402_16V 4Z
1 2
L21 KC FBM-L 1 1-201209-221LMAT_0805
1 2
C277 10U _0805_10V4Z
1 2
C276 1 U _ 0402_6.3V 4Z
1 2
C504 0 . 1 U_0402_16V 4Z
1 2
Control by EC
Delay 50ms after +3VALW ready
Compal Electronics, Inc.
Title
SB450 USB/ACPI/AC97/GPIO
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1 2
1 2
10K_1206_8P4R_5%
45
36
27
18
RP5
1
+3VALW
EC_RSMRST#
12
R137
47K_0402_5%
1
+3VALW
16 43
of
Page 17
5
hexainf@hotmail.com
Place closely SATA CONN.
+5VS
10U_0805_10V4Z
1
C815
2
D D
+3V_SATA
0.1U_0402_16V4Z
10U_0805_10V4Z@
1
C820
2
0.1U_0402_16V4Z@
0.1U_0402_16V4Z
1
C816
2
1
C821
2
1
C817
2
0.1U_0402_16V4Z@
1
C822
2
1
C818
2
0.1U_0402_16V4Z
1
C823
2
0.1U_0402_16V4Z@
SATA HDD CONNECTOR
+PLLVDD_SATA+1.8VS
CHB1608U301_0603
C C
L46
0.1U_0402_16V4Z
C827
ODD CONNECTOR
1 2
R305 10K_0402_1%@
4.7K_0402_5%
R302
+3VS
R300
8.2K_0402_5%
SHDD_LED#<28>
B B
+5VS
+5VS
+5VS
A A
1 2
R293 100K_0402_5%
1 2
R692 4.7K_0402_5%@
R276 470_0402_5%
R129
10K_0402_5%
VGATE<40>
R128
1M_0402_1%
+3VS
12
12
12
1
2
12
12
12
5
1U_0402_6.3V4Z
14
7
P
G
O2I
U7A
1
C829
10U_0805_10V4Z
2
1
C828
2
SIDE_RST#
IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0
IDE_SDIOW#
IDE_SDIORDY
INT_IRQ15
IDE_SDA1
IDE_SDA0
IDE_SDCS1# IDE_SDCS3#
SHDD_LED#
SEC_CSEL
+3VALW +3VALW +3VALW+3VALW+3VALW
1
SN74LVC14APWLE_TSSOP14
CHB1608U301_0603
0.1U_0402_16V4Z
JP39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
53 54
OCTEK_CDR-50JD1
14
P
3
O4I
G
U7B
7
SN74LVC14APWLE_TSSOP14
4
JP25
1
GND
2
A+
3
A-
4
GND
5
B-
6
B+
7
GND
8
VCC3.3
9
VCC3.3
10
VCC3.3
11
GND
12
GND
13
GND
14
VCC5
15
VCC5
16
VCC5
17
GND
18
RESERVED
19
GND
20
VCC12
21
VCC12
22
VCC12
SUYIN_127043FB022G208ZR_22P_RV
L47
C830
1U_0402_6.3V4Z
12
1
2
+3VS
12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1
2
R748
10K_0402_5%
PHDD_LED#
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
IDE_SDDREQ
IDE_SDIOR#
IDE_SDDACK#
IDE_SDA2
C476 0.1U_0402_10V7K
C831
1 2
Place near SB side
PCIRST#<15,20,21,23,26,28,29,31,32>
SIDERST#<16>
R130
1 2
330K_0402_5%
0.1U_0402_10V7K
CLK_OK
4
C308
CLK_OK <12,16>
1
2
SATA_TX0+_C
SATA_TX0-_C
SATA_RX0-_C
SATA_RX0+_C
+3V_SATA
J5
2
JUMP_43X118
100 mil
+XTLVDD_SATA+1.8VS
1
C832
10U_0805_10V4Z
2
L48
CHB1608U301_0603
0.1U_0402_16V4Z
5.6K_0603_1%
1 2
@
R296
1 2
100K_0402_5%
+3VALW +3VALW
5
SN74LVC14APWLE_TSSOP14
12
1
C833
2
0.1U_0402_16V4Z
R304
+3VALW
0.1U_0402_16V4Z
C893
5
U34
1
P
B
Y
2
A
G
TC7SH08FU_SSOP5
3
14
P
O6I
G
U7C
7
3
Place SATA CAP & RES very close to SB
1 2
C812 0.01U_0402_16V7K
1 2
C813 0.01U_0402_16V7K
1 2
C814 0.01U_0402_16V7K
1 2
C819 0.01U_0402_16V7K
1230 modify C814,C819 near SB side
+3VS
112
+5VS
27P_0402_50V8J
1
C834
2
R744 10M_0402_5%
Y4
1 2
2
C825
25MHZ_20P
1
0.1U_0402_16V4Z
1
C835
2
0.1U_0402_16V4Z
EMC_SATA_X1
EMC_SATA_X2
12
1
2
1U_0402_6.3V4Z
1
C836
2
0.01U_0402_16V7K@
PHDD_LED#<28>
C826
27P_0402_50V8J
1
C837
2
1U_0402_6.3V4Z
C824
R717
1K_0402_1%
+PLLVDD_SATA
+XTLVDD_SATA
1
C838
C839
2
10U_0805_10V4Z
Place closely ODD CONN.
+5VS
10U_0805_10V4Z
1
C840
2
0.1U_0402_16V4Z
1 2
SIDE_RST#
4
14
P
9
O8I
G
U7D
7
SN74LVC14APWLE_TSSOP14
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1
C841
2
R115
1 2
0_0402_5%
3
0.1U_0402_16V4Z
1
C842
2
0.1U_0402_16V4Z
12
CLK_OK
13
2005/11/01 2006/11/30
SATA_TX0+
SATA_TX0ÂSATA_RX0ÂSATA_RX0+
12
1
2
PHDD_LED#
+1.8_SATA+1.8VS
1
2
1
C843
2
+3VALW
14
U5D
P
A
11
O
B
G
SN74LVC08APW_TSSOP14
7
R111
1 2
330K_0402_5%
0.47U_0603_16V7K
Compal Secret Data
NB_PWRGD <8>
C293
Deciphered Date
AK22
AK21
AK19
AK18
AK14
AK13
AK11
AK10
AK16
AH15
AH16
AG10
AG14
AH12
AG12
AG18
AG21
AH18
AG20
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AG11
AG15
AG17
AG19
AG22
AG23
AH17
AH23
AH13
AH20
AK17
AK23
AH10
11
SN74LVC14APWLE_TSSOP14
AJ22
AJ21
AJ19
AJ18
AJ14
AJ13
AJ11
AJ10
AJ15
AJ16
AG9
AH9
AJ12
AJ23
2
AK8
AF9
AK9
2
U9C
SATA_TX0+
SATA_TX0-
SATA_RX0ÂSATA_RX0+
SATA_TX1+
SATA_TX1-
SATA_RX1ÂSATA_RX1+
SATA_TX2+
SATA_TX2-
SATA_RX2ÂSATA_RX2+
SATA_TX3+
SATA_TX3-
SATA_RX3ÂSATA_RX3+
SATA_CAL
SATA_X1
SATA_X2
SATA_ACT#
PLLVDD_SATA
XTLVDD_SATA
AVDD_SATA_1
AVDD_SATA_2
AVDD_SATA_3
AVDD_SATA_4
AVDD_SATA_5
AVDD_SATA_6
AVDD_SATA_7
AVDD_SATA_8
AVSS_SATA_1
AVSS_SATA_2
AVSS_SATA_3
AVSS_SATA_4
AVSS_SATA_5
AVSS_SATA_6
AVSS_SATA_7
AVSS_SATA_8
AVSS_SATA_9
AVSS_SATA_10
AVSS_SATA_11
AVSS_SATA_12
AVSS_SATA_13
AVSS_SATA_14
AVSS_SATA_15
AVSS_SATA_16
AVSS_SATA_17
AVSS_SATA_18
AVSS_SATA_19
AVSS_SATA_20
AVSS_SATA_21
AVSS_SATA_22
AVSS_SATA_23
AVSS_SATA_24
AVSS_SATA_25
AVSS_SATA_26
AVSS_SATA_27
AVSS_SATA_28
AVSS_SATA_29
AVSS_SATA_30
AVSS_SATA_31
AVSS_SATA_32
SB450
14
P
O10I
G
U7E
7
SB450 SB
Part 2 of 4
SERIAL ATA
SERIAL ATA POWER
C127 0.1U_0402_16V4Z
14
P
13
O12I
G
U7F
7
SN74LVC14APWLE_TSSOP14
SB_PWRGD# <8>
1
PIDE_IORDY
PIDE_DACK#
PRIMARY ATA 66/100
SIDE_IORDY
SIDE_DACK#
SIDE_D0/GPIO15
SIDE_D1/GPIO16
SIDE_D2/GPIO17
SIDE_D3/GPIO18
SIDE_D4/GPIO19
SIDE_D5/GPIO20
SIDE_D6/GPIO21
SIDE_D7/GPIO22
SIDE_D8/GPIO23
SIDE_D9/GPIO24
SIDE_D10/GPIO25
SIDE_D11/GPIO26
SIDE_D12/GPIO27
SIDE_D13/GPIO28
SIDE_D14/GPIO29
SIDE_D15/GPIO30
SECONDARY ATA 66/100
AVSS_SATA_33
AVSS_SATA_34
AVSS_SATA_35
AVSS_SATA_36
AVSS_SATA_37
AVSS_SATA_38
AVSS_SATA_39
AVSS_SATA_40
AVSS_SATA_41
AVSS_SATA_42
AVSS_SATA_43
AVSS_SATA_44
AVSS_SATA_45
CLK_OK
Compal Electronics, Inc.
Title
SB450 IDE/SATA
Size Document Number Re v
HAWAA(LA3141)
Custom
Thursday, January 26, 2006
Date: Sheet
AD30
AE28
PIDE_IRQ
AD27
PIDE_A0
AC27
PIDE_A1
AD28
PIDE_A2
AD29
AE27
PIDE_DRQ
AE30
PIDE_IOR#
AE29
PIDE_IOW#
AC28
PIDE_CS1#
AC29
PIDE_CS3#
AF29
PIDE_D0
AF27
PIDE_D1
AG29
PIDE_D2
AH30
PIDE_D3
AH28
PIDE_D4
AK29
PIDE_D5
AK28
PIDE_D6
AH27
PIDE_D7
AG27
PIDE_D8
AJ28
PIDE_D9
AJ29
PIDE_D10
AH29
PIDE_D11
AG28
PIDE_D12
AG30
PIDE_D13
AF30
PIDE_D14
AF28
PIDE_D15
V29
T27
SIDE_IRQ
T28
SIDE_A0
U29
SIDE_A1
T29
SIDE_A2
V30
U28
SIDE_DRQ
W29
SIDE_IOR#
W30
SIDE_IOW#
R27
SIDE_CS1#
R28
SIDE_CS3#
V28
W28
Y30
AA30
Y28
AA28
AB28
AB27
AB29
AA27
Y27
AA29
W27
Y29
V27
U27
AG13
AH22
AK12
AH11
AJ17
AH14
AH19
AJ20
AH21
AJ9
AG16
AK15
AK20
C128 0.1U_0402_16V4Z
14
9
P
A
O
10
B
G
7
IDE_SDIORDY
INT_IRQ15
IDE_SDA0
IDE_SDA1
IDE_SDA2
IDE_SDDACK#
IDE_SDDREQ
IDE_SDIOR#
IDE_SDIOW#
IDE_SDCS1#
IDE_SDCS3#
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
U5C
8
SN74LVC08APW_TSSOP14
1
IDE_PDDACK# <19>
SB_PWRGD <16>
of
17 43
0.3
Page 18
+3VS +1.8VALW
1
C600
2
22U_0805_6.3V6M
+3VS
+5VS
1
C661
2
22U_0805_6.3V6M
D14
2 1
CH751H-40_SC76
R154
1 2
1K_0402_5%
C337
1U_0603_10V4Z
C587 1U_0402_6.3V4Z
1 2
C585 1U_0402_6.3V4Z
1 2
C651 1U_0402_6.3V4Z
1 2
C652 1U_0402_6.3V4Z
1 2
C520 0.1U_0402_16V4Z
1 2
C543 0.1U_0402_16V4Z
1 2
C522 0.1U_0402_16V4Z
1 2
C542 0.1U_0402_16V4Z
1 2
C564 0.1U_0402_16V4Z
1 2
C579 0.1U_0402_16V4Z
1 2
C584 0.1U_0402_16V4Z
1 2
C568 0.1U_0402_16V4Z
1 2
C576 0.1U_0402_16V4Z
1 2
C565 0.1U_0402_16V4Z
1 2
C586 0.1U_0402_16V4Z
1 2
C581 0.1U_0402_16V4Z
1 2
C594 0.1U_0402_16V4Z
1 2
C519 0.1U_0402_16V4Z
1 2
C598 0.1U_0402_16V4Z
1 2
C596 0.1U_0402_16V4Z
1 2
C597 0.1U_0402_16V4Z
1 2
C566 1U_0402_6.3V4Z
1 2
C553 1U_0402_6.3V4Z
1 2
C560 1U_0402_6.3V4Z
1 2
C573 1U_0402_6.3V4Z
1 2
C653 1U_0402_6.3V4Z
1 2
C654 1U_0402_6.3V4Z
1 2
C655 1U_0402_6.3V4Z
1 2
C656 1U_0402_6.3V4Z
1 2
C570 0.1U_0402_16V4Z
1 2
C569 0.1U_0402_16V4Z
1 2
C547 0.1U_0402_16V4Z
1 2
C571 0.1U_0402_16V4Z
1 2
C556 0.1U_0402_16V4Z
1 2
C554 0.1U_0402_16V4Z
1 2
C572 0.1U_0402_16V4Z
1 2
C578 0.1U_0402_16V4Z
1 2
C557 0.1U_0402_16V4Z
1 2
C577 0.1U_0402_16V4Z
1 2
C555 0.1U_0402_16V4Z
1 2
C546 0.1U_0402_16V4Z
1 2
C266 10U_0805_10V4Z
1 2
C275 10U_0805_10V4Z
1 2
C508 0.1U_0402_16V4Z
1 2
C507 0.1U_0402_16V4Z
1 2
C523 0.1U_0402_16V4Z
1 2
C525 0.1U_0402_16V4Z
1 2
C535 0.1U_0402_16V4Z
1 2
C536 1U_0402_6.3V4Z
1 2
C657 1U_0402_6.3V4Z
1 2
C526 0.1U_0402_16V4Z
1 2
C530 0.1U_0402_16V4Z
1 2
C524 0.1U_0402_16V4Z
1 2
C534 0.1U_0402_16V4Z
1 2
C532 0.1U_0402_16V4Z
1 2
C540 0.1U_0402_16V4Z
1 2
C533 0.1U_0402_16V4Z
1 2
+V5_VREF
2
2
C589
0.1U_0402_16V4Z
1
1
C269 10U_0805_10V4Z
C282 1U_0402_6.3V4Z
C280 0.1U_0402_16V4Z
+3VS
+1.8VS
+3VALW
+1.8VALW
0.1U_0402_16V4Z
C516
+1.05VS
+1.8VS
R86
0_0805_5%
1 2
1 2
1 2
+V5_VREF (20mils)
+AVDD_CK(40mils)
220mA
1 2
12
+AVDD_CK
D30
U26
U30
AA5
AA26
AB5
AC30
AD5
AD26
AE1
AE5
AE26
AF6
AF7
AF24
AF25
AK1
AK4
AK26
AK30
M12
M13
M18
M19
N12
N13
N18
N19
W12
W13
W18
W19
C30
AG6
A30
E24
E25
J5
K1
K5
N5
P5
R1
U5
V5
V26
Y1
Y26
V12
V13
V18
V19
A3
A7
E6
E7
E1
F5
E9
E10
E20
E21
E13
E14
E16
E17
A24
B24
A4
A8
A29
B28
C1
E5
E8
E11
E12
E15
E18
U9D
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18
VDDQ_19
VDDQ_20
VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
VDDQ_27
VDDQ_28
VDDQ_29
VDDQ_30
VDDQ_31
VDDQ_32
VDDQ_33
VDDQ_34
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
S5_3.3V_1
S5_3.3V_2
S5_3.3V_3
S5_3.3V_4
S5_3.3V_5
S5_3.3V_6
S5_1.8V_1
S5_1.8V_2
S5_1.8V_3
S5_1.8V_4
USB_PHY_1.8V_1
USB_PHY_1.8V_2
USB_PHY_1.8V_3
USB_PHY_1.8V_4
CPU_PWR
V5_VREF
AVDDCK
AVSSCK
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
SB450
SB450 SB
Part 3 of 4
POWER
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
E19
E22
E23
E26
E30
F1
F4
G5
H5
J1
J4
K4
L5
M5
P1
R5
R26
T5
T26
T30
W1
W5
W26
Y5
AB26
AB30
AC5
AC26
AD1
AF5
AF8
AF23
AF26
AG8
AJ1
AJ24
AJ30
AK5
AK25
M14
M15
M16
M17
N14
N15
N16
N17
P12
P13
P14
P15
P16
P17
P18
P19
R12
R13
R14
R15
R16
R17
R18
R19
T12
T13
T14
T15
T16
T17
T18
T19
U12
U13
U14
U15
U16
U17
U18
U19
V14
V15
V16
V17
W14
W15
W16
W17
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
SB450/POWER/GND
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
18 43
of
Page 19
5
hexainf@hotmail.com
+3VALW +3VS +3VALW +3VS +3VS +3VS +3VS +3VS +3VS +3VS
R315
10K_0402_5%
AUTO_ON#<15>
AC_SDOUT<16>
D D
RTC_CLK<15>
SPDIF_OUT<16>
PCI_CLK3_R<15>
PCI_CLK4_R<15>
PCI_CLK5_R<15>
PCI_CLK6_R<15>
PCI_CLK7_R<15>
PCI_CLK8_R<15>
LPC_FRAME#<15,28,29,31,32>
4
R329
12
R309
10K_0402_5%
12
R321
10K_0402_5%@
12
R341
10K_0402_5%
12
10K_0402_5%@
12
12
10K_0402_5%@
R355
3
12
R345
10K_0402_5%
2
+3VS
12
R351
10K_0402_5%@
12
R122
10K_0402_5%
12
R367
10K_0402_5%@
12
R741
10K_0402_5%
PCI_CLK2_R<15>
+3VS
12
R335
10K_0402_5%@
1
Selects type of 48MHz
12
R328
10K_0402_5%
12
R320
10K_0402_5%
12
R342
10K_0402_5%@
12
R356
10K_0402_5%
12
R346
10K_0402_5%@
12
10K_0402_5%
R350
12
R123
10K_0402_5%@
12
10K_0402_5%
R366
12
R742
10K_0402_5%@
clock pad
12
R334
10K_0402_5%
REQUIRED STRAPS
ACPWRON
AUTO_ON#
PULL
C C
IDE_PDDACK#<17>
PCI_AD31<15,20,21,26>
PCI_AD30<15,20,21,26>
PCI_AD29<15,20,21,26>
PCI_AD28<15,20,21,26>
B B
PCI_AD27<15,20,21,26>
PCI_AD26<15,20,21,26>
PCI_AD25<15,20,21,26>
PCI_AD24<15,20,21,26>
PCI_AD23<15,20,21,26>
HIGH
PULL
LOW
Pop R634 when debug .
MANUAL
PWR ON
DEFAULT
AUTO
PWR
ON
+3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS +3VS
12
R142
10K_0402_5%
12
R143
10K_0402_5%@
AC97_SDOUT SPDIF_OUT
USE
DEBUG
STRAPS
IGNORE
DEBUG
STRAPS
DEFAULT
12
R149
10K_0402_5%@
12
R148
10K_0402_5%@
RTC_CLK
INTERNAL
RTC
PU for 48Mhz
XTAL mode
DEFAULT
EXTERNAL
RTC (NOT
SUPPORTED
W/ IT8712 )
R127
10K_0402_5%@
R126
10K_0402_5%@
12
12
12
12
R146
10K_0402_5%@
R147
10K_0402_5%@
48M OSC
mode
DEFAULT
12
R373
10K_0402_5%@
12
R374
10K_0402_5%@
CLK_PCI3
USB PHY
PWRDOWN
DISABLE
DEFAULT
USB PHY
PWRDOWN
ENABLE
12
R141
10K_0402_5%@
12
R140
10K_0402_5%
CLK_PCI4
Internal PLL
External
Clock
DEFAULT
12
R369
10K_0402_5%@
12
R370
10K_0402_5%
CLK_PCI5
PCIE AUTO
detect
DEFAULT
Forcing PCIE
to 2 lanes
(debug only)
12
R381
10K_0402_5%@
12
R380
10K_0402_5%
PCI_CLK6
CPU I/F = K8
CPU I/F = P4
DEFAULT
12
R132
10K_0402_5%@
12
R131
10K_0402_5%
12
R138
10K_0402_5%@
12
R139
10K_0402_5%@
PCI_CLK7
ROM TYPE
H,H = PCI ROM
H,L = LPC ROM I
L,H = LPC ROM II
L,L = FWH ROM
PCI_CLK8
LFRAME#
THERMTRIP#
ENABLE
DEFAULT
THERMTRIP#
DISABLE
CLK_PCI2
Crystal Pad
Clock input
buffer
DEFAULT
DEBUG STRAPS
IDE_PDDACK#
PULL
HIGH
A A
PULL
LOW
USE
LONG
RESET
DEFAULT
USE
SHORT
RESET
PCI_AD31
Reserved
PCI_AD30
Reserved
PCI_AD29
PCI_AD28
Reserved Reserved
PCI_AD27 PCI_AD26
BYPASS
PCI PLL
USE PCI
PLL
DEFAULT DEFAULT DEFAULT DEFAULT
BYPASS
ACPI
BCLK
USE
ACPI
BCLK
PCI_AD25 PCI_AD24
BYPASS IDE
PLL
USE IDE
PLL
USE EEPROM
PCIE STRAPS
USE DEFAULT
PCIE STRAPS
PCI_AD23
Reserved
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
HARDWARE TRAP
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
of
19 43
Page 20
A
B
C
D
E
F
G
H
Q31
12
R819 0_0402_5%
12
R820 0_0402_5%@
ACTIVITY#
Q1
+3VALW
LINK_10_100#
R210
49.9_0402_1%
+3VALW
Closed to RTL8100CL Closed to RTL8100CL
+2.5V_LAN
+3VALW
1
2
0.1U_0402_16V4Z
PCI_AD[0..31]<15,19,21,23,26>
PCI_AD0
1 2
1
2
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
100_0402_5%
1 1
2 2
3 3
4 4
PCI_C/BE#0<15,21,23,26>
PCI_C/BE#1<15,21,23,26>
PCI_C/BE#2<15,21,23,26>
PCI_C/BE#3<15,21,23,26>
PCI_AD22
PCI_PAR<15,21,26>
PCI_FRAME#<15,21,23,26>
PCI_IRDY#<15,21,26>
PCI_TRDY#<15,21,23,26>
PCI_DEVSEL#<15,21,26>
PCI_STOP#<15,21,26>
PCI_PERR#<15,21,26>
PCI_SERR#<15,21,26>
PCI_REQ#1<15>
PCI_GNT#1<15>
PCI_PIRQG#<15>
EC_PME#<26,28>
PCIRST#<15,17,21,23,26,28,29,31,32>
CLK_PCI_LAN<15>
PM_CLKRUN#<15,21,26,28,31>
22P_0402_50V8J@
10_0402_5%@
R238
PCI_PIRQG#
R235
C433
1 2
PCI_AD[0..31]
U20
104
AD0
103
AD1
102
AD2
98
AD3
97
AD4
96
AD5
95
AD6
93
AD7
90
AD8
89
AD9
87
AD10
86
AD11
85
AD12
83
AD13
82
AD14
79
AD15
59
AD16
58
AD17
57
AD18
55
AD19
53
AD20
50
AD21
49
AD22
47
AD23
43
AD24
42
AD25
40
AD26
39
AD27
37
AD28
36
AD29
34
AD30
33
AD31
92
C/BE#0
77
C/BE#1
60
C/BE#2
44
C/BE#3
46
IDSEL
76
PAR
61
FRAME#
63
IRDY#
67
TRDY#
68
DEVSEL#
69
STOP#
70
PERR#
75
SERR#
30
REQ#
29
GNT#
25
INTA#
31
PME#
27
RST#
28
CLK
65
CLKRUN#
4
GND/VSS
17
GND/VSS
128
GND/VSS
21
GND/VSSPST
38
GND/VSSPST
51
GND/VSSPST
66
GND/VSSPST
81
GND/VSSPST
91
GND/VSSPST
101
GND/VSSPST
119
GND/VSSPST
35
GND
52
GND
80
GND
100
GND
RTL8100CL_LQFP128
EEDO
AUX/EEDI
EESK
EECS
LED0
LED1
LED2
NC/LED3
TXD+/MDI0+
TXD-/MDI0-
RXIN+/MDI1+
RXIN-/MDI1-
NC/MDI2+
NC/MDI2-
NC/MDI3+
NC/MDI3-
X1
X2
LWAKE
ISOLATE#
RTSET
NC/SMBCLK
NC/SMBDATA
NC/M66EN
NC/AVDDH
NC/HV
PCI I/F
NC/HSDAC+
GND
GND
NC/LV2
NC/VSS
NC/VSS
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
LAN I/F
NC/GND
CTRL25
RTT3/CRTL18
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL
NC/AVDDL
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
Power
AVDD25/HSDAC-
0.1U_0402_16V4Z
R215 3.6K_0402_5%
EEDO
108
EEDI
109
EESK
111
EECS
106
ACTIVITY#
117
LINK_10_100#
115
114
113
LAN_TD+
1
LAN_TD-
2
LAN_RD+
5
LAN_RD-
6
14
15
18
19
EMC_LAN_X1
121
EMC_LAN_X2
122
105
10mil
23
127
10mil
72
74
88
10
120
11
123
124
126
9
13
22
48
62
73
112
118
8
125
26
41
56
71
84
94
107
3
7
20
16
32
54
78
99
24
45
64
110
116
12
20mil
R233
12
12
R221
+LAN_DVDD CTRL25
CTRL25
+3VALW
+LAN_AVDDL
40mil
1
C428
0.1U_0402_16V4Z
2
+LAN_DVDD
40mil
2
C421
0.1U_0402_16V4Z
1
+2.5V_LAN_VDD
1
1
2
C38
2
0.1U_0402_16V4Z
C39
15K_0402_5%
5.6K_0603_1%
27P_0402_50V8J
12
12
U4
4
DO
3
DI
2
SK
1
CS
AT93C46-10SI-2.7_SO8
+3VS
R2311K_0402_5%
22U_0805_6.3V6M
1
C416
2
1
C425
0.1U_0402_16V4Z
2
2
C431
0.1U_0402_16V4Z
1
L9
12
0_0805_5%
GND
VCC
NC
NC
+3VALW
5
6
7
8
+3VALW
31
E
Q8
2
B
2SB1197K_SOT23
C
1
C34
2
Y2
25MHZ_20P
1 2
KC FBM-L1 1-201209-221LMAT_0805
1
C423
0.1U_0402_16V4Z
2
L31
2
0_0805_5%
C440
0.1U_0402_16V4Z
1
+3VALW
2
1
C17
0.1U_0402_16V4Z
40mil
1
C35
0.1U_0402_16V4Z
2
EMC_LAN_X2EMC_LAN_X1
12
L32
12
+2.5V_LAN
+3VS
+3VALW
+2.5V_LAN
2
1
DTA114YKA_SC59 @
C415
27P_0402_50V8J
DTA114YKA_SC59@
13
1 2
10K
13
R200 300_0402_5%
RJ45_RX-
RJ45_RX+
RJ45_TXÂRJ45_TX+
1 2
R203 300_0402_5%@
R201
75_0402_5%
RJ45_PR
12
47K
2
47K
10K
2
Termination plane should be coupled to chassis ground
LAN_TD+ RJ45_TX+
LAN_TD-
12
12
R211
49.9_0402_1%
1
C412
0.01U_0402_16V7K
2
0.1U_0402_16V4Z
1
C419
2
C426
R212
49.9_0402_1%
1
C442
2
0.1U_0402_16V4Z
LAN_RD+ RJ45_RX+
LAN_RD-
12
12
R213
49.9_0402_1%
1
C413
0.01U_0402_16V7K
2
0.1U_0402_16V4Z
1
1
C424
2
2
0.1U_0402_16V4Z
10mil
10mil
12
R202
75_0402_5%
1000P_1206_2KV7K
Layout Note
TS6121 pls close to
conn.
1
C14
0.1U_0402_16V4Z
2
1
C441
2
BLAN <30>
JP12
12
NC
11
NC
8
PR4-
7
PR4+
6
PR2-
5
PR3-
4
PR3+
3
PR2+
2
PR1-
1
PR1+
10
NC
9
NC
TYCO_3-440470-4
C391
1 2
U18
1
TD+
3
TD-
2
CT
4
NC
5
NC
7
CT
6
RD+
RD-8RX-
0.5u_TS6121C
C434
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C1
2
16
TX+
14
TX-
15
CT
13
NC
12
NC
10
CT
11
RX+
9
R5
75_0402_5%
SHLD2
SHLD1
SHLD2
SHLD1
1
2
12
16
15
14
13
LANGND
C2
4.7U_0805_10V4Z
RJ45_TX-
RJ45_RX-
12
R6
75_0402_5%
RJ45_PR
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
C
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
2005/11/01 2006/11/30
E
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
RTL8100CL
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
F
Date: Sheet
G
20 43
of
H
Page 21
5
hexainf@hotmail.com
4
3
2
1
G1
F3
VCC2
VCC1
CAD31/D10
CAD30/D9
CAD29/D1
CAD28/D8
CAD27/D0
CAD26/A0
CAD25/A1
CAD24/A2
CAD23/A3
CAD22/A4
CAD21/A5
CAD20/A6
CAD19/A25
CAD18/A7
CAD17/A24
CAD16/A17
CAD14/A9
CAD12/A11
CAD11/OE#
CAD10/CE2#
CAD9/A10
CAD8/D15
CAD7/D7
CAD6/D13
CAD5/D6
CAD4/D12
CAD3/D5
CAD2/D11
CAD1/D4
CAD0/D3
CCBE2#/A12
CCBE1#/A8
CIRDY#/A15
CTRDY#/A22
CSTOP#/A20
CPERR#/A14
CPAR/A13
CGNT#/WE#
CCLK/A16
SPKROUT
CCD2#/CD2#
CCD1#/CD1#
CVS2/VS2#
CVS1/VS1
CRSV3/D2
CRSV2/A18
CRSV1/D14
+S1_VCC
+3VS
B2
C3
B3
A3
C4
A6
D7
C7
A8
D8
A9
C9
A10
B10
D10
E12
F10
E13
F13
F11
G10
G11
G12
H12
H10
J11
J12
K13
J10
K10
K12
L13
B7
A11
E11
H13
B9
B11
A12
A13
B13
C12
C13
A5
D13
B8
C11
B12
C5
D5
D11
D6
M9
B5
A4
L12
D9
C6
A2
E10
J13
S1_A[0..25]
S1_D[0..15]
S1_D10
S1_D9
S1_D1
S1_D8
S1_D0
S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A25
S1_A7
S1_A24
S1_A17
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_OE#
S1_CE2#
S1_A10
S1_D15
S1_D7
S1_D13
S1_D6
S1_D12
S1_D5
S1_D11
S1_D4
S1_D3
S1_REG#
S1_A12
S1_A8
S1_CE1#
S1_RST
S1_A23
S1_A15
S1_A22
S1_A21
S1_A20
S1_A14
S1_WAIT#
S1_A13
S1_INPACK#
S1_WE#
S1_BVD1
S1_WP
S1_A19
S1_RDY#
PCM_SPK#
S1_BVD2
S1_CD2#
S1_CD1#
S1_VS2
S1_VS1
S1_D2
S1_A18
S1_D14
S1_A[0..25] <22>
S1_D[0..15] <22>
S1_IOW R# <22>
S1_IORD# <22>
S1_OE# <22>
S1_CE2# <22>
S1_REG# <22>
S1_CE1# <22>
S1_RST <22>
S1_WAIT# <22>
S1_INPACK# <22>
S1_WE# <22>
1 2
R160 33_0402_5%
S1_BVD1 <22>
S1_WP <22>
S1_RDY# <22>
PCM_SPK# <24>
S1_BVD2 <22>
S1_CD2# <22>
S1_CD1# <22>
S1_VS2 <22>
S1_VS1 <22>
S1_A16
+3VS
1
2
+3VS
1
2
+S1_VCC
1
2
C345
0.1U_0402_16V4Z
C343
0.1U_0402_16V4Z
C351
0.1U_0402_16V4Z
C336
1
C348
0.1U_0402_16V4Z
2
1
C359
0.1U_0402_16V4Z
2
1
2
1
2
C340
0.1U_0402_16V4Z
10P_0402_50V8J
1
C355
0.1U_0402_16V4Z
2
1
C347
0.1U_0402_16V4Z
2
1
C334
0.1U_0402_16V4Z
2
S1_CD1# S1_CD2#
10P_0402_50V8J
Close chip termenal
2
C354
0.1U_0402_16V4Z
1
1
C358
0.1U_0402_16V4Z
2
1
C349
0.1U_0402_16V4Z
2
+S1_VCC
1
C357
2
Closed to Pin A4Closed to Pin L12
S1_WP
12
R180
43K_0402_5%@
VPPD0<22>
VPPD1<22>
VCCD0#<22>
VCCD1#<22>
D D
CLK_PCI_CB
12
R407
10_0402_5%@
IDSEL:
PCI_AD20
1
C612
18P_0402_50V8K@
2
PCI_PIRQB#<15>
SERIRQ<15,28,29,31,32>
PM_CLKRUN#<15,20,26,28,31>
C C
B B
+3VS
PCI_AD[0..31]<15,19,20,23,26>
PCI_C/BE#3<15,20,23,26>
PCI_C/BE#2<15,20,23,26>
PCI_C/BE#1<15,20,23,26>
PCI_C/BE#0<15,20,23,26>
PCI_FRAME#<15,20,23,26>
PCI_IRDY#<15,20,26>
PCI_TRDY#<15,20,23,26>
PCI_DEVSEL#<15,20,26>
PCI_STOP#<15,20,26>
PCI_PERR#<15,20,26>
PCI_SERR#<15,20,26>
PCI_REQ#2<15>
PCI_GNT#2<15>
CLK_PCI_CB<15>
PCI_PIRQB#
PCIRST#<15,17,20,23,26,28,29,31,32>
PCI_PAR<15,20,26>
PCI_AD[0..31]
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
PCIRST#
CLK_PCI_CB A16_CLK
3V_PCM_SUSP
1 2
R159 10K_0402_5%
R406 100_0402_5%
1 2
1 2
1 2
1 2
1 2
1 2
R161 0_0402_5%
PCM_IDPCI_AD20
PCIRST#
R69510K_0402_5%@
R17410K_0402_5%@
R17110K_0402_5%@
R16810K_0402_5%@
M11
M10
C2
C1
D4
D2
D1
E4
E3
E2
F2
F1
G2
G3
H3
H4
J1
J2
N2
M3
N3
K4
M4
K5
L5
M5
K6
M6
N6
M7
N7
L7
K7
N8
E1
J3
N1
N5
G4
J4
K1
K3
L1
L2
L3
M1
M2
A1
B1
H1
L8
L11
F4
K8
N9
K9
N10
L10
N11
J9
M13
U29
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
CBE3#
CBE2#
CBE1#
CBE0#
PCIRST#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
PCIREQ#
PCIGNT#
PCICLK
RIOUT#_PME#
SUSPEND#
IDSEL
MFUNC0
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
MFUNC7
GRST#
VCCD1#
N13
VCCD0#
M12
VPPD1
N12
VPPD0
PCI Interface
A7
VCCA2
G13
VCCA1
B4
K2
N4
L6
C8
L9
H11
D12
VCC3
VCC4
VCC5
VCC9
VCC6
VCC7
VCC8
VCC10
CAD15/IOWR#
CAD13/IORD#
CCBE3#/REG#
CCBE0#/CE1#
CARDBUS
CRST#/RESET
CFRAME#/A23
CDEVSEL#/A21
CSERR#/WAIT#
CREQ#/INPACK#
CSTSCHG/BVD1_STSCHG#
CCLKRUN#/WP_IOIS16#
CBLOCK#/A19
CINT#/READY_IREQ#
CAUDIO/BVD2_SPKR#
GND1D3GND2H2GND3L4GND4M8GND5
GND6
GND7
GND8
PCI1410AGGU_PBGA144
B6
F12
K11
C10
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
ENE-CB1410
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet of
1
21 43
Page 22
5
4
3
2
1
C321
+S1_VPP+S1_VCC
S1_A[0..25]<21>
S1_D[0..15]<21>
CardBus Socket
JP7
69
GND
70
GND
71
GND
72
GND
SANTA_130602-2
GND
GND
DATA3
CD1#
DATA4
DATA11
DATA5
DATA12
DATA6
DATA13
DATA7
DATA14
CE1#
DATA15
ADD10
CE2#
VS1#
ADD11
IORD#
ADD9
IOWR#
ADD8
ADD17
ADD13
ADD18
ADD14
ADD19
WE#
ADD20
READY
ADD21
ADD16
ADD22
ADD15
ADD23
ADD12
ADD24
ADD7
ADD25
ADD6
VS2#
ADD5
RESET
ADD4
WAIT#
ADD3
INPACK#
ADD2
REG#
ADD1
BVD2
ADD0
BVD1
DATA0
DATA8
DATA1
DATA9
DATA2
DATA10
CD2#
GND
GND
OE#
VCC
VCC
VPP
VPP
1
35
2
36
3
37
4
38
5
39
6
40
7
41
8
42
9
43
10
44
11
45
12
46
13
47
14
48
15
49
16
50
17
51
18
52
19
53
20
54
21
55
22
56
23
57
24
58
25
59
26
60
27
61
28
62
29
63
30
64
31
65
32
66
33
WP
67
34
68
S1_D[0..15]
S1_D3
S1_CD1#
S1_D4
S1_D11
S1_D5
S1_D12
S1_D6
S1_D13
S1_D7
S1_D14
S1_CE1#
S1_D15
S1_A10
S1_CE2#
S1_OE#
S1_VS1
S1_A11
S1_IORD#
S1_A9
S1_IOWR#
S1_A8
S1_A17
S1_A13
S1_A18
S1_A14
S1_A19
S1_WE#
S1_A20
S1_RDY#
S1_A21
S1_A16
S1_A22
S1_A15
S1_A23
S1_A12
S1_A24
S1_A7
S1_A25
S1_A6
S1_VS2
S1_A5
S1_RST
S1_A4
S1_WAIT#
S1_A3
S1_INPACK#
S1_A2
S1_REG#
S1_A1
S1_BVD2
S1_A0
S1_BVD1
S1_D0
S1_D8
S1_D1
S1_D9
S1_D2
S1_D10
S1_WP
S1_CD2#
S1_A[0..25]
+S1_VCC
+S1_VPP
D D
C335
10U_0805_10V4Z
10U_0805_10V4Z
C C
B B
PCMCIA Power Controller
1
2
C329
W=40mil
1
C331
C325
0.1U_0402_16V4Z
2
W=40mil
0.1U_0402_16V4Z
1
C326
2
0.1U_0402_16V4Z
S1_A[0..25]<21>
S1_D[0..15]<21>
Close to
CardBus Conn.
10U_0805_10V4Z
4.7U_0805_10V4Z
1
2
1
2
C316
C320
U10
9
+5VS
5
6
+3VS
3
4
12
R135
10K_0402_5%
S1_A[0..25]
S1_D[0..15]
1
0.1U_0402_16V4Z
2
1
0.01U_0402_16V7K
2
12V
5V
5V
3.3V
3.3V
C323
C319
+S1_VCC
1
2
+S1_VPP
1
2
VCC
VCC
VCC
VPP
VCCD0
VCCD1
VPPD0
VPPD1
OC
GND
SHDN
TPS2211AIDBR_SSOP16
7
16
40mil
13
12
11
10
1
2
15
14
8
+S1_VCC
VCCD0#
VCCD1#
VPPD0
VPPD1
1
C303
4.7U_0805_10V4Z
2
+S1_VPP
40mil
1
C304
0.1U_0402_16V4Z
2
VCCD0# <21>
VCCD1# <21>
VPPD0 <21>
VPPD1 <21>
Reserve for Debug.
S1_WP
S1_OE#
S1_RST
S1_CE1#
S1_CE2#
12
R17343K_0402_5%
12
R33247K_0402_5%
12
R15347K_0402_5%
12
R31647K_0402_5%
12
R32447K_0402_5%
+S1_VCC
C317
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+S1_VCC +S1_VPP
C318
0.1U_0402_16V4Z
0.1U_0402_16V4Z
S1_CD1# <21>
S1_CE1# <21>
S1_CE2# <21>
S1_OE# <21>
S1_VS1 <21>
S1_IORD# <21>
S1_IOW R# <21>
S1_WE# <21>
S1_RDY# <21>
S1_VS2 <21>
S1_RST <21>
S1_WAIT# <21>
S1_INPACK# <21>
S1_REG# <21>
S1_BVD2 <21>
S1_BVD1 <21>
S1_WP <21>
S1_CD2# <21>
C322
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
CARD BUS SOCKET
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
22 43
of
Page 23
+3VS +1.5VS +3VALW
hexainf@hotmail.com
C745
WLAN@
0.01U_0402_16V7K
1
0.1U_0402_16V4Z
2
WLAN@
C746
1
4.7U_0805_10V4Z
2
WLAN@
C747
1
0.01U_0402_16V7K
2
WLAN@
C748
1
0.1U_0402_16V4Z
2
WLAN@
C749
1
4.7U_0805_10V4Z
2
WLAN@
C750
1
2
0.1U_0402_16V4Z
Mini-Express Card
MINI_WAKE#<16,28>
MINI_CLKREQ#<12>
CLK_PCIE_MCARD#<12>
CLK_PCIE_MCARD<12>
R681 0_0402_5%WLAN@
PCIE_WLAN_C_RX_N1<7>
PCIE_WLAN_C_RX_P1<7>
PCIE_WLAN_C_TX_P1<7>
PCIE_WLAN_C_RX_P1
PCIE_WLAN_C_TX_N1
PCIE_WLAN_C_TX_P1
1 2
1 2
R682 0_0402_5%WLAN@
MINI_WAKE#
MINI_CLKREQ#
CLK_PCIE_MCARD#
CLK_PCIE_MCARD
PCIE_C_RXN2PCIE _W LAN_C_RX_N1
PCIE_C_RXP2
JP38
1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
FOX_AS0B226-S40N-7F~D
WLAN@
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
R683 0_0402_5%@
R684 0_0402_5%@
SB_SMCLK <10,11,12,16>
SB_SMDATA <10,11,12,16>PCIE_WLAN_C_TX_N1<7>
12
12
USBP1ÂUSBP1+
XMIT_OFF#
PCIRST#
C751
WLAN@
+3VALW
USBP1- <16>
USBP1+ <16>
1
2
+1.5VS +3VS
+3VALW
C752 0.1U_0402_16V4Z
1 2
5
WL_OFF#<28>
KILL_SW#<28>
WL_OFF#
KILL_SW#
1
B
2
A
U33
P
Y
G
TC7SH08FU_SSOP5
3
WLAN@
WLAN@
4
WLAN@
CH751H-40_SC76
TIP
D48
XMIT_OFF#
21
Kill SWITCH
5
3
11223
G14G2
SW9
1BS003-1210L_3P
+3VALW
R685
100K_0402_5%
1 2
KILL_SW#
Port 80 Debug Card Connector
+5VS
PCI_C/BE#0
PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_AD8
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
CLK_PCI_MINI
PCIRST#
PCI_FRAME#
PCI_TRDY#
PCI_AD9
PCI_C/BE#0<15,20,21,26>
PCI_AD6<15,20,21,26>
PCI_AD4<15,20,21,26>
PCI_AD2<15,20,21,26>
PCI_AD0<15,20,21,26>
PCI_AD1<15,20,21,26>
PCI_AD3<15,20,21,26>
PCI_AD5<15,20,21,26>
PCI_AD7<15,20,21,26>
PCI_AD8<15,20,21,26>
PCI_C/BE#1<15,20,21,26>
PCI_C/BE#2<15,20,21,26>
PCI_C/BE#3<15,20,21,26>
CLK_PCI_MINI<15>
PCIRST#<15,17,20,21,26,28,29,31,32>
PCI_FRAME#<15,20,21,26>
PCI_TRDY#<15,20,21,26>
PCI_AD9<15,20,21,26>
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
JP29
20
20
19
19
18
18
17
17
16
16
15
15
14
14
13
13
12
12
11
11
10
10
9
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
ACES_85201-2005
Compal Electronics, Inc.
Title
MINI Express Card
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet of
23 43
Page 24
A
B
C
D
E
F
G
H
EC Beep
1 2
BEEP#<28>
1 1
CardBus Beep
PCM_SPK#<21>
0.01U_0402_16V7K
C390
C385
1U_0402_6.3V4Z
C387
1 2
2
1U_0402_6.3V4Z
1
1 2
R197
560_0402_5%
R199
1 2
560_0402_5%
NOISE#
PCI Beep
C384
1 2
SPKR<16>
1U_0402_6.3V4Z
1 2
R196
560_0402_5%
10K_0402_5%
12
R440
+AVDD_AC97
2
D34
CH751H-40_SC76
2 1
12
R431
10K_0402_5%
12
R430
10K_0402_5%
Q30
MMBT3904_SOT23
3 1
1
C386
1U_0402_6.3V4Z
@
2
1 2
1U_0402_6.3V4Z
R189
2.4K_0402_5%
1 2
C381
MONO_IN
SYSON<28,30,33>
SUSP#<28,29,33,38,39>
1
C369
10U_0805_10V4Z
2
R773 0_0603_5%
1 2
R774 0_0603_5%@
1 2
Adjustable Output
U42
4
VIN
2
SENSE or ADJ
DELAY
ERROR7CNOISE
C465
8
0.1U_0402_16V4Z
SD#
SI9182DH-AD_MSOP8
VOUT
GND
40mil60mil
5
6
1
3
1
C606
2
0.1U_0402_16V4Z
R405
30K_0402_1%
1 2
12
R404
10K_0402_1%
+VDDA
+VDDA+5VALW
4.85V
1
C367
10U_0805_10V4Z
2
@
4.7U_0603_6.3V6M
C662
+S1_VCC
2
1
HD Audio Codec
2 2
L28
+VDDA
3 3
1 2
R750 0_0603_5%
1 2
4 4
R751 0_0603_5%
1 2
R587 0_0603_5%
1 2
R588 0_0603_5%
1 2
R590 0_0603_5%
1 2
FBM-L11-160808-800LMT_0603
SENSE_A<25>
C946
1000P_0402_50V7K
2
1
680P_0402_50V7K
1
C935
0105 add 0105 add
2
680P_0402_50V7K
AMP_LEFT_HP<25>
AMP_RIGHT_HP<25>
ACZ_VREF
MIC1_L<25>
MIC1_R<25>
R831
1 2
47_0402_5%
0.1U_0402_16V4Z
1
1
C389
C936
2
2
10U_0805_10V4Z
1 2
C896 1U_0603_10V4Z
MIC1_L
C616 1U_0603_10V4Z
C619 1U_0603_10V4Z
AZ_RST_HD#<16>
AZ_SYNC_HD<16>
AZ_SDOUT_HD<16>
40mil
1
2
0.1U_0402_16V4Z
MIC1_C_L
MIC1_C_RMIC1_R
MONO_IN
1
C786
2
C388
1 2
1 2
DGND AGND
+AVDD_AC97
U16
AVDD125AVDD2
14
LINE2_L
15
LINE2_R
16
MIC2_L
17
MIC2_R
23
LINE1_L
24
LINE1_R
18
CD_L
20
CD_R
19
CD_GND
21
MIC1_L
22
MIC1_R
13
SENSE A
12
PC_BEEP
11
RESET#
10
SYNC
5
SDATA_OUT
45
SIDE-SURR-L
46
SIDE-SURR-R
48
SPDIFO
4
DVSS1
7
DVSS2
ALC861-GR_LQFP48
GND GNDA
A
B
C
38
20mil
DVDD11DVDD2
FRONT-OUT-L
FRONT-OUT-R
SURR_OUT_L
SURR_OUT_R
BIT_CLK
SDATA_IN
MIC2_VREFO
MIC1_VREFO_L
VREF
MIC1_VREFO_R
LINE2_VREFO
SENSE B
CEN-OUT
LFE-OUT
JDREF
AVSS1
AVSS2
0.1U_0402_16V4Z
1
C632
2
9
NC
NC
NC
NC
NC
NC
0.1U_0402_16V4Z
AMP_LEFT
35
AMP_RIGHT
36
39
41
6
R426 33_0402_5%
8
2
33
47
37
3
29
30
28
10mil
27
10mil
32
10mil
31
34
43
44
40
26
42
D
1
C785
2
680P_0402_50V7K
1000P_0402_50V7K
@
1 2
680P_0402_50V7K
1
1
C933
0105 add 0105 add
2
2
C635
L52
FBM-L11-160808-800LMT_0603
C934
1
1
2
2
AZ_BITCLK_HD <16>
AZ_SDIN3_HD <16>
1 2
C634
1000P_0402_50V7K
@
+3VS
MMBT3904_SOT23@
AMP_LEFT <25>
AMP_RIGHT <25>
10U_0805_10V4Z
1
C383
2
C630 27P_0402_50V8J
1 2
Analog Reference V
+MIC1_VREFO_L
ACZ_VREF
+MIC1_VREFO_R
R775
12
47_0402_5%
12
R707
5.1K_0402_1%
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
C791
10U_0805_10V4Z
SENSE_B <25>
2
C897
1000P_0402_50V7K
1
C363 0.1U_0402_16V4Z
2005/11/01 2006/11/30
E
Compal Secret Data
Deciphered Date
+MIC1_VREFO_L +MIC1_VREFO_R
C365
@
F
NOISE#
4.7U_0805_10V4Z
R461
@
4.7K_0402_5%
Q52
2
3 1
C792 0.1U_0402_16V4Z
Title
Size Document Number Re v
Custom
Date: Sheet
D37
CH751H-40_SC76@
1 2
2 1
R462
12
2.2K_0402_5%@
C793
@
Compal Electronics, Inc.
HD Audio Codec ALC861
HAWAA(LA3141)
G
NOISE_TEST
4.7U_0805_10V4Z
NOISE_TEST <28>
24 43Thursday, January 26, 2006
of
H
0.3
Page 25
VOL_AMP1
hexainf@hotmail.com
1SS355_SOD323
1 2
0.1U_0402_16V4Z@
A
C906 1U_0402_6.3V4Z
1 2
C907 1U_0402_6.3V4Z
1 2
R798
R799
+5VALW
12
D51
@
R702
0_0402_5% @
1
C765
2
C380
1
10U_0805_10V4Z
2
@
R791 100K_0402_5%
1 2
C360 1U_0402_6.3V4Z
C613 1U_0402_6.3V4Z
C899 1U_0402_6.3V4Z
C900 1U_0402_6.3V4Z
1 2
1.5K_0402_5%
1 2
1.5K_0402_5%
VS
0.1U_0603_25V7K
12
C446
LM358A_SO8
1
OUT
U22A
R697
1 2
6.19K_0603_1%
8
P
+IN
-IN
G
4
3
2
1 2
1 2
1 2
1 2
C356
1
2
22U_0805_6.3V6M
0.1U_0402_16V4Z
NBA_PLUG
+5VS
(0.65V -> 10dB )
R699
@
10K_0402_1%
1 2
1 2
R700
12
0_0402_5%@
R701
4 4
3 3
1.5K_0402_1%@
AMP_LEFT<24>
AMP_RIGHT<24>
AMP_LEFT_HP<24>
AMP_RIGHT_HP<24>
VOL_AMP1
Gain Settings
dB
SPK
2 2
HP
10
-6
VOL_AMP
0.4V~2.5V
0.75V~2.5V
+5VS
1
2
SPKL+
SPKR+
1 2
C617
B
+OPAMP
0.1U_0402_16V4Z
1
C904
2
1U_0402_6.3V4Z
R698
10K_0402_1%
VOL_AMP1
W=30mil
C894
U47
7
18
19
2
3
4
21
5
23
6
20
17
TPA0232PWP_TSSOP24
1
C905
0.047U_0402_16V7K
2
1
2
PVDD
SHUTDOWN#
PVDD
VDD
HP/LINE#
VOLUME
LOUT+
ROUT+
LLINEIN
RLINEIN
LHPIN
RHPIN
CLK
VOL_AMP <28>
SE/BTL#
PC-BEEP
BYPASS
LOUT-
ROUT-
GND
GND
GND
GND
BGND
C
22
15
14
BYPASS
11
9
16
10
LIN
8
RIN
1
12
13
24
25
W=30mil
C901
1U_0402_6.3V4Z
@
NBA_PLUG
SPKLÂSPKR-
2
1
4.7U_0603_6.3V6M
C939
C903
2
2
2
2
C902
1
1
1
1
1U_0402_6.3V4Z
4.7U_0603_6.3V6M
C940
@
2
G
Q69 AO3413_SOT23 @
1 3
D
R823
0_0805_5%
R824
0_0805_5%
D53 CH551H-30_SC76@
SHUTDOWN#
2
@
1
1U_0402_6.3V4Z
S
12
12
21
C908
+5VS
D
S
4.7U_0603_6.3V6M
+5VS+OPAMP
12
R190
100K_0402_5%
Q29
13
2N7002_SOT23
2
G
EC_EAPD <28>
SENSE_A<24>
SENSE_B<24>
NBA_PLUG
10mil
+
1 2
+
1 2
HPOUT1_R_2
HPOUT1_L_2
SPKR+
C737 150U _D_6.3V M
SPKL+
C738 150U _D_6.3V M
D
SPKL+
R35 0_0603_5%
SPKL-
R36 0_0603_5%
SPKR+
R25 0_0603_5%
SPKR-
R26 0_0603_5%
R829
1 2
20K_0402_1%
R776
1 2
39.2K_0402_1%
2
G
NBA_PLUG<28>
L53
FBM-11-160808-700T_0603
1 2
1 2
L54
FBM-11-160808-700T_0603
Speaker Conn.
1 2
1 2
1 2
1 2
D6
PSOT24C_SOT23@
13
D
Q65
2N7002_SOT23
S
NBA_PLUG
HPOUT1_R_3
HPOUT1_L_3
2N7002_SOT23
330P_0402_50V7K
2
3
1
13
D
Q70
S
R505 1K_0402_5%
1 2
2
C736
1U_0603_10V4Z
1
C739
2
INT_MIC_R
2
G
+5VS
330P_0402_50V7K
E
JP2
1
2
ACES_85204-0200
JP33
1
2
ACES_85204-0200
3
D5
PSOT24C_SOT23@
1
Headphone JACK 1
12
R504
100K_0402_5%
JP34
5
4
3
6
2
1
C740
FOX_JA6033L-5S1-TR
Volumn Control VR
Reserve for noise.
0.1U_0402_16V4Z@
VOL_AMP1
1 1
100K_0402_5%
NBA_PLUG
1 2
R782
0_0402_5%
+5VS
R784
1 2
13
D
Q67
2
2N7002_SOT23
G
S
A
C898
2
G
1
2
3.32K_0603_1%
13
D
Q66
2N7002_SOT23
S
R783
R781
3.9K_0402_1%
1 2
Int MIC Conn.
1
4
0.01W_10KC_EVUTW ZB19C 14
VR1
2
12
3
R785
6.19K_0603_1%
1 2
5
B
MIC2
WM-64PCY_2P@
MIC1
WM-64PCY_2P@
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
15mil
1
2
15mil
1
2
INT_MIC_L
2005/11/01 2006/11/30
C
MIC1_R<24>
MIC1_L<24>
Compal Secret Data
INT_MIC_R
Deciphered Date
MIC1_R
MIC1_L
1 2
1 2
D
FBM-11-160808-700T_0603
FBM-11-160808-700T_0603
10mil 10mil
R509
4.7K_0402_5%
L44
L45
220P_0402_50V9J
+MIC1_VREFO_R+MIC1_VREFO_L
12
R510
4.7K_0402_5%
1
C742
2
Title
Size Document Number Re v
Custom
Date: Sheet
+5VS
12
R830
MIC1_L_1
100K_0402_5%
MIC JACK
JP35
5
4
3
6
2
1
FOX_JA6033L-5S1-TR
12
MIC1_R_1
1
C794
220P_0402_50V9J
2
Compal Electronics, Inc.
AMP&Audio Jack
HAWAA(LA3141) 0.3
Thursday, January 26, 2006
E
of
25 43
Page 26
5
D D
PCI_AD[0..31]<15,19,20,21,23>
C C
IDSEL:PCI_AD16
PCI_AD16
B B
CLK_PCI_1394
R839
1 2
1394@
1394_IDSEL
100_0402_5%
PCI_C/BE#3<15,20,21,23>
PCI_C/BE#2<15,20,21,23>
PCI_C/BE#1<15,20,21,23>
PCI_C/BE#0<15,20,21,23>
CLK_PCI_1394<15>
PCI_FRAME#<15,20,21,23>
PCI_TRDY#<15,20,21,23>
PCI_DEVSEL#<15,20,21>
PCI_PERR#<15,20,21>
PCI_PIRQA#<15>
PCI_SERR#<15,20,21>
PM_CLKRUN#<15,20,21,28,31>
12
R846
10_0402_5%
@
C967
10P_0402_50V8K
@
PCI_AD[0..31]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
CLK_PCI_1394
PCI_GNT#0<15>
PCI_REQ#0<15>
PCI_IRDY#<15,20,21>
PCI_STOP#<15,20,21>
EC_PME#<20,28>
PCI_PAR<15,20,21>
PCIRST#<15,17,20,21,23,28,29,31,32>
PCI_GNT#0
PCI_REQ#0
1394_IDSEL
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_PIRQA#
EC_PME#
PCI_SERR#
PCI_PAR
PM_CLKRUN#
PCIRST# TPA0+
R848
220_0402_5%1394@
1 2
1 2
R849
84
82
81
80
79
77
76
74
71
70
69
67
66
65
63
61
46
45
43
42
41
40
38
37
32
31
29
28
26
25
24
22
34
47
60
73
16
18
19
36
49
50
52
53
54
56
13
21
57
58
12
85
14
89
90
220_0402_5%1394@
4
U48
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE3
PCI_C/BE2
PCI_C/BE1
PCI_C/BE0
PCI_CLK
PCI_GNT
PCI_REQ
PCI_IDSEL
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_PERR
PCI_INTA/CINT
PCI_PME/CSTSCHG
PCI_SERR
PCI_PAR
PCI_CLKRUN
PCI_RST
G_RST
GPIO3
GPIO2
+3VS
VDDP20VDDP35VDDP48VDDP62VDDP
TSB43AB21
/(TSB43AB22)
PCI BUS INTERFACE
PLLGND18REG_EN9AGND
AGND
AGND
AGND
AGND
AGND
AGND
109
110
111
117
126
127
128
87
CYCLEIN
86
96
CNA
CYCLEOUT/CARDBUS
NC/(TPBIAS1)
78
BIAS CURRENT
OSCILLATOR
FILTER
EEPROM 2 WIRE BUS
POWER CLASS
PHY PORT 1
DGND17DGND23REG1830DGND33DGND44DGND55DGND64DGND68DGND75DGND83REG1893DGND
103
C968
0.1U_0402_16V4Z1394@
C969
1 2
1 2
1 2
1 2
11
DVDD
DVDD
TEST1710TEST16
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
PLLVDD
AVDD
AVDD
AVDD
AVDD
AVDD
NC/(TPA1+)
NC/(TPA1-)
NC/(TPB1+)
NC/(TPB1-)
FILTER0
FILTER1
TPBIAS0
TPA0+
TPA0-
TPB0 +
TPB0 -
TEST9
TEST8
TEST3
TEST2
TEST1
TEST0
TSB43AB21_PQFP1281394@
0.1U_0402_16V4Z1394@
R832
1394@
R833
1394@
1394@
1394@
CPS
R0
R1
X0
X1
SDA
SCL
PC0
PC1
PC2
4.7K_0402_5%
10K_0402_5%
R834
4.7K_0402_5%
R835
4.7K_0402_5%
R836
12
4.7K_0402_5%1394@
15
27
39
51
59
72
88
100
7
1
2
107
108
120
106
125
124
123
122
121
118
119
6
5
3
4
92
91
99
98
97
116
115
114
113
112
94
95
101
102
104
105
3
+3VS
R837
1 2
R838
6.34K_0603_1%
1394@
C964
0.1U_0402_16V4Z1394@
R840
1 2
220_0402_5%1394@
R841
1 2
220_0402_5%1394@
TPBIAS0
TPA0-
TPB0+
TPB0-
+3VS
C947
0.1U_0402_16V4Z1394@
+3VS
1394_PLLVDD
0.01U_0402_16V7K
1K_0402_5%1394@
X3
1394@
24.576MHZ_16P_X8A024576FG1H
1 2
+3VS
C955
1000P_0402_50V7K1394@
1
C960
2
1394@
EMC_1394_X0
C962
EMC_1394_X1
C963
2
C948
0.1U_0402_16V4Z1394@
22P_0402_50V8J1394@
22P_0402_50V8J1394@
1394@
1394@
C961
4.7U_0805_10V4Z1394@
R842
56.2_0603_1%
R844
56.2_0603_1%
C966
220P_0402_50V8K1394@
C949
0.1U_0402_16V4Z1394@
C956
1000P_0402_50V7K1394@
L59
1 2
BLM21A601SPT_08051394@
C950
0.1U_0402_16V4Z1394@
C957
1000P_0402_50V7K1394@
R843
56.2_0603_1%1394@
0.33U_0603_16V4Z1394@
R845
56.2_0603_1%1394@
R847
5.11K_0603_1%1394@
C951
0.1U_0402_16V4Z1394@
C958
1000P_0402_50V7K1394@
+3VS
C965
0.1U_0402_16V4Z1394@
1
4
4
1
C952
C959
1000P_0402_50V7K1394@
1 2
R850 0_0402_5%1394@
L60
1
4
WCM2012F2S-900T04_0805@
1 2
R851 0_0402_5%1394@
1 2
R852 0_0402_5%1394@
L61
4
1
WCM2012F2S-900T04_0805@
1 2
R853 0_0402_5%1394@
C953
0.1U_0402_16V4Z1394@
2
2
3
3
3
3
2
2
1
C954
0.1U_0402_16V4Z1394@
JP40
4
4
3
6
3
G
2
5
2
G
1
1
TYCO_1470383-21394@
A A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
TSB43AB21
Size Document Number Re v
HAZ00/BL10E (LA2861) 0.3
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
26 43
of
Page 27
+5VALW
hexainf@hotmail.com
1
+
C729
150U_D2_6.3VM@
2
2 port in right side
ACES_87213-1000
1
2
3
4
5
6
7
8
9
10
JP32
+5VALW
1
2
USB_EN#
3
4
5
6
7
8
9
10
USBP0-C
USBP0+C
USBP2-C USBP0+
USBP2+C
USB_EN#<28>
+5VALW
1
C726
4.7U_0805_10V4Z@
2
USB_EN#
+5VALW
1
C733
4.7U_0805_10V4Z
2
USB_EN#
1 2
R854 0_0402_5%@
WCM2012F2S-900T04_0805
4
4
1
1
L62
1 2
R855 0_0402_5%@
1 2
R856 0_0402_5%@
WCM2012F2S-900T04_0805
4
4
1
1
L63
1 2
R857 0_0402_5%@
C724
0.1U_0402_16V4Z@
D38
W=60mils
1
2
3
@
1
USB CONN. 1
1
C725
1000P_0402_50V7K@
2
1
2
3
4
2
SUYIN_2537A-04G5T@
Place on the left side
JP13
VCC
DÂD+
GND
GND
GND
5
6
1
2
3
4
U1
1
2
3
4
G528_SO8
GND
IN
IN
EN#
OUT
OUT
OUT
FLG
8
7
6
5
8
7
6
5
+USB_VCCC
+USB_VCCA
1 2
R777 0_0402_5%@
L50
4
USBP6-<16>
USBP6+<16>
USBP6-
USBP6+
4
1
1
WCM2012F2S-900T04_0805@
1 2
R778 0_0402_5%@
3
3
2
2
U6
GND
IN
IN
EN#
G528_SO8@
OUT
OUT
OUT
FLG
150U_D_6.3VM@
USBP6-C
USBP6+C
+USB_VCCC
1
+
C723
2
PSOT24C_SOT23
+USB_VCCC
USB CONN.2
+USB_VCCA
C730
USBP4-C
USBP4+C
1
+
2
PSOT24C_SOT23
150U_D_6.3VM
1 2
3
3
2
2
USBP0-
USBP2ÂUSBP2+
3
3
2
2
USBP0- <16>
USBP0+ <16>
USBP2- <16>
USBP2+ <16>
USBP4-<16>
USBP4+<16>
USBP4-
USBP4+
R779 0_0402_5%@
L51
1
1
4
4
WCM2012F2S-900T04_0805
1 2
R780 0_0402_5%@
2
2
3
3
+USB_VCCA
1
C731
0.1U_0402_16V4Z
2
3
D39
@
W=60mils
1
2
2
1
C732
1000P_0402_50V7K
JP23
1
VCC
2
D-
3
D+
4
GND
SUYIN_2537A-04G5T
Place on the rear side
GND
GND
5
6
FM1
1
1
CF1
CF2
1
1
CF8
CF3
1
1
CF11
CF7
FM3
H26
1230 add
1230 add
H25
H_C177D126
1
H29
H_C126D126N
1
H27
H_C315D118
1
H31
H_s315D138
1
Title
Size Document Number Re v
Custom
Date: Sheet
H28
H_S394D323
H_C315D118
1
1
0105 add
H38
H_R63x43D47x28
1
Compal Electronics, Inc.
USB Conn.
HAWAA(LA3141) 0.2
Thursday, January 26, 2006
of
27 43
H1
H_C295D124
1
H7
FM4
FM2
1
1
CF10
CF12
1
1
CF13
1
1
CF6
CF9
1
1
1
CF14
1
1
FM5
FM6
1
CF4
CF5
1
1
H_S394D159
1
H13
H_S394D323
1
H19
H_C315D138
1
H3
H2
H_C295D124
H_C295D124
1
1
1230 add
H9
H8
H_S315D159
H_C236D159
1
1
H15
H14
H_S394D118
H_S394D118
1
1
H20
H_O205X126D205X126N
1
H4
H_C295D124
1
H10
H_C315D165
1
H16
H_C394D138
1
H21
H_O205X126D205X126N
1
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
H6
H5
H_C197D157
H_C197D157
1
1
H11
H12
H_S394D118
H_S315D118
1
1
H17
H18
H_C315D138
H_S394D118
1
1
H22
H_O205X126D205X126N
1
2005/11/01 2006/11/30
Compal Secret Data
H23
H_C157BC217D128
1
H36
H_R63x43D47x28
1
Deciphered Date
1230 add
H24
H_C157BC217D128
1
H34
H_R63x43D47x28
1
H39
H_R63x43D47x28
1
Page 28
5
KBA[0..19]
ADB[0..7]
L20
1 2
FBM-L11-160808-800LMT_0603
D D
C C
EC_PME#<20,26>
+5VS
RP18
1 8
2 7
3 6
4 5
4.7K_1206_8P4R_5%
+3VALW
RP19
1 8
2 7
3 6
4 5
+5VALW
B B
A A
C338
100K_1206_8P4R_5%
1 2
R375 4.7K_0402_5%
1 2
R371 4.7K_0402_5%
1 2
R156 4.7K_0402_5%
1 2
R157 4.7K_0402_5%
1 2
R112 100K_0402_5%
EMC_CRY1
1 2
20M_0603_5%@
1
2
10P_0402_50V8J
32.768KHZ_12.5P_1TJS125DJ2A073
PSCLK1
PSDATA1
PSCLK2
PSDATA2
MODE#
FRD#
SELIO#
FSEL#
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
100P_0402_50V8J@
R150
1
4
IN
OUT
NC3NC
2
KBA[0..19] <29>
ADB[0..7] <29>
ECAGND
22P_0402_50V8J@
+3VALW
1 2
C333
ENBKL
EMC_CRY2
X2
5
12
C306
R152
10K_0402_5%
EC_PME#
1
2
1
C342
2
CLK_PCI_LPC<15>
R125 10_0402_5%@
1
C332
100P_0402_50V8J@
2
10P_0402_50V8J
+3VALW
12
C301 0.1U_0402_16V4Z
12
R119 47K_0402_5%
1
C309
2
0.1U_0402_16V4Z
12
0.1U_0402_16V4Z
TP_CLK
TP_DATA
KBA1
KBA4
KBA5
C292
1
2
0.1U_0402_16V4Z
LPC_AD0<15,29,31,32>
LPC_AD1<15,29,31,32>
LPC_AD2<15,29,31,32>
LPC_AD3<15,29,31,32>
LPC_FRAME#<15,19,29,31,32>
PCIRST#<15,17,20,21,23,26,29,31,32>
SERIRQ<15,21,29,31,32>
PM_CLKRUN#<15,20,21,26,31>
LPCPD#<31>
FRD#<29>
FWR#<29>
FSEL#<29>
IE_BTN#<30>
+3VALW
TP_CLK<31>
TP_DATA<31>
EC_SMB_CK1<29,35>
EC_SMB_DA1<29,35>
EC_SMB_CK2<4>
EC_SMB_DA2<4>
EC_SCI#<16>
ENBKL<8>
BKOFF#<13>
FSTCHG<36>
EC_SMI#<16>
WL_OFF#<23>
EC_SWI#<16>
NBA_PLUG<25>
LID_SW#<31>
MODE#<30>
SYSON<24,30,33>
SUSP#<24,29,33,38,39>
VR_ON<40>
PBTN_OUT#<16>
PADS_LED#<31>
CAPS_LED#<31>
NUM_LED#<31>
PHDD_LED#<17>
GATEA20<16>
KBRST#<16>
1 2
R357
1 2
R358
1 2
R372 10K_0402_5%
1 2
R376 10K_0402_5%
1 2
R377 10K_0402_5%
4
0.1U_0402_16V4Z
1
1
C273
C328
2
2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
FRD#
FWR#
FSEL#
SELIO#
ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
IE_BTN#
12
R114 100K_0402_5%
PSCLK1
PSDATA1
PSCLK2
PSDATA2
TP_CLK
TP_DATA
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
EC_SCI#
ENBKL
BKOFF#
FSTCHG
EC_SMI#
NBA_PLUG
LID_SW#
MODE#
SYSON
SUSP#
VR_ON
PBTN_OUT#
PADS_LED#
CAPS_LED#
NUM_LED#
+5VS
4.7K_0402_5%
4.7K_0402_5%
+3VALW
4
2
C315
1000P_0402_50V7K
1
U8
15
LAD0
14
LAD1
13
LAD2
10
LAD3
9
LFRAME#
165
LRST#/GPIO2C
18
LCLK
7
SERIRQ
25
CLKRUN#/GPIO0C
24
LPCPD#/GPIO0B
150
RD#
151
WR#
173
MEMCS#
152
IOCS#
138
D0
139
D1
140
D2
141
D3
144
D4
145
D5
146
D6
147
D7
124
A0
125
A1/XIOP_TP
126
A2
127
A3
128
A4/DMRP_TP
131
A5/EMWB_TP
132
A6
133
A7
143
A8
142
A9
135
A10
134
A11
130
A12
129
A13
121
A14
120
A15
113
A16
112
A17
104
A18
103
A19
108
A20/GPIO23
105
E51CS#/GPIO20/ISPEN
110
PSCLK1
111
PSDAT1
114
PSCLK2
115
PSDAT2
116
PSCLK3
117
PSDAT3
163
SCL1
164
SDA1
169
SCL2
170
SDA2
8
GPIO04
20
GPIO07
21
GPIO08
22
GPIO09
27
GPIO0D
28
GPIO0E
48
GPIO10
62
GPIO13
63
GPIO14
69
GPIO15
70
GPIO16
75
GPIO17
109
GPIO24
118
GPIO25
119
GPIO26
148
GPIO27
149
GPIO28
155
GPIO29
156
GPIO2A
162
GPIO2B
168
GPIO2D
55
FnLock#/GPIO12
54
CapLock#/GPIO011
23
NumLock#/GPIO0A
41
ScrollLock#/GPIO0F
19
ECRST#
5
GA20/GPIO02
6
KBRST#/GPIO03
31
ECSCI#
+3VALW
1 2
FBM-L11-160808-800LMT_0603
2
C330
1000P_0402_50V7K
1
VCC16VCC34VCC45VCC
LPC Interface
*
*
X-BUS Interface
PS2 Interface
SMBus
GPIO
*
*
*
*
MISC
3
L23
1
C290
2
0.1U_0402_16V4Z
ECAGND
96
123
136
157
166
VCC
VCC
VCC
159
95
161
VCCA
AGND
VCCBAT
BATGND
FAN2PWM/GPOW2/PWM2
Pulse Width
FAN1PWM/GPOW7/PWM7
Wake Up Pin
ENE-KB910-B4
Analog To Digital
Digital To Analog
Expanded I/O
GPIO2E/TOUT1/FANFB1
DPLL_TP/GPIO06/FANFB3
FAN
TEST_TP/GPIO05/FAN3PWM
Timer Pin
E51RXD/GPIO21/ISPCLK
E51TXD/GPIO22/ISPDAT
GND17GND35GND46GND
GND
GND
122
137
167
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
0.1U_0402_16V4Z
GPOK0/KSO0
GPOK1/KSO1
GPOK2/KSO2
GPOK3/KSO3
GPOK4/KSO4
GPOK5/KSO5
GPOK6/KSO6
GPOK7/KSO7
GPOK8/KSO8
GPOK9/KSO9
GPOK10/KSO10
GPOK11/KSO11
GPOK12/KSO12
GPOK13/KSO13
GPOK14/KSO14
GPOK15/KSO15
GPOK16/KSO16
GPOK17/KSO17
GPIK0/KSI0
GPIK1/KSI1
GPIK2/KSI2
GPIK3/KSI3
GPIK4/KSI4
Internal Keyboard
GPIK5/KSI5
GPIK6/KSI6
GPIK7/KSI7
GPOW0/PWM0
GPOW1/PWM1
GPOW3/PWM3
GPOW4/PWM4
GPOW5/PWM5
GPOW6/PWM6
GPWU0
GPWU1
GPWU2
GPWU3
GPWU4
GPWU5
TIN1/GPWU6
TIN2/FANFB2/GPWU7
GPIAD0/AD0
GPIAD1/AD1
GPIAD2/AD2
GPIAD3/AD3
GPIAD4/AD4
GPIAD5/AD5
GPIAD6/AD6
GPIAD7/AD7
GPODA0/DA0
GPODA1/DA1
GPODA2/DA2
GPODA3/DA3
GPODA4/DA4
GPODA5/DA5
GPODA6/DA6
GPODA7/DA7
GPIO18/XIO8CS#
*
GPIO19/XIO9CS#
*
GPIO1A/XIOACS#
*
GPIO1B/XIOBCS#
*
GPIO1C/XIOCCS#
*
GPIO1D/XIODCS#
*
GPIO1E/XIOECS#
*
GPIO1F/XIOFCS#
*
TOUT2/GPIO2F
E51IT0/GPIO00
E51IT1/GPIO01
XCLKI
XCLKO
KB910Q B4_LQFP176
49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68
153
154
71
72
73
74
77
78
79
80
32
33
36
37
38
39
40
43
2
26
29
30
44
76
172
176
81
82
83
84
87
88
89
90
99
100
101
102
1
42
47
174
85
86
91
92
93
94
97
98
171
12
11
175
3
4
106
107
158
160
2005/11/01 2006/11/30
1
C327
2
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO17
KSI4
KSI5
KSI6
KSI7
INVT_PWM
BEEP#
PWR_SUSP_LED
ACOFF
USB_EN#
EC_ON
EC_LID_OUT#
EC_EAPD
KILL_SW#
EC_PME#
BATT_TEMPA
BTN_ID
BATT_OVP
ALI/MH#
SKU_ID1
AD_BID0
DAC_BRIG
IREF
EN_DFAN1
VOL_AMP
PWR_LED#
WL_LED#
HDD_LED#
BATT_LOW_LED#
BATT_CHGI_LED#
FAN_SPEED1
EC_THRM#
E51_RXD
E51_TXD
EMC_CRY2
EMC_CRY1
+3VALW
12
L55
CHB1608U301_0603
1
C339
1U_0402_6.3V4Z
2
KSO0 <31>
KSO1 <31>
KSO2 <31>
KSO3 <31>
KSO4 <31>
KSO5 <31>
KSO6 <31>
KSO7 <31>
KSO8 <31>
KSO9 <31>
KSO10 <31>
KSO11 <31>
KSO12 <31>
KSO13 <31>
KSO14 <31>
KSO15 <31>
KSO17 <30>
KSI0
EC_PLAYBTN# <30,31>
KSI1
EC_STOPBTN# <30,31>
KSI2
EC_FRDBTN# <30,31>
KSI3
EC_REVBTN# <30,31>
KSI4 <31>
KSI5 <31>
KSI6 <31>
KSI7 <31>
INVT_PWM <13>
BEEP# <24>
PWR_SU SP_LED# <30>
ACOFF <36>
USB_EN# <27>
EC_ON <33>
EC_LID_OUT# <16>
EC_EAPD <25>
ON/OFF <33>
KILL_SW# <23>
PM_SLP_S3# <16>
PM_SLP_S5# <16>
BTN_ID <30>
BATT_OVP <36>
ALI/MH# <35,36>
DAC_B RIG <13>
IREF <36>
EN_DFAN1 <32>
VOL_AMP <25>
PWR_LED# <30>
WL_LED# <30>
HDD_LED# <30>
BATT_LOW_LED# <30>
BATT_CHGI_LED# <30>
NOISE_TEST <24>
FAN_SPEED1 <32>
EC_THRM# <16>
EC_RSMRST# <16>
SHDD_LED# <17>
Compal Secret Data
Deciphered Date
2
+3VALW
R770 10K_0402_5%
R769 0_0402_5%@
R93
C271 0.22U_0603_16V7K
R133
R800
0.1U_0402_16V4Z
2
R116
10K_0402_5%
1 2
D13
2 1
CH751H-40_SC76
1 2
1 2
ECAGND
12
C272 0.01U_0402_16V7K
1 2
100K_0402_5%
1 2
For TI bug
R310
12
10K_0402_5%
1 2
4.7K_0402_5%
1 2
4.7K_0402_5%
100K_0402_5%
AD_BID0
1
C284
2
1
For EC Tools
JP6
ACES_85205-0400@
KSI[0..7]
KSO[0..15]
ACIN <30,34>
+3VALW
MINI_WAKE# <16,23>
BATT_TEMPA <35>
ADP_I <36>
+S1_VCC
1
1
2
3
4
E51_RXD
2
E51_TXD
3
4
KSI[0..7] <30,31>
KSO[0..15] <31>
+3VALW
E51_RXD <32>
E51_TXD <32>
SKU IDAnalog Board ID
100K_0402_5%
1
R745
0_0402_5%
2
1
+3VALW
R91
Rc
1 2
12
Rd
28 43
+3VALW
R92
Ra
1 2
R101
Rb
0_0402_5%
1 2
Compal Electronics, Inc.
Title
ENE-KB910
Size Document Number Rev
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
SKU_ID1
C873
0.1U_0402_16V4Z
of
Page 29
EC_SMB_CK1<28,35>
hexainf@hotmail.com
EC_SMB_DA1<28,35>
FWE#
SN74LVC32APWLE_TSSOP14
C341
1 2
0.1U_0402_16V4Z
6
U12B
+5VALW
+3VALW
O
1 2
14
P
A
B
G
7
8
7
6
5
C324
0.1U_0402_16V4Z
U11
A0
VCC
A1
WP
SCL
A2
SDA
GND
AT24C16AN-10SI-2.7_SO8
+3VALW
12
R170
100K_0402_5%
4
5
+5VALW
12
R145
100K_0402_5%
1
2
3
4
12
R158
100K_0402_5%
2
G
1 3
D
S
Q28
2N7002_SOT23
INT_FSEL#
R178
1 2
22_0402_5%
SUSP# <24,28,33,38,39>
EC_FLASH# <16>
FWR# <28>
+3VALW
14
INT_FLASH_EN#
1
P
A
3
O
1 2
FSEL#
2
B
G
7
U12A
SN74LVC32APWLE_TSSOP14
R177
0_0402_5%@
Reserve R4, if U1B is single gate.
R176
100K_0402_5%
1 2
FSEL# <28>
LPC Debug Port
+5VS +3VS
JP30
1
1
2
2
3
3
4
4
5
5
CLK_14M_SIO
6
6
LPC_AD0
7
7
LPC_AD1
8
8
LPC_AD2
9
9
LPC_AD3
10
10
LPC_FRAME#
11
11
LPC_DRQ1#
12
12
PCIRST#
13
13
14
1 2
14
R458 0_0402_5%@
15
15
SERIRQ
16
16
17
17
18
18
19
19
20
20
ACES_85201-2005@
CLK_14M_SIO <12>
LPC_AD0 <15,28,31,32>
LPC_AD1 <15,28,31,32>
LPC_AD2 <15,28,31,32>
LPC_AD3 <15,28,31,32>
CLK_PCI_SIO
PCIRST# <15, 1 7 , 20 ,21,23,26,28,31,32>
close to RAM Door
LPC_AD[0..3]<15,28,31,32>
CLK_PCI_SIO
@
22_0402_5%
LPC_FRAME# <15,19,28,31,32>
LPC_DRQ1# <15,32>
CLK_PCI_SIO <15,32>
SERIRQ <15,21,28,31,32>
LPC_AD[0..3]
R457
1 2
1
C658 10P_0402_50V8K@
2
KBA[0..19]<28>
ADB[0..7]<28>
KBA[0..19]
ADB[0..7]
1MB Flash ROM
1 2
+3VALW
1
C352
0.1U_0402_16V4Z
2
+3VALW
SB_INT_FLASH_SEL tie to ATI SB
GPIO1 and pull down
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
SB_INT_FLASH_SEL<16>
2005/11/01 2006/11/30
KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19
INT_FSEL#
FRD#<28>
FRD#
FWE#
U13
21
A0
20
A1
19
A2
18
A3
17
A4
16
A5
15
A6
14
A7
8
A8
7
A9
36
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
READY/BUSY#
40
A17
13
A18
37
A19
22
CE#
24
OE#
9
WE#
SST39VF080-70_TSOP40
VCC0
VCC1
GND0
GND1
RP#
NC0
NC1
31
30
ADB0
25
D0
D1
D2
D3
D4
D5
D6
D7
NC
ADB1
26
ADB2
27
ADB3
28
ADB4
32
ADB5
33
ADB6
34
ADB7
35
RESET#
10
11
12
29
38
23
39
R179
100K_0402_5%
1MB ROM Socket
KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
INT_FLASH_EN#
SB_INT_FLASH_SEL
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
Compal Secret Data
JP8
SUYIN_80065AR-040G2T@
Deciphered Date
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
KBA17
KBA19
KBA10
ADB7
ADB6
ADB5
ADB4
ADB3
ADB2
ADB1
ADB0
FRD#
FSEL#
KBA0
+3VALW
Title
Size Document Number Re v
Date: Sheet
Compal Electronics, Inc.
BIOS& I/O PORT
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
of
29 43
Page 30
5
4
3
2
1
+5VALW
21
D41 HT -191U YG-D T _G RN _0603
Green
12
R664
300_0402_5%
13
D
2
G
Q58
S
2N7002_SOT23
+5VALW
Battery LED
Green
300_0402_5%
R670
R767
300_0402_5%@
D52
HT-191UD_AMBER_0603 @
R822
0_0402_5%
Amber
300_0402_5%
R671
1 2
1 2
21
34
A
YG
HT-297DQ/GQ_AMB/YG_0603
D44
Green/Amber:SC500001900
Blue/Amber:SC597UDB000
BLAN <20>
100K_0402_5%
BTN_ID
R746
+3VALW
1 2
Q59
DTA114YKA_SC59
Vivace Button
Mode_Key
INBTN#
D43
1
CHN202U_SC70
D42
1
CHN202U_SC70
+3VALW
47K
2
10K
1 3
R668 300_0402_5%
1 2
R669 300_0402_5%
1 2
2N7002_SOT23
2
3
R665 100K_0402_5%
2
3
Q60
1 3
D
R667
1 2
51_ON#
1 2
51_ON#
2
G
PWR_SUSP_LED#
S
0_0402_5%@
IE_BTN# <28>
51_ON# <33,34>
SYSON
PWR_SUSPLED0#
PWR_SUSPLED1#
AC-IN LED
+3VALW
ACIN<28,34>
PWR_SUSP_LED# <28>
Low Active
PWR BTN/B
EC_PLAYBTN#<28,31>
D D
C C
EC_STOPBTN#<28,31>
EC_FRDBTN#<28,31>
EC_REVBTN#<28,31>
KSO17<28> MODE# <28>
BTN_ID<28>
ON/OFFBTN#<33>
EC_PLAYBTN#
EC_STOPBTN#
EC_FRDBTN#
EC_REVBTN#
KSO17
INBTN#
PWR_LED0#
PWR_SUSPLED0#
Mode_Key
BTN_ID
ON/OFFBTN#
EC_PLAYBTN#
EC_STOPBTN#
EC_FRDBTN#
EC_REVBTN#
KSO17
INBTN#
PWR_LED0#
PWR_SUSPLED0#
Mode_Key
BTN_ID
ON/OFFBTN#
ACES_85201-1205
12
11
10
9
8
7
6
5
4
3
2
1
JP37
C874 100P_0402_25V8K
C875 100P_0402_25V8K
C876 100P_0402_25V8K
C877 100P_0402_25V8K
C878 100P_0402_25V8K
C879 100P_0402_25V8K
C880 100P_0402_25V8K
C881 100P_0402_25V8K
C882 100P_0402_25V8K
C883 120P_0402_25V8K
C884 120P_0402_25V8K
HDD LED
+5VS
12
Green
B B
HDD_LED#<28>
PWR_SUSPLED1#
PWR_LED1#
A A
R672
300_0402_5%
21
D45
HT-191UYG-DT_GRN_0603
Amber
D47
YG
3 4
A
2 1
HT-297DQ/GQ_AMB/YG_0603
Green
Q61
DTA114YKA_SC59
+5VALW
47K
1 3
2N7002_SOT23
2
10K
R674 300_0402_5%
1 2
R675 300_0402_5%
1 2
Power LED
2
Q62
1 3
D
R673
1 2
G
S
0_0402_5%@
PWR_LED#
PWR_LED0#
PWR_LED1#
SYSO N <24,28,33>
PWR_LED# <28>
Low Active
Wireless Lan LED
Amber
HT-110UD_1204
Amber:SC5110UD000
WL_LED
WL_LED#<28>
2
2N7002_SOT23
G
Q63
BATT_CHGI_LED#<28> BATT_LOW_LED# <28>
+5VS
12
1 2
13
D
S
R676
300_0402_5%
D46
R821 0_0402_5%@
+5VS
12
21
12
12
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Kill SW/ Sub Conn./LEDS
Size Document Number Re v
HAWAA(LA3141) 0.2
Custom
Thursday, January 26, 2006
2
Date: Sheet
1
30 43
of
Page 31
5
hexainf@hotmail.com
4
3
2
1
TP CONN.
D D
TP Button
SW_L SW_R
C C
KSI[0..7]
KSO[0..15]
TP_DATA<28>
TP_CLK<28>
SW7
1
2
5
6
PSOT24C_SOT23
+5VS
3
4
SMT1-05_4P
3
D50
@
1
KSI[0..7] <28,30>
KSO[0..15] <28>
SW_R
SW_L
TP_DATA
TP_CLK
2
INT_KBD CONN.
1
C895 0.1U_0402_16V4Z
2
ACES_85201-0605
1
2
3
4
5
6
JP36
SW8
5
6
3
4
SMT1-05_4P
1
2
SW_R
C885 100P_0402_25V8K
SW_L
C886 100P_0402_25V8K
TP_DATA
C887 100P_0402_25V8K
TP_CLK
C888 100P_0402_25V8K
+3VS
12
R736
4.7K_0402_5%
TPM@
12
R738
4.7K_0402_5%@
Base I/O Address
0 = 02Eh
1 = 04Eh
*
TPM_XTALI
12
R740
10M_0402_5%
TPM@
TPM_XTALO
C867
0.1U_0402_16V4Z
TPM@
T1 PAD
T2 PAD
12
R739
0_0402_5%
TPM@
C871
TPM@
1 2
32.768KHZ_12.5P_1TJS125BJ2A251
1
IN
4
OUT
Y5
1 2
C872 18P_0402_50V8J
TPM@
TPM1.2 on board
+3VS+3VALW
1
2
6
GPIO
2
GPIO2
8
TEST1
9
TESTB1/BADD
3
NC
12
NC
1
NC
18P_0402_50V8J
2
NC
3
NC
TPM@
U44
0.1U_0402_16V4Z
C868
TPM@
5
10
19
24
VSB
VDD
VDD
VDD
LFRAME#
LRESET#
SLB 9635 TT 1.2
GND
4
XTALI/32K IN
GND
GND
11
18
CLKRUN#
GND
25
2
1
0.1U_0402_16V4Z
LAD0
LAD1
LAD2
LAD3
LPCPD#
SERIRQ
LCLK
PP
XTALO
SLB 9635 TT 1.2_TSSOP28TPM@
C869
TPM@
26
23
20
17
22
16
28
27
21
15
7
14
13
LPCPD1#
2
2
C870
0.1U_0402_16V4Z
1
CLK_PCI3
PM_CLKRUN#
+3VS
TPM@
1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
PCIRST#
LPCPD1#
SERIRQ
R737
12
4.7K_0402_5%TPM@
TPM_XTALO
TPM_XTALI
12
R789
10K_0402_5%@
R790 0_0402_5%
1 2
TPM@
LPC_AD0 <15,28,29,32>
LPC_AD1 <15,28,29,32>
LPC_AD2 <15,28,29,32>
LPC_AD3 <15,28,29,32>
LPC_FRAME# <15,19,28,29,32>
PCIRST# <15, 1 7 , 2 0,21,23,26,28,29,32>
SERIRQ <15,21,28,29,32>
CLK_PCI3 <15>
PM_CLKRUN# <15,20,21,26,28>
+3VS
LPCPD# <28>
JP5
1
2
B B
A A
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
ACES_88170-3400
KSO15
KSO14
KSO10
KSO11
KSO8
KSO9
KSO13
KSI7
KSO3
KSO7
KSO12
KSI4
KSI6
KSI5
KSO6
KSO5
KSI3
KSI0
KSO0
KSO1 KSO8
KSI1
KSI2
KSO2
KSO4
5
1 2
300_0402_5%
1 2
1 2
R297
R298300_0402_5%
R299300_0402_5%
+3VS
+3VS
+3VS
NUM_LED# <28>
PADS_LED# <28>
CAPS_LED# <28>
KSO7
C241 100P_0402_25V8K
KSO6
C236 100P_0402_25V8K
KSO5
C235 100P_0402_25V8K
KSO4
C227 100P_0402_25V8K
KSO3
C242 100P_0402_25V8K
KSI4
C239 100P_0402_25V8K
KSO2
C228 100P_0402_25V8K
KSO1
C231 100P_0402_25V8K
KSO0
C232 100P_0402_25V8K
KSI5
C237 100P_0402_25V8K
KSI6
C238 100P_0402_25V8K
KSI7
C243 100P_0402_25V8K
C246 100P_0402_25V8K
4
KSO15
KSO14
KSO13
KSO12
KSI0
KSO11
KSO10
KSI1
KSI2
KSO9
KSI3
PADS_LED#
NUM_LED#
CAPS_LED#
C250 100P_0402_25V8K
C249 100P_0402_25V8K
C244 100P_0402_25V8K
C240 100P_0402_25V8K
C233 100P_0402_25V8K
C247 100P_0402_25V8K
C248 100P_0402_25V8K
C230 100P_0402_25V8K
C229 100P_0402_25V8K
C245 100P_0402_25V8K
C234 100P_0402_25V8K
C252 100P_0402_25V8K
C253 100P_0402_25V8K
C251 100P_0402_25V8K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/11/01 2006/11/30
+3VALW
R515
1 2
0_0402_5%
0.1U_0402_16V4Z
Compal Secret Data
Deciphered Date
C743
1 2
R516 47K_0402_5%
U32
A3212EEH_MLP6
VDD5OUTPUT
4
1
NC
2
2
GND
3
Lid Switch
1
2
1
NC
C744
10P_0402_50V8J
2
LID_SW#
Compal Electronics, Inc.
Title
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
Date: Sheet
LID_SW# <28>
KB/Touch Pad
1
of
31 43
Page 32
A
B
C
D
E
FAN
1 2
FAN_SPEED1<28>
2
B
+5VS
1
C
E
3
12
Q36
FMMT619_SOT23
FAN1
D23
1N4148_SOT23
1000P_0402_50V7K@
12
D22
1SS355_SOD323
C170
+3VALW
1
C449
10U_0805_10V4Z
2
JP17
3
2
1
ACES_85205-0300
2
2
C171
1000P_0402_50V7K@
1
1
14
9
P
A
8
O
10
B
G
7
U12C
SN74LVC32APWLE_TSSOP14
+3VALW
14
12
P
A
11
O
13
B
G
7
U12D
SN74LVC32APWLE_TSSOP14
VS
1 1
R239
10K_0402_5%
EN_DFAN1
12
EN_DFAN1<28>
2 2
5
+IN
6
-IN
1 2
R240 8.2K_0402_5%
OUT
U22B
LM358A_SO8
7
EN_FAN1
1 2
R241
100_0402_5%
+3VS
2
C448
0.1U_0402_16V4Z@
1
R41 10K_0402_5%
MDC CONN.
R825
0_0402_5%@
R827
0_0402_5%
E51_TXD
LPC_DRQ1#
PCIRST# <15,1 7 , 2 0,21,23,26,28,29,31>
LPC_AD2 <15,28,29,31>
LPC_AD0 <15,28,29,31>
CLK_PCI_SIO <15,29>
E51_TXD <28>
LPC_DRQ1# <15,29>E51_RXD<28>
AZ_SDOUT_MDC<16>
AZ_SYNC_MDC<16>
AZ_SDIN0_MDC<16>
AZ_SDOUT_MDC
AZ_SYNC_MDC
AZ_SDIN0_MDC
AZ_RST#_MDC
+3VALW
R826
E51_RXD
SERIRQ<15,21,28,29,31>
3 3
SERIRQ
0_0402_5%@
1 2
1 2
R828
0_0402_5%
LPC_AD3<15,28,29,31>
LPC_AD1<15,28,29,31>
LPC_FRAME#<15,19,28,29,31>
LPC_AD3
LPC_AD1
LPC_FRAME#
H40
7
8
9
10
DEBUG_PAD
1 2
1 2
56
PCIRST#
4
LPC_AD2
3
LPC_AD0
2
CLK_PCI_SIO
1
Connector for MDC Rev1.5
JP27
1
GND1
3
IAC_SDATA_OUT
5
GND2
7
IAC_SYNC
9
IAC_SDATA_IN
11
IAC_RESET#
IAC_BITCLK
GND13GND14GND15GND16GND17GND
2
RES0
4
RES1
6
3.3V
8
GND3
10
GND4
12
ACES_88018-124G
18
MDC@
12
R747
10_0402_5%
@
C889
10P_0402_50V8K
@
AZ_BITCLK_MDC
+3VALW
AZ_BITCLK_MDC <16>AZ_RST_MDC#<16>
+3VALW
1
C353
0.1U_0402_16V4Z
2
MDC@
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
+3VALW
1
C350
1U_0402_6.3V4Z
2
MDC@
Compal Electronics, Inc.
Title
FAN & MDC
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
D
Date: Sheet
E
32 43
of
Page 33
A
hexainf@hotmail.com
+1.8VALW TO +1.8VS
+1.8VALW
Q19
8
D
7
D
1 1
6
D
5
D
SI4800BDY_SO8
1
C208
2
4.7U_0805_10V4Z
G
S
S
S
1
2
3
4
1
2
0.1U_0603_25V7K
+1.8VS
1
C226
2
1U_0402_6.3V4Z
D
C222
S
13
G
Q18
2N7002_SOT23
2
1
R58
1 2
100K_0402_1%
2
C225
10U_0805_10V4Z
SUSP
R52
470_0805_5%
1 2
13
D
2
G
Q17
S
2N7002_SOT23
B
+5VALW TO +5VS
+5VALW
Q46
8
7
6
5
SI4800BDY_SO8
1
C607
2
4.7U_0805_10V4Z
D
D
D
D
+5VS
1
C624
1
C618
2
C625
1U_0603_10V4Z
2
1 2
6.8K_0402_5%
13
D
2
G
Q45
S
2N7002_SOT23
1
S
2
S
3
S
4
G
0.1U_0603_25V7K
1
4.7U_0805_10V4Z
2
R417
SUSP
C
ON/OFFBTN#<30>
SMT1-05_4P
R418
470_0805_5%
1 2
+VSBP+VSBP
13
D
2
G
Q47
S
2N7002_SOT23
1
2
D
SW6
3
ON/OFFBTN#
4
5
6
Remove when MP
EC_ON<28>
4.7K_0402_5%
EC_ON
R247
1 2
100K_0402_5%
D26
1
CHN202U_SC70
2
+3VALW
R244
1 2
3
2
13
D
G
S
2N7002_SOT23
Power Button
51_ON#
1000P_0402_50V7K
C455
Q38
E
ON/OFF <28>
51_ON# <30,34>
D24
12
MMGZ5248B_LL34
2 1
+1.8VALW TO +1.8V
2 2
3 3
4 4
+1.8VALW +1.8V
S
S
S
G
1
2
3
4
1
2
0.1U_0603_25V7K
C27
1U_0402_6.3V4Z
C26
Q4
8
D
7
D
6
D
5
D
SI4800BDY_SO8
1
C16
2
4.7U_0805_10V4Z
+3VALW TO +3VS
+3VALW +3VS
S
S
S
G
1
2
3
4
1
2
0.1U_0603_25V7K
C608
1U_0402_6.3V4Z
C611
Q48
8
D
7
D
6
D
5
D
SI4800BDY_SO8
1
C622
2
4.7U_0805_10V4Z
1
C24 4.7U_0805_10V4Z
2
1 2
13
D
2
G
Q7
S
2N7002_SOT23
1
C610 4.7U_0805_10V4Z
2
1 2
68K_0402_1%
13
D
2
G
Q51
S
2N7002_SOT23
1
2
R18
100K_0402_1%
SYSON#
1
2
R416
SUSP
+VSBP
+VSBP
+5VALW
R24
470_0805_5%
1 2
13
D
2
G
Q9
S
2N7002_SOT23
+VSBP +5VALW +5VALW
1
R793
470_0805_5%
1 2
@
R415
470_0805_5%
1 2
13
D
2
G
Q49
S
2N7002_SOT23
C937
2
0.1U_0402_10V7K
SUSP<39>
SUSP#<24,28,29,38,39>
1
C938
2
0.1U_0402_10V7K
SYSON<24,28,30>
R53
10K_0402_5%
R54
10K_0402_5%
SUSP
1 2
SYSON#
1 2
R55
10K_0402_5%
1 2
13
D
Q16
2
2N7002_SOT23
G
S
+5VALW
R56
10K_0402_5%
1 2
13
D
Q15
2
2N7002_SOT23
G
S
SW10
SMT1-05_4P
1
2
3
ON/OFFBTN#
4
5
6
Remove when MP
+1.2VS +0.9VS
R39
470_0805_5%
1 2
13
D
SUSP SUSP
2
G
Q10
S
2N7002_SOT23
R109
470_0805_5%
1 2
@
13
D
2
G
Q25
S
2N7002_SOT23
@
A
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
DC-DC INTERFACE
Size Document Number Re v
HAWAA(LA3141) 0.3
Custom
Thursday, January 26, 2006
D
Date: Sheet
E
of
33 43
Page 34
A
DC301000O00
PJP1
1
+
2
+
3
1 1
2 2
+CHGRTC
3 3
-
4
-
SINGA_2DW-0005-B03@
BATT+
CHGRTCP N1
51_ON#<30,33>
1 2
560_0603_5%
(5A,200mils ,Via NO.= 10)
+5VALWP +5VALW
(5A,200mils ,Via NO.= 10)
DC_IN_S1 DC_IN_S2
PR17
1 2
560_0603_5%
PJ1
2
112
JUMP_43X118@
PJ3
2
112
JUMP_43X118@
PF1
PD2
PR11
PR12
PR14
RTCVREF
12
12
3.3V
12
PC10
10U_0805_10V4Z
21
7A_24VDC_429007.WRML
RLS4148_LLDS2
200_0603_5%
1 2
100K_0402_1%
1 2
22K_0402_1%
PR18
12
PC1
1000P_0402_50V7K
12
PC7
0.22U_1206_25V7M
S-812C33AUA-C2NT2G_SOT89-3
3
OUT
+1.2VSP +1.2VS+3VALWP +3VALW
FBMA-L18-453215-900LMA90T_1812
12
PQ1
TP0610K-T1-E3_SOT23
2
PU2
2
IN
GND
1
1U_0805_25V4Z
(5A,200mils ,Via NO.= 10)
(2A,80mils ,Via NO.= 4)
PJ5
+1.8VALWP +1.8VALW
4 4
+1.05VSP
2
112
JUMP_43X118@
PJ7
2
112
(8A,320mils ,Via NO.= 16)
(5A,200mils ,Via NO.= 10)
JUMP_43X118@
PJ8
2
112
JUMP_43X118@
A
(1A,40mils ,Via NO.= 2)
+1.05VS
PL1
1 2
PC2
100P_0402_50V8J
13
PR181
200_0603_5%
1 2
12
PC9
PJ2
2
JUMP_43X118@
PJ4
2
JUMP_43X118@
PJ6
2
JUMP_43X118@
VIN
1 2
12
12
2 1
112
112
112
12
PC3
1000P_0402_50V7K
PD1
RLS4148_LLDS2
12
PR8
68_1206_5%
PC8
0.1U_0603_25V7K
PD15
RLZ16B_LL34
B
PR9
68_1206_5%
+0.9VS+0.9VSP
VIN
VS
12
PC4
100P_0402_50V8J
1000P_0402_50V7K
MAINPWON<4,16,35,37>
ACON<36>
PC5
VL
VIN
12
VIN
PR20
100K_0402_1%
1 2
PD5
2
3
RB715F_SOT323
1000P_0402_50V7K
12
PR3
84.5K_0402_1%
12
PR6
20K_0402_1%
PD4
RLS4148_LLDS2
1
PC12
PR5
22K_0402_1%
1 2
12
12
PU1B
LM393DG_SO8
7
O
12
1000P_0402_50V7K
C
PC6
0.1U_0402_16V7K
10K_0402_1%
8
5
P
+
6
-
G
4
12
PC13
Precharge detector
15.97V/14.84V FOR
+1.5VS+1.5VSP
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
ADAPTOR
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
C
1 2
PR1 1M_0402_1%
VS
8
PU1A
3
P
+
1
O
2
-
G
LM393DG_SO8
4
PR10
12
RTCVREF
3.3V
PR13
1 2
1K_1206_5%
PR15
1 2
1K_1206_5%
PR16
1 2
1K_1206_5%
PR21
1 2
2.2M_0402_5%
PR23
1 2
12
34K_0402_1%
PR24
66.5K_0402_1%
2N7002-7-F_SOT23-3
PD3
RLZ4.3B_LL34
VL
12
PR25
191K_0402_1%
13
D
PQ2
S
PQ3
DTC115EUA_SC70
D
VS
12
PR2
5.6K_0402_5%
12
1 2
PR4
1K_0402_1%
PACIN
12
PR7
10K_0402_1%
ACIN <28,30>
PACIN <36,37>
Vin Detector
High 18.384 17.901 17.430
Low 17.728 17.257 16.976
B+
12
PR19
499K_0402_1%
12
PR22
499K_0402_1%
PR26
47K_0402_1%
1 2
2
G
13
2
Compal Electronics, Inc.
Title
Size Document Number Rev
B
Thursday, January 26, 2006
Date: Sheet
12
PC11
1000P_0402_50V7K
PACIN
+5VALWP
DCIN & DETECTOR
HAWAA(LA3141)
D
34 43
of
0.3
Page 35
A
hexainf@hotmail.com
B
C
D
PH1 under CPU botten side :
CPU thermal protection at 84 degree C
Recovery at 45 degree C
+3VALWP
VMB_A
FBMA-L18-453215-900LMA90T_1812
1 2
12
PC15
1000P_0402_50V7K
ALI/MH# <28,36>
+3VALWP
PL2
12
BATT_TEMPA <28>
EC_SMB_DA1 <28,29>
EC_SMB_CK1 <28,29>
PC16
0.01U_0402_25V7K
BATT+
100K_0603_1%_TH11-4H104FT
PH1
12
PC17
0.22U_0805_16V7K
VL VS
12
0.1U_0603_25V7K
12
PR36
22K_0402_1%
13.7K_0402_1%
1 2
PC14
PR32
12
12
TM_REF1
PC18
12
1000P_0402_50V7K
3
+
2
-
PR37
100K_0402_1%
PR39
100K_0402_1%
PR30
47K_0402_1%
1 2
8
PU3A
P
1
O
G
LM393DG_SO8
4
12
VL
VL
PR27
47K_0402_1%
1 2
1SS355_SOD323
PD6
MAINPWON <4,16,34,37>
13
PQ4
DTC115EUA_SC70
12
2
1 1
2 2
PJP2
SUYIN_250005MR007G132ZR@
BATT+
SMD
SMC
GND
BATT_S1
1
ALI/NIMH#
2
ID
B/I
TS
AB/I
3
TS_A
4
EC_SMDA
5
EC_SMCA
6
7
PR33
100_0402_5%
1 2
1 2
PR34
100_0402_5%
PR28
1K_0402_1%
1 2
12
PR38
1K_0402_1%
12A_65V_451012MRL
12
PR31
1K_0402_1%
PF2
21
1 2
47K_0402_1%
PR35
6.49K_0402_1%
PR29
12
PH2 near main Battery CONN :
BAT. thermal protection at 79 degree C
Recovery at 45 degree C
PQ41
TP0610K-T1-E3_SOT23
B+
3 3
2
G
100K_0402_1%
22K_0402_1%
1 2
13
D
PQ42
2N7002-7-F_SOT23-3
S
VL
PR184
100K_0402_1%
1 2
PR185
0_0402_5%
POK<37,38>
4 4
1 2
PC133
0.1U_0402_16V7K
A
12
PR183
PR182
12
12
PC131
0.22U_1206_25V7K
13
2
B
+VSBP
12
PC132
0.1U_0603_25V7K
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
100K_0603_1%_TH11-4H104FT
PC19
0.22U_0805_16V7K
2005/06/23 2006/10/22
Compal Secret Data
12
PH2
12
12
PR43
22K_0402_1%
Deciphered Date
C
PR42
10.7K_0402_1%
1 2
TM_REF1
5
+
6
-
47K_0402_1%
1 2
VLVL
PR40
PR41
8
P
G
4
47K_0402_1%
1 2
PU3B
7
O
LM393DG_SO8
Title
Size Document Number Rev
B
Date: Sheet
PD7
12
1SS355_SOD323
Compal Electronics, Inc.
BATTERY CONN /OTP
HAWAA(LA3141)
Thursday, January 26, 2006
D
35 43
0.3
of
Page 36
A
B
C
D
1
2
1 2
4700P_0402_25V7K
1 2
PC29
1000P_0402_50V7K
0.1U_0402_16V7K
12
PC33
0.1U_0402_16V7K
7
Iadp=0~3.7A
4
3
PR44
0.02_2512_1%
12
PR49
100K_0402_1%
PR52
10K_0402_1%
PC27
1 2
PR54
1K_0402_1%
PC30
1 2
12
PR59
10K_0402_1%
ALI/MH#<28,35>
8
PU5B
5
P
+
0
6
-
G
LM358DT_SO8
4
Security Classification
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SE CRET INFOR MATI ON. THIS SHEET MAY NOT BE TRANSF ERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B
PR62
150K_0603_0.1%
VL
Issued Date
PU4
1
-INC2
+INC2
2
OUTC2
GND
3
+INE2
CS
4
-INE2
VCC(o)
5
FB2
OUT
6
VREF
VH
7
FB1
VCC
8
-INE1
RT
9
+INE1
-INE3
10
OUTC1
FB3
11
OUTD
CTL
12
-INC1
+INC1
MB3887PFV-ERE1_SSOP24
12
100K_0402_1%
DTC115EUA_SC70
1 2
PR180
2
PQ40
2N7002-7-F_SOT23-3
PJ9
2
112
JUMP_43X118@
24
23
22
21
20
1 2
19
PC28
0.1U_0603_25V7K
18
1 2
17
PR55
68K_0402_5%
16
1 2
15
47K_0402_1%
ACON
14
13
CS
0.1U_0603_25V7K
PR60
12
PC20
4.7U_1206_25V6K
PC24
0.022U_0402_16V7K
1 2
1 2
PC25
0.1U_0603_25V7K
PC31
1 2
1 2
PC32
1500P_0402_50V7K
12
PC21
4.7U_1206_25V6K
EC31QS04
4.2V
PQ39
D
S
13
G
2
13
12
PR179
300K_0603_0.1%
PR63
300K_0603_0.1%
BATT Type Charge Current IREF
8 CE LL 3 A 3.144V
6 CELL 3A 3.144V
4 CE LL 0V 1.5A 1.572V
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
C
12
PC22
4.7U_1206_25V6K
36
N18
578
16UH_LF919AS-160M=P3_3.7A_20%
12
PD9
12
12
ALI/MH#
3.3V
B++
241
PQ9
AO4407_SO8
LXCHRG
PL3
1 2
PD10
EC31QS04
0V
PQ5
ACOFF#
47K_0402_1%
1 2
PR48
10K_0402_1%
1 2
13
2
PQ11
DTC115EUA_SC70
AO4407_SO8
1
2
3 6
PR47
8
7
5
4
VIN
ACOFF <28>
CC=0.5~3.0A
CV=12.6V(6 CELLS LI-ION)
CV=16.8V(4/8 CELLS LI-ION)
1
2
Title
Size Document Number Rev
B
Date: Sheet
4
PR58
0.02_2512_1%
3
4.7U_1206_25V6K
4.7U_1206_25V6K
PC34
12
PC35
12
Compal Electronics, Inc.
CHARGER
HAWAA(LA3141)
Thursday, January 26, 2006
D
4.7U_1206_25V6K
12
PC36
36 43
0.3
of
BATT+
P2
PQ6
AO4407_SO8
VIN
1 1
12
PR46
47K_0402_1%
2
13
D
2
G
PQ12
S
2N7002-7-F_SOT23-3
2 2
PACIN<34,37>
ACON<34>
8
7
5
47K
2
47K
13
PQ10
DTC115EUA_SC70
ACOFF#
PACIN
1 3
1SS355_SOD323
1 2
1 2
4
PQ8
DTA144EUA_SC70
PD8
PR57
3K_0402_1%
1
2
36
12
PC23
0.1U_0603_25V7K
2
G
IREF=1.07*Icharge
PQ7
AO4407_SO8
1
2
3 6
12
PR45
200K_0402_1%
12
PR53
150K_0402_1%
PQ13
13
D
2N7002-7-F_SOT23-3
S
8
7
5
4
ADP_I<28>
12
PC26
PR51
0.1U_0402_16V7K
162K_0402_1%
IREF<28>
1 2
100K_0402_1%
IREF=0.6V~3.144V
+3VALWP
12
PR64
47K_0402_1%
3 3
FSTCHG<28>
2
13
PQ15
DTC115EUA_SC70
CS
13
2
PQ14
DTC115EUA_SC70
OVP voltage : LI
3S2P : 13.5V--> BATT_OVP= 1.5V
4S1P/4S2P : 18V--> BATT_OVP= 2V
(BAT_OVP=0.1111 *VMB)
VS
8
PU5A
3
P
+
1
4 4
BATT_OVP<28>
12
PR69
2.2K_0402_5%
A
0
2
-
G
LM358DT_SO8
4
PR70
105K_0402_1%
P3 B+
12
12
PR50
30K_0402_1%
10K_0402_1%
PR56
VMB_A
12
12
12
12
PR61
PR65
340K_0402_1%
PR68
499K_0402_1%
12
12
PC38
0.01U_0402_25V7K
Page 37
5
hexainf@hotmail.com
4
3
2
1
+3.3VALWP/+5VALWP
GND
12
20
V+
PC55
PR73
10_1206_5%
12
PC48
13
TON
LDO3
25
12
4.7U_0805_6.3V6K
BST_3V
1 2
0.1U_0603_25V7K
17
VCC
PGOOD
PRO#
10
1 2
VL
12
PC44
47_0402_5%
0.1U_0402_16V7K
PR71
2VREF_8734
PC46
1 2
1U_0603_6.3V6M
ILIM3
5
ILIM3
ILIM5
11
ILIM5
28
BST3
26
DH3
24
DL3
27
LX3
22
OUT3
FB3
MAX8734AEEI+_QSOP28
PR88
0_0402_5%
FB3
7
2
B+++
PQ18
PQ20
1 2
1 2
5
4
5
4
PR86
6.81K_0402_1%
PR89
10K_0402_1%
PL5
D8D7D6D
S1S2S3G
D8D7D6D
S1S2S3G
12
+3VALWP
1
+
PC53
150U_V_6.3VM_R18
2
12
12
PC43
PC42
PR76
PR77
1 2
1 2
43.2K_0402_1%
43.2K_0402_1%
PR79
PR80
1 2
1 2
BST_3V-1
DH_3V-1
499K_0402_1%
0_0603_5%
POK <35,38>
499K_0402_1%
PR82
12
LX_3V
4.7U_1206_25V6K
PC50
0.1U_0603_25V7K
12
0_0603_5%
SI4800BDY-T1-E3_SO8
4.7U_1206_25V6K
DH_3V
SI4810BDY-T1-E3_SO8
PR81
1 2
DL_3V
10U_LF919AS-100M-P3_4.5A_20%
BST_5V
2
14
16
15
19
21
9
1
6
4
3
12
8
0.22U_0603_10V7K
PU6
BST5
DH5
LX5
DL5
OUT5
FB5
N.C.
SHDN#
ON5
ON3
SKIP#
REF
3
1
12
PR72
10_1206_5%
12
PC45
4.7U_1206_25V6K
18
LD05
B+++
23
D D
PJ12
B+
112
JUMP_43X118@
C C
B B
B+++
2
12
12
PC40
PC39
4.7U_1206_25V6K
4.7U_1206_25V6K
10U_LF919AS-100M-P3_4.5A_20%
+5VALWP
1
+
PC51
2
150U_V_6.3VM_R18
PL4
PR83
10.5K_0402_1%
1 2
PR87
1 2
6.81K_0402_1%
12
PC41
2200P_0402_50V7K
12
1 2
VS
MAINPWON<4,16,34,35>
PD12
RLZ5.1B_LL34
5
D8D7D6D
S1S2S3G
4
5
PQ21
D8D7D6D
SI4810BDY-T1-E3_SO8
S1S2S3G
4
PR84
1 2
47K_0402_1%
100K_0402_1%
PQ19
SI4800BDY-T1-E3_SO8
PR75
0_0603_5%
DH_5V
1 2
DL_5V
12
12
PR172
0_0402_5%
PR92
PC52
1U_1206_25V7K@
12
DH_5V-1
PC49
0.1U_0603_25V7K
PACIN<34,36>
VL
12
PR91
12
806K_0603_1%
PR85
1 2
10K_0402_1%
DAP202U_SOT323
PC47
PR78
0_0603_5%
2VREF_8734
VL
4.7U_0805_6.3V6K
LX_5V
12
12
FB5
PD11
BST_5V-1
12
PC54
12
0.047U_0603_16V7K
A A
5
PC56
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/11/01 2006/11/30
3
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
2
Date: Sheet
+5V/+3V
HAWAA(LA3141)
Thursday, January 26, 2006
1
of
37 43
0.3
Page 38
A
B
C
D
PJ13
2
PC60
4.7U_1206_25V6K
12
1 2
1 2
JUMP_43X118@
PC71
0.01U_0402_25V7K
12
12
PC66
PD14
BST_1.8V-1
12
1 2
0_0603_5%
PR98
1 2
0_0603_5%
PR102
3K_0402_1%
1 2
DL_1.8V
PC58
4.7U_1206_25V6K
12
1
2
PR96
PC61
3
BST_1.2V-1
PC64
12
0.01U_0402_25V7K
12
4.7U_0805_6.3V6K
6
5
4
ISE_1.8V ISE_1.2V
7
2
PC57
4.7U_1206_25V6K
1 1
DAP202U_SOT323
5
D8D7D6D
+1.8V
+1.8VALWP
1.8U_D104C-919AS-1R8N_9.5A_30%
1
+
PC68
220U_D2_4VM_R15
2
12
PR100
12
PC69
0.01U_0402_25V7K
2 2
10K_0402_1%
PR101
1 2
1 2
0_0402_5%
SI4800BDY-T1-E3_SO8
PL7
SI4810BDY-T1-E3_SO8
PQ25
LX_1.8V
PQ27
S1S2S3G
D8D7D6D
S1S2S3G
4
DH_1.8V-2
5
4
0.1U_0603_25V7K
3
10
15
11
12
PR113
100K_0402_1%
9
8
PR108
10K_0402_1%
VSE_1.8V
POK<35,37> SUSP# <24,28,29,33,39>
12
PR111
0_0402_5%@
1 2
1 2
PR106
0_0402_5%
0.1U_0402_16V7K@
PC73
12
PR94
0_1206_5%
12
PC62
0.1U_0603_25V7K
PU7
SOFT1
BOOT1
UGATE1
PHASE1
ISEN1
LGATE1
PGND1
VOUT1
VSEN1
EN1
PG1
OCSET1
12
12
PL8
1 2
0_0402_5%
VSE_1.2V
PR109
0_0402_5%@
12
PR104
PC59
LX_1.2V
4.7U_1206_25V6K
5
4
5
4
D8D7D6D
PQ26
SI4800BDY-T1-E3_SO8
S1S2S3G
1.8U_D104C-919AS-1R8N_9.5A_30%
D8D7D6D
PQ28
SI4810BDY-T1-E3_SO8
S1S2S3G
+5VALW
PC65
17
0.01U_0402_25V7K
BST_1.2V-2BST_1.8V-2
23
DH_1.2V-1 DH_1.2V-2DH_1.8V-1
24
25
22
27
26
20
19
21
16
18
12
PC63
2.2U_0805_10V6K
12
PR97
1 2
0_0603_5%
12
PR112
100K_0402_1%
0.1U_0603_25V7K
PR99
1 2
0_0603_5%
PR103
2K_0402_1%
1 2
12
PC67
12
DL_1.2V
1 2
PR107
0_0402_5%
PC72
0.1U_0402_16V7K@
PR95
2.2_0603_5%
1 2
14
28
VCC
SOFT2
VIN
BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
PGND2
VOUT2
VSEN2
EN2
PG2/REF
GND
1
OCSET2
DDR
ISL6227CAZ-T_SSOP28
13
B+
112
+1.2V
+1.2VSP
12
PR105
2.21K_0402_1%
12
PR110
6.49K_0402_1%
1
+
PC70
220U_D2_4VM_R15
2
3 3
4 4
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2005/11/01 2006/11/30
Compal Secret Data
Deciphered Date
C
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
Date: Sheet
+1.8V/+1.2V
HAWAA(LA3141)
Thursday, January 26, 2006
0.3
of
D
38 43
Page 39
5
hexainf@hotmail.com
4
3
2
1
D D
PR117
10K_0402_1%
1 2
PGD_IN<40>
SUSP#<24,28,29,33,38>
C C
B B
10U_1206_25VAK
0.1U_0402_16V7K@
1 2
PR123
0_0402_5%
SUSP<33>
A A
+3VS
PC87
PQ38
2N7002-7-F_SOT23-3
PC94
2
G
12
1
PJ11
1
JUMP_43X79@
2
2
12
1.15K_0402_1%
13
D
1K_0402_1%
S
12
PR124
12
PR127
0.1U_0402_16V7K
PR114
0_0402_5%
1 2
12
PC78
0.1U_0402_16V7K@
PU10
2
3
4
APL5331KAC-TRL_SO8
+1.5VSP
12
12
PC92
PC93
10U_1206_25VAK
PU8
7
POK
8
EN
VIN1VCNTL
GND
VREF
VOUT
+5VS
12
6
VIN
VOUT
VCNTL
VOUT
FB
VIN
GND
APL5912-KAC-TRL_SO8
1
6
5
NC
7
NC
8
NC
9
TP
PC76
1U_0603_6.3V6M
5
4
3
2
9
+5VALWP
12
PC91
1U_0603_6.3V6M
+1.2VSP
1
1
2
2
12
PC77
22U_1206_6.3V6M
316_0402_1%
1K_0402_1%
PJ14
JUMP_43X118@
PR115
PR116
12
12
12
PC79
0.01U_0402_25V
SUSP
0.1U_0402_16V7K@
12
PC80
22U_1206_6.3V6M
10U_1206_25VAK
2N7002-7-F_SOT23-3
1 2
PR125
0_0402_5%
PC97
PC88
12
+1.8V
PQ31
+1.05VSP
1
+
PC81
150U_D2E_6.3VM_R18@
2
1
PJ10
1
JUMP_43X118@
2
2
12
13
D
2
G
S
PR122
1K_0402_1%
PR126
1K_0402_1%
12
12
PC95
0.1U_0402_16V7K
12
PU9
2
3
4
APL5331KAC-TRL_SO8
+0.9VSP
12
PC96
10U_1206_25VAK
VIN1VCNTL
GND
VREF
VOUT
6
5
NC
7
NC
8
NC
9
TP
+3VALWP
12
PC89
1U_0603_6.3V6M
5
Security Classification
Issued Date
THIS SHEET OF EN GINEER ING DR AWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED B Y OR D ISCLOS ED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2005/06/23 2006/10/22
Compal Secret Data
Deciphered Date
Compal Electronics, Inc.
Title
Size Document Number Rev
Custom
2
Date: Sheet
+1.05V/+1.5V/+0.9V
HAWAA(LA3141)
Thursday, Jan uary 26, 2006
0.3
39 43
1
of
Page 40
5
4
3
2
1
D D
<5>
<5>
<5>
PR129
0_0402_5%
DPRSLPVR<4,15>
H_DPRSTP#<4>
CLK_EN#<12>
+3VS
+3VS
12
PR135
C C
VGATE<17>
PGD_IN<39>
VR_TT#
0.015U_0402_16V7K@
B B
VCCSENSE<5>
+CPU_CORE
A A
H_PSI#<5>
PR143
1 2
4.22K_0402_1%@
1 2
PC112
1000P_0402_50V7K
1 2
61.9K_0402_1%
PR160
1 2
20_0402_5%
499_0402_1%
PC115
PR153
1 2
3.4K_0402_1%
PR158 1.82K_0402_1%
VSSSENSE<5>
5
1.91K_0402_1%
PR136
1 2
PR142
1 2
147K_0402_1%
PH3
1 2
100K_0603_1%_TH11-4H104FT@
1 2
PR144
1 2
13K_0402_1%
1 2
PR147
1 2
3.57K_0402_1%
1 2
PC116
5600P_0402_25V7K
PC118
1500P_0402_50V7K
PC121
1 2
390P_0402_50V7K
PR156
1 2
1 2
PR159
0_0402_5%
20_0402_5%
VCC_PRM
PC113
0.033U_0603_25V7K
12
PC122
1 2
470P_0402_50V7K
12
@
12
PR163
0.22U_0603_10V7K
PC124 0.018U_0603_50V7J
PC125
0.018U_0603_50V7J
1 2
1 2
PR130
0_0402_5%
1 2
PR131 0_0402_5%
1 2
PR133
0_0402_5%
1 2
12
PC106
1 2
1U_0603_6.3V6M
10
11
12
PR154
0_0402_5%@
1
2
3
4
5
6
7
8
9
49
PGOOD
PSI#
PGD_IN
RBIAS
VR_TT#
NTC
SOFT
OCSET
VW
COMP
FB
FB2
12
PR155
0_0402_5%@
GND
1 2
1 2
PR162 0_0402_5%
PC127 180P_0402_50V8J
1 2
1 2
PR165
1K_0402_1%
PC129
1 2
5.36K_0402_1%
48
47
3V3
VDIFF13VSEN14RTN15DROOP16DFB17VO18VSUM19VIN20GND21VDD22ISEN223ISEN1
12
PR166
PR132
45
46
CLK_EN#
DPRSTP#
DPRSLPVR
ISL6262CRZ-T_QFN48
PC126
0.018U_0603_50V7J
1 2
4
VR_ON
12
44
VR_ON
<5>
<28>
CPU_VID4
CPU_VID3
CPU_VID5
CPU_VID6
0_0402_5%
43
12
PC123
0.22U_0603_16V7K
VSUM
12
PR164
11K_0402_1%
PC128
0.068U_0402_16V7K
12
PC130
0.22U_0402_6.3V6K
1 2
<5>
<5>
<5>
CPU_VID2
CPU_VID1
CPU_VID0
12
12
PC102
PC103
0.01U_0402_25V7K
1U_0603_6.3V6M
PC107
0.22U_0603_10V7K
BOOT_CPU1
1 2
0_0603_5%
VID037VID138VID239VID340VID441VID542VID6
36
BOOT1
UGATE1
PHASE1
PGND1
LGATE1
PVCC
LGATE2
PGND2
PHASE2
UGATE2
BOOT2
NC
24
1 2
PR152
12
1_0603_5%
PC120
1U_0603_6.3V6M
PR157
10_0603_5%
12
PR161
2.61K_0402_1%
PH4
10KB_0603_5%_ERTJ1VR103J
1 2
Security Classification
35
34
33
32
31
30
29
28
27
26
25
PU11
ISEN1
ISEN2
UGATE_CPU1
PHASE_CPU1
BOOT_CPU2
+CPU_B+
LGATE_CPU1
PHASE_CPU2
1 2
PR145
0_0603_5%
+5VS
LGATE_CPU2
UGATE_CPU2
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
1 2
PR134
IRF8113PBF_SO8
1 2
PC114
0.22U_0603_10V7K
IRF8113PBF_SO8
2005/11/01 2006/11/30
3
+5VS
PR128
1_0603_5%
1 2
12
12
PC105
PC104
0.01U_0402_25V7K
PQ33
PQ36
1U_0603_6.3V6M
578
3 6
578
PQ32
SI7840DP-T1-E3_SO8
3 5
241
578
241
PQ34
IRF8113PBF_SO8
3 6
241
3 5
241
PQ35
SI7840DP-T1-E3_SO8
578
3 6
241
PQ37
IRF8113PBF_SO8
3 6
241
PC99
10U_1206_25VAK
12
PC100
10U_1206_25VAK
12
PR137
4.7_1206_5%@
12
PC108
680P_0603_50V8J@
PC110
12
PR146
4.7_1206_5%@
12
PC117
680P_0603_50V8J@
Compal Secret Data
Deciphered Date
2
12
12
10U_1206_25VAK
+CPU_B+
1
12
PC101
10U_1206_25VAK
12
PR138
3.65K_0805_1%
VSUM VSUM
2
0.36UH_MPC1040LR36_24A_20%
12
ISEN1
FBMA-L18-453215-900LMA90T_1812
+
PC98
220U_25V_M
PL12
PR139
10K_0402_1%
PR141
0_0603_5%@
1 2
1 2
PC109
0.22U_0603_10V7K
+CPU_B+
PL11
1 2
12
12
PR140
1_0402_5%
VCC_PRM
B+
+CPU_CORE
12
PC111
10U_1206_25VAK
0.36UH_MPC1040LR36_24A_20%
12
PR149
3.65K_0805_1%
Title
Size Document Number Rev
Custom
Date: Sheet
PL13
12
12
PR148
10K_0402_1%
PR151
0_0603_5%@
1 2
1 2
PC119
0.22U_0603_10V7K
ISEN2
12
PR150
1_0402_5%
VCC_PRM
Compal Electronics, Inc.
+CPU_CORE
HAWAA(LA3141)
Thursday, January 26, 2006
1
40 43
0.3
of
Page 41
5
hexainf@hotmail.com
D D
C C
AZ_SDOUT_MOM<16>
AZ_SYNC_MOM<16>
AZ_SDIN1_MOM<16>
AZ_RST_MOM#<16> AZ_BITCLK_MOM <16>
AZ_SDOUT_MOM
AZ_SYNC_MOM
AZ_SDIN1_MOM
AZ_RST_MOM#
AC17 47pF
GND
4
AJ1
1
GND
AC97_SDATA_OUT3RSVD
5
GND
7
AC97_SYNC
9
AC97_SDATA_IN
AC97_RESETN11AC97_BITCLK
13
MT1
MDC1.5 MODEM MALE@
1
AM1
AR15
100
GND
AR13
10K
2
3
4
5
6
15
@
MTG_HOLE
SDATA_IN
SDATA_OUT
SYNC
BITCLK
ASEL
RESET_N
+3.3V
9
VDD1VDD7VDD
LSEL/GPO0
VSS8VSS
11
SV92A3_16
TSEL
XFRP
XFRN
GPIO1
AU1
3
AFB3
BLM21AG601SN1
+3VALW
2
RSVD
4
6
3.3V
8
GND
10
GND
12
14
MT2
AC18
0.1uF
AC15
0.1uF
14
13
12
10
16
AR14
10K
+3.3V
GND
@
AC13
10uF
P-XFRP <42>
P-XFRN <42>
AZ_BITCLK_MOM
2
1
GND
B B
GND
A A
5
4
AM2
1
MTG_HOLE
AC-97 Line Select:
-Line 1: DNP R14
-Line 2:
POPULATE R14
Compal Electronics, Inc.
123
Design Engineer: C. Russo
Title
DELPHI SV92A3 MDC 1.5 Reference Design
Size Document Number Rev
B
HAWAA(LA3141)
3
2
Date: Sheet
41 43Thursday, January 26, 2006
1
0.3
of
Page 42
5
4
3
2
1
See FUSE Note, bottom of page.
AFB1
D D
AU2 CSP1040_TSSOP20
1
VDDA
2
VDDD
C C
AC9
2.2uF
DAA
3
6
7
TSTCLK
SCL
SDA
CSP1040
TSSOP_20
POLARIS
ATX1
1
Locate C11, C12
as close to
digital device as
possible.
B B
P-XFRP<41>
P-XFRN<41>
AC11
22pF
GND
AC12
22pF
GND
4
2 3
P950003
FUSE Note:
The UL standard UL 1950 dictates the use of a fuse (needed to pass the
M1, 600 V, 40A, 1.5 sec) to prevent component flaming during the
overvoltage test. Unless one can insure that the modem is in a fire
enclosure and provide 26 gauge line cord (acts as a fuse), a fusing
element wou l d be required.
A A
DAA
4
XFRP
5
XFRN
8
GPIO0
9
GPIO1
10
VSS
VSS_PAD
21
DAA
TDC
RDC
HS1
HS2
RXAC
RXDC
LMS
ACM
GYC
20
19
18
17
11
DAA
12
14
LM
15
16
13
475K 1%
E C
AC5
0.015uF
AR5
4.99K 1% 1/4W
AR5A
4.99K 1% 1/4W
AC7
4700pF
AR8
DAA
AR1 15M 1%
AR2 15M 1%
AQ3
MMBTA42
B
AC14
0.027uF
DAA
AC6
DAA
B
AQ5
PMBTA06
AR6
340 1%
AC8
0.47uF
AC3 0.047U_0603_50V7K
AR3 100K 1%
AR11
665K, 1%
MMBTA92
AR4
1.5K 1%
E C
1
AR7
6.8 1%
32
4
DAA
0.015uF
AD1
CMPD2004S
AD2
CMPD2004S
0.015uF
AQ4
PHILIPS BCP53-16
Collector Heat Sink Area
B
AQ2
AC4
2
2
AR10
487K, 1%
3
3
B
EC
DAA
EC
AQ1
MMBTA92
A K
330pF
1
1
DAA
330pF
AD3
BZT52C43
AC1
AC2
Alternatively , i f a T N V-1 flame resistant material is used, either as a
wrap or cover over the DAA portion of the modem, this could satisfy both
overvoltage protection and the separation requirement also contained in
UL 1950. This latter requirement provides isolation such that unearthed
parts of the D AA cannot be touched by a test finger or test probe.
5
4
3
2
BLM21AG601SN1
GND
AFB2
BLM21AG601SN1
GND
Compal Electronics, Inc.
123
Design Engineer: R. Trevino
Title
DELPHI SV92A3 MDC 1.5 Reference Design
Size Document Number Rev
B
HAWAA(LA3141)
Date: Sheet
P3100SB
2 1
ASID1
AF1
0466005
AC19
0.012uF
@
1
AE1
1
AJ2
1
2
E&T
AE2
1
0.3
42 43Thursday, January 26, 2006
of
Page 43
5
hexainf@hotmail.com
4
3
HW4 Product Improvement Record (P.I.R.)
2
1
Phase: A to B Date: 2006/01/04
Page#
D D
33
28
Action Plan
(add; del; change)
Add
Change Change to the corret NET name
Location or
Net_List
R793
EC_PLAYBTN#
EC_STOPBTN#
EC_FRDBTN#
EC_REVBTN#
Before value
(Attached file)
EC_PLAYBTN#
EC_STOPBTN#
EC_FRDBTN#
EC_REVBTN#
Add R800
15
C C
25 Add
Add 10K_0402_5%
R794 For EMI SSC chip use
C906,C907
R798,R799
After value
(Attached file)
470_0805_5% 0.2
KSI0
KSI1
KSI2
KSI3
1K_0402_5% For solve AC-IN LED issue
1U_0402
1.5K_0402_5%
Writer: Steve Chiu
Detail Discretion and Root Cause
For B+ issue
Update DDR DIMM Footprint
For solve audio noise 0.2
Rev.
DL/DM Check
0.2
0.228
0.210 Change JP16
0.2
B B
A A
5
Security Classification
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
Compal Secret Data
Deciphered Date
2006/11/012005/11/01
2
Title
Size Document Number Rev
Date: Sheet
Compal Electronics, Inc.
PIR
43 43Thursday, January 26, 2006
1
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