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XC61F Series
ETR0202_006
Voltage Detectors, Delay Circuit Built-In
GENERAL DESCRIPTION
The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies. A delay circuit is built-in to each detector.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-ch open drain output configurations are available.
Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible.
PPLICATIONS
●Microprocessor reset circuitry
●Memory battery back-up circuits
●Power-on reset circuits
●Power failure detection
●System battery life and charge voltage monitors
●Delay circuitry
TYPICAL APPLICATION CIRCUITS
FEATURES
Highly Accurate : ± 2%
Low Power Consumption
Detect Voltage Range
Operating Voltage Range
Detect Voltage Temperature Characteristics
:±100ppm/℃(TYP.)
Built-In Delay Circuit : ① 1ms ~ 50ms
② 50ms ~ 200ms
③ 80ms ~ 400ms
Output Configuration :
Operating Ambient Temperature :
Packages : SOT-23
SOT-89
TO-92
Environmentally Friendly
arts are available with an accuracy of ± 1%
* No
TYPICAL PERFORMANCE
CHARACTERISTICS
●Release Delay Time vs. Ambient Temperature
(ms)
DR
: 1.0μA(TYP.)[ VIN=2.0V ]
:
1.6V ~ 6.0V in 0.1V increments
: 0.7V ~ 10.0V
N-ch open drain output or CMOS
30℃〜+80℃
: EU RoHS Compliant, Pb Free
N-ch open drain output
Release Delay Time: t
Ambient Temperature:Ta(℃)
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XC61F Series
PIN CONFIGURATION
PIN ASSIGNMENT
PIN NUMBER
SOT-23 SOT-89 TO-92
3 2 2 VIN Supply Voltage Input
2 3 3 VSS Ground
1 1 1 V
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1
V
OUT
(TOP VIEW)
２
V
IN
SOT-89
3
V
SS
TO-92
(SIDE VIEW)
PIN NAME FUNCTION
Output
OUT
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PRODUCT CLASSIFICATION
●Ordering Information
XC61F ①②③④⑤⑥⑦‑⑧
(*1)
DESIGNATOR ITEM SYMBOL DESCRIPTION
①
Output Configuration
C CMOS output
N N-ch open drain output
②③
Detect Voltage 16 ~ 60
e.g. 2.5V → ②2 , ③5
e.g. 3.8V → ②3, ③8
1 50ms ~ 200ms
④
Release Output Delay
4 80ms ~ 400ms
5 1ms ~ 50ms
⑤
Detect Accuracy 2
Within ± 2.0%
MR SOT-23 (3,000/Reel)
MR-G SOT-23 (3,000/Reel)
PR SOT-89 (1,000/Reel)
⑥⑦-⑧
(*1)
Packages (Order Unit)
PR-G SOT-89 (1,000/Reel)
TH TO-92 Taping Type: Paper type (2,000/Tape)
TH-G TO-92 Taping Type: Paper type (2,000/Tape)
TB TO-92 Taping Type: Bag (500/Bag)
TB-G TO-92 Taping Type: Bag (500/Bag)
(*1)
The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
BLOCK DIAGRAMS
(1) CMOS output
(2) N-ch open drain output
XC61F
Series
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ABSOLU
GS
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XC61F Series
Output Voltage
Power Dissipation
Operating Ambient Temperature Topr
ELECTRICAL CHARACTERISTICS
PAR AMETER
Detect Voltage VDF
Hysteresis Width VHYS
Supply Current ISS
Operating Voltage VIN VDF= 1.6V to 6.0V 0.7 - 10.0 V ①
Output Current IOUT
Leak
Current
Detect Voltage
Temperature
Characteristics
Release Delay Time
(V
DR → VOUT inversion)
VDF (T): Setting detect voltage value
Release Voltage: V
* Release Delay Time: 1ms to 50ms & 80ms to 400ms versions are also available.
Note: The power consumption during power-start to output being stable (release operation) is 2μA greater than it is after that period
(completion of release operation) because of delay circuit through current.
TE MAXIMUM RATIN
PAR AMETER SYMBOL RATINGS UNITS
Input Voltage VIN V
Output Current I
50 mA
OUT
CMOS VSS -0.3 ~ VIN + 0.3
V
N-ch open drain
OUT
output
SOT-23 250
SOT-89 500
Pd
TO-92
Storage Temperature Tstg
SYMBOL
CONDITIONS MIN. TYP. MAX.
VIN = 1.5V - 0.9 2.6
VIN = 2.0V - 1.0 3.0
VIN = 3.0V - 1.3 3.4
VIN = 4.0V - 1.6 3.8
V
IN = 5.0V - 2.0 4.2
VIN = 1.0V 1.0 2.2 -
VIN = 2.0V 3.0 7.7 -
N-ch VDS =0.5V VIN = 3.0V 5.0 10.1 -
VIN = 4.0V 6.0 11.5 -
VIN = 5.0V 7.0 13.0 -
CMOS Output
(P-ch)
N-ch Open
Drain Output
DR = VDF + VHYS
P-ch VDS=2.1V
(CMOS Output)
V
I
LEAK
V
ΔV
/
DF
(ΔTopr･V
)
DF
t
DR VIN changes from 0.6V to 10V
x 0.9V, V
IN=VDF
= 10.0V，V
IN
-30℃≦Topr≦80℃
VIN = 8.0V - -10.0 -2.0
=0V
OUT
=10.0V
OUT
-0.3~12.0 V
SS
VSS -0.3 ~ 9
300
-30〜+80 ℃
-40〜+125 ℃
V
DF(T)
x 0.98
V
DF
x 0.02
DF(T)
V
VDF
x 0.05
VDF(T)
x 1.02
x 0.08
- -0.01 -
- 0.01 0.1
- ±100 -
50 - 200
80 400
1 50
Ta = 2 5℃
V
mW
UNITS
VDF
μA ②
mA
μA ③
ppm/
ms ⑤
Ta = 2 5℃
CIRCUIT
V ①
V ①
③
④
℃
①
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OPERATIONAL EXPLANATION
●CMOS output
① When a voltage higher than the release voltage (V
fall. When a voltage higher than the detect voltage (V
VIN.
Note that high impedance exists at V
with the N-ch open drain output configuration. If the pin is pulled up, V
OUT
be equal to the pull up voltage.
② When V
falls below VDF, V
IN
will be equal to the ground voltage (VSS) level (detect state). Note that this also applies
OUT
to N-ch open drain output configurations.
③ When V
falls to a level below that of the minimum operating voltage (V
IN
the output pin is generally pulled up with configurations, output will be equal to pull up voltage.
④ When V
until V
⑤ Although V
⑥ Following transient delay time, V
rises above the VSS level (excepting levels lower than minimum operating voltage), V
IN
reaches the VDR level.
IN
N will rise to a level higher than VDR, V
I
will be output at V
IN
output configuration and that voltage will be dependent on pull up.
Notes:
1. The difference between V
2. Release delay time (t
level.
V
DR
and VDF represents the hysteresis range.
DR
) represents the time it takes for VIN to appear at V
DR
●Timing Chart
XC61F
) is applied to the voltage input pin (VIN), the voltage will gradually
DR
) is applied to VIN, output (V
DF
) output will become unstable. Because
MIN
maintains ground voltage level via the delay circuit.
OUT
. Note that high impedance exists with the N-ch open drain
OUT
once the said voltage has exceeded the
OUT
) will be equal to the input at
OUT
will be equal to VSS
OUT
OUT
Series
will
Release Delay Time (tDR)
(t
)
DLY
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