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XC61F Series
ETR0202_006
Voltage Detectors, Delay Circuit Built-In
GENERAL DESCRIPTION
The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies. A delay circuit is built-in to each detector.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-ch open drain output configurations are available.
Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible.
PPLICATIONS
●Microprocessor reset circuitry
●Memory battery back-up circuits
●Power-on reset circuits
●Power failure detection
●System battery life and charge voltage monitors
●Delay circuitry
TYPICAL APPLICATION CIRCUITS
FEATURES
Highly Accurate : ± 2%
Low Power Consumption
Detect Voltage Range
Operating Voltage Range
Detect Voltage Temperature Characteristics
:±100ppm/℃(TYP.)
Built-In Delay Circuit : ① 1ms ~ 50ms
② 50ms ~ 200ms
③ 80ms ~ 400ms
Output Configuration :
Operating Ambient Temperature :
Packages : SOT-23
SOT-89
TO-92
Environmentally Friendly
arts are available with an accuracy of ± 1%
* No
TYPICAL PERFORMANCE
CHARACTERISTICS
●Release Delay Time vs. Ambient Temperature
(ms)
DR
: 1.0μA(TYP.)[ VIN=2.0V ]
:
1.6V ~ 6.0V in 0.1V increments
: 0.7V ~ 10.0V
N-ch open drain output or CMOS
30℃〜+80℃
: EU RoHS Compliant, Pb Free
N-ch open drain output
Release Delay Time: t
Ambient Temperature:Ta(℃)
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XC61F Series
PIN CONFIGURATION
PIN ASSIGNMENT
PIN NUMBER
SOT-23 SOT-89 TO-92
3 2 2 VIN Supply Voltage Input
2 3 3 VSS Ground
1 1 1 V
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1
V
OUT
(TOP VIEW)
２
V
IN
SOT-89
3
V
SS
TO-92
(SIDE VIEW)
PIN NAME FUNCTION
Output
OUT
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PRODUCT CLASSIFICATION
●Ordering Information
XC61F ①②③④⑤⑥⑦‑⑧
(*1)
DESIGNATOR ITEM SYMBOL DESCRIPTION
①
Output Configuration
C CMOS output
N N-ch open drain output
②③
Detect Voltage 16 ~ 60
e.g. 2.5V → ②2 , ③5
e.g. 3.8V → ②3, ③8
1 50ms ~ 200ms
④
Release Output Delay
4 80ms ~ 400ms
5 1ms ~ 50ms
⑤
Detect Accuracy 2
Within ± 2.0%
MR SOT-23 (3,000/Reel)
MR-G SOT-23 (3,000/Reel)
PR SOT-89 (1,000/Reel)
⑥⑦-⑧
(*1)
Packages (Order Unit)
PR-G SOT-89 (1,000/Reel)
TH TO-92 Taping Type: Paper type (2,000/Tape)
TH-G TO-92 Taping Type: Paper type (2,000/Tape)
TB TO-92 Taping Type: Bag (500/Bag)
TB-G TO-92 Taping Type: Bag (500/Bag)
(*1)
The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
BLOCK DIAGRAMS
(1) CMOS output
(2) N-ch open drain output
XC61F
Series
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ABSOLU
GS
■
XC61F Series
Output Voltage
Power Dissipation
Operating Ambient Temperature Topr
ELECTRICAL CHARACTERISTICS
PAR AMETER
Detect Voltage VDF
Hysteresis Width VHYS
Supply Current ISS
Operating Voltage VIN VDF= 1.6V to 6.0V 0.7 - 10.0 V ①
Output Current IOUT
Leak
Current
Detect Voltage
Temperature
Characteristics
Release Delay Time
(V
DR → VOUT inversion)
VDF (T): Setting detect voltage value
Release Voltage: V
* Release Delay Time: 1ms to 50ms & 80ms to 400ms versions are also available.
Note: The power consumption during power-start to output being stable (release operation) is 2μA greater than it is after that period
(completion of release operation) because of delay circuit through current.
TE MAXIMUM RATIN
PAR AMETER SYMBOL RATINGS UNITS
Input Voltage VIN V
Output Current I
50 mA
OUT
CMOS VSS -0.3 ~ VIN + 0.3
V
N-ch open drain
OUT
output
SOT-23 250
SOT-89 500
Pd
TO-92
Storage Temperature Tstg
SYMBOL
CONDITIONS MIN. TYP. MAX.
VIN = 1.5V - 0.9 2.6
VIN = 2.0V - 1.0 3.0
VIN = 3.0V - 1.3 3.4
VIN = 4.0V - 1.6 3.8
V
IN = 5.0V - 2.0 4.2
VIN = 1.0V 1.0 2.2 -
VIN = 2.0V 3.0 7.7 -
N-ch VDS =0.5V VIN = 3.0V 5.0 10.1 -
VIN = 4.0V 6.0 11.5 -
VIN = 5.0V 7.0 13.0 -
CMOS Output
(P-ch)
N-ch Open
Drain Output
DR = VDF + VHYS
P-ch VDS=2.1V
(CMOS Output)
V
I
LEAK
V
ΔV
/
DF
(ΔTopr･V
)
DF
t
DR VIN changes from 0.6V to 10V
x 0.9V, V
IN=VDF
= 10.0V，V
IN
-30℃≦Topr≦80℃
VIN = 8.0V - -10.0 -2.0
=0V
OUT
=10.0V
OUT
-0.3~12.0 V
SS
VSS -0.3 ~ 9
300
-30〜+80 ℃
-40〜+125 ℃
V
DF(T)
x 0.98
V
DF
x 0.02
DF(T)
V
VDF
x 0.05
VDF(T)
x 1.02
x 0.08
- -0.01 -
- 0.01 0.1
- ±100 -
50 - 200
80 400
1 50
Ta = 2 5℃
V
mW
UNITS
VDF
μA ②
mA
μA ③
ppm/
ms ⑤
Ta = 2 5℃
CIRCUIT
V ①
V ①
③
④
℃
①
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OPERATIONAL EXPLANATION
●CMOS output
① When a voltage higher than the release voltage (V
fall. When a voltage higher than the detect voltage (V
VIN.
Note that high impedance exists at V
with the N-ch open drain output configuration. If the pin is pulled up, V
OUT
be equal to the pull up voltage.
② When V
falls below VDF, V
IN
will be equal to the ground voltage (VSS) level (detect state). Note that this also applies
OUT
to N-ch open drain output configurations.
③ When V
falls to a level below that of the minimum operating voltage (V
IN
the output pin is generally pulled up with configurations, output will be equal to pull up voltage.
④ When V
until V
⑤ Although V
⑥ Following transient delay time, V
rises above the VSS level (excepting levels lower than minimum operating voltage), V
IN
reaches the VDR level.
IN
N will rise to a level higher than VDR, V
I
will be output at V
IN
output configuration and that voltage will be dependent on pull up.
Notes:
1. The difference between V
2. Release delay time (t
level.
V
DR
and VDF represents the hysteresis range.
DR
) represents the time it takes for VIN to appear at V
DR
●Timing Chart
XC61F
) is applied to the voltage input pin (VIN), the voltage will gradually
DR
) is applied to VIN, output (V
DF
) output will become unstable. Because
MIN
maintains ground voltage level via the delay circuit.
OUT
. Note that high impedance exists with the N-ch open drain
OUT
once the said voltage has exceeded the
OUT
) will be equal to the input at
OUT
will be equal to VSS
OUT
OUT
Series
will
Release Delay Time (tDR)
(t
)
DLY
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XC61F Series
DIRECTIONS FOR USE
●Notes on Use
1. Please use this IC within the stated absolute maximum ratings. For temporary, transitional voltage drop or voltage rising
phenomenon, the IC is liable to malfunction should the ratings be exceeded.
2. When a resistor is connected between the VIN pin and the power supply with CMOS output configurations, oscillation
may occur as a result of voltage drops at RIN if load current (I
(refer to Oscillation Description (1) below)
3. When a resistor is connected between the V
N-ch output configurations, oscillation may occur as a result of through current at the time of voltage release even if load
current (I
4. If a resistor (R
occurrences of oscillation as described above. Further, please ensure that R
0.1μF, please test with the actual device. However, N-ch open drain output only. (Figure 1).
5. With a resistor (RIN) connected between the V
power supply voltage as a result of the IC's supply current flowing through the V
6. Depending on circuit's operation, release delay time of this IC can be widely changed due to upper limits or lower limits of
operational ambient temperature.
7. Torex places an importance on improving our products and its reliability.
However, by any possibility, we would request user fail-safe design and post-aging treatment on system or equipment.
●Oscillation Description
(1) Oscillation as a result of load current with the CMOS output configuration:
When the voltage applied at power supply, release operations commence and the detector's output voltage increases.
Load current (I
between the power supply and the V
to a fall in the voltage level at the VIN pin. When the VIN pin voltage level falls below the detect voltage level, detect
operations will commence. Following detect operations, load current flow will cease and since voltage drop at R
disappear, the voltage level at the VIN pin will rise and release operations will begin over again.
Oscillation may occur with this " release - detect - release " repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Oscillation as a result of through current:
Since the XC61F series are CMOS IC
(during release and detect operations). Consequently, oscillation is liable to occur during release voltage operations
as a result of output current which is influenced by this through current (Figure 3).
Since hysteresis exists during detect operations, oscillation is unlikely to occur.
) does not exist. (refer to Oscillation Description (2) below)
OUT
) must be used, then please use with as small a level of input impedance as possible in order to control the
IN
OUT) will flow through RL. Because a voltage drop (RIN x IOUT) is produced at the RIN resistor, located
IN pin, the load current will flow via the IC's VIN pin. The voltage drop will also lead
Power supply
pin and the power supply with CMOS output configurations, irrespective of
IN
pin and the power supply, the VIN pin voltage will be getting lower than the
IN
S, through current will flow when the IC's internal circuit switching operates
Figure 1. When using an input resistor
) exists. It is therefore recommend that no resistor be added.
OUT
Power supply
is less than 10kΩ and that C
IN
pin.
IN
is more than
IN
IN will
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■DIRECTIONS FOR USE (Continued)
●Oscillation Description (Continued)
Power supply
XC61F
Series
Power supply
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●
①
●
② ●
●
④ ●
XC61F Series
TEST CIRCUITS
測定回路１ 測定回路２
Circuit
*
220KΩ
Circuit
測定回路３ 測定回路４
Circuit ③
測定回路５
Circuit ⑤
220KΩ
Circuit
* CMOS出力品の場合は不要です。
*Not necessary with CMOS output products.
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TYPICAL PERFORMANCE CHARACTERISTICS
XC61F
Series
(4) N-ch Driver Output Current vs. VDS
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(7)
XC61F Series
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(4) N-ch Driver Output Current vs. V
(5) N-ch Driver Output Current vs. Input Voltage
(6) P-ch Driver Output Current vs. Input Voltage
Release Delay Time vs. Ambient Temperature
(ms)
DR
Release Delay Time: t
10/14
(Continues)
DS
(ms)
Release Delay Time: t
(ms)
DR
DR
Release Delay Time: t
■
(8)
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Release Delay Time vs. Input Voltage
(ms)
DR
Release Delay Time: t
XC61F
Series
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XC61F Series
PACKAGING INFORMATION
●SOT-23
●SOT-89
●TO-92 TH Type
●TO-92 TB Type
+0.4
4.8
-0.5
13.5±0.5
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●
T
MARKING RULE
SOT-23, SO
-89
3
① ② ③ ④
12
②①
123
●TO-92
F
6 1
123
（SIDE VIEW）
④③② ⑤
⑥ ⑦
TO-92
XC61F
Series
① represents integer of detect voltage and output configuration
CMOS output (XC61FC series)
MARK CONFIGURATION VOLTAGE (V)
A CMOS 0.x
B CMOS 1.x
C CMOS 2.x
D CMOS 3.x
E CMOS 4.x
F CMOS 5.x
H CMOS 6.x
N-ch open drain output (XC61FN series)
MARK CONFIGURATION VOLTAGE (V)
④③
K N-ch 0.x
L N-ch 1.x
M N-ch 2.x
N N-ch 3.x
P N-ch 4.x
R N-ch 5.x
S N-ch 6.x
② represents decimal number of detect voltage
MARK VOLTAGE (V) MARK VOLTAGE (V)
0 x.0 5 x.5
1 x.1 6 x.6
2 x.2 7 x.7
3 x.3 8 x.8
4 x.4 9 x.9
③ represents delay time
VOLTAGE (V) DELAY TIME
5 50 ~ 200ms
6 80 ~ 400ms
7 1 ~ 50ms
④ represents assembly lot number (Based on internal standards)
① represents output configuration
MARK OUTPUT CONFIGURATION
①
C CMOS
N N-ch
②, ③ represents detect voltage
MARK
② ③
VOLTAGE (V)
3 3 3.3
5 0 5.0
④ represents delay time
MARK DELAY TIME
1 50ms ~ 200ms
4 80ms ~ 400ms
5 1ms ~ 50ms
⑤ represents detect voltage accuracy
MARK DETECT VOLTAGE ACCURACY
2 Within +2%
⑥ represents a least significant digit of the production year (ex.)
MARK PRODUCTION YEAR
3 2003
4 2004
⑦ represents production lot number
0 to 9, A to Z repeated (G, I, J, O, Q, W excluded)
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XC61F Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics. Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this datasheet.
4. The products in this datasheet are not developed, designed, or approved for use with
such equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this datasheet within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this datasheet may be copied or reproduced without the
prior permission of TOREX SEMICONDUCTOR LTD.
14/14
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