TOREX XC6127 User Manual

XC6127 Series
Ultra Small Voltage Detector with High Precision Delay Circuit and Manual Reset Function
GENERAL DESCRIPTION
XC6127 series is ultra small highly accurate voltage detector with delay circuit built-in.
The device includes a highly accurate reference voltage source, manufactured using CMOS process technology and laser
operation temperature range.
The release delay time periods are internally set in a range from 50ms to 800ms. Moreover, with the manual reset function, reset can be asserted at any time. The device is available in both CMOS and N-channel open drain output configurations. Also detect logic is available in both RESETB (Active Low) and RESET (Active High).
Ultra small package USPN-4 is ideally suited for small design of portable devices and high densely mounting applications.
The conventional packages SSOT-24,SOT-25 is also available for upper compatible replacements.
■APPLICATIONS
Microprocessor logic reset circuitry
System battery life and charge voltage monitors
Memory battery back-up circuits
Power-on reset circuits
Power failure Detection
Delay circuit
TYPICAL APPLICATION CIRCUIT
V
IN
RESET
SW
XC6127 series
RESETB
V
IN
RESET
MRB
V
SS
VCC
μP
RESETB/RESET
INPUT
VSS
V
IN
RESET
SW
CMOS output
XC6127 series
RESETB
V
IN
RESET
MRB
V
SS
Vpull-Up
Rpull
RESETB/RESET
INPUT
VCC
μP
VSS
FEATURES
High Accuracy Temperature Characteristics Low Power Consumption
Operating Voltage Range Detect Voltage Range Manual Reset Input Output Configuration Output Logic
Release Delay Time Operating Ambient Temperature Packages Environmentally Friendly
: ±0.8% (25℃) : ±50ppm/℃
0.6μA TYP. (Detect: VDF=1.8V, VIN=1.62V)
:
0.7μA TYP. (R e lea se: VDF=1.8V, VIN=1.98V)
: 0.7V6.0V : 1.5V5.5V (0.1V increments)
MRB Pin (Built-in Pull-up resistance)
:
N-channel open drain or CMOS
:
RESETB (Active Low)
:
RESET (Active High)
50ms/100ms/200ms/400ms/800ms±15%
: : : -40℃ ~ +85℃
USPN-4, SSOT-24, SOT-25
EU RoHS Compliant, Pb Free
:
TYPICAL PERFORMANCE
CHARACTERISTICS
XC6127x27Bx
VIN=V
×0.9→V
DFL
(ms)
DR
115
110
105
100
95
90
Release Delay Time: t
85
-50 -25 0 25 50 75 100 Ambient Temperature: Ta (℃)
×1.1 , MRB=O PEN
DFL
ETR0217-006
N-ch open drain output
1/24
XC6127 Series
PIN CONFIGURATION
V
V
IN
V
SS
RESETB
14
RESET
MRB
23
RESETB RESET
MRB
34
1
V
IN
2
V
SS
USPN-4
(BOTTOM VIEW)
SSOT-24
(TOP VIEW)
PIN ASSIGNMENT
PIN NUMBER
USPN-4 SSOT-24 SOT-25
PIN NAME FUNCTIONS
1 4 4 RESETB Signal Output (Active Low) 1 4 4 RESET Signal Output (Active High) 2 3 1 MRB Manual Reset Input 3 2 2 VSS Ground 4 1 5 VIN Power Input
(*1) Type A~E (Refer to the ④ in Ordering Information table) (*2) Type F~K (Refer to the ④ in Ordering Information table)
FUNCTION CHART
PIN NAME SIGNAL STATUS
L Forced Reset
MRB
H Normal Operation
OPEN Normal Operation
IN
5 4
1
MRB NC
2
V
SS
SOT-25
(TOP VIEW)
RESETB RESET
(*1)
(*2)
3
2/24
PRODUCT CLASSIFICATION
Ordering Information
XC6127①②③④⑤⑥-⑦
(*1)
DESIGNATOR ITEM SYMBOL DESCRIPTION
②③
Output Configuration
Detect Voltage
C CMOS output N N-ch open drain output
1555 e.g. 2.7V =2, =7
A Reset Active Low, Release Delay Time: 50ms B Reset Active Low, Release Delay Time: 100ms C Reset Active Low, Release Delay Time: 200ms D Reset Active Low, Release Delay Time: 400ms
Type
E Reset Active Low, Release Delay Time: 800ms F Reset Active High, Release Delay Time: 50ms G Reset Active High, Release Delay Time: 100ms H Reset Active High, Release Delay Time: 200ms
J Reset Active High, Release Delay Time: 400ms
K Reset Active High, Release Delay Time: 800ms
7R-G USPN-4 (5,000/Reel)
MR-G SOT-25 (3,000/Reel)
⑤⑥-
(*1)
Packages (Order Unit)
NR-G SSOT-24 (3,000/Reel)
(*1)
The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant.
XC6127
Series
3/24
XC6127 Series
BLOCK DIAGRAMS
1) XC6127 Series, Type CxxA/CxxB/CxxC/CxxD/CxxE (CMOS Output, Output Logic: Active Low)
2) XC6127 Series, Type NxxA/NxxB/NxxC/NxxD/NxxE (N-ch Open Drain Output, Output Logic: Active Low)
4/24
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
BLOCK DIAGRAMS (Continued)
3) XC6127 Series, Type CxxF/CxxG/CxxH/CxxJ/CxxK (CMOS Output, Output Logic: Active High)
4) XC6127 Series, Type NxxF/NxxG/NxxH/NxxJ/NxxK (N-ch Open Drain Output, Output Logic: Active High)
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
XC6127
Series
5/24
XC6127 Series
■ABSOLUTE MAXIMUM RATINGS
PAR AMETER SYMBOL RATINGS UNITS
Input Voltage VIN
MRB Input Voltage V
Output Current
MRB
(*1)
VSS-0.3~VSS+6.5
VSS~VSS+6.5
20 mA
Ta =2 5
V
V
(*2)
(*3)
Output Voltage
XC6127C
XC6127N
USPN-4 100
Power Dissipation
SOT-25 250
SSOT-24
Operating Ambient Temperature Topr
Storage Temperature Tst g
Note:
(*1) SYMBOL is different for each product. I
I
(*2) CMOS Output
(*3) N-ch Open Drain Output (*4) SYMBOL is different for each product.
V V
: Type XC6127CxxA/CxxB/CxxC/CxxD/CxxE, Type XC6127NxxA/NxxB/NxxC/NxxD/NxxE
RBOUT
: Type XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, Type XC6127NxxF/NxxG/NxxH/NxxJ/NxxK
ROUT
: Type XC6127CxxA/CxxB/CxxC/CxxD/CxxE, Type XC6127NxxA/NxxB/NxxC/NxxD/NxxE
RESETB
: Type XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, Type XC6127NxxF/NxxG/NxxH/NxxJ/NxxK
RESET
(*4)
Pd
VSS-0.3~VIN+0.3≦VSS+6.5
V
VSS-0.3~VSS+6.5
mW
150
-40+85
-55+125
6/24
ELECTRICAL CHARACTERISTICS
XC6127CxxA/CxxB/CxxC/CxxD/CxxE, XC6127NxxA/NxxB/NxxC/NxxD/NxxE (Output Logic: Active Low)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CIRCUIT
Operating Voltage VIN
Detect Voltage V
Hysteresis Width V
DFL
HYS
(*1)
V
=1.5~5.5V, MRB=OPEN
DF(T)
V
=1.55.5V, MRB=OPEN
DF(T)
(*2)
0.7
V
×0.992 V
DF(T)
V
×0.02 V
DFL
(*3)
DF(T)
(*4)
E-1
×0.05 V
DFL
6.0 V -
V
DF(T)
×1.008
×0.08
DFL
V
V
XC6127
Series
Ta =2 5
Supply Current 1 I
Supply Current 2 I
RESETB
Output Current
RESETB Leakage
Current
CMOS
Output(Pch)
Nch Open
Drain Output
Temperature Characteristics
Detect Delay Time
(*11)
SS1
SS2
I
RBOUT1
I
RBOUT2
I
LEAK
ΔV
DFL
(ΔTopr・V
tDF
(*10)
/
DFL
)
VIN=V
VIN=V
VIN=0.7V, V
VIN=1.0V, V
(*6)
VIN=2.0V
(*7)
VIN=3.0V
(*8)
VIN=4.0V
(*9)
VIN=5.0V
VIN=6.0V, V
VIN=V
×0.9, V
DFL
VIN=6.0V, V
VIN=V
DFL
×0.9 , MRB=OPEN
DFL
V
=1.51.8V - 0.6 1.4
DF(T)
V
=1.93.0V - 0.7 1.6
DF(T)
V
=3.15.5V - 1.0 1.9
DF(T)
(*5)
×1.1
DFL
V
V
V
RESETB
RESETB
, V
, V
, V
, V
RESETB
, MRB=OPEN
=1.51.8V - 0.7 1.6
DF(T)
=1.93.0V - 0.8 1.9
DF(T)
=3.15.5V - 1.1 2.35
DF(T)
=0.5V(Nch) , MRB=OPEN
=0.5V(Nch) , MRB=OPEN
=0.5V(Nch) , MRB=OPEN
RESETB
=0.5V(Nch) , MRB=OPEN
RESETB
=0.5V(Nch) , MRB=OPEN
RESETB
=0.5V(Nch) , MRB=OPEN
RESETB
=5.5V(Pch) , MRB=OPEN
=0V , MRB=OPEN
RESETB
0.014 0.2 -
0.5 1.6 -
4.4 7.0 -
7.0 9.0 -
8.5 11.0 -
9.0 12.0 -
- -4.5 -3.0 mA
- -0.01 - μA
μA
μA
mA
=6.0V , MRB=OPEN
RESETB
- 0.01 0.15 μA
-40℃≦Topr85 - ±50 - ppm/
DFL
×0.9
(*11)
, MRB=OPEN
- - 100 μs ④
×1.1→V
Release Delay Time
MRB “Low” Level Voltage
MRB “High” Level Voltage
MRB pull-up Resistance R
Minimum MRB Pulse Width
(*12)
(*14)
(*14)
tDR
V
V
MRL
V
V
MRH
0.4 0.8 3.0 M
MRB
T
MRB
VIN=V
×0.9→V
DFL
×1.1
DFL
×1.1≦VIN≦6.0V VSS - 0.3 V
DFL
×1.1≦VIN≦6.0V 1.0 - 6.0 V
DFL
V
=6.0V,
IN
Applied pulse to MRB pin,
Note: (*1) V (*2) For the N-ch Open Drain, Rpull=100k, Vpull-Up=V
Rpull: An External Pull-up resistor
Vpull-Up: Pull-up Voltage (*3) V (*4) For the detail value, please refer to “Voltage Table” in P10. (*5) V (*6) For V (*7) For V (*8) For V (*9) For V (*10) For the XC6127C (CMOS output) (*11) A time between V (*12) A time between V
: Nominal detect voltage
DF(T)
voltage for V
IN
= 5.5V where VIN=6.0V
DF(T)
2.0V products.
DF(T)
3.0V products.
DF(T)
4.0V products.
DF(T)
5.0V products.
DF(T)
0.3V is under detect state.
OUT
IN=VDFL
IN=VDFL+VHYS
and V
RESETB=VDFL
and V
RESETB=VDFL
IN
×0.45 when VIN falls.
×0.55 when VIN rises. (*13) For the detail value, please refer to “Release Delay Time” in P11. (*14) For MRB pin, please do not apply the voltage below V
.
SS
(*12)
, MRB=OPEN
(*13)
E-2
ms
150 - - ns
7/24
XC6127 Series
ELECTRICAL CHARACTERISTICS (Continued)
XC6127CxxF/CxxG/CxxH/CxxJ/CxxK, XC6127NxxF/NxxG/NxxH/NxxJ/NxxK (Output Logic: Active High)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CIRCUIT
Operating Voltage VIN
Detect Voltage V
DFH
(*1)
V
=1.5~5.5V, MRB=OPEN
DF(T)
V
=1.5~5.5V, MRB=OPEN
DF(T)
(*2)
(*3)
0.7
6.0 V -
V
×0.992
DF(T)
V
E-1
DF(T)
(*4)
Ta =2 5
V
×1.008
DF(T)
V
Hysteresis Width V
Supply Current 1 I
Supply Current 2 I
RESET
Output Current
RESET
Leakage
Current
CMOS
Output (P-ch)
N-ch Open
Drain Output
Temperature
Characteristics
Detect Delay Time
(*16)
t
HYS
SS1
SS2
VIN=1.65V
VIN=2.0V
VIN=3.0V
I
ROUT1
VIN=4.0V
VIN=5.0V
VIN=6.0V, V
VIN=0.7V, V
VIN=1.0V, V
I
ROUT2
(*11)
VIN=2.0V
VIN=3.0V
VIN=4.0V
VIN=5.0V
V
I
LEAK
VIN=V
ΔV
/
DFH
(ΔTopr・V
)
DFH
DF
V
VIN=V
VIN=V
(*7)
(*8)
(*9)
(*10)
(*12)
(*13)
(*14),
(*15)
=6.0V, V
IN
×0.9, V
DFH
×0.02 V
DFH
×0.9 , MRB=OPEN
DFH
V
=1.51.8V - 0.6 1.4
DF(T)
V
=1.93.0V - 0.7 1.6
DF(T)
V
=3.15.5V - 1.0 1.9
DF(T)
(*5)
×1.1
DFH
V
V
V
(*6)
, V
, V
, V
, V
, V
, V
, V
, V
, MRB=OPEN
=1.51.8V - 0.7 1.6
DF(T)
=1.93.0V - 0.8 1.9
DF(T)
=3.15.5V - 1.1 2.35
DF(T)
=0.5V(Nch) , MRB=OPEN
RESET
=0.5V(Nch) , MRB=OPEN
RESET
=0.5V(Nch) , MRB=OPEN
RESET
=0.5V(Nch) , MRB=OPEN
RESET
=0.5V(Nch) , MRB=OPEN
RESET
=0.5V(Nch) , MRB=OPEN
RESET
=0.2V(Pch) , MRB=OPEN
RESET
=0.5V(Pch) , MRB=OPEN
RESET
=1.5V(Pch) , MRB=OPEN
RESET
=2.5V(Pch) , MRB=OPEN
RESET
V
=3.5V(Pch) , MRB=OPEN
RESET
=4.5V(Pch) , MRB=OPEN
RESET
=0V, MRB=OPEN - -0.01 - μA
RESET
=6.0V, MRB=OPEN
RESET
0.5 1.6 -
4.4 7.0 -
7.0 9.0 -
8.5 11.0 -
9.0 12.0 -
9.0 12.0 -
- -0.07 -0.001
- -0.4 -0.09
- -2.0 -1.3
- -3.0 -1.8
- -4.0 -2.5
- -4.5 -3.0
- 0.01 0.15 μA
×0.05 V
DFH
DFH
×0.08
-40℃≦Topr85 - ±50 - ppm/
VIN=V
×1.1→V
DFH
DFH
×0.9
(*16)
, MRB=OPEN
- - E-3
(*17)
μs
V
μA
μA
mA
mA
Release Delay Time
MRB “Low” Level Voltage
MRB “High” Level Voltage
MRB pull-up Resistance
Minimum MRB Pulse Width
8/24
(*18)
t
(*20)
(*20)
DR
V
MRL
V
MRH
R
MRB
T
MRB
VIN=V
V
V
DFH
×1.1
(*18)
, MRB=OPEN
×0.9→V
DFH
×1.1≦VIN≦6.0V VSS - 0.3 V
DFH
×1.1≦VIN≦6.0V 1.0 - 6.0 V
DFH
(*19)
E-2
ms
0.4 0.8 3.0 M
VIN=6.0V, Applied pulse to MRB pin, 6.0V→0V
150 - - ns
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