r
A
XC6119 Series
ETR02016-003
Voltage Detector with Delay Time Adjustable
■GENERAL DESCRIPTIO N
The XC6119 series is a highly precise, low power consumption voltage detector, manufactured using CMOS and laser trimming
technologies.
The device includes the built-in delay circuit. A release delay time can be set freely by connecting an external delay capacitor to
the Cd pin.
The device using an ultra small package (USPN-4) is suited for high density mounting applications.
Both CMOS and N-channel open drain output configurations are available.
■
PPLICATIONS
●Microprocessor reset circuitry
●Charge voltage monitors
●Memory battery back-up switch circuits
●Power failure detection circuits
■TYPICAL APPLICATION CIRCUIT
(No Pull-Up resistor needed
for CMOS output product)
■FEATURES
High Accuracy : +2%
(Detection Voltage >1.5V)
+30mV
(Detection Voltage <1.5V)
Low Power Consumption : 0.5μA
0.9μA
TYP.
in detect state
(VDF=1.0V, VIN= 0.9V)
TYP.
in release state
(VDF=1.0V, VIN= 1.1V)
Detect Voltage Options : 0.8V ~ 5.0V (0.1V increments)
Operating Voltage Range : 0.7V ~ 6.0V
Detect Voltage Temperature Characteristics
: ±100ppm/
O
C TYP.
Output Configuration : CMOS or
N-channel open drain
Built-In Delay Circuit : Delay Time Adjustable
Operating Ambient Tempera ture
: -40
O
C ~ +85
Packages : SSOT-24,
O
C
USPN-4
Environmentally Friendly : EU RoHS Compliant, Pb Free
■TYPICAL PERFORMANCE
CHARACTERISTICS
●Release Delay Time vs. Delay Capacitance
XC6119xxxAx
VIN(min)=0.7V VIN(max)=6.0V
=5μs Ta=25
10000
t
(ms)
1000
DR
100
10
1
0.1
Release Delay Tim e: t
0.0001 0.001 0.01 0.1 1
℃
Delay Capacitance: Cd (μF)
1/16
XC6119 Series
■PIN CONFIGURATION
■PIN ASSIGNMENT
■PRODUCT CLASSIFICATION
●Ordering Information
XC6119①②③④⑤⑥-⑦
(*1)
The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant.
USPN-4
(BOTTOM VIEW)
PIN NUMBER
PIN NAME FUNCTION
USPN-4 SSOT-24
1 4 VOUT Output (Detect ”L”)
2 3 Cd Delay Capacitance
3 2 VSS Ground
4 1 VIN Input
(*1)
DESIGNATOR ITEM SYMBOL DESCRIPTION
①
②③
④
⑤⑥-⑦
Output Configuration
Detect Voltage
Output Delay &
Hysteresis
Packages
(Order Unit)
SSOT-24
（TOP VIEW）
C CMOS output
N N-ch open drain output
08 ~ 50 e.g. 18→1.8V
A Built-in delay pin & hysteresis 5% (TYP.)
7R-G
USPN-4 (5,000/Reel)
NR-G SSOT-24 (3,000/Reel)
2/16
A
■BLOCK DIAGRAMS
(1) XC6119C (CMOS Output)
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
■
BSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATINGS UNITS
Input Voltage VIN
Output
Voltage
Output Current I
XC6119C (*1)
XC6119N (*2)
V
OUT
OUT
Delay Pin Voltage VCD
Delay Pin Current ICD 5.0 mA
Power
Dissipation
USPN-4 * 100
SSOT-24
Pd
Operating Ambient Temperature T a
Storage Temperature Tstg
NOTE:
*1: CMOS output
*2: N-ch open drain output
XC6119
Series
(2) XC6119N (N-ch Open Drain Output)
Ta=25℃
-0.3～+7.0
V
SS
10 mA
-0.3～VIN+0.3
V
SS
VSS-0.3～+7.0
-0.3～VIN+0.3
V
SS
150
-40～+85
-55～+125
V
V
V
mW
o
C
o
C
3/16
XC6119 Series
■ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT CIRCUIT
OUT
(*1)
0.7 6.0 V -
V
×0.02
0.01
0.1
0.8
1.2
1.6
DF
VDF
×0.05
0.5
0.6
0.7
0.9
1.1
1.2
0.36
0.7
1.6
2.0
2.3
VDF
×0.08
1.2
1.3
1.4
1.8
2.0
2.2
mA ③
E-2 mA ④
= 0V,
OUT
= 6.0V,
-0.20
0.20 0.40
30 230 μs ⑧
30 200 μs ⑧
Operating Voltage VIN V
Detect Voltage VDF V
Hysteresis Width V
V
HYS
=0.8～5.0V
DF(T)
=0.8～5.0V E-1 V ①
DF(T)
=1.0～6.0V
IN
VIN=VDF×0.9
V
=0.8～1.9V
Supply Current 1 I
SS1
V
V
DF(T)
DF(T)
DF(T)
=2.0～3.9V
=4.0～5.0V
VIN=VDF×1.1
V
=0.8～1.9V
Supply Current 2 I
SS2
V
V
DF(T)
DF(T)
DF(T)
=2.0～3.9V
=4.0～5.0V
VIN=0.7V
V
=0.5V(Nch)
DS
VIN=1.0V(※2)
V
=0.5V(Nch)
DS
VIN=2.0V(※3)
V
=0.5V(Nch)
DS
VIN=3.0V(※4)
V
=0.5V(Nch)
DS
=4.0V(※5)
V
IN
V
=0.5V(Nch)
DS
=VDF×1.1
V
IN
V
=0.5V(Pch)
DS
VIN = V
×
0.9V, V
DF
Cd: Open
VIN = 6.0V, V
Cd: Open
o
C≦Ta≦85 oC ±100
-40
Output Current
CMOS output
N-ch Open
(P-ch)
Leakage
Current
Drain Output
Temperature
Characteristics
Delay Resistance
(ΔTa・
(*7)
R
I
OUT1
I
OUT2
(*6)
I
LEAK
ΔV
/
DF
V
)
DF
VIN=6.0V, Cd=0V 1.6 2.0 2.4 MΩ ⑤
DELAY
Delay Pin Sink Current ICD Cd=0.5V, VIN=0.7V 8 60 μA ⑤
Delay Capacitance Pin
Threshold Voltage
Unspecified Operating
Voltage
Detect Delay Time
Detect Delay Time
NOTE:
*1: V
DF(T): Setting Detect Voltage
*2: V
DF(T)＞1.0V
DF(T)＞2.0V
*3: V
*4: V
DF(T)＞3.0V
*5: V
DF(T)＞4.0V
*6: This numerical value is applied only to the XC6119C series (CMOS output).
*7: Calculated from the voltage value and the current value of both ends of the resistor.
*8: The maximum voltage of the V
(CMOS output).
*9: Time which ranges from the state of V
*10: Time which ranges from the state of V
pin.
(*8)
(*9)
t
(*9)
t
V
TCD
V
V
UNS
DF0
DR0
OUT in the range of the VIN 0 to 0.7V. This numerical value is applied only to the XC6119C series
VIN=1.0V 0.4 0.5 0.6
=6.0V 2.9 3.0 3.1
V
IN
=0～0.7V 0.3 0.4 V ⑦
IN
V
=6.0→0.7V
IN
Cd: Open
V
=0.7V→6.0V
IN
Cd: Open
IN =VDF to the VOUT reaching 0.6V when the VIN falls without connecting to the Cd pin.
IN= VDF +VHYS to the VOUT reaching 5.4V when the VIN rises without connecting to the Cd
Ta=25℃
V ①
μA ②
μA ②
μA
o
ppm/
C
V ⑥
③
①
4/16
■VOLTAGE CHART
SYMBOL E-1 E-2
PARAMETER
SETTING
DETECT
DETECT VOLTAGE
(V)
(*1)
OUTPUT CURRENT
(mA)
VOLTAGE
V
DF(T)
MIN. TYP. MAX. MIN. TYP.
VDF I
OUT2
0.8 0.770 0.8 0.830
0.9 0.870 0.9 0.930
-0.40 -0.20
1.0 0.970 1.0 1.030
1.1 1.070 1.1 1.130
1.2 1.170 1.2 1.230
1.3 1.270 1.3 1.330
-0.60 -0.30
1.4 1.370 1.4 1.430
1.5 1.470 1.5 1.530
1.6 1.568 1.6 1.632
1.7 1.666 1.7 1.734
-0.80 -0.40
1.8 1.764 1.8 1.836
1.9 1.862 1.9 1.938
2.0 1.960 2.0 2.040
2.1 2.058 2.1 2.142
2.2 2.156 2.2 2.244
2.3 2.254 2.3 2.346
2.4 2.352 2.4 2.448
2.5 2.450 2.5 2.550
-1.00 -0.50
2.6 2.548 2.6 2.652
2.7 2.646 2.7 2.754
2.8 2.744 2.8 2.856
2.9 2.842 2.9 2.958
3.0 2.940 3.0 3.060
3.1 3.038 3.1 3.162
3.2 3.136 3.2 3.264
3.3 3.234 3.3 3.366
3.4 3.332 3.4 3.468
3.5 3.430 3.5 3.570
-1.20 -0.60
3.6 3.528 3.6 3.672
3.7 3.626 3.7 3.774
3.8 3.724 3.8 3.876
3.9 3.822 3.9 3.978
4.0 3.920 4.0 4.080
4.1 4.018 4.1 4.182
4.2 4.116 4.2 4.284
4.3 4.214 4.3 4.386
4.4 4.321 4.4 4.488
4.5 4.410 4.5 4.590
-1.30 -0.65
4.6 4.508 4.6 4.692
4.7 4.606 4.7 4.794
4.8 4.704 4.8 4.896
4.9 4.802 4.9 4.998
5.0 4.900 5.0 5.100
NOTE:
*1: When V
*2: This numerical value is applied only to the XC6119C series (CMOS output).
DF(T)≦1.4V, the detection accuracy is ±30mV. When VDF(T)≧1.5V, the detection accuracy is ±2%.
(*2)
XC6119
Series
5/16
XC6119 Series
■TEST CIRCUITS
Circuit 1
Circuit 3
Circuit 5
Circuit 7
A
Cd
VIN
XC6119 Series
Cd
VSS
VIN
XC6119 Series
VSS
VOUT
R
=100kΩ
PULL
(No resistor needed for
CMOS output products)
VOUT
V
Circuit 2
Circuit 4
Circuit 6
Circuit 8
R
=100kΩ
PULL
(No resistor needed for
CMOS output
R
=100kΩ
PULL
(No resistor needed for
CMOS output products)
Waveform Measurement Point
6/16
■OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.
The circuit which uses the delay
Capacitance pin as power input.
N-ch transictor for the delay
Capacitance discharge.
Delay Capacitor
Figure 1: Typical application circuit example
Input Voltage: V
IN
Release Voltage: V
Detect Voltage: VDF
DF+VHYS
Minimum Operationg Voltage (0.7V)
XC6119
Series
Delay Capacitance Pin Voltage: V
Delay Capacitance Pin Threshold Voltage: V
Output Pin Voltage: V
OUT
Figure 2: The timing chart of Figure 1
① As an early state, the input voltage pin is a pplied sufficiently high voltage to the releas e voltage and the delay capacitance
(Cd) is charged to the input pin voltage. W hile the input pin voltage (V
> VDF), the output voltage (V
(V
IN
) keeps the “High” level (=VIN).
OUT
) starts dropping to reach the detect voltage (VDF)
IN
② When the input pin voltage keeps dropping and becomes equal to the detect voltage (V
= VDF), an N-ch transistor for the
IN
delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit, which
uses the delay capacitance pin as power input, the reference voltage operates as a comparator of VIN, and the output
voltage changes into the “Low” level (≦V
to the V
of “Low” level (especially, when the Cd pin is not connected: t
OUT
×0.1). The detect delay time (tDF) is defined as time which ranges from VIN =VDF
IN
DF0
).
③ While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the
ground voltage (=V
) level. Then, the output voltage (V
SS
) maintains the “Low” level.
OUT
④ While the input pin voltage drops to less than 0.7V and it increases again to 0.7V or more, the output voltage may not be able
to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the output pin
voltage is defined as unstable operating voltage (V
UNS
).
7/16
CD
TCD
)
XC6119 Series
■OPERATIONAL EXPLANATION (Continued
⑤ While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (VIN＜VDF +V
output voltage (V
) maintains the “Low” level.
OUT
⑥ When the in put pin voltage continues to increase more than 0.7V up to the release voltage level (= VDF + V
transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging via a
delay resistor (
hysteresis comparator (Rise Logic Threshold: V
higher than the detect voltage (V
R
). The internal circuit, which uses the delay capacitance pin as power input, will operate as a
DELAY
> VDF).
IN
TLH=VTCD
, Fall Logic Threshold: V
THL=VSS
) while the input pin voltage keeps
⑦ While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the delay
capacitance (Cd) will be charged up to the input pin voltage. When the delay capacitance pin voltage (V
delay capacitance pin threshold voltage (V
time which ranges from V
IN =VDF+VHYS
to the V
), the output voltage changes into the “High” (=VIN) level. tDR is defined as
TCD
of “High” level (especially when the Cd pin is not connected: t
OUT
can be given by the formula (1).
t
= －R
DR
DELAY
×Cd×
In (1－VTCD / VIN) +t
DR0
…(1)
* In = a natural logarithm
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and the
delay capacitance pin threshold voltage is VIN /2 (TYP.)
* R
is 2.0MΩ(TYP.)
DELAY
t
DR=RDELAY
×Cd×
0.69 …(2)
As an example, presuming that the delay capacitance is 0.68μF, tDR is :
2.0
×
10
6
×
0.68×10
-6
×
0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground (=VSS)
level because time described in ③ is short.
⑧ While the input pin voltage is higher than the detect voltage (V
“High”(=V
) level.
IN
> VDF), therefore, the output voltage maintains the
IN
), the
HYS
), the N-ch
HYS
) reaches to the
CD
). tDR
DR0
●Release Delay Time Chart
Delay Capacitance [Cd]
(μF)
0.01 13.8 11.0 ~ 16.6
0.022 30.4 24.3 ~ 36.4
0.047 64.9 51.9 ~ 77.8
0.1 138 110 ~ 166
0.22 304 243 ~ 364
0.47 649 519 ~ 778
1 1380 1100 ~ 1660
* The release delay time values above are calculate by using formula (2).
*1: The release delay time (t
Release Delay Time [tDR] (TYP.)
(ms)
) is influenced by the release capacitance (Cd).
DR
Release Delay Time [tDR] (MIN. ~ MAX.) *1
(ms)
8/16
XC6119
Series
■NOTES ON USE
1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising
phenomenon, the IC is liable to malfunction should the ratings be exceeded.
2. The input pin voltage drops by the resistance between power supply and the V
the IC. At this time, the operation may be wrong if the input pin voltage falls below the minimum operati ng voltage range.
In CMOS output, for output current, drops in the input pin voltage similarly occur. Oscillation of the circuit may occur if the
drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis voltage. Note it especially
when you use the IC with the V
3. Note that a rapid and high fluctuation of the input pin voltage may cause a wrong operation.
4. Power supply noise may cause an operational function error. Care must be taken to put an external capacitor between
-GND and test on the board carefully.
V
IN
5. When there is a possibility of which the input pin voltage fall s rapidly (e.g.: 6.0V to 0V) at release operation with the delay
capacitance pin (Cd) connected to a capacitor, use a schottky barrier diode connected between the V
as the Figure 3 shown below.
6. When N-channel o pen drain output is used, output voltages V
pull-up resistor tied to the output pin. A resistance value of the pull-up resistor can be selected with referring to the
followings. (Refer to Figure 4)
During detection, the formula is given as
where V
characteristics table).
For example, when V
V
=3.0V, R
PULL
R
Therefore, pull-up resistance should be selected 18kΩ or higher.
During release, the formula is given as
V
For examples, if you want to get V
R
Therefore, pull-up resistance should be selected 25kΩ or below.
7. Torex places an importance on improving our products and their reliability. We request that users incorporate fail-safe
where V
electrical characteristics table)
designs and post-aging protection treatment when using Torex products in their s ystems.
V
OUT=VPULL
is pull-up voltage and RON (*1) is ON resistance of N-channel driver M5 (RON=VDS/I
PULL
IN
can be calculated as follows;
PULL
=(V
PULL
PULL
(*1) VIN is smaller, RON is bigger
(*2) For the calculation, the lowest V
is pull-up voltage R
PULL
IN pin connected to a resistor.
/(1+R
PULL/RON
=2.0V (*2), R
/V
-1)×RON=(3/0.1-1)×625≒18ｋΩ
OUT
OUT=VPULL
OUT
=(V
PULL
)
= 0.5/0.8×10-3=625Ω(MIN.) and if you want to get V
ON
IN
/(1+R
PULL/ROFF
is OFF resistance of N-channel driver M5 (R
OFF
larger than 5.99V when V
PULL/VOUT
-1)×R
at voltage detection and release are determined by a
OUT
should be used among of the VIN range
)
is 6.0V, R
PULL
=(6/5.99-1)×15×106≒25kΩ
OFF
(No resistor needed for
CMOS output products)
Figure 3: Circuit example with the delay capacitance pin (Cd)
connected to a schottky barrier diode
IN pin, and by through current at operation of
IN pin and the Cd pin
from the electrical
OUT1
less than 0.1V when
OUT
OFF=VOUT/ILEAK
can be calculated as follows;
PULL
Note: R
OFF=VOUT/ILEAK
=15MΩ from the
Figure 4: Circuit example of XC6109N Series
9/16
XC6119 Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(1) Supply Current vs. Input Voltage (2) Detect Voltage vs. Ambient Temperature
XC6119x25Ax
A)
μ
2.0
1.5
1.0
0.5
Supply Current: ISS (
0.0
0123456
Input Voltage: V IN (V)
(3) Hysteresis Voltage vs. Ambient Temperature
XC6119x25Ax
0.20
0.15
0.10
0.05
Hys teresis Voltage: V HYS (V)
-50 -25 0 25 50 75 100
Ambi ent Temperature: Ta (℃)
(4) Output Voltage vs. Input Voltage
XC6119C25Ax
4.0
3.0
2.0
1.0
0.0
Output Voltage: VOUT (V)
-1.0
Ta=85
℃
25
℃
-40℃
0 0.5 1 1.5 2 2.5 3
Input Voltage: VIN (V)
Ta=85
No Pull-up
-40
25
2.55
℃
℃
2.50
℃
Detect Voltage: VDF (V)
2.45
-50 -25 0 25 50 75 100
4.0
3.0
2.0
1.0
0.0
Output V ol tage: V OUT (V )
-1.0
XC6119x25Ax
Ambi ent Temperat ure: Ta (℃)
XC6119N25Ax
Pull-up=VIN R=100k
Ta=85
℃
25
℃
-40
℃
0 0.5 1 1.5 2 2.5 3
Input Voltage: VIN (V)
Ω
10/16
r
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Output Current vs. Input Voltage
4.0
3.0
2.0
XC6119x50Ax
25
℃
VDS(nch)=0.5V
Ta=-40
℃
0.0
-0.5
-1.0
XC6119C08Ax
VDS(pch)=0.5V
Ta=85
25
1.0
Output Current: IOUT (mA)
0.0
0123456
Input Voltage: VIN (V)
85
℃
-1.5
Output Current: IOUT (mA)
-2.0
0123456
Input Voltage: V IN (V)
℃
-40
℃
(6) Cd Pin Sink Current vs. Input Voltage (7) Delay Resistance vs. Ambient Temperature
3.0
2.5
2.0
1.5
XC6119x50Ax
25
℃
Ta=-40
VDS=0.5V
℃
)
Ω
XC6119xxxAx
VCD=0.0V VIN=6.0V
4
3.5
3
2.5
1.0
0.5
Cd PIN Current: ICD (mA)
0.0
0123456
Input Voltage: VIN (V)
85
℃
2
1.5
1
Delay Resis tance: Rdelay ( M
-50 -25 0 25 50 75 100
Ambi ent Temperature: Ta (℃)
(8) Release Delay Time vs. Delay Capacitance
(9) Detect Delay Time vs. Delay Capacitance
(ms )
DR
10000
1000
100
XC6119xxxAx
VIN(min)= 0.7V VIN(max)=6.0V
=5μs Ta=25
t
℃
100000
s)
μ
(
DF
10000
1000
XC6119xxxAx
VIN(min)=0.7 V VIN(max)=6.0 V
t
=5μs Ta=25
f
10
1
0.1
Release Delay Tim e: t
0.0001 0.001 0.01 0.1 1
tDR=Cd×2.0×106×0.69
Delay Capacitanc e : Cd (μF)
100
10
1
Detect Delay Time: t
0.0001 0.001 0.01 0.1 1
Delay Capacitanc e : Cd (μF)
XC6119
Series
℃
℃
11/16
XC6119 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(10) Leak Current vs. Ambient Temperature
0.25
A)
μ
XC6119N25Ax
VIN=6.0V VOUT=6.0V
(11) Leak Current vs. Supply Voltage
XC6119N25Ax
0.25
A)
μ
VIN=6.0V
0.20
0.15
Leak Current: ILE A K (
0.10
-50 -25 0 25 50 75 100
Ambi ent Temperature: Ta (℃)
0.20
0.15
Leak Current: ILEAK (
0.10
0123456
Output V ol tage: V OUT (V)
12/16
■PA CKAGING INFORMATION
●SSOT-24 ●USPN-4
+0.2
-0.1
1.25
2.1±0.3
+0
-0.2
0.3
1.1MAX
0.9±0.1
1.2±0.05
+0.02
-0.03
0.38
●USPN-4 Reference Pattern Layout
XC6119
Series
05
0.
C
0.425±0.05
0.25±0.05
0.25 0.25
4
C0.075
1
0.125 0.55 0.125
3
0.60.25
2
●USPN-4 Reference Metal Mask Design
0.2 0.2
0.55
3
2
4
1
0.1 0.1
13/16
XC6119 Series
■MARKING RULE
●SSOT-24
① represents output configuration and integer number of detect voltage
CMOS Output (XC6119C Series)
MARK VOLTAGE (V) PRODUCT SERIES
A 0.X XC6119C0**N*
B 1.X XC6119C1**N*
C 2.X XC6119C2**N*
D 3.X XC6119C3**N*
E 4.X XC6119C4**N*
F 5.X XC6119C5**N*
N-channel Open Drain Output (XC6119N Series)
MARK VOLTAGE (V) PRODUCT SERIES
H 0.X XC6119N0**N*
K 1.X XC6119N1**N*
L 2.X XC6119N2**N*
M 3.X XC6119N3**N*
N 4.X XC6119N4**N*
P 5.X XC6119N5**N*
② represents decimal number of detect voltage
MARK VOLTAGE (V)
N X.0 XC6119**0*N*
P X.1 XC6119**1*N*
R X.2 XC6119**2*N*
S X.3 XC6119**3*N*
T X.4 XC6119**4*N*
U X.5 XC6119**5*N*
V X.6 XC6119**6*N*
X X.7 XC6119**7*N*
Y X.8 XC6119**8*N*
Z X.9 XC6119**9*N*
③④ represents production lot number
01 to 09, 0A to 0Z,11 to 9Z, A1 to A9,AA to Z9,ZA to ZZ repeated (G, I, J, O, Q, W excluded).
Note: No character inversion used.
PRODUCT SERIES
3
④
②①
③
2
SSOT-24
(TOP VIEW)
14/16
■ MARKING RULE (Continued)
●USPN-4
① represents product series.
MARK
B
② represents output configuration and integer number of detect voltage
PRODUCT SERIES
XC6119******-G
CMOS Output (XC6119C Series)
MARK VOLTAGE (V) PRODUCT SERIES
A 0.X XC6119C0**7*-G
B 1.X XC6119C1**7*-G
C 2.X XC6119C2**7*-G
D 3.X XC6119C3**7*-G
E 4.X XC6119C4**7*-G
F 5.X XC6119C5**7*-G
N-channel Open Drain Output (XC6119N Series)
MARK VOLTAGE (V) PRODUCT SERIES
H 0.X XC6119N0**7*-G
K 1.X XC6119N1**7*-G
L 2.X XC6119N2**7*-G
M 3.X XC6119N3**7*-G
N 4.X XC6119N4**7*-G
P 5.X XC6119N5**7*-G
③ represents decimal number of detect voltage
MARK VOLTAGE (V) PRODUCT SERIES
N X.0
P X.1
R X.2
S X.3
T X.4
U X.5
V X.6
X X.7
Y X.8
Z X.9
④⑤ represents production lot number
01 to 09, 0A to 0Z,11 to 9Z, A1 to A9,AA to Z9,ZA to ZZ repeated (G, I, J, O, Q, W excluded).
Note: No character inversion used.
XC6119**0*7*-G
XC6119**1*7*-G
XC6119**2*7*-G
XC6119**3*7*-G
XC6119**4*7*-G
XC6119**5*7*-G
XC6119**6*7*-G
XC6119**7*7*-G
XC6119**8*7*-G
XC6119**9*7*-G
1
2
USPN-4
(TOP VIEW)
①②
④⑤③
XC6119
Series
4
3
15/16
XC6119 Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics. Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this datasheet.
4. The products in this datasheet are not developed, designed, or approved for use with
such equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this datasheet within the spe cified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this datasheet may be copied or reproduced without the
prior permission of TOREX SEMICONDUCTOR LTD.
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