TOREX XC6118 User Manual

A

y

XC6118 Series

ETR02013-005

Voltage Detector with Separated Sense Pin & Delay Capacitor Pin

■GENERAL DESCRIPTIO N

The XC6118 series is a low power consumption voltage detector with high accuracy detection, manufactured using CMOS process and laser trimming technologies. Since the sense pin is separated from the power supply pin, it allows the IC to monitor the other power supply. The XC6118 can maintain the state of detection even when voltage of the monitored power supply drops to 0V. Moreover, a release delay time can be adjusted by the external capacitor connected to the Cd pin. The V

■

●Microprocessor reset circuitry

●Charge voltage monitors

●Memory battery back-up switch circuits

●Power failure detection circuits

■TYPICAL APPLICATION CIRCUIT

pin is available in both CMOS and N-channel open drain output configurations.

OUT

PPLICATIONS

■FEATURES

High Accuracy :±2％(Detect Voltage≧1.5V)

Low Power Consumption : 0.4μA TYP. (Detect, V

Detect Voltage Range : 0.8V～5.0V (0.1V increments) Operating Voltage Range : 1.0V～6.0V Temperature Characteristics : ±100ppm/℃ TYP. Output Configuration : CMOS, N-channel open drain Pin Function : Power supply separation

Release delay time adjustable

Operating Ambient Temperature Packages : USP-4, SOT-25 Environmentall

■TYPICAL PERFORMANCE CHARACTERISTICS

●Output Voltage vs. Sense Voltage

Monitering Power

別電源

supply

(No Pull-Up resistor needed for CMOS output product)

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

Output V ol tage: V OUT (V )

-1.0

±30mV(Detect Voltage＜1.5V)

=1.0V)

IN

0.8μA TYP. (Release, V

IN

: -40℃～+85℃

Friendly : EU RoHS Compliant, Pb Free

XC6118C25AGR

Ta=25

℃

VIN= 6.0V

4.0V

1.0V

0123456

Sense Voltage: VSEN (V)

=1.0V)

1/20

XC6118 Series

■PIN CONFIGURATION

Cd/NC 2 VOUT 1

USP-4

（BOTTOM VIEW）

* In the XC6118xxxA/B series, the dissipation pad

should not be short-circuited with other pins.

* In the XC6118xxxC/D series, when the dissipation

pad is short-circuited with other pins, connect it to the NC pin (No.2) pin before use.

■PIN ASSIGNMENT

PIN NUMBER

USP-4 SOT-25

1 1 V

5

VSS

3 VSEN 4 VIN

PIN NAME FUNCTION

Output (Detect ”L”)

OUT

2 5 Cd Delay Capacitance 2 5 NC No Connection 3 4 V

Sense

SEN

4 3 VIN Input 5 2 VSS Ground

NOTE:

*1: With the V *2: In the case of selecting no built-in delay capacitance pin type, the delay capacitance (Cd) pin will

be used as the NC.

■PRODUCT CLASSIFICATION

●Ordering Information

XC6118①②③④⑤⑥-⑦

SS pin of the USP-4 package, a tab on the backside is used as the pin No.5.

(*1)

Cd/NC

SOT-25

（TOP VIEW）

(*2)

(*1)

DESIGNATOR ITEM SYMBOL DESCRIPTION

①

②③

Output Configuration

Detect Voltage

C CMOS output N N-ch open drain output

08~50 e.g. 18 → 1.8V

A Built-in delay capacitance pin, hysteresis 5% (TYP.)(Standard*) B Built-in delay capacitance pin, hysteresis less than 1%(Standard*)

④

Options

C D

⑤⑥-⑦

*When delay function isn’t used, open the delay capacitance pin before use.

(*1)

The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant.

Packages

(Order Unit)

GR-G USP-4 (3,000/Reel)

MR-G SOT-25 (3,000/Reel)

No built-in delay capacitance pin, hysteresis 5% (TYP.) (Semi-custom) No built-in delay capacitance pin, hysteresis less than 1% (Semi-custom)

2/20

■BLOCK DIAGRAMS

(1) XC6118CxxA

(2) XC6118CxxB

(3) XC6118NxxA

(4) XC6118NxxB

XC6118

Series

*The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118CxxC (semi-custom).

*The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118CxxD (semi-custom).

*The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118NxxC (semi-custom).

* Diodes inside the circuits are ESD protection diodes and parasitic diodes.

*The delay capacitance pin (Cd) is not connected to the circuit in the block diagram of XC6118NxxD (semi-custom).

3/20

A

XC6118 Series

■

4/20

BSOLUTE MAXIMUM RATINGS

●XC6118xxxA/B

Output Current I

Output Voltage

Sense Pin Voltage V Delay Capacitance Pin Voltage VCD Delay Capacitance Pin Current ICD 5.0 mA

Power Dissipation

Operating Ambient Temperature Ta

Storage Temperature T stg

●XC6118xxxC/D

Output Current I

Output Voltage

Sense Pin Voltage V

Power Dissipation

Operating Ambient Temperature Ta

Storage Temperature T stg

NOTE: *1: CMOS output *2: N-ch open drain output

Ta=25℃

PARAMETER SYMBOL RATINGS UNITS

Input Voltage VIN

V

OUT

SEN

Pd

XC6118C XC6118N

(*1) (*2)

USP-4 120

SOT-25

-0.3～7.0

V

SS

10 mA

-0.3～VIN+0.3

V

SS

VSS-0.3～7.0

-0.3～7.0

V

SS

-0.3～VIN+0.3

V

SS

250

-40～+85

-55～+125

V

V V

V

mW

o

C

o

C

Ta=25℃

PARAMETER SYMBOL RATINGS UNITS

Input Voltage VIN

V

OUT

SEN

Pd

XC6118C XC6118N

(*1) (*2)

USP-4 120

SOT-25

-0.3～7.0

V

SS

10 mA

-0.3～VIN+0.3

V

SS

V

SS

V

SS

-0.3～7.0

250

-40～+85

-55～+125

V

V V

mW

o

C

o

C

■ELECTRICAL CHARACTERISTICS

●XC6118xxxA

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX.

Operating Voltage

Detect Voltage

Hysteresis Width

Detect Voltage

Line Regulation

Supply Current 1

Supply Current 2

Output Current

Leakage

Current

(*2)

I

(*2)

I

(*3)

CMOS Output

(P-ch)

N-ch Open Drain

Output

V

IN

V

DF

V

HYS

ΔV

/

DF

)

IN・VDF

SS1

SS2

(ΔV

V

I

OUT1

I

OUT2

I

LEAK

V

OUT

=0.8～5.0V

DF(T)

=1.0～6.0V E-1 V ①

IN

=1.0～6.0V E-2 V ①

IN

VIN=1.0～6.0V ±0.1 %/V ① V

SEN=VDF

V V

V

SEN=VDF

V V

=0V, VDS=0.5V(Nch)

SEN

V V V V V V

V

DS

V V

VIN=6.0V, V

=0V, Cd: Open

V

OUT

=6.0V, V

V

IN

=6.0V, Cd: Open

×0.9

=1.0V

IN

=6.0V

IN

×1.1

=1.0V

IN

=6.0V

IN

=1.0V

IN

=2.0V

IN

=3.0V

IN

=4.0V

IN

=5.0V

IN

=6.0V

IN

=6.0V,

SEN

=0.5V(Pch)

=1.0V

IN

=6.0V

IN

=0V,

SEN

=6.0V,

SEN

XC6118

Ta=25℃

UNITS

(*1)

1.0 6.0 V -

0.1

0.8

1.2

1.6

1.8

1.9

0.4

0.8

0.9

0.7

1.6

2.0

2.3

2.4

2.5

-0.30

-1.00

1.0

μA ②

1.0

1.6

μA ②

1.8

mA ③

-0.08

mA ④

-0.70

-0.20 μA ③

0.20 0.40

CIRCUITS

Series

Temperature Characteristics

Sense Resistance

Delay Resistance

Delay capacitance pin

Sink Current

Delay Capacitance Pin Thresho ld

Voltage

Undefined Operation

Detect Delay Time

Release Delay Time

NOTE:

*1: V

: Nominal detect voltage

DF (T)

*2: Current to the sense resistor is not included.

is applied only to the XC6118C series (CMOS output).

*3: I

OUT2

*4: It is calculated from the voltage value and the current value of the V *5: It is calculated from the voltage value of the V

*6: Maximum V

This value is effective only to the XC6118C series (CMOS output). *7: Delay time from the time of V *8: Delay time from the time of V

/

ΔV

DF

(ΔT

(*4)

(*5)

R

(*6)

V

(*7)

(*8)

voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the V

OUT

SEN=VDF

= VDF +V

IN

)

opr・VDF

R

V

SEN

DELAY

ICD Cd=0.5V, VIN=1.0V 200 μA ⑥

V

TCD

V

UNS

t

DF0

t

DR0

to the time of V

HYS

o

-40

C≦T

≦85 oC ±100 ppm/oC ①

opr

=5.0V VIN=0V E-4 MΩ ⑤

SEN

V

=6.0V VIN=5.0V

SEN

Cd=0V

V

=6.0V VIN=1.0V

SEN

=6.0V VIN=6.0V

V

SEN

=0～1.0V 0.3 0.4 V ⑧

IN=VSEN

V

=6.0V, V

IN

=6.0V→0V

SEN

Cd: Open

V

=6.0V, V

IN

=0V→6.0V

SEN

Cd: Open

and the current value of the Cd.

IN

= 0.6V when the V

OUT

SEN

= 5.4V when the V

1.6 2.0 2.4 MΩ ⑥

0.4

2.9

0.5

3.0

30 230 μs ⑨

30 200 μs ⑨

.

falls.

SEN

rises.

SEN

0.6

3.1

SEN

V ⑦

pin.

5/20

XC6118 Series

■ELECTRICAL CHARACTERISTICS (Continued)

●XC6118xxxB

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX.

Operating Voltage

Detect Voltage

Hysteresis Width

Detect Voltage

Line Regulation

Supply Current 1

Supply Current 2

Output Current

Leakage

Current

(*2)

(*3)

CMOS Output

(P-ch)

N-ch Open

Drain Output

V

IN

V

DF

V

HYS

ΔV

/

DF

IN・VDF

I

SS1

I

SS2

I

OUT1

I

OUT2

)

V

SEN

V

SEN

(ΔV

VIN=6.0V, V

I

LEAK

V

=6.0V, Cd: Open

V

OUT

=0.8～5.0V

DF(T)

=1.0～6.0V E-1 V ①

IN

=1.0～6.0V E-3 V ①

IN

V

=1.0～6.0V ±0.1 %/V ①

IN

V

SEN=VDF

=1.0V

V

IN

=6.0V

V

IN

V

SEN=VDF

=1.0V

V

IN

=6.0V

V

IN

=0V VDS=0.5V(Nch)

=1.0V

V

IN

=2.0V

V

IN

=3.0V

V

IN

=4.0V

V

IN

=5.0V

V

IN

=6.0V

V

IN

=6.0V VDS=0.5V(Pch)

=1.0V

V

IN

=6.0V

V

IN

=0V, Cd: Open

OUT

=6.0V, V

IN

(*1)

1.0 6.0 V -

×0.9

×1.1

0.1

0.8

1.2

1.6

1.8

1.9

=0V,

SEN

=6.0V,

-0.20

0.20 0.40

0.4

0.8

0.9

0.7

1.6

2.0

2.3

2.4

2.5

-0.30

-1.00

UNITS

1.0

μA ②

1.0

1.6

μA ②

1.8

mA ③

-0.08

mA ④

-0.70

μA ③

Ta=25℃

CIRCUITS

Temperature Characteristics

Sense Resistance

Delay Resistance

Delay capacitance pin

Sink Current

Delay Capacitance Pin

Threshold Voltage

Undefined Operation

Detect Delay Time

Release Delay Time

NOTE:

*1: V *2: Current to the sense resistor is not included.

*3: I *4: It is calculated from the voltage value and the current value of the V *5: It is calculated from the voltage value of the V

*6: Maximum V

*7: Delay time from the time of V *8: Delay time from the time of V

: Nominal detect voltage

DF (T)

is applied only to the XC6118C series (CMOS output).

OUT2

This value is effective only to the XC6118C series (CMOS output).

/

ΔV

DF

(ΔT

(*4)

(*5)

R

(*6)

V

(*7)

(*8)

voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the V

OUT

)

opr・VDF

R

V

SEN

V

DELAY

I

Cd=0.5V, VIN=1.0V 200 μA ⑥

CD

V

TCD

V

UNS

t

DF0

t

DR0

to the time of V

SEN=VDF

= VDF +V

IN

HYS

o

-40

C≦T

≦85 oC ±100 ppm/oC ①

opr

=5.0V VIN=0V E-4 MΩ ⑤

SEN

=6.0V VIN=5.0V Cd=0V 1.6 2.0 2.4 MΩ ⑥

SEN

V

=6.0V VIN=1.0V

SEN

=6.0V VIN=6.0V

V

SEN

=0～1.0V 0.3 0.4 V ⑧

IN=VSEN

V

=6.0V, V

IN

=6.0V→0V

SEN

Cd: Open

V

=6.0V, V

IN

=0V→6.0V

SEN

Cd: Open

and the current value of the Cd.

IN

= 0.6V when the V

to the time of V

OUT

SEN

= 5.4V when the V

0.4

2.9

.

SEN

0.5

3.0

30 230 μs ⑨

30 200 μs ⑨

falls.

rises.

SEN

0.6

3.1

SEN

pin.

V ⑦

6/20

)

■ELECTRICAL CHARACTERISTICS(Continued

●XC6118xxxC

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX.

×0.9

×1.1

SEN

=0V

SEN

=6.0V

(*1)

1.0 6.0 V -

0.1

0.8

1.2

1.6

1.8

1.9

=0V,

=6.0V,

-0.20

0.20 0.40

Operating Voltage

Detect Voltage

Hysteresis Width

Detect Voltage

Line Regulation

Supply Current 1

Supply Current 2

Output Current

Leakage

Current

(*2)

I

(*3)

CMOS Output

(P-ch)

Nch Open Drain

Output

V

IN

V

DF

V

HYS

ΔV

/

DF

IN・VDF

I

SS1

SS2

I

OUT1

I

OUT2

)

V

SEN

V

SEN

(ΔV

VIN=6.0V, V

I

LEAK

V

=0.8～5.0V

DF(T)

=1.0～6.0V E-1 V ①

IN

=1.0～6.0V E-2 V ①

IN

V

=1.0～6.0V ±0.1 %/V ①

IN

V

SEN=VDF

=1.0V

V

IN

=6.0V

V

IN

V

SEN=VDF

=1.0V

V

IN

=6.0V

V

IN

=0V VDS=0.5V(Nch)

=1.0V

V

IN

=2.0V

V

IN

=3.0V

V

IN

=4.0V

V

IN

=5.0V

V

IN

=6.0V

V

IN

=6.0V VDS=0.5V(Pch)

=1.0V

V

IN

=6.0V

V

IN

V

OUT

=6.0V, V

IN

V

OUT

0.4

0.8

0.9

0.7

1.6

2.0

2.3

2.4

2.5

-0.30

-1.00

Ta=25℃

UNITS

1.0

1.6

1.8

mA ③

-0.08

-0.70

μA ②

mA ④

μA ③

XC6118

Series

CIRCUITS

Temperature Characteristics

Sense Resistance

Undefined Operation

Detect Delay Time

Release Delay Time

NOTE:

*1: V

DF (T)

*2: Current to the sense resistor is not included.

*3: I

OUT2

*4: It is calculated from the voltage value and the current value of the V *5: Maximum V

This value is effective only to the XC6118C series (CMOS output). *6: Delay time from the time of V *7: Delay time from the time of V

(*4)

(*6)

(*7)

(*5)

ΔVDF/

(ΔT

)

opr・VDF

R

V

SEN

V

UNS

t

V

DF0

t

V

DR0

o

-40

C≦ T

SEN

IN=VSEN

=6.0V, V

IN

=6.0V, V

IN

≦85 oC ±100 ppm/oC ①

opr

=5.0V VIN=0V E-4 MΩ ⑤

=0～1.0V 0.3 0.4 V ⑦

=6.0→0V 30 230 μs ⑨

SEN

=0→6.0V 30 200 μs ⑨

SEN

: Nominal detect voltage

is applied only to the XC6118C series (CMOS output).

voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the V

OUT

SEN=VDF

= VDF +V

IN

to the time of V

HYS

= 0.6V when the V

OUT

.

SEN

= 5.4V when the V

OUT

SEN

falls.

SEN

rises.

SEN

pin.

7/20

)

●

XC6118 Series

■ELECTRICAL CHARACTERISTICS(Continued

8/20

XC61 18xxxD

PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX.

Operating Voltage

Detect Voltage

Hysteresis Width

Detect Voltage

Line Regulation

Supply Current 1

Supply Current 2

Output Current

(*2)

I

(*2)

I

(*3)

CMOS Output

Leakage

Current

(P-ch)

Nch Open

Drain Output

Temperature Characteristics

Sense Resistance

Undefined Operation

Detect Delay Time

Release Delay Time

(*4)

(*6)

(*5)

(*7)

V

IN

V

DF

V

HYS

ΔV

/

DF

IN・VDF

SS1

SS2

)

(ΔV

V

I

OUT1

V

SEN

I

OUT2

I

LEAK

ΔVDF/

(ΔT

)

opr・VDF

R

V

SEN

V

UNS

t

V

DF0

t

V

DR0

=0.8～5.0V

DF(T)

=1.0～6.0V E-1 V ①

IN

=1.0～6.0V E-3 V ①

IN

V

=1.0～6.0V ±0.1 %/V ①

IN

V

SEN=VDF

=1.0V

V

IN

=6.0V

V

IN

V

SEN=VDF

=1.0V

V

IN

=6.0V

V

IN

=0V VDS=0.5V(Nch)

SEN

=1.0V

V

IN

=2.0V

V

IN

=3.0V

V

IN

=4.0V

V

IN

=5.0V

V

IN

=6.0V

V

IN

=6.0V VDS=0.5V(Pch)

=1.0V

V

IN

=6.0V

V

IN

VIN=6.0V, V

V

OUT

V

=6.0V, V

IN

V

OUT

o

-40

C≦T

=5.0V VIN=0V E-4 MΩ ⑤

SEN

IN=VSEN

=6.0V V

IN

=6.0V V

IN

NOTE:

*1: V

: Nominal detect voltage

DF (T)

*2: Current to the sense resistor is not included.

is applied only to the XC6118C series (CMOS output).

*3: I

OUT2

*4: It is calculated from the voltage value and the current value of the V *5: Maximum V

voltage when VIN is changed from 0V to 1.0V under connecting the VIN pin to the V

OUT

This value is effective only to the XC6118C series (CMOS output). *6: Delay time from the time of V *7: Delay time from the time of V

SEN=VDF

= VDF +V

IN

to the time of V

HYS

(*1)

1.0 6.0 V -

×0.9

×1.1

0.1

0.8

1.2

1.6

1.8

1.9

=0V,

SEN

=0V

=6.0V,

SEN

=6.0V

≦85 oC ±100 ppm/oC ①

opr

-0.20

0.20 0.40

=0～1.0V 0.3 0.4 V ⑦

=6.0→0V 30 230 μs ⑨

SEN

=0→6.0V 30 200 μs ⑨

SEN

.

SEN

= 0.6V when the V

OUT

= 5.4V when the V

OUT

SEN

0.4

0.8

0.9

0.7

1.6

2.0

2.3

2.4

2.5

-0.30

-1.00

falls.

SEN

rises.

Ta=25℃

UNITS

1.0

1.6

1.8

mA ③

-0.08

-0.70

μA ②

mA ④

μA ③

pin.

SEN

CIRCUITS

■VOLTAGE CHART

SYMBOL E-1 E-2 E-3 E-4

NOMINAL VOLTAGE

NOTE:

*1: When V

When V

PARAMETER

DF(T)

(V)

0.8 0.770 0.830 0.015 0.066 0.008

0.9 0.870 0.930 0.017 0.074 0.009

1.0 0.970 1.030 0.019 0.082 0.010

1.1 1.070 1.130 0.021 0.090 0.011

1.2 1.170 1.230 0.023 0.098 0.012

1.3 1.270 1.330 0.025 0.106 0.013

1.4 1.370 1.430 0.027 0.114 0.014

1.5 1.470 1.530 0.029 0.122 0.015

1.6 1.568 1.632 0.031 0.131 0.016

1.7 1.666 1.734 0.033 0.085 0.017

1.8 1.764 1.836 0.035 0.147 0.018

1.9 1.862 1.938 0.037 0.155 0.019

2.0 1.960 2.040 0.039 0.163 0.020

2.1 2.058 2.142 0.041 0.171 0.021

2.2 2.156 2.244 0.043 0.180 0.022

2.3 2.254 2.346 0.045 0.188 0.023

2.4 2.352 2.448 0.047 0.196 0.024

2.5 2.450 2.550 0.049 0.204 0.026

2.6 2.548 2.652 0.051 0.212 0.027

2.7 2.646 2.754 0.053 0.220 0.028

2.8 2.744 2.856 0.055 0.228 0.029

2.9 2.842 2.958 0.057 0.237 0.030

3.0 2.940 3.060 0.059 0.245 0.031

3.1 3.038 3.162 0.061 0.253 0.032

3.2 3.136 3.264 0.063 0.261 0.033

3.3 3.234 3.366 0.065 0.269 0.034

3.4 3.332 3.468 0.067 0.277 0.035

3.5 3.430 3.570 0.069 0.286 0.036

3.6 3.528 3.672 0.071 0.294 0.037

3.7 3.626 3.774 0.073 0.302 0.038

3.8 3.724 3.876 0.074 0.310 0.039

3.9 3.822 3.978 0.076 0.318 0.040

4.0 3.920 4.080 0.078 0.326 0.041

4.1 4.018 4.182 0.080 0.335 0.042

4.2 4.116 4.284 0.082 0.343 0.043

4.3 4.214 4.386 0.084 0.351 0.044

4.4 4.312 4.488 0.086 0.359 0.045

4.5 4.410 4.590 0.088 0.367 0.046

4.6 4.508 4.692 0.090 0.375 0.047

4.7 4.606 4.794 0.092 0.384 0.048

4.8 4.704 4.896 0.094 0.392 0.049

4.9 4.802 4.998 0.096 0.400 0.050

5.0 4.900 5.100 0.098 0.408

DF(T)≦1.4V, the detection accuracy is ±30mV. DF(T)≧1.5V, the detection accuracy is ±2%.

DETECT VOLTAGE

MIN. MAX. MIN. MAX. MIN. MAX. MIN. TYP.

(*1)

(V) VDF V

HYSTERESIS RANGE

(V)

V

HYS

HYSTERESIS RANGE

XC6118

Series

(V)

R

HYS

0

0.051

SENSE RESISTANCE

(MΩ)

V

SEN

10 20

13 24

15 28

9/20

XC6118 Series

■TEST CIRCUITS

Circuit 1

Circuit 3

Circuit 5

Circuit 7

Circuit 9

10/20

VSEN

Cd

VSEN

Cd

V

VIN

XC6118 Series

VSS

VIN

VSS

VOUT

VIN

VSEN

XC6118 Series

Cd

VSS

R

=100kΩ

PULL

(No resistor needed for CMOS output products)

V

AXC6118 Series

VOUT

Circuit 2

Circuit 4

Circuit 6

Circuit 8

=100kΩ

R

PULL

(No resistor needed for CMOS output products)

V

R

=100kΩ

PULL

(No resistor needed for CMOS output products)

Waveform Measurement Point

*No delay capacitance pin available in the XC6118xxxC/D series.

VSEN

XC6118 Series

Cd

A

VIN

VSS

VSEN

Cd

VOUT

VIN

XC6118 Series

VSS

A

VOUT

XC6118

Series

■OPERATIONAL EXPLANATION

A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2.

① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay ca pacitance (Cd) is charged

to the power supply input voltage, (V reach the detect voltage (V

* If a pull-up resistor of the XC6118N series (N-ch open drain) is connected to added power supply different from the input

voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected.

② When the sense pin voltage keeps dropping and becomes equal to the detect voltage (VSEN =VDF), an N-ch transistor (M1)

for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An inverter (Inv.1) operates as a comparator of the reference voltage VIN, and the output voltage changes into the “Low” level (=VSS). The detect delay time [t Cd pin is not connected: t

③ While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground voltage

(=V

SS) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to reach the

release voltage (V

VIN

SEN< VDF +VHYS).

VIN

VSEN

Cd

DF) (VSEN>VDF), the output voltage (VOUT) keeps the “High” level (=VIN).

] is defined as time which ranges from VSEN=VDF to the VOUT of “Low” level (especially, when the

DF

).

DF0

*The XC6118N series (N-ch open drain output) requires a pull-up resistor for pulling up output.

VOUT

VSS

ＲＳEN=R1+R2+R3

R1

R2

R3

Comparator

Vref

M5

M2

delay

R

M1

M4

Inverter

M3

Figure 1: Typical application circuit example

Sense Pin Voltage: V Release Voltage: VDF+V

Detect Voltage: V

Delay Capacitance Pin Voltage: VCD(MIN.:V

Delay Capacitance Pin Threshold Voltage: V

Output Voltage Pin Voltage: V

(MIN.:0V MAX.:6.0V)

SEN

HYS

DF

OUT

Figure 2: The timing chart of Figure 1

IN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to

SS,

TCD

(MIN.:VSS MAX:VIN)

MAX.:VIN)

11/20

XC6118 Series

■OPERATIONAL EXPLANATION (Continued)

④ When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor (M1) for

the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay resistor (R Threshold: V

⑤ While the delay capacitance pin voltage (VCD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the

sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC series circuit. Assuming the time to the release delay time (tDR), it can be given by the formula (1).

The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and the delay capacitance pin threshold voltage is V

As an example, presuming that the delay capacitance is 0.68μF, tDR is :

* Note that the release delay time may remarkably be short when the del ay capacitance (Cd) is not discharged to the ground

SS) level because time described in ③ is short.

(=V

⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (VCD=VTCD), the inv erter

(Inv.1) will be inverted. As a result, the out put voltage changes i nto the “High” (=V ranges from V

⑦ While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the delay

capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=V

). The inverter (Inv.1) will operate as a comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic

DELAY

THL=VSS) while the sense pin voltage keeps higher than the detect voltage (VSEN > VDF).

t

=-R

DR

tDR=R

2.0×10

DELAY

IN /2 (TYP.)

DELAY

*

：

R

DELAY

6

×

×Cd×

is 2.0M

0.68×10

ln(1-V

0.69

Ω（

-6

×

TCD/VIN

) …(1)

…

(2)

TYP.）

0.69=938(ms)

IN) level. t

SEN=VDF+VHYS to the VOUT of “High” level without connecting to the Cd.

is defined as time which

DR0

IN) level.

●Function Chart

V

Cd

SEN

L

H

L

H

L

H

L

H

*1: V

transits from condition ① to ② because of the combination of V

OUT

VIN should be more than the lowest operation voltage.

●Example ex. 1) V ex. 2) V

ranges from ‘L’ to ‘H’ in case of VSEN = ‘H’ (VDR≧VSEN), Cd=’H’ (VTCD≧Cd) while VOUT is ‘L’.

OUT

maintains ‘H’ when Cd ranges from ‘H’ to ‘L’, VSEN=’H’ and Cd=’L’ when V

OUT

TRANSITION OF V

①

L

H

L

H

CONDITION *1

OUT

⇒

⇒ ⇒

⇒

●Release Delay Time Chart

DELAY

CAPACITANCE [Cd]

(μF)

RELEASE DELAY TIME [tDR]

(TYP.)

(ms)

0.010 13.8 11.0 ~ 16.6

0.022 30.4 24.3 ~ 36.4

0.047 64.9 51.9 ~ 77.8

0.100 138 110 ~ 166

0.220 304 243 ~ 364

0.470 649 519 ~ 778

1.000 1380 1100 ~ 1660

* The release delay time values above are calculated by using the formula (2). *2: The release delay time (t

) is influenced by the delay capacitance Cd.

DR

②

L

H

and VCD,VIN.

SEN

becomes ‘H’ in ex.1.

OUT

RELEASE DELAY TIME [tDR] *2

(MIN. ~ MAX.)

(ms)

12/20

r

XC6118

Series

■NOTES ON USE

1. Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising phenomenon, the IC is liable to malfunction should the ratings be exceeded.

2. The power supply input pin voltage drops by the resistance between power supply and the V operation of the IC. At this time, the operation may be wrong if the power supply input pin voltage falls below the minimum operating voltage range. In CMOS output, for output current, drops in the power supply input pin voltage similarly occur. Moreover, in CMOS output, when the V occur if the drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis voltage. Note it especially when you use the IC with the V

3. W hen the setting voltage is less than 1.0V, be sure to separate the V

1.0V to the V

4. Note that a rapid and high fluctuation of the power supply input pin voltage may cause a wrong operation.

5. Power supply noise may cause operational function errors, Care must be taken to put the capacitor between V test on the board carefully.

6. When there is a possibility of which the power supply input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operat ion

with the delay capacitance pin (Cd) connected to a capacitor, use a Schottky barrier diode connected between the V and the Cd pin as the Figure 3 shown below.

7. In N channel open drain output, V

connected at the V

During detection: V

V

R

(※1)：On resistance of N channel driver M3 can be calculated as V

ON

For example, when (※2) R R In this case, R

IN pin.

: Pull up voltage

PULL

pin. Please choose proper resistance values with refer to Figure 4;

OUT

= V

/ (1+R

PULL

= 0.5 / 0.8×10

ON

/V

-1)×RON= (3 / 0.1-1)×625≒18ｋΩ

OUT

= (V

OUT

PULL

should be selected higher or equal to 18kΩ in order to keep the output voltage less than 0.1V during

IN pin and the sense pin are short-circuited and used, oscillation of the circuit may

IN pin connected to a resistor.

IN pin and the sense pin, and to apply the voltage over

voltage at detect and release is determined by resistance of a pull up resistor

OUT

/ RON)

PULL

/ I

-3

= 625Ω（MAX.）at VIN=2.0V, V

DS

from electrical characteristics,

OUT1

= 3.0V and V

PULL

detection.

(※1) R (※2) For calculation, Minimum V

is bigger when VIN is smaller, be noted.

ON

should be chosen among the input voltage range.

IN

During releasing：V

V

：Pull up voltage

PULL

R

：On resistance of N channel driver M3 is 15MΩ（MIN.） when the driver is off (as to V

OFF

For example：when V R

In this case, R

PULL

= (V

OUT

= V

PULL

/ (1 + R

PULL

= 6.0V and V

PULL

/ V

-1)×R

OUT

/ R

PULL

OUT

= (6/5.99-1)×15×106 ≒25 kΩ

OFF

)

OFF

≧ 5.99V,

should be selected smaller or equal to 25 kΩ in order to obtain output voltage higher than 5.99V during

releasing.

8. Torex places an importance on improving our products and their relia bility.

We request that users incorporate fail-safe designs and post-aging protection treatment when us ing Torex products in their systems.

R

=100kΩ

VIN

VSEN

VSENVIN

Cd

VOUT

VSS

PULL

(No resistor needed fo CMOS output products)

VOUT

VIN

VSEN

Cd

VIN

ＲＳEN=R1+R2+R3

Cd

IN pin, and by through current at

≦0.1V at detect,

OUT

/ I

OUT

LEAK

M2

delay

R

Inverter

M1

R1

R2

R3

Comparator

Vref

M5

-GND and

IN

)

M4

M3

IN pin

VOUT

VSS

Figure 3: Circuit example with the delay capacitance pin (Cd) connected to a Schottky barrier diode

NOTE：R

OFF=VOUT/ILEAK

Figure 4: Circuit example of XC6118N Series

13/20

XC6118 Series

■TYPICAL PERFORMANCE CHARACTERISTICS

(1) Supply Current vs. Sense Voltage

2.0

A)

μ

1.5

1.0

0.5

Supply Current: ISS (

0.0

(2) Supply Current vs. Input Voltage

1.2

A)

1.0

μ

0.8

0.6

0.4

0.2

Supply Current: ISS (

0.0

(3) Detect Voltage vs. Ambient Temperature

2.55

2.50

Detect Voltage: VDF (V)

2.45

14/20

XC6118C25Ax

VIN=3.0V

Ta=85

℃

25

℃

-40

℃

0123456

Sense Voltage: VSEN (V)

XC6118C25Ax

VSEN=2.25V

Ta=85

℃

25

℃

-40

℃

0123456

Input Voltage: V IN (V)

XC6118C25Ax

VIN=4.0V

-50-25 0 25 50 75100

Ambi ent Temperature: Ta (℃)

1.2

A)

1.0

μ

0.8

0.6

0.4

0.2

Supply Current: ISS (

0.0 0123456

(4) Detect Voltage vs. Input Voltage

2.55

2.50

Detect Voltage: VDF (V)

2.45

1.0 2.0 3.0 4.0 5.0 6.0

XC6118C25Ax

VSEN=2.75V

Input Voltage: VIN (V)

XC6118C25Ax

Input Voltage: V IN (V)

Ta=85

-40

Ta=25

85

-40

25

℃

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(5) Hysteresis Voltage vs. Ambient Temperature

(6) CD Pin Sink Current vs. Input Voltage

0.20

0.15

0.10

0.05

Hys t eresis Volt age: V HY S (V)

XC6118C25Ax

VIN=4.0V

-50 -25 0 25 50 75 100

Ambi ent Temperature: Ta (℃)

3.0

2.5

2.0

1.5

1.0

0.5

Cd PIN Curren t: ICD (m A)

0.0

XC6118C25Ax

VSEN=0V VDS=0.5V

Ta=-40

25

℃

85

℃

0123456

Input Voltage : V IN (V)

(7) Output Voltage vs. Sense Voltage

(8) Output Voltage vs. Input Voltage

7.0

6.0

5.0

4.0

3.0

2.0

1.0

0.0

Output V ol tage: V OUT (V )

-1.0

XC6118C25Ax

Ta=25

℃

VIN= 6.0V

4.0V

1.0V

0123456

Sense Voltage: VSEN (V)

4.0

3.0

2.0

1.0

0.0

Output V ol tage: V OUT (V )

-1.0

XC6118N25A x

VSEN=VIN Pull-up=VIN R=100k

Ta=85

℃

25

℃

-40

℃

0 0.5 1 1.5 2 2.5 3

Input Voltage : V IN (V)

(9) Output Current vs. Input Voltage

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

Output Current: Iout (m A )

0.0

XC6118C25Ax

VDS(Nch)=0.5V

Ta=-40

℃

25

℃

85

℃

0123456

Input Voltage : VIN (V)

0.0

-0.5

-1.0

-1.5

Output Current: Iout (mA)

-2.0

XC6118C25Ax

VDS(Pch)=0.5V

Ta=85

25

℃

-40

0123456

Input Voltage : V IN (V)

XC6118

Series

℃

Ω

℃

15/20

XC6118 Series

■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

(10) Delay Resistance vs. Ambient Temperature

)

4

Ω

3.5 3

2.5 2

1.5 1

Delay Resis tance: Rdelay ( M

-50 -25 0 25 50 75 100

(12) Detect Delay Time vs. Delay Capacitance

1000

s)

μ

100

10

1

Detect Delay time: TDF (

0.0001 0.001 0.01 0.1 1

(14) Leakage Current vs. Supply Voltage

0.25

A)

μ

0.20

0.15

Leak Current: ILEAK (

0.10 0123456

XC6118C25Ax

VSEN=6.0V VCD=0.0V VIN=5.0V

Ambi ent Temperature: Ta (℃)

XC6118C25Ax

Ta=25

VIN=6.0V

4.0V

3.0V

2.0V

1.0V

Delay Capac i t or: Cd (μF)

XC6118N25Ax

VIN=VSEN=6.0V

Output V ol tage: V OUT (V)

16/20

℃

(11) Release Delay Time vs. Delay Capacitance

XC6118C25Ax

10000

1000

100

10

0.1

Relea se Del ay t ime: TDR (ms )

0.0001 0.001 0.01 0.1 1

(13) Leakage Current vs. Ambient Temperature

0.25

A)

μ

0.20

0.15

Leak Current: ILE A K (

0.10

VIN=1.0V

3.0V

6.0V

1

tDR=Cd×2.0×106×0.69

Delay Capac i t or: Cd (μF)

XC6118N25Ax

VIN=VSEN =6. 0V VOUT=6.0V

-50 -25 0 25 50 75 100

Ambi ent Temperature: Ta (℃)

Ta=25

℃

■PA CKAGING INFORMATION

●USP-4

●USP-4 Reference Pattern Layout

●USP-4 Reference Metal Mask Design

0.3

1.9

0.3

1.0

0.35 0.35

43

12

0.6

0.5

●SOT-25

+0.2

1.6

1.1±0.1

XC6118

Series

-0.1

2.8±0.2

0.2MIN

1.3MAX

17/20

XC6118 Series

■MARKING RULE

●SOT-25 ① represents output configuration and integer number of detect voltage

CMOS Output (XC6118C Series) N-ch Open Drain Output (XC6118N Series)

MARK VOLTAGE (V)

L 0.X M 1.X N 2.X

P 3.X R 4.X

S 5.X

② represents decimal number of detect voltage

(ex.)

MARK VOLTAGE (V) PRODUCT SERIES

3 X.3 XC6118**3*** 0 X.0 XC6118**0***

③ represents options

MARK OPTIONS PROD UCT SERIES

A

B C D

④⑤ represents production lot number 0 to 9 A to Z, or inverted characters of 0 to 9, A to Z repeated. (G, I, J, O, Q, and W excluded) *No character inversion used.

Built-in delay capacitance pin with hysteresis 5% (TYP.)

(Standard)

Built-in delay capacitance pin with hysteresis less than 1%

(Standard)

No built-in delay capacitance pin with hysteresis 5% (TYP.)

(Semi-custom)

No built-in delay capacit an ce pi n w ith hy stere sis le ss than 1%

(Semi-custom)

MARK VOLTAGE (V)

T 0.X U 1.X V 2.X X 3.X Y 4.X

Z 5.X

XC6118***A**

XC6118***B** XC6118***C** XC6118***D**

54

① ② ③ ④ ⑤

123

SOT-25

(TOP VIEW)

18/20

■MARKING RULE (Continued)

●USP-4 ① represents output configuration and integer number of detect voltage

CMOS Output (XC6118C Series) N-ch Open Drain Output (XC6118N Series)

MARK VOLTAGE (V)

L 0.X M 1.X N 2.X

P 3.X R 4.X

S 5.X

② represents decimal number of detect voltage

(ex.)

MARK VOLTAGE (V) PRODUCT SERIES

3 X.3 XC6118**3*** 0 X.0 XC6118**0***

③ represents options

MARK VOLTAGE (V)

T 0.X

U 1.X

V 2.X X 3.X Y 4.X Z 5.X

MARK OPTIONS PRODUCT SERIES

A B C D

④⑤ represents production lot number 0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated. (G, I, J, O, Q, and W excluded) *No character inversion used.

Built-in delay capacitance pin with hysteresis 5% (TYP.)

(Standard)

Built-in delay capacitance pin with hysteresis less than 1%

(Standard)

No built-in delay capacitance pin with hysteresis 5% (TYP.)

(Semi-custom)

No built-in delay capacitance pin with hysteresis less than 1%

(Semi-custom)

XC6118***A** XC6118***B** XC6118***C** XC6118***D**

1

2

(TOP VIEW)

④ ⑤

USP-4

XC6118

Series

① ②

4

③

3

19/20

XC6118 Series

1. The products and product specifications contained herein are subject to change without notice to improve performance characteristics. Consult us, or our representatives before use, to confirm that the information in this datasheet is up to date.

2. We assume no responsibility for any infringement of patents, patent rights, or other rights arising from the use of any information and circuitry in this datasheet.

3. Please ensure suitable shipping controls (including fail-safe designs and aging protection) are in force for equipment employing products listed in this datasheet.

4. The products in this datasheet are not developed, designed, or approved for use with such equipment whose failure of malfunction can be reasonably expected to directly endanger the life of, or cause significant injury to, the user. (e.g. Atomic energy; aerospace; transport; combustion and associated safety equipment thereof.)

5. Please use the products listed in this datasheet within the specified ranges. Should you wish to use the products under conditions exceeding the specifications, please consult us or our representatives.

6. We assume no responsibility for damage or loss due to abnormal use.

20/20

TOREX XC6118 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual