*2: Current flows the sense resistor is not included.
*3: The Pch values are applied only to the XC6108C series (CMOS output).
*4: Calculated from the voltage value and the current value of the V
*5: The maximum voltage of the V
This value is applied only to the XC6108C series (CMOS output).
*6: Time which ranges from the state of V
*7: Time which ranges from the state of V
(*5)
(*6)
(*7)
: Nominal detect voltage
UNS VIN = VSEN = 0V ~ 1.0V - 0.3 0.4 V 7
V
t
DF0
t
DR0
OUT in the range of the VIN 0V to 1.0V when the VIN and the VSEN are short-circuited
SEN=VDF to the VOUT reaching 0.6V when the VSEN falls.
IN= VDF +VHYS to the VOUT reaching 5.4V when the VSEN rises.
-40 ℃ ≦ Ta ≦ 85℃
IN = 6.0V, VSEN = 6.0V→ 0.0V
V
IN = 6.0V, VSEN = 0.0V→ 6.0V
V
8/22
VIN = 1.0V - -0.30 -0.08
VIN = 6.0V
- -2.00 -0.70
0.20 -
-
0.20 0.40
- ±100 -
E-4
30 230
30 200
SEN.
mA 4
μA 3
ppm/
℃
MΩ
μs
μs
1
5
9
9
■VOLTAGE CHART
SYMBOL E-1 E-2 E-3 E-4
NOMINAL DETECT
DETECT VOLTAGE
VOLTAGE
VDF(T)
(V)
MIN. MAX. MIN. MAX. MIN. MAX. MIN. TYP.
0.8 0.770 0.830 0.015 0.066 0.008
0.9 0.870 0.930 0.017 0.074 0.009
1.0 0.970 1.030 0.019 0.082 0.010
1.1 1.070 1.130 0.021 0.090 0.011
1.2 1.170 1.230 0.023 0.098 0.012
1.3 1.270 1.330 0.025 0.106 0.013
1.4 1.370 1.430 0.027 0.114 0.014
1.5 1.470 1.530 0.029 0.122 0.015
1.6 1.568 1.632 0.031 0.131 0.016
1.7 1.666 1.734 0.033 0.085 0.017
1.8 1.764 1.836 0.035 0.147 0.018
1.9 1.862 1.938 0.037 0.155 0.019
2.0 1.960 2.040 0.039 0.163 0.020
2.1 2.058 2.142 0.041 0.171 0.021
2.2 2.156 2.244 0.043 0.180 0.022
2.3 2.254 2.346 0.045 0.188 0.023
2.4 2.352 2.448 0.047 0.196 0.024
2.5 2.450 2.550 0.049 0.204 0.026
2.6 2.548 2.652 0.051 0.212 0.027
2.7 2.646 2.754 0.053 0.220 0.028
2.8 2.744 2.856 0.055 0.228 0.029
2.9 2.842 2.958 0.057 0.237 0.030
3.0 2.940 3.060 0.059 0.245 0.031
3.1 3.038 3.162 0.061 0.253 0.032
3.2 3.136 3.264 0.063 0.261 0.033
3.3 3.234 3.366 0.065 0.269 0.034
3.4 3.332 3.468 0.067 0.277 0.035
3.5 3.430 3.570 0.069 0.286 0.036
3.6 3.528 3.672 0.071 0.294 0.037
3.7 3.626 3.774 0.073 0.302 0.038
3.8 3.724 3.876 0.074 0.310 0.039
3.9 3.822 3.978 0.076 0.318 0.040
4.0 3.920 4.080 0.078 0.326 0.041
4.1 4.018 4.182 0.080 0.335 0.042
4.2 4.116 4.284 0.082 0.343 0.043
4.3 4.214 4.386 0.084 0.351 0.044
4.4 4.312 4.488 0.086 0.359 0.045
4.5 4.410 4.590 0.088 0.367 0.046
4.6 4.508 4.692 0.090 0.375 0.047
4.7 4.606 4.794 0.092 0.384 0.048
4.8 4.704 4.896 0.094 0.392 0.049
4.9 4.802 4.998 0.096 0.400 0.050
NOTE:
5.0
*1: When V
When V
DF(T)≦1.4V, the detection accuracy is ±30mV.
DF(T)≧1.5V, the detection accuracy is ±2%.
4.900 5.100 0.098 0.408
(V)
(*1)
HYSTERESIS
RANGE
(V)
HYSTERESIS
RANGE
(V)
SENSE
RESISTANCE
(MΩ)
VDFVHYSVHYSRSEN
10 20
0
13 24
15 28
0.051
XC6108
Series
9/22
XC6108Series
■TEST CIRCUITS
Circuit 1
Circuit 2
Circuit 3
Circuit 4
Circuit 5
10/22
XC6108 Series
XC6108 Series
XC6108 Series
XC6108 Series
XC6108 Series
R=100kΩ
(No resistor needed for CMOS output products)
■TEST CIRCUITS (Continued)
Circuit 6
Circuit 7
XC6108 Series
XC6108
Series
(No resistor needed for CMOS output products)
XC6108 Series
Circuit 8
Circuit 9
XC6108 Series
(No resistor needed for CMOS output products)
Waveform Measurement Point
XC6108 Series
*No delay capacitance pin available in the XC6108xxxC/D series.
11/22
XC6108Series
■OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on page 14.
① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged
to the power supply input voltage, (V
reach the detect voltage (V
* If a pull-up resistor of the XC6108N series (N-ch open drain) is connected to added power supply different from the input
voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected.
② When the sense pin voltage keeps dropping and becomes equal to the detect voltage (V
(M1) for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An
inverter (Inv.1) operates as a comparator of the reference voltage VIN, and the output voltage changes into the “Low” level
(=V
SS). The detect delay time [tDF] is defined as time which ranges from VSEN=VDF to the VOUT of “Low” level
(especially, when the Cd pin is not connected: t
③ While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground
voltage (=V
SS) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to
reach the release voltage (V
④ When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor (M1) for
the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay
resistor (Rdelay). The inverter (Inv
Threshold: V
THL=VSS) while the sense pin voltage keeps higher than the detect voltage (VSEN > VDF).
⑤ While the delay capacitance pin voltage (V
sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC
series circuit. Assuming the time to the release delay time (tDR), it can be given by the formula (1).
DF) (VSEN>VDF), the output voltage (VOUT) keeps the “High” level (=VIN).
SEN< VDF +VHYS).
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin voltage is V
As an example, presuming that the delay capacitance is 0.68μF, t
* Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the
ground (=VSS) level because time described in ③ is short.
⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (V
(Inv.1) will be inverted. As a result, the output voltage changes into the “High” (=V
which ranges from V
⑦ While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the
delay capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=V
level.
SEN=VDF+VHYS to the VOUT of “High” level without connecting to the Cd.
IN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to
SEN =VDF), an N-ch transistor
DF0).
1) will operate as a comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic
.
CD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the
DR =
-
t
Rdelay×Cd×In (1-VTCD / VIN) …(1)
* In = a natural logarithm
IN /2 (TYP.)
tDR = Rdelay×Cd×0.69…(2)
*:Rdelay is 2.0MΩ(TYP.)
DR is :
2.0×10
6
×
0.68×10
-6
×
0.69=938(ms)
IN) level. tDR0 is defined as time
CD=VTCD), the inverter
IN)
12/22
■OPERATIONAL EXPLANATION (Continued)
●Function Chart
V
Cd
SEN
L
L
H
L
H
L
H
H
L
H
*1: VOUT transits from condition ① to ② because of the combination of VSEN and Cd.
●Example
ex. 1) V
ex. 2) V
●Release Delay Time Chart
DELAY CAPACITANCE [Cd]
ranges from ‘L’ to ‘H’ in case of VSEN = ‘H’ (VDR≧VSEN), Cd=’H’ (VTCD≧Cd) while VOUT is ‘L’.
OUT
maintains ‘H’ when Cd ranges from ‘H’ to ‘L’, VSEN=’H’ and Cd=’L’ when V
OUT
(μF)
TRANSITION OF V
①
L
H
L
H
RELEASE DELAY TIME [tDR]
(TYP.)
(ms)
0.010 13.8 11.0 ~ 16.6
0.022 30.4 24.3 ~ 36.4
0.047 64.9 51.9 ~ 77.8
0.100 138 110 ~ 166
0.220 304 243~ 364
0.470 649 519 ~ 778
1.000 1380 1100 ~ 1660
* The release delay time values above are calculated by using the formula (2).
*2: The release delay time (t
) is influenced by the delay capacitance Cd.
DR
CONDITION *1
OUT
⇒
⇒
⇒
⇒
②
L
L
H
becomes ‘H’ in ex.1.
OUT
RELEASE DELAY TIME [tDR] *2
(MIN. ~ MAX.)
(ms)
XC6108
Series
13/22
XC6108Series
■OPERATIONAL EXPLANATION (Continued)
Figure 1: Typical application circuit example
VIN
Figure 2: The timing chart of Figure 1
14/22
VIN
VSEN
VSEN
Cd
Cd
RSEN=R1+R2+R3
R1
R2
R3
Comparator
Vref
M5
M2
M4
R
delay
M1
Inverter
M3
VOUT
VSS
V
VDF+V
V
DF
*The XC6108N series (N-ch open
drain output) requires a pull-up
resistor for pulling up output.
(MIN.:0V, MAX.:6.0V)
SEN
HYS
VCD(MIN.:VSS, MAX.:VIN)
V
(MIN.:VSS, MAX:VIN)
OUT
V
TCD
XC6108
Series
■NOTES ON USE
1. Use this IC within the stated maximum ratings. Operation beyond these limits may cause degrading or permanent damage
to the device.
2. The power supply input pin voltage drops by the resistance between power supply and the V
at operation of the IC. At this time, the operation may be wrong if the power supply input pin voltage falls below the
minimum operating voltage range. In CMOS output, for output current, drops in the power supply input pin voltage
similarly occur. Moreover, in CMOS output, when the V
the circuit may occur if the drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis
voltage. Note it especially when you use the IC with the V
3. When the setting voltage is less than 1.0V, be sure to separate the V
1.0V to the V
4. Note that a rapid and high fluctuation of the power supply input pin voltage may cause a wrong operation.
5. Power supply noise may cause operational function errors, Care must be taken to put the capacitor between V
test on the board carefully.
6. When there is a possibility of which the power supply input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operation
with the delay capacitance pin (Cd) connected to a capacitor, use a schottky barrier diode connected between the V
and the Cd pin as the Figure 3 shown below.
6. In N channel open drain output, V
connected at the V
During detection : V
Vpull: Pull up voltage
R
(※1):On resistance of N channel driver M3 can be calculated as V
ON
For example, when (※2) R
Rpull= (Vpull /V
In this case, Rpull should be selected higher or equal to 18kΩ in order to keep the output voltage less than 0.1V during
detection.
During releasing:V
Vpull:Pull up voltage
For example:when Vpull = 6.0V and V
Rpull = (Vpull / V
In this case, Rpull should be selected smaller or equal to 25kΩ in order to obtain output voltage higher than 5.99V
during releasing.
Figure 3: Circuit example with the delay capacitance pin (Cd) connected to a schottky barrier diode
Figure 4: Circuit example of XC6108N Series
IN pin.
voltage at detect and release is determined by resistance of a pull up resistor
OUT
pin. Please choose proper resistance values with reffering to Figure 4;
OUT
= Vpull / (1+Rpull / RON)
OUT
= 0.5 / 0.8×10
ON
-1)×RON= (3 / 0.1-1)×625≒18kΩ
OUT
(※1) R
is bigger when VIN is smaller, be noted.
ON
(※2) For calculation, Minimum V
= Vpull / (1 + Rpull / Roff)
OUT
-3
= 625Ω(MIN.)at VIN=2.0V, Vpull = 3.0V and V
should be chosen among the input voltage range.
IN
Roff:On resistance of N channel driver M3 is 15MΩ(MIN.) when the driver is off (as to V
≧ 5.99V,
OUT
-1)×Roff = (6/5.99-1)×15×106 ≒25kΩ
OUT
IN pin and the sense pin are short-circuited and used, oscillation of
IN pin connected to a resistor.
IN pin and the sense pin, and to apply the voltage over
/ I
DS
from electrical characteristics,
OUT1
IN pin, and by through current
-GND and
IN
≦0.1V at detect,
OUT
/ I
LEAK
)
OUT
VSEN
VSENVIN
Cd
Cd
VIN
VOUT
VSS
R=100kΩ
(No resistor needed for
CMOS output products)
VOUT
VIN
VSEN
VSEN
VIN
M2
RSEN=R1+R2+R3
Comparator
R1
R2
Vref
M5
R3
Cd
Rdelay
Inverter
M1
ILEA
K
M3
Figure 3
NOTE: Roff=V
Figure 4
OUT/ILEAK
15/22
IN pin
Vpull
Rpull
VOUT
VSS
XC6108Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(1) Supply Current vs. Sense Voltage
2.0
1.5
1.0
0.5
Supply Current: ISS (μA)
Supply Current : ISS (μA)
0.0
0123456
(2) Supply Current vs. Input Voltage
1.2
1.0
0.8
0.6
0.4
0.2
SupplyCurrent: ISS (μA)
Supply Current : ISS (μA)
0.0
0123456
(3) Detect Voltage vs. Ambient Temperature (4) Detect Voltage vs. Input Voltage
2.55
2.50
Detect Voltage : VDF (V)
DetectVoltage: VDF (V)
2.45
-50-250255075100
16/22
XC6108C25AGR
VIN = 3.0V
Ta=85
℃
25
℃
-40
℃
Sense Voltage : VSEN (V)
Sense Voltage: VSEN(V)
XC6108C25AGR
VSEN=2.25V
Ta= 8 5
℃
25
℃
-40
℃
Input Voltage:VIN (V)
Input Voltage : VIN (V) Input Voltage : VIN (V)
Supply Current : ISS (μA)
1.2
1.0
0.8
0.6
0.4
0.2
SupplyCurrent: ISS (μA)
0.0
0123456
XC6108C25AGR
Ambient Temperature:Ta (℃)
Ambient Temperature : Ta (℃)
VIN= 4.0V
2.55
2.50
Detect Voltage: VDF (V)
Detect Voltage : VDF (V)
2.45
1.02.03.04.05.06.0
XC6108C25AGR
Input Voltage:VIN (V)
XC6108C25AGR
Input Voltage: VIN (V)
Input Voltage : VIN (V)
VSEN=2.75V
Ta= 8 5
Ta= 2 5
-40
85
-40
℃
℃
℃
25
℃
℃
℃
g
)
p
(
)
p
(
)
XC6108
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Hysteresis Voltage vs. Ambient Temperature (6) CD Pin Sink Current vs. Input Voltage
0.20
0.15
VHYS (V)
0.10
Hysteresis Voltage:
Hysteresis Voltage : VHYS (V)
0.05
-50-250255075100
(7) Output Voltage vs. Sense Voltage (8) Output Voltage vs. Input Voltage
7.0
6.0
5.0
4.0
3.0
2.0
1.0
Output Voltage : VOUT (V)
Output Voltage:VOUT (V)
0.0
-1.0
0123456
(9) Output Current vs. Input Voltage
4.0
3.5
3.0
mA
2.5
2.0
1.5
1.0
ut Current : IOUT
Output Current: IOUT (mA)
0.5
Out
0.0
0123456
XC6108C25AGR
Ambient Temperature : Ta (℃)
AmbientTemperature: Ta (℃)
XC6108C25AGR
VIN=6.0V
Sense Volta
Sense Voltage : VSEN (V)
XC6108C25AGR
InputVoltage: VIN (V)
Input Voltage : VIN (V)
e: VSEN(V
Ta= -40
VDS(N ch)=0.5V
℃
25
℃
85
VIN = 4.0V
Ta=25
4.0V
1.0V
℃
3.0
2.5
2.0
1.5
1.0
0.5
Cd PIN Sink Current: ICD (mA)
Cd PIN Sink Current : ICD (mA)
0.0
0123456
℃
4.0
3.0
2.0
1.0
0.0
Output Voltage : VOUT (V)
Output Voltage: VOUT(V)
-1.0
00.511.522.53
0.0
-0.5
mA
-1.0
-1.5
ut Current : IOUT
Output Current: IOUT (mA)
Out
-2.0
0123456
XC6108C25AGR
VSEN=0V, VDS=0.5V
Ta= -40
℃
25
℃
85
℃
InputVoltage: VIN (V)
Input Voltage : VIN (V)
XC6108N25AGR
VSEN=VIN Pull-up=VIN R=100k
Ta=8 5
℃
25
℃
-40
℃
Input Voltage : VIN (V)
Supply Voltage: VIN (V)
XC6108C25AGR
VDS(Pch)=0.5V
Ta= 85
25
℃
-40
Input Voltage: VIN (V)
Input Voltage : VIN (V)
Ω
℃
℃
17/22
XC6108Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(10) Delay Resistance vs. Ambient Temperature (11) Release Delay Time vs. Delay Capacitance
(12) Detect Delay Time vs. Delay Capacitance
(14) Leakage Current vs. Supply Voltage
3.5
)
Ω
2.5
(M
1.5
Delay Resistance : Rdelay (MΩ)
Delay Resistance: Rdelay
1000
s)
μ
100
Detect Delay Time: TDF(
Detect Delay Time : TDF (μs)
0.25
A)
μ
0.20
0.15
Leak Current: ILEAK (
0.10
XC6108C25AGR
VSEN=6.0V VCD=0.0V VIN=5.0V
4
3
2
1
-50-250255075100
Ambient Temperature : Ta (℃)
Ambient Temperature: Ta (℃)
XC6108C25AGR
VIN=6.0V
4.0V
3.0V
10
1.0V
1
0.00010.0010.010.11
Delay Capacitance:Cd (μF)
Delay Capacitance : Cd (μF)
XC6108N25AGR
VIN=VSEN=6.0V
01234 56
Output Voltage: VOUT (V)
18/22
2.0V
Ta=25
10000
1000
100
Release Delay time:TDR(ms)
Release Delay Time : TDR (ms)
(13) Leakage Current vs. Ambient Temperature
℃
A)
μ
Leak Carrent: ILEAK (
XC6108C25AGR
Ta=25
VIN=1.0V
3.0V
6.0V
10
1
0.1
0.00010.0010.010.11
0.25
0.20
0.15
0.10
-50-250255075100
TDR=Cd×2.0×106×0.69
Delay Capacitor: Cd (μF)
Delay Capacitance : Cd (μF)
XC6108N25AGR
VIN=VSEN=6.0V VOUT=6.0V
Ambient Temperature: Ta (℃)
℃
* Solderi
fill
r
f
■PACKAGING INFORMATION
●USP-4
ng
formed because the sides of the
pins are plated.
et su
●SOT-25
+0.1
0.4
-0.05
2.9±0.2
54
0~0.1
1
2
(0.95)
3
1.9±0.2
0.15
+0.1
-0.05
XC6108
Series
ace is not
19/22
XC6108Series
■PACKAGING INFORMATION (Continued)
●USP-4 Reference Pattern Layout
20/22
●USP-4 Reference Metal Mask Design
①②③
④
4
r
r
②
r
r
(
(
■MARKING RULE
●SOT-25
5
123
SOT-25
TOP VIEW)
●USP-4
1
2
USP-4
TOP VIEW)
③
① ②
④
4
3
XC6108
Series
① represents output configuration and integer number of detect voltage
CMOS Output (XC6108C Series) N-ch Open Drain Output (XC6108N Series)
MARK VOLTAGE (V) MARK VOLTAGE (V)
A 0.x K 0.x
B 1.x L 1.x
C 2.x M 2.x
D 3.x N 3.x
E 4.x P 4.x
F 5.x R 5.x
② represents decimal number of detect voltage
(ex.)
MARK VOLTAGE (V) PRODUCT SERIES
3 x.3 XC6108xx3xxx
0 x.0 XC6108xx0xxx
③ represents options
MARK
A
B
C
D
④
epresents production lot numbe
Built-in delay capacitance pin with hysteresis 5% (TYP.)
Built-in delay capacitance pin with hysteresis less than 1%
No built-in delay capacitance pin with hysteresis 5% (TYP.)
No built-in delay capacitance pin with hysteresis less than 1%
OPTIONS PRODUCT SERIES
(Standard)
(Standard)
(Semi-custom)
(Semi-custom)
XC6108xxxAxx
XC6108xxxBxx
XC6108xxxCxx
XC6108xxxDxx
0 to 9, A to Z or inverted characters of 0 to 9, A to Z repeated.
(G, I, J, O, Q, W excluded)
① represents output configuration and integer number of detect voltage
CMOS Output (XC6108C Series) N-ch Open Drain Output (XC6108N Series)
MARK VOLTAGE (V) MARK VOLTAGE (V)
A 0.x K 0.x
B 1.x L 1.x
C 2.x M 2.x
D 3.x N 3.x
E 4.x P 4.x
F 5.x R 5.x
represents decimal number of detect voltage
(ex.)
MARK VOLTAGE (V) PRODUCT SERIES
3 x.3 XC6108xx3xxx
0 x.0 XC6108xx0xxx
③ represents options
MARK OPTIONS
A
B
C
D
④
epresents production lot numbe
Built-in delay capacitance pin with hysteresis 5% (TYP.)
(Standard)
Built-in delay capacitance pin with hysteresis less than 1%
(Standard)
No built-in delay capacitance pin with hysteresis 5% (TYP.)
(Semi-custom)
No built-in delay capacitance pin with hysteresis less than 1%
(Semi-custom)
0 to 9, A to Z repeated. (G, I, J, O, Q, W excluded)
*No character inversion used.
PRODUCT
SERIES
XC6108xxxAxx
XC6108xxxBxx
XC6108xxxCxx
XC6108xxxDxx
21/22
XC6108Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics. Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.