TOREX XC6101, XC6105, XC6111, XC6117 User Manual

r

XC6101~XC6105, XC6111~XC6117

Series

ETR0207_016

Voltage Detector (VDF=1.6V~5.0V)

■GENERAL DESCRIPTION

The XC6101~XC6105, XC6111~XC6117 series are groups of high-precision, low current consumption voltage detectors with
manual reset input and watchdog functions incorporating CMOS process technology. The series consist of a reference
voltage source, delay circuit, comparator, and output driver. With the built-in delay circuit, the XC6101 ~ XC6105, XC6111 ~
XC6117 series do not require any external components to output signals with release delay time. Moreover, with the manual
reset function, reset can be asserted at any time. The ICs produce two types of output; V
(high when detected). With the XC6101 ~ XC6105, XC6111 ~ XC6115 series, the WD pin can be left open if the watchdog



function is not used. Whenever the watchdog pin is opened, the internal counter clears before the watchdog timeout occurs.
Since the manual reset pin is internally pulled up to the V
pin unconnected if the pin is unused. The detect voltages are internally fixed 1.6V ~ 5.0V in increments of 0.1V, using laser
trimming technology. Six watchdog timeout periods are available in a range from 6.25ms to 1.6s. Seven release delay times
are available in a range from 3.13ms to 1.6s.

■APPLICATIONS

●Microprocessor reset circuits

●Memory battery backup circuits

●System power-on reset circuits

●Power failure detection

■TYPICAL APPLICATION CIRCUIT

VIN

* Not necessary with CMOS output products.

XC6101/XC6102

VIN

MRB

VSS

RESETB

WD

Rpull

＊

VIN

RESETB
INPUT

I/O

IN pin voltage level, the ICs can be used by leaving the manual reset

■FEATURES

Detect Voltage Range : 1.6V ~ 5.0V, +2%
Hysteresis Width : V
V

Operating Voltage Range : 1.0V ~ 6.0V
Detect Voltage Temperature
Coefficient
Output Configuration : N-channel open drain,

Reset Output Options : V
Watchdog Function : Watchdog input WD;

Manual Reset Function : Manual Reset Input MRB;

Release Delay Time : 1.6s, 400ms, 200ms, 100ms,
Watchdog Timeout Period : 1.6s, 400ms, 200ms, 100ms,

Operating Ambient Tempera ture
Packages
Environmentally Friendly

■TYPICAL PERFORMANCE
CHARACTERISTICS

μP

VSS

●Supply Current vs. Input Voltage

30

25

20

ISS (μA)

15

10

Supply Current:

5

0

0123456

* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)

DFL (low when detected) and VDFH

(0.1V increments)

x 5%, TYP.

DF

(XC6101~XC6105)

x 0.1%, TYP.

DF

(XC6111~XC6117)

: +

100ppm/OC (TYP.)

CMOS

(Low when detected)

DFL

V

(High when detected)

DFH

If it remains ether high or low fo
the duration of the watchdog
timeout period, a reset is
asserted.

When it changes from high to

low, a reset is asserted.

50ms, 25ms, 3.13ms (TYP.)

50ms, 6.25ms (TYP.)

:

-40℃～+85℃

: SOT-25, USP-6C
: EU RoHS Compliant, Pb Free

XC61X1~ XC61X5 (2.7V)

Ta= 25

℃

Input Voltage:　VIN (V)

Ta= 85

Ta= -40

℃

℃

1/27

XC6101~XC6105, XC6111~XC6117 Series

■PIN CONFIGURATION

●SOT-25

XC6101, XC6102 Series
XC6111, XC6112 Series

IN

V

5

WD

4

123

RESETB

MRB

SS

V

SOT-25 (TOP VIEW)

●USP-6C

XC6101, XC6102 Series
XC6111, XC6112 Series

V

V

RESETB

IN

SS

6

5

4

1

2

3

WD

MRB

NC

USP-6C (BOTTOM VIEW)

* The dissipation pad for the USP-6C package should be

solder-plated in reference mount pattern and metal masking
so as to enhance mounting strength and heat release. If
the pad needs to be connected to other pins, it should be
connected to the V

SS (No.5) pin.

■PIN ASSIGNMENT

XC6101, XC6102 XC6103 XC6104, XC6105

XC6111, XC6112 XC6113 XC6114, XC6115
SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C

1 4 - - 1 4 1 4

2 5 2 5 2 5 2 5

3 2 3 2 - - 4 1 MRB Manual Reset

4 1 4 1 4 1 - - WD Watchdog

5 6 5 6 5 6 5 6 VIN Power Input

- - 1 4 3 2 3 2 RESET

2/27

XC6103 & XC6113 Series

XC6104, XC6105 Series
XC6114, XC6115 Series

IN

V

5

123

RESET

SOT-25 (TOP VIEW)

XC6103 & XC6113 Series

WD

4

MRB

SS

V

IN

V

5

123

RESETB

SS

V

RESET

SOT-25 (TOP VIEW)

XC6104, XC6105 Series
XC6114, XC6115 Series

V

IN

V

SS

RESET

6

5

4

1

2

3

WD

MRB

NC

V

V

RESETB

IN

6

SS

5

USP-6C (BOTTOM VIEW) USP-6C (BOTTOM VIEW)

PIN NUMBER

XC6116, XC6117

PIN NAME FUNCTION

RESETB

V

SS Ground

XC6116, XC6117 Series

IN

WD

4

V

5

123

RESETB

SOT-25 (TOP VIEW)

XC6116, XC6117 Series

WD

1

RESET

2

34

NC

V

IN

V

SS

RESETB

6

5

4

USP-6C (BOTTOM VIEW)

Reset Output

DFL: Low Level When Detected)

(V

Reset Output

DFH: High Level When Detected)

(V

V

SS

RESET

MRB

4

MRB

1

2

RESET

NC

3

XC6101 ~ XC6105, XC6111~ XC6117

■PRODUCT CLASSIFICATION

●Selection Guide

SERIES WATCHDOG

MANUAL

RESET

VDFL (RESETB) VDFH (RESET)

XC6101 XC6111 Available Available CMOS -

XC6102 XC6112 Available Available N-channel open drain -

XC6103 XC6113 Available Available - CMOS

XC6104 XC6114 Available Not Available CMOS CMOS

XC6105 XC6115 Available Not Available N-channel open drain CMOS

XC6116 Not Available Available CMOS CMOS

XC6117 Not Available Available N-channel open drain CMOS

●Ordering Information

XC61①②③④⑤⑥⑦⑧-⑨

(*1)

DESIGNATOR ITEM SYMBOL DESCRIPTION

① Hysteresis Width

②

Functions and

Type of Reset Output

0 VDF x 5% (TYP.) with hysteresis

1 V

x 0.1% (TYP.) without hysteresis

DF

Watchdog and manual functions, and reset

1 ~ 7

output type as per Selection Guide in the above

chart

A 3.13ms (TYP.)

B 25ms (TYP.)

C 50ms (TYP.)

③ Release Delay Time *

D 100ms (TYP.)

E 200ms (TYP.)

F 400ms (TYP.)

H 1.6s (TYP.)

0

No WD timeout period for

XC6116, XC6117 Series

1 6.25ms (TYP.)

④ Watchdog Timeout Period

2 50ms (TYP.)

3 100ms (TYP.)

4 200ms (TYP.)

5 400ms (TYP.)

6 1.6s (TYP.)

⑤⑥ Detect Voltage 16 ~ 50

MR

⑦⑧-⑨ Packages (Order Unit)

MR-G

ER

ER-G

* Please set the release delay time shorter than or equal to the watchdog timeout period.

ex.) XC6101D427MR or XC6101D327MR

(*1)

The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant.

Detect voltage
ex.) 4.5V: ⑤⇒4, ⑥⇒5

SOT-25 (3,000/Reel)

SOT-25 (3,000/Reel)

USP-6C (3,000/Reel)

USP-6C (3,000/Reel)

RESET OUTPUT

Series

3/27

,

,

XC6101~XC6105, XC6111~XC6117 Series

■BLOCK DIAGRAMS

●XC6101, XC6111 S er ies

●XC6102

●XC6103

4/27

XC6112 Series

XC6113 Series

,

,

■BLOCK DIAGRAMS (Continued)

●XC6104

●XC6105

●XC6116 Series

●XC6117 Series

XC6114 Series

XC6115 Series

XC6101 ~ XC6105, XC6111~ XC6117

Series

5/27

XC6101~XC6105, XC6111~XC6117 Series

■ABSOLUTE MAXIMUM RATINGS

PAR AMETER SYMBOL RATINGS UNITS

Input Voltage

Ta = 2 5OC

VIN VSS -0.3 ~ 7.0 V

V

V

MRB

VSS -0.3 ~ 7.0 V

V

WD

-0.3～VIN+0.3≦7.0

SS

V

Output Voltage

Power Dissipation

Output Current I

CMOS Output V

N-ch Open Drain Output V

RBOUT/IROUT

RESETB/VRESET

RESETB

20 mA

V

-0.3～VIN+0.3≦7.0

SS

VSS -0.3 ~ 7.0

SOT-25 250

Pd

USP-6C

100

Operating Ambient Temperature Topr -40 ~ +85

Storage Temperature Tstg -40 ~ +125

V

mW

O

C

O

C

6/27

XC6101 ~ XC6105, XC6111~ XC6117

■ELECTRICAL CHARACTERISTICS

●XC6101~XC6105, XC6111~XC6117 Series

PAR AMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS

Detect Voltage

Hysteresis Width

XC6101~XC6105

Hysteresis Width

XC6111~XC6117

(*3)

(*4)

Supply Current ISS

VDFL

VDFH

VHYS

VHYS 0

XC6101~XC6105
XC6111~XC6115

(The MRB & the WD Pin:

No connection)

XC6116/XC6117

(The MRB Pin:

No connection)

VIN=VDF(T)×0.9V - 5 11

VIN=VDF(T)×1.1V - 10 16

IN=6.0V - 12 18

V

VIN=VDF(T)×0.9V - 4 10

VIN=VDF(T)×1.1V - 8 14

IN=6.0V - 10 16

V

VDF(T)

× 0.98

VDF
× 0.02

(*1)

(*2)

VDF(T)

VDF

× 0.05

VDF

× 0.001

VDF(T)

× 1.02

VDF

× 0.08

VDF

x 0.01

Operating Voltage VIN 1.0 - 6.0 V ①

VIN=1.0V 0.15 0.5 -

VIN=2.0V (VDFL(T)> 2.0V) 2.0 2.5 -

VIN=3.0V (VDFL(T) >3.0V) 3.0 3.5 -

V

IN=4.0V (VDFL(T) >4.0V) 3.5 4.0 -

VDFL

Output Current

(RESETB)

N-ch.

VDS = 0.5V

IRBOUT

CMOS,

VIN=6.0V - - 1.1 -0.8

VIN=6.0V 4.4 4.9 - ③

VIN=1.0V - - 0.08 - 0.02

IN=4.0V (VDFH(T)>4.0V) - - 0.95 - 0.75

O

C - +100 - ppm/ OC ①

VDFH

Output Current

(RESET)

Temperature

Coefficient

IROUT

△VDF /

(△To pr・V

DFL

)

P-ch

DS = 0.5V

V

N-ch

VDS = 0.5V

P-ch.

DS = 0.5V

V

-40OC < Topr < 85

VIN=2.0V (VDFH(T)> 2.0V) - - 0.50 - 0.30

VIN=3.0V (VDFH(T)>3.0V) - - 0.75 - 0.55

V

2 3.13 5

18 25 31

Release Delay Time

(VDF<1.8V)

tDR

Time until VIN is increased from

1.0V to 2.0V

and attains to the release time level,

and the Reset output pin inverts.

37 50 63

75 100 125

150 200 250

300 400 500

1200 1600 2000

2 3.13 5

18 25 31

Release Delay Time

(VDF>1.9V)

tDR

Time until VIN is increased from

1.0V to (VDFx1.1V)

and attains to the release time level,

and the Reset output pin inverts.

37 50 63

75 100 125

150 200 250
300 400 500

1200 1600 2000

Time until VIN is decreased from 6.0V to

Detect Delay Time tDF

1.0V and attains to the detect voltage

level, and the Reset output pin detects

- 3 30 μs ⑤

while the WD pin left opened.

V

DFL

Leakage

Current

CMOS

Output

V
CMOS
Output

V

DFL

N-ch Open

Drain

DFH

Nch

I

LEAK

V

V

V

IN=VDFL

=6V, V

IN

=6V, V

IN

×0.9V, V

=0V

RESET

RESETB

RESETB

=6V

=0V

-0.01

0.01 0.1

Output

Ta = 2 5OC

V ①

V ①

V ①

μA ②

mA

mA

ms ⑤

ms ⑤

μA

Series

CIRCUIT

③

④

④

③

7/27

XC6101~XC6105, XC6111~XC6117 Series

■ELECTRICAL CHARACTERISTICS (Continued)

●XC6101~XC6105, XC6111~XC6117 Series

PAR AMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CIRCUIT

Watchdog

Timeout Period

(V

DF<1.8V)

tWD

Watchdog

Timeout Period

(V

DF>1.9V)

Watchdog

Minimum Pulse Width

Watchdog

High Level Voltage

Watchdog

Low Level Voltage

Watchdog

Input Current

Watchdog

Input Resistance

●XC6101 ~ XC6103, XC6111 ~ XC6113, XC6116 , XC6117 Series

tWD

t

WDIN

VIN=VDF x 1.1V ~ 6.0V VIN x 0.7 - 6 V ⑦

V

WDH

V

VIN=VDF x 1.1V ~ 6.0V 0 - VIN x 0.3 V ⑦

WDL

I

WD

RWD VIN=6.0V, VWD=0V, RWD=VIN/ |IWD| 315 500 880 k ⑧

Time until V

the Reset output pin is released to go into

the detection state. (V

Time until V

and the Reset output pin is released to go

into the detection state. (VWD=VSS)

Apply pulse from 6.0V to 0V

VIN=6.0V, VWD=6.0V (Avg. when peak ) - 12 19

VIN=6.0V, VWD=0V (Avg. when peak)

PAR AMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNITS CIRCUIT

MRB

High Level Voltage

MRB

Low Level Voltage

MRB

Pull-up Resistance

MRB Minimum
Pulse Width

(*5)

XC6101~XC6105

V

MRH VIN=VDFx1.1V ~ 6.0V 1.4 - VIN ⑨

V

MRL VIN=VDFx1.1V ~ 6.0V 0 - 0.35

MR VIN=6.0V, MRB=0V, RMR=VIN/ |IMRB| 1.6 2.4 3.0 M ⑩

R

t

MRIN

Apply pulse from 6.0V to 0V to

XC6111~XC6115

MRB Minimum
Pulse Width

(*6)

t

MRIN

Apply pulse from 6.0V to 0V to

XC6116, XC6117

NOTE:

*1: V

*2: If only “V

DF(T): Setting detect voltage

DF” is indicated, it represents both VDFL (low when detected) and VDFH (high when detected).

*3: XC6101~XC6105 (with hysteresis)
*4: XC6111~XC6117 (without hysteresis)
*5: Watchdog function is available.
*6: Watchdog function is not available.

IN increases form

1.0V to 2.0V and

IN increases form

1.0V to (V

DFx1.1V)

IN=6.0V,

V

to the WD pin.

IN=6.0V,

V

the MRB pin

V

IN=6.0V,

the MRB pin

WD=VSS

)

Ta = 2 5OC

4.25 6.25 8.25

37 50 63

75 100 125

150 200 250

ms ⑥

300 400 500

1200 1600 2000

4.25 6.25 8.25
37 50 63
75 100 125

150 200 250

ms ⑥

300 400 500

1200 1600 2000

300 - - ns ⑦

μ

- 19 -12 -

A ⑧

Ta = 2 5

V

2.8 - -

μs ⑪

1.2 - -

⑨

O

C

8/27

XC6101 ~ XC6105, XC6111~ XC6117

Series

■OPERATIONAL EXPLANATION

The XC6101~XC6105, XC6111~XC6117 series compare, using the amplifier, the voltage of the internal voltage reference
source with the voltage divided by R1, R2 and R3 connected to the V
amplifier activates the watchdog logic, manual reset logic, delay circuit and the output driver. When the VIN pin voltage
gradually falls and finally reaches the detect voltage, the RESETB pin output goes from high to low in the case of the VDFL type
ICs, and the RESET pin output goes from low to high in the case of the V

<RESETB / RESET Pin Output Signal>

DFL (RESETB) type - output signal: Low when detected.

* V
The RESETB pin output goes from high to low whenever the VIN pin voltage falls below the detect voltage, or whenever the
MRB pin is driven from high to low. The RESETB pin remains low for the release delay time (tDR) after the VIN pin voltage
reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period,
the RESETB pin output remains low for the release delay time (t

DFH (RESET) type – output signal: High when detected.

* V
The RESET pin output goes from low to high whenever the VIN pin voltage falls below the detect voltage, or whenever the
MRB pin is driven from high to low. The RESET pin remains high for the release delay time (tDR) after the VIN pin voltage
reaches the release voltage. If neither rising nor falling signals are applied to the WD pin within the watchdog timeout period,

OUT pin output remains high for the release delay time (tDR), and thereafter the RESET pin outputs low level signal.

the V

<Hysteresis>
When the internal comparator output is high, the N-Channel transistor connected in parallel to R3 is turned ON, activating the
hysteresis circuit. The difference between the release and detect voltages represents the hysteresis width, as shown by the
following calculations:

DF (detect voltage) = (R1+R2+R3) x Vref(R2+R3)

V
VDR (release voltage) = (R1+R2) x Vref(R2)

HYS (hysteresis width)=VDR-VDF (V)

V

VDR > VDF
* Detect voltage (VDF) includes conditions of both VDFL (low when detected) and VDFH (high when detected).
* Please refer to the block diagr ams for R1, R2, R3 and Vref.

Hysteresis width is selectable from V

<Watchdog (WD) Pin>
The XC6101~XC6105, XC6111~XC6117 series use a watchdog timer to detect malfunction or “runaway” of the
microprocessor. If neither rising nor falling signals are applied from the microprocessor within the watchdog timeout period,
the RESETB/RESET pin output maintains the detection state for the release delay time (t
RESET/RESETB pin output returns to the release state (Please refer to the FUNCTION CHART). The timer in the watchdog
is then restarted. Six watchdog timeout period settings are available in 1.6s, 400ms, 200ms, 100ms, 50ms, 6.25ms.

<MRB Pin>
Using the MRB voltage pin input, the RESET/RESETB pin signal can be forced to the detection state. When the MRB pin is
driven from high to low, the RESETB pin output goes from high to low level signal in the case of the V
RESET pin output goes from low to high in the case of the V
RESET/RESETB pin output maintains the detection state for the release delay time (t
pulled up to the V
which is an input protection element, is connected between the MRB pin and VIN pin. Therefore, if the MRB pin is applied
voltage that exceeds VIN, the current will flow to VIN through the diode. Please use this IC within the stated maximum ratings

-0.3～VIN+0.3≦7.0V) on the MRB pin.

(V

SS

<Release Delay Time>
Release delay time (t
timeout period expires with no rising signal applied to the WD pin, until the RESET/RESETB pin output is released from the
detection state. Seven release delay time (t
100ms, 50ms, 25ms, 3.13ms.

<Detect Delay Time>
Detect Delay Time (t
RESETB pin output goes into the detection state.

IN pin voltage level, leave the MRB pin open if unused (Please refer to the FUNCTION CHART). A diode,

DR) is the time that elapses from when the VIN pin reaches the release voltage, or when the watchdog

DF) is the time that elapses from when the VIN pin voltage falls to the detect voltage until the RESET/

DF x 0.05V (XC6101~XC6105) or VDF x 0.001V (XC6111~XC6117).

) watchdog timeout period settings are available in 1.6s, 400ms, 200ms,

WD

DR), and thereafter the RESET pin outputs high level signal.

DFH type. Even after the MRB pin is driven back high, the

IN pin. The resulting output signal from the error

DFH type ICs.

DR), and thereafter the

DFL type ICs, and the

DR). Since the MRB pin is internally

9/27