PLL Clock Generator ICs with Built-In Divider/Multiplier Circuits
(For Low Frequency Range)
GENERAL DESCRIPTIO N
The XC25BS5 series are high frequency, low power consumption PLL clock generator ICs with divider circuit & multiplier
PLL circuit.
Laser trimming gives the option of being able to select from divider ratios (M) of 1,3 to 2047 and multiplier ratios (N) of 6 to
2047.
Output frequency (Q0) is equal to reference oscillation (fCLKin) multiplied by N/M, within a range of 3MHz to 30MHz. Q1
output is selectable from input reference frequency (f0), input reference freque ncy/2 (f0/2) , ground (GND), and comparative
frequency (f0/M). Further, comparative frequencies, within a range of 12KHz to 500KHz, can be obtained by dividing the
reference oscillation. By halting operation via the CE pin, consumption current can be controlled and output will be o ne of
high-impedance.
■APPLICATIONS
●Crystal oscillation modules
●Personal computers
●PDAs
●Portable audio systems
●Various system clocks
PIN CONFIGURATION
SOT-26
(TOP VIEW)
*The dissipation pad for the USP-6B package
should be solder-plated in recommended mount
pattern and metal masking so as to enhance
mounting strength and heat release.
If the pad needs to be connected to other pins,
it should be connected to the V
FUNCTION LIST
C E FUNCTION
●CE, Q0/Q1 Pin Function
"H"Q0, Q1 Clock Output
"L"Stand-by. Output Pin = High Impedance
Open
Stand-by. Output Pin = High Impedance
(V
SS Pin Pull-Down Due to IC's Internal Resistor)
Q1 6
VDD 5
CLKin4
USP-6B
(BOTTOM VIEW)
1 Q0
2 VSS
3 CE
DD pin.
FEATURES
Output Frequency : 3MHz ~ 30MHz (Q0=fCLKin×N/M)
Input Frequency (fCLKin)
: 12kHz ~ 35MHz
Divider Ratio (M) :
Multiplier Ratio (N) :
Output : 3-State
Operating Voltage Range
: 2.97V ~ 5.5V
Low Power Consumption
: CMOS (stand-by function included)*1
Comparative Frequency
: 12kHz~500kHz
Package
Environmentally Friendly
Selectable from divisions of 1, 3~2047
Selectable from multiplications of 6~2047