TMI TAMARACK TC9021A, TC9020A Datasheet

TC9021A/TC9020A

-1-

e-mail: [e-mail]

website: www.tmi.com.tw

Gigabit Ethernet Controller with integrated PHY

Features

l IEEE 802.1p, 802.1Q, 802.3x, 802.3z compliant
l PCI Specification Revision 2.2 compliant
l Fully integrated IEEE 802.3 compliant 1000BASE-T,

100BASE-TX and 10BASE-T port triple speed, half/full
duplex operation

l 32/64-bit, 33/66MHz bus support – TC9021A

32-bit, 33Mhz bus support – TC9020A

l Automatic MDI crossover function for 10/100/1000

Mbps modes operation

l Direct drive PHY LED support
l Supports low cost 25 MHz external clock source
l IP, TCP, UDP checksum calculation/verification

l 802.3 MIB & RMON MIB statistic register sets
l Transmit "interrupt -less" mode of operation
l Provides a variety of flexible receive filtering modes,

including VLAN, IP multicast, and hash table

l VLAN tag insertion/removal, frame filtering.
l Symmetrical and asymmetrical 802.x flow control

support

l Jumbo frame support
l ACPI and WakeOnLAN support
l 1.8/2.5/3.3V CMOS with 5V tolerant I/O
l 276-pin PBGA (27 X 27mm)

Functional Description

TC9021A/TC9020A are part of a new generation of high perform ance, host-optimized network interface cards designed for
mission critical systems such as servers and high-end workstations. Offering two gigabits per second of aggregate
bandwidth, the TC9021A/TC9020A optimizes performance while minimizing network overhead on the host system.
Compared to leading Fast Ethernet solutions, the TC9021A/TC9020A transfers data at less than one tenth of the host CPU
utilization rate.

IEEE 802.3z Gigabit Ethernet MAC

The TC9021A/TC9020 implements IEEE 802.3z half duplex functions such as Carrier Extension and Packet Bursting. In
full duplex mode, the TC9021A/TC9020A implements both symmetrical and asymmetrical flow control via IEEE 802.3x
PAUSE MAC Control frames. PAUSE frames can be automatically generated by the TC9021A/TC9020A according to
programmable flow control thresholds within the on -chip receive FIFO. The TC9021A/TC9020A MAC has been carefully
implemented to ensure full wire speed at 1Gbps with 96 -bit transmit and 64-bit receive inter-frame spacing.

Integrated 10BASE-T/100BASE-TX/1000BASE-T PHY

The TC9021A contains a triple-speed Ethernet Transceiver as the physical layer device for Ethernet
1000BASE-T/100BASE-TX/10BASE-T applications. It includes all the active circuitry required to implement the physical
layer functions to transmit and receive data on standard CAT 5 unshielded twisted pair cable. The triple -speed Phy uses
advanced mixed-signal processing to perform equalization, echo and cross-talk cancellation, data recovery, and error
correction at a gigabit per second data rate, to achieve robust performance in noisy environments with low power
dissipation.

32/64-bit, 33/66MHz PCI Bus

The TC9021A/TC9020A can operate in systems utilizing a 32-bit or 64-bit wide PCI bus running at 33MHz or 66 MHz. The
TC9021A/TC9020A is compliant with PCI specification revision 2.2, and is capable of accessing up to 1 terabytes of
system memory via the PCI Dual Address Cycle (DAC) command. Advanced PCI commands, such as Write and Invalidate,
Read Line, and Read Multiple, are also implemented to further improve sys-tem performance.

Bus Master Dual Channel DMA

The TC9021A/TC9020A implements independent scatter/gather DMA engines to support full duplex Gigabit Ethernet
connectivity. These two DMA engines are capable of accessing data on any byte boundary and moving data to and from
discontinuous memory locations. This capability eliminates CPU-intensive data copying. Furthermore, each DMA engine
has been carefully designed to sustain well over 1 gigabit per second of throughput across a PCI bus. This ensures that
the TC9021 will not be a bottleneck in high performance data networking applications.

TC9021A/TC9020A

-2-

e-mail: [e-mail]

website: www.tmi.com.tw

Gigabit Ethernet Controller with integrated PHY

Protocol Offloading

The TC9021A/TC9020A also off-loads network protocol tasks from the host CPU. It generates TCP, UDP and IP
checksum values for outgoing frames and verifies the checksum value on incoming frames. Ethernet MAC frame CRC
calculation is also implemented on -chip.

Interrupt Coalescence

While receiving frames, the TC9021A/TC9020A can be configured to operate with adaptive interrupts to maximize the host
CPU efficiency. For heavy traffic, the TC9021A/TC9020A issues a single interrupt for a series of back-to-back receive
frames which reduces CPU interrupt overhead significantly. For light traffic, the TC9021A/TC9020A issues an interrupt
when a frame arrives to minimize the latency. On the transmit side, the frequency of interrupt is programmable on a
frame-by-frame basis. An “interrupt-less’ transmit operation is provided to further reduce interrupt to the host CPU.

IEEE 802.1p Priority Support

The TC9021A/TC9020A supports transmit packet priority queuing, allowing the host to insert higher priority frames into the
front of the transmit queue for lower latency transfer. The TC9021A/TC9020A also examines the IEEE standard priority
field of appropriately tagged receive frames and generates a host system interrupt according to a user programmable
priority threshold. This mechanism provides immediate notification to the host of high priority fr ame arrivals.

IEEE 802.1Q VLAN Support

The TC9021A/TC9020A can be programmed to insert VLAN tags automatically into outgoing frames on a global or
individual frame basis. On the receive side, the TC9021A/TC9020A examines all incoming frames for 802.1Q compliant
VLAN tags. Once a VLAN tag is detected, the TC9021A/TC9020A will optionally remove the VLAN tag before uploading
the frame into system memory. The TC9021A/TC9020A also offers a receive filtering mode based on either a VLAN ID
exact or hashed match.

Jumbo Frame Support

The TC9021A/TC9020A can be configured to use a maximum frame size of up to 9,018 bytes. This Jumbo Frame size
reduces packet processing overhead on the host CPU by as much as 85 percent. In systems that are CPU bound, it can
provide for layer 4 throughput increases of greater than 100%.

Network Management

The TC9021A/TC9020A includes management statistic counters based on IEEE 802.3 MIB and IETF RMON statistic
register sets, allowing the programmer implementing the network management.

Power Management

The TC9021A/TC9020A is fully compliant with PCI Power Management v1.1 and ACPI Power Management specification
v1.0. It implements multiple wakeup events including Wakeup Packets, Magic Packets, and Link Status change.
The TC9021A/TC9020A also supports legacy Wake-On-LAN and Magic Packet power management mechanisms.