THAT Corporation; 45 Sumner St., Milford, Massachusetts; 01757-1656; USA
Tel: +1 (508) 478-9200; Fax: +1 (508) 478-0990; Web: www.thatcorp.com
THAT
Corporation
1
2
3
4
5
6
7
SUB
NC
8
9
10
11
12
13
14
Q2
Q1
Q4
Q3
Figure 1. Pin
Configuration
0.750±0.004
(19.05±0.10)
0.25±.004
(6.35±0.10)
0.32 Max.
(8.13)
0.060
(1.52)
0.075
(1.91)
0.10 Typ.
(2.54)
0.018
(0.46)
0.125±0.004
(3.18±0.10)
Typ.
1
0.010
(0.25)
Figure 2. Dual-In-Line Package Outline
Quad Low-Noise
NPN Transistor Array
THAT100
FEATURES
•
Four Matched NPN Transistors
•
Low noise — 0.8
nV
Hz
•
High Speed — 350 MHz f
t
•
Excellent Matching — 500 µVtyp
•
Dielectrically Isolated
•
25VV
CEO
APPLICATIONS
•
Microphone Preamplifiers
•
Tape Head Preamplifiers
•
Current Sources
•
Current Mirrors
•
Log/Antilog Amplifiers
•
Multipliers
DESCRIPTION
THAT100 is a quad, large-geometry monolithic
NPN transistor array which combines low noise, high
speed and excellent parametric matching. The large
geometry typically results in 30Ω base spreading re-
sistance, producing 0.8
nV Hz
voltage noise. This
makes these parts an excellent choice for low-noise
amplifier input stages.
Fabricated on a Complementary Bipolar Dielec-
trically Isolated process, all four transistors are elec-
trically isolated from each other by a layer of oxide.
The resulting low collector-to-substrate capacitance
produces a typical f
t
of 350 MHz, for AC perfor-
mance similar to 2N3904-class devices. The dielec-
tric isolation also minimizes crosstalk and provides
complete DC isolation.
Substrate biasing is not required for normal op-
eration, though the substrate should be grounded to
optimize speed. The one-chip construction assures
excellent parameter matching and tracking over
temperature.
0.050
(1.27)
Typ
0.245
(6.2)
Max
0.157
(3.99)
Max
0.018 (0.46)
Max
0.344 (8.74)
Max
0.069
(1.75)
Max
0.010
(0.25)
Max
1
Figure 3. Surface Mount Package Outline