Texas Instruments Incorporated AN-2150 User's Guide

1 Introduction

The LM3450A evaluation board is designed to provide an AC to LED solution for a 30W LED load. Specifically, it takes an AC mains input and converts it to a constant current output of 700mA for a series string of 1 to 13 LEDs (maximum LED stack voltage of 45V). There are two assembly versions designed to operate from two different nominal AC input voltages, 120VACor 230VAC. .

The board employs a two stage design with an LM3450A flyback primary stage and an LM3409HV secondary stage. The LM3450A provides an isolated 50V regulated output voltage and a power factor corrected input current. The LM3409HV uses the 50V flyback output as its input and provides a constant current of 700mA to the LED load. This two stage design provides excellent line and load regulation as well as isolation. The board is comprised of two copper layers with components on both sides and an FR4 dielelctric.

The two-stage design has several key advantages over a single stage design including:

• No 120Hz LED current ripple

• Better dimming performance at low dimming levels.

• Better line disturbance rejection

• Better efficiency using small LED stack voltages

User's Guide

SNVA485B–June 2011–Revised May 2013

AN-2150 LM3450A Evaluation Board

2 Specifications

120VAC30W Version

• Input Voltage Range: VIN= 90VAC– 135V

• Regulated Flyback Output Voltage: V

• Maximum LED Stack Voltage: V

• Regulated LED Current: I

230VAC30W Version

• Input Voltage Range: VIN= 180VAC– 265V

• Regulated Flyback Output Voltage: V

• Maximum LED Stack Voltage: V

• Regulated LED Current: I

= 700mA

LED

= 700mA

LED

OUT

< 45V

OUT

< 45V

= 50V

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ZCD

GATE

LM3450A

GND

COMP

HOLD

DIM

FLT2

FLT1

PWM

BIAS

RETURN

OPTICAL

ISOLATION

RETURN

EMI FILTER

PWM

INPUT

LED

LOAD

SEN

REF

ADJ

HOLD

LM3409HV LED Driver

Specifications

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Figure 1. Schematic

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OUT

(W)

1.00

0.98

0.96

0.94

0.92 16 20 24 28 32

100 V

120 V

OUT

(W)

1.00

0.98

0.96

0.94

0.92 16 20 24 28 32

200 V

230 V

OUT

(W)

EFFICIENCY (%)

16 20 24 28 32

100 V

120 V

OUT

(W)

EFFICIENCY (%)

16 20 24 28 32

200 V

230 V

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3 Typical Performance

Figure 2. 120V, 30W Version Figure 3. 230V, 30W Version Efficiency vs. Output Power Efficiency vs. Output Power

Typical Performance

Figure 4. 120V, 30W Version Figure 5. 230V, 30W Version

Power Factor vs. Output Power Power Factor vs. Output Power

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100

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

AMPLITUDE (mA)

HARMONIC NUMBER

Limits

Measured

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

AMPLITUDE (mA)

HARMONIC NUMBER

Limits

Measured

AMPLITUDE in dbuV

FREQUENCY

AMPLITUDE in dbuV

FREQUENCY

Conducted EMI Performance

4 Conducted EMI Performance

Figure 6. 120V, 30W Conducted EMI Peak Scan Figure 7. 230V, 30W Conducted EMI Peak Scan

Line and Neutral - CISPR/FCC Class B Quasi Peak and Line and Neutral - CISPR/FCC Class B Quasi Peak and

Average Limits Average Limits

5 THD / Harmonic Performance

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Figure 8. 120V, 30W THD Measurements Figure 9. 230V, 30W THD Measurements

EN 61000-3 Class C Limits EN 61000-3 Class C Limits

THD = 6.27% ; Fundamental = 316mA THD = 8.96% ; Fundamental = 167mA

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REF

ZCDFLT2

DIM GATE V

CS COMP GND FB I

SEN

HOLDV

ADJ

FLT1

BIAS

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6 LM3450A Pin Descriptions

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LM3450A Pin Descriptions

Pin Name Description Application Information

1 V

REF

3V Reference

Reference Output: Connect directly to V divider feeding V

and to necessary external circuits.

ADJ

Analog Dim and Phase Dimming Range Input: Connect

2 V

ADJ

Analog Adjust range. Connect to resistor divider from V

directly to V usable range of some phase dimmers or for analog

to force standard 70% phase dimming

REF

dimming. Connect to GND for low power mode. Ramp Comparator Input: Connect a series resistor from

3 FLT2 Filter 2 FLT1 capacitor and a capacitor to GND to establish

second filter pole.

4 FLT1 Filter 1

Angle Decoder Output: Connect a series resistor to a capacitor to ground to establish first filter pole.

Open Drain PWM Dim Output: Connect to dimming input

5 DIM 500 Hz PWM Output of output stage LED driver (directly or with isolation) to

provide decoded dimming command.

6 V

Sampled Rectified Line

7 COMP Compensation

Multiplier and Angle Decoder Input: Connect to resistor divider from rectified AC line.

Error Amplifier Output and PWM Comparator Input: Connect a capacitor to GND to set the compensation.

Error Amplifier Inverting Input: Connect to output voltage via resistor divider to control PFC voltage loop for non-

8 FB Feedback isolated designs. Connect to a 5.11kΩ resistor to GND

for isolated designs (bypasses error amplifier). Also includes over-voltage protection and shutdown modes.

Input Current Sense Non-Inverting Input: Connect to diode bridge return and resistor to GND to sense input

9 I

SEN

Input Current Sense current for dynamic hold. Connect a 0.1µF capacitor and

Schottky diode to GND, and a 0.22µF capacitor to HOLD.

10 GND Power Ground System Ground 11 CS Current Sense

MosFET Current Sense Input: Connect to positive terminal of sense resistor in PFC MosFET source.

Gate Drive Output: Connect to gate of main power

12 GATE Gate Drive MosFET for PFC.Gate Drive Output: Connect to gate of

main power MosFET for PFC.

13 V

14 ZCD Zero Crossing Detector transformer/inductor winding to detect when all energy

15 HOLD Dynamic Hold

Input Supply

Power Supply Input: Connect to primary bias supply. Connect a 0.1µF bypass capacitor to ground.

Demagnetization Sense Input: Connect a resistor to has been transferred.

Open Drain Dynamic Hold Input: Connect to holding resistor which is connected to source of passFET.

or to resistor

ADJ

to extend

REF

UVLO

CSP

VIN

COFF

CSN

GND PGATE

DAP

VCC

IADJ

LM3409HV Pin Descriptions

Pin Name Description Application Information

16 BIAS Pre-regulator Gate Bias passFET and to resistor to rectified AC (drain of

7 LM3409HV Pin Descriptions

Pin Name Description Application Information

1 UVLO Input Under Voltage Lock-out 1.24V and hysteresis is provided by a 22µA current

2 I

3 EN Logic Level Enable

4 COFF Off-time programming 5 GND Power Ground Connect to the system ground.

6 PGATE Gate Drive Connect to the gate of the external PFET. 7 CSN Negative Current Sense Connect to the negative side of the sense resistor.

8 CSP Positive Current Sense

9 V

10 V

DAP DAP Thermal PAD on bottom of IC

ADJ

VIN-referenced Linear Regulator Output

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Pre-regulator Gate Bias Output: Connect to gate of passFET) to aid with startup.

Connect to a resistor divider from VIN. UVLO threshold is source.

Apply a voltage between 0 - 1.24V, or connect a resistor

Analog LED Current Adjust from this pin to GND, to set the current sense threshold

voltage. Apply a voltage >1.6V to enable device, a PWM signal

to dim, or a voltage <0.6V for low power shutdown. Connect an external resistor from VOto this pin, and a

capacitor from this pin to GND to set the off-time.

Connect to the positive side of the sense resistor (also connected to VIN).

Connect at least a 1 µF ceramic capacitor from this pin to CSN. The regulator provides power for P-FET drive.

Input Voltage Connect to the input voltage.

Connect to pin 5 (GND). Place 4-6 vias from DAP to bottom layer GND plane.

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ZCD

GATE

LM3450A

GND

COMP

HOLD

ADJ

DIM

FLT2

FLT1

SEN

PWM

REF

BIAS

IADJ

CSN

LM3409HV

UVLO

VCC

COFF

GND

CSP

PGATE

DAP

VIN

OUT

PWM

OP1

OP2

RETURN

LED

LMV431

OPTO1

OPTO2

OP2

OP1

POP2

OUT

EMI

FILTER

CONTROL

FEEDBACK

SECONDARY

LED DRIVER

DIMMING

VREF

MAINS

LED

LOAD

D10 D23

C8 C9

C30

C2 C3

C66

C26

C11 C13

C4 C5

C42 C44

D16

C43

C17

C18

C24

C23

D17

C22

R8 R9

R56

R2 R3

R47

R5 R7

R17

R23

R24

R25

R26 R29

R32

R38

R30 R31

R34 R36

R70

R77

R72

R81

R16

R71

R84

R65 R66 R83

R58

C35

C34

C38

C36

C39

C37 C47

D15

D13

D14

D22

D11D12

R57

HOLD

LED

R39

U10

U11

POP2

R18

D18

C21

C46

ADJ

COMPBIAS

D21

D24

R20

R21

SOFTSTART

C12

D20

THERMAL PROTECT

R10

R12 R14 R15

AUX

R11

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8 Simplified Evaluation Board Schematic

Simplified Evaluation Board Schematic

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Figure 10. Simplified Evaluation Board Schematic

VREF

LM3450A FLYBACK

VREF

EMI + BRIDGE

LM3409HV BUCK

Design Information

9 Design Information

The following section explains how to design using the LM3450A power factor controller and phase dimming decoder. Refer to AN-1953 LM3409HV Evaluation Board (SNVA390) for a detailed design procedure of the LM3409HV secondary stage and to the LM3450/A LED Drivers with Active Power Factor Correction & Phase Dimming Decoder (SNVAS681) data sheet for specific details regarding the function of the LM3450A device. All reference designators refer to the Simplified Evaluation Board Schematic. Note that parallel and series resistances are combined in one schematic symbol for simplification. To improve readability of this design document, each subsection is followed by a list of Definitions for new terms used in the calculations. Section 11, showing all components and connectors, is found at the end of this document as well as a Bill of Materials for each assembly version.

9.1 1STStage - CRM Flyback

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Figure 11. Two-Stage PFC LED Driver

The first stage of the evaluation board shown in Figure 11 is a critical conduction mode (CRM) flyback converter controlled with the LM3450A. CRM converters operate at the boundary of continuous conduction mode (CCM) and discontinuous conduction mode (DCM). CRM is implemented by turning on the main switching FET (Q3) until the primary current rises to a peak threshold. Q3 is then turned off and the current falls until a zero crossing is detected. At this point, Q3 is turned on and the cycle repeats.

In the CRM flyback PFC application, the rectified AC input is fed forward to the control loop, yielding a sinusoidal peak current threshold. This peak threshold creates a sinusoidal primary peak current envelope I

as shown in Figure 12. The secondary peak current envelope I

P-pk

will simply be a scaled version of

S-pk

the primary according to the turns ratio of the transformer. Assuming good attenuation of the switching ripple via the EMI filter, the average input current IIN(t), shown in red, can also be approximated as a sinusoid. Since the input current has the same shape and phase as the input voltage, high power factor (PF) can easily be achieved.

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IN-PK

P-PK

S-PK

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The input current shaping happens instantly in CRM due to the feed-forward mechanism; however, the converter must also regulate the flyback output voltage with a traditional feedback loop. This is accomplished with a narrow bandwidth error amplifier coupled with energy storage capacitance at the output to limit the twice line frequency ripple. The output of the error amplifier is multiplied with the scaled rectified AC voltage to achieve both input current shaping and output voltage regulation. Refer to the datasheet for a more detailed explanation of the power factor controller.

The LM3450A also has a phase decoder that interprets the phase dimming angle and maps it to a 500Hz PWM open-drain output at the DIM pin. This signal is directly connected to an opto-isolator to send across the isolation boundary to the second stage LED driver. In addition, the LM3450A provides a dynamic hold circuit to ensure that the holding current requirement is satisfied in forward phase dimmers. Refer to the datasheet for a more detailed explanation of the phase dimmer decoder.

Design Information

Figure 12. CRM Flyback Current Waveforms

9.2 2NDStage - Buck LED Driver

The second stage of the evaluation board is a buck LED driver controlled with the LM3409HV. The input to this stage is the flyback output voltage and the output is a regulated constant current of 700mA to a stack of <45V of LEDs. The LM3409HV is a hysteretic PFET controller using peak current detection and a constant off-timer to provide regulated LED current with a constant switching frequency ripple. Coupled with the flyback energy storage capacitance, the LM3409HV is able to remove all 120HZ ripple content from the LED output. The 500Hz PWM signal from the first stage is used as the dimming input to the LM3409HV. The output of the opto-isolator is connected directly to the EN pin of the LM3409HV to provide a PWM dimmed LED current according to the detected phase angle at the primary.

The LM3409HV design is not included in this document. Refer to AN-1953 for a detialed design procedure. The specifications for the second stage are:

• Nominal Input Voltage = 50V

• Regulated LED Current = 700mA

• Nominal LED Stack Voltage = 45V

• Switching Frequency at Nominal Input = 100kHz

• Inductor/LED Current Ripple = 115mA

9.3 CRM Flyback Converter

Operating Points

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Design Information

The AC mains voltage, at the line frequency fL, is assumed to be perfectly sinusoidal and the diode bridge ideal. This yields a perfect rectified sinusoid at the input to the flyback. The input voltage Vin(t) is defined in terms of the peak input voltage:

The controller and the transformer are also assumed to be ideal. These assumptions yield a sinusoidal peak primary current envelope I Both are defined in terms of the peak primary current:

The output voltage reflected to the primary is defined:

CRM control yields a variable duty cycle over a single line cycle with a minimum occurring at the peak input voltage:

The resulting sinusoidal average input current Iin(t), shown in Figure 12, is approximated as the average of each triangular current pulse during a switching period. The peak input current occurs at the peak primary current:

(t) and peak secondary current envelope I

P-pk

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(t) as shown in Figure 12.

S-pk

(1)

(2)

(3)

(4)

Turns Ratio

The first thing to decide with an isolated design is the desired transformer turns ratio. This should be based on the specified output voltage and the maximum peak input voltage. Frequently the MosFET is already chosen for a design, given its cost and availability. With a desired MosFET voltage, the maximum reflected voltage at the primary is calculated:

Generally, an integer turns ratio is selected to achieve a reflected voltage at or below the defined maximum:

Switching MosFET

The main switching MosFET (Q3) can be sized as desired; to block the maximum drain-to-source voltage, operate at the maximum RMS current, and dissipate the maximum power:

The peak current limit should be at least 25% higher than the maximum peak input current:

(5)

(6)

(7)

(8)

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The parallel sense resistor combination (R30||R31) has to dissipate the maximum power:

Switching Diode

The main switching diode (D10) should be sized to block the maximum reverse voltage , operate at the maximum average current, and dissipate the maximum power:

Definitions

n – Primary to Secondary Turns Ratio V VIN– Nominal AC Input Voltage V V I

P-PK

S-PK

IN-PK

LIM

D VR– Output Voltage Reflected to Primary V V V I

T-RMS-MAX

T-PK-MAX

P V I

D-MAX

D-PK-MAX

– Regulated Output Voltage

OUT

– Peak Input Voltage

IN-PK

IN-PK-MAX

– Maximum Peak Input Voltage – Peak Primary Current – Peak Secondary Current

– Peak Input Current

– Peak Current Limit

– Minimum Duty Cycle over Line Cycle

MIN

– Maximum Tolerable Reflected Voltage

R-MAX

T-DES-MAX

T-MAX

– Maximum Tolerable MosFET Voltage

– Maximum MosFET Blocking Voltage

– Maximum MosFET RMS Current

– Maximum MosFET Peak Current

– Maximum MosFET Power Dissipation

T-MAX

– Maximum Diode Blocking Voltage

RD-MAX

– Maximum Diode Average Current

– Maximum Diode Peak Current

– Maximum Diode Power Dissipation

D-MAX

Design Information

(9)

(10)

(11)

9.4 Transformer

Primary Inductance

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+ 25 hidden pages

Texas Instruments Incorporated AN-2150 User's Guide

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

2 Specifications

3 Typical Performance

4 Conducted EMI Performance

5 THD / Harmonic Performance

6 LM3450A Pin Descriptions

7 LM3409HV Pin Descriptions

8 Simplified Evaluation Board Schematic

9 Design Information

9.1 1STStage - CRM Flyback

9.2 2NDStage - Buck LED Driver

9.3 CRM Flyback Converter

9.4 Transformer