Texas Instruments XIO3130 EVM User Manual

SLLU108 July 2008
XIO3130 EVM

1.1 Overview

The Texas Instruments XIO3130 EVM is a functional implementation of a four-port PCIe-to-PCIe switch. The XIO3130 EVM was designed to allow validation of three separate functional modes. In normal mode, the EVM is configured as a generic PCI Express (PCIe) switch. In hot-plug mode, downstream ports 1 and 2 are configured as hot-pluggable slots. In ExpressCard mode, all three downstream ports are configured to support the ExpressCard adapter board. The different functional modes are discussed later in this document.
Figure 1-1 shows the EVM board. There are various jumpers, dipswitches, push buttons, and LEDs to
support the various functional modes. For the board to operate, power must be applied via the peripheral power connector located to the right side of the board. Endpoints can be plugged directly into any one or all of the downstream ports. The upstream edge connector can be plugged into any PCIe slot on a motherboard. Once the EVM with attached endpoints is plugged into a PCIe motherboard and power is provided to the EVM, nothing else needs to be done in order for the EVM to operate. The two LEDs in the upper right-hand corner light up when power is applied to the peripheral power connector.
Figure 1-1. EVM Board
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Normal-Mode Operation

1.2 Normal-Mode Operation

By default, the EVM should be configured to operate in normal mode. The six jumpers (J7, J11, J13, J14, J15, and J16) should be covering both pins of each header (see Figure 1-2 ).
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Figure 1-2. Power Jumpers
The dipswitch should be configured with SCL slide switch in the up position and DN1_DPSTRP, DN2_DPSTRP, and DN3_DPSTRP slide switches in the down position (see Figure 1-3 ). This configuration enables the EEPROM and disables hot-plug operation.
Figure 1-3. Dipswitch Configuration
The EEPROM (U3) should also be preconfigured for normal-mode operation. See Section 1.5 for an explanation of how to configure the EEPROM. Upon deassertion of PERST, the XIO3130 automatically reads data from the EEPROM. This data is used to preset various PCI configuration register bits. For normal-mode operation, the data in the EEPROM will configure bits in the following registers:
GPIO C control register (PCI register offset: C0h in upstream bridge) PCIE_GPIO12_CTL = 010b Port 1 ACT_LED0
PCIE_GPIO13_CTL = 011b Port 2 ACT_LED1 – PCIE_GPIO14_CTL = 100b Port 3 ACT_LED2
Setting these bits configures LED1 as activity LED for port 1, LED2 as activity LED for port 2, and LED3 as activity LED for port 3. Any time a TLP is transferred to or from the slot, the activity LED flashes. LEDs 4 and 5 are nonfunctional in normal mode; pressing the push buttons will have no effect on the XIO3130.
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General control register (PCI register offset: D4h in each downstream bridge) RCVR_PRSNT_EN = 0b PRSNT pin is used to determine whether slot is present
REFCK_DIS = 0b REFCK enabled – LINK_ACT_RPT_CAP = 1b Slot is link active reporting capable – SLOT_PRSNT = 1b Port connected to slot
General slot info register (PCI register offset EEh in each downstream bridge) SLOT_NUM = 1b for slot 1, 2b for slot 2, and 3b for slot 3

1.3 Hot-Plug-Mode Operation

In hot-plug mode, the EVM board utilizes the TPS2363 PCIe server dual-slot hot-plug controller to switch power on and off to slots 1 and 2. The TPS2363 is directly controlled by the hot-plug controller built into the XIO3130. Slot 3 operates in normal mode. To configure the EVM for hot-plug operation, the six jumpers (J7, J11, J13, J14, J15, J16) must be removed (see Figure 1-5 ).
Hot-Plug-Mode Operation
Figure 1-4. GPIO Control Register
Figure 1-5. Power Jumpers
The dipswitch should be configured with SCL, DN1_DPSTRP and DN2_DPSTRP slide switches in the up position, and DN3_DPSTRP slide switches in the down position (see Figure 1-6 ). This configuration enables the EEPROM and enables hot-plug operation on slots 1 and 2.
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Hot-Plug-Mode Operation
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Figure 1-6. Dipswitch Configuration
The EEPROM (U3) should be reconfigured for hot-plug-mode operation. See Section 1.5 for an explanation of how to configure the EEPROM. Upon deassertion of PERST, the XIO3130 automatically reads data from the EEPROM. This data is used to preset various PCI configuration register bits. For hot-plug-mode operation, the data in the EEPROM configures bits in the following registers:
GPIO B control register (PCI Register offset: BEh in upstream bridge) PCIE_GPIO8_CTL = 010b Port 1 ACT_BTN0
PCIE_GPIO9_CTL = 100b Port 1 ATN_LED0
GPIO C control register (PCI register offset: C0h in upstream bridge) PCIE_GPIO10_CTL = 011b –Port 2 ACT_BTN1
PCIE_GPIO11_CTL = 101b Port 2 PWRFLT1 – PCIE_GPIO12_CTL = 101b Port 1 PWR_LED0 – PCIE_GPIO13_CTL = 110b Port 2 PWR_LED1
GPIO D control register (PCI register offset: C2h in upstream bridge) PCIE_GPIO15_CTL = 101b Port 1 PWRFLT0
PCIE_GPIO16_CTL = 011b Port 2 ATN_LED1
Setting these bits configures LED1 as PWR_LED0 for port 1 and LED2 as PWR_LED1 for port 2. LED3 is not used in hot-plug mode. LEDs 4 will be configured as ATN_LED0 for port 1 and LED5 will be configured as ATN_LED1 for port 2. Push-button switch SW2 is the attention button for port 1 and SW3 is the attention button for port 2.
Figure 1-7. GPIO Control Register
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ExpressCard-Mode operation
General control register (PCI register offset: D4h in port 1 and port 2 downstream bridges) RCVR_PRSNT_EN = 0b PRSNT pin is used to determine whether slot is present
REFCK_DIS = 0b REFCK enabled – LINK_ACT_RPT_CAP = 1b Slot is link active reporting capable – SLOT_PFIP = 1b Power fault input implemented – SLOT_PRSNT = 1b Port connected to slot – SLOT_ABP = 1b Attention button implemented – SLOT_PCP = 1b Power controller implemented – SLOT_AIP = 1b Attention indicator implemented – SLOT_PIP = 1b Power indicator implemented – SLOT_HPS = 1b Device present that can be removed without prior notification. – SLOT_HPC = 1b Slot is hot-plug capable – RC_PF_CTL = 1b REFCK output enable is a function of PWR_FAULT
General control register (PCI register offset: D4h in port 3 downstream bridge) RCVR_PRSNT_EN = 0b PRSNT pin is used to determine whether slot is present
REFCK_DIS = 0b REFCK enabled – LINK_ACT_RPT_CAP = 1b Slot is link active reporting capable – SLOT_PRSNT = 1b Port connected to slot
General slot info register (PCI register offset EEh in each downstream bridge) SLOT_NUM = 1b for slot 1, 2b for slot 2, and 3b for slot 3

1.4 ExpressCard-Mode operation

For this mode of operation, the ExpressCard adapter board is used in conjunction with the XIO3130 EVM board. This adapter board utilizes the TI TPS2231 power interface switch to switch power on and off to the ExpressCard slot. TI also offers a dual-power interface switch called the TPS2236. Figure 1-8 shows the adapter board.
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ExpressCard-Mode operation
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Figure 1-8. ExpressCard Adapter Board
To configure the XIO3130 EVM for ExpressCard-mode operation, connect the ribbon cable connector from J1 on the adapter board to one of the matching connectors (J2, J3 or J4) on the XIO3130 EVM board. Then plug the adapter board into the adjacent PCIe slot as shown in Figure 1-9 . It does not matter which PCIe slot is used, but the ribbon cable must be plugged into the connector just below and to the right of the PCIe slot that the adapter board is plugged into.
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