Page 1
XIO2000A/XIO2000AI PCI Express
r
to PCI Bus Translation Bridge
Data Manual
Literature Number: SCPS155C
April 2007 Revised October 2008
Printed on Recycled Pape
Page 2
Contents
Section Page
1 XIO2000A Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Introduction 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Related Documents 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Trademarks 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Document Conventions 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Document History 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Ordering Information 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Terminal Assignments 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Terminal Descriptions 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Power-Up/-Down Sequencing 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 Power-Up Sequence 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.2 Power-Down Sequence 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Bridge Reset Features 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 PCI Express Interface 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 External Reference Clock 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Beacon 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Wake 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 Initial Flow Control Credits 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.5 PCI Express Message Transactions 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 PCI Bus Interface 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 I/O Characteristics 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Clamping Voltage 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 PCI Bus Clock Run 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 PCI Bus External Arbiter 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.5 MSI Messages Generated from the Serial IRQ Interface 27. . . . . . . . . . . . . . . . . . . . . .
3.4.6 PCI Bus Clocks 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Quality of Service and Isochronous Features 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 PCI Port Arbitration 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 PCI Isochronous Windows 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3 PCI Express Extended VC With VC Arbitration 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 128-Phase, WRR PCI Port Arbitration Timing 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Configuration Register Translation 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 PCI Interrupt Conversion to PCI Express Messages 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 PME Conversion to PCI Express Messages 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 PCI Express To PCI Bus Lock Conversion 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Two-Wire Serial-Bus Interface 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.1 Serial-Bus Interface Implementation 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.2 Serial-Bus Interface Protocol 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.3 Serial-Bus EEPROM Application 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.4 Accessing Serial-Bus Devices Through Software 42. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Advanced Error Reporting Registers 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Data Error Forwarding Capability 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 General-Purpose I/O Interface 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 Set Slot Power Limit Functionality 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 PCI Express and PCI Bus Power Management 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Contents
4 Classic PCI Configuration Space 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Vendor ID Register 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Device ID Register 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Command Register 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Status Register 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Class Code and Revision ID Register 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Cache Line Size Register 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Primary Latency Timer Register 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Header Type Register 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 BIST Register 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Device Control Base Address Register 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 Primary Bus Number Register 50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Secondary Bus Number Register 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Subordinate Bus Number Register 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Latency Timer Register 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 I/O Base Register 51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 I/O Limit Register 52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Secondary Status Register 53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 Memory Base Register 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Memory Limit Register 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Prefetchable Memory Base Register 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 Prefetchable Memory Limit Register 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 Prefetchable Base Upper 32-Bit Register 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Prefetchable Limit Upper 32-Bit Register 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 I/O Base Upper 16-Bit Register 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 I/O Limit Upper 16-Bit Register 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Capabilities Pointer Register 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Interrupt Line Register 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 Interrupt Pin Register 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.29 Bridge Control Register 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 Capability ID Register 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Next Item Pointer Register 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Power Management Capabilities Register 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.33 Power Management Control/Status Register 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.34 Power Management Bridge Support Extension Register 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 Power Management Data Register 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.36 MSI Capability ID Register 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.37 Next Item Pointer Register 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.38 MSI Message Control Register 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.39 MSI Message Lower Address Register 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.40 MSI Message Upper Address Register 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 MSI Message Data Register 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.42 Capability ID Register 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.43 Next Item Pointer Register 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.44 Subsystem Vendor ID Register 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.45 Subsystem ID Register 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.46 PCI Express Capability ID Register 65. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.47 Next Item Pointer Register 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 PCI Express Capabilities Register 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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April 2007 Revised October 2008SCPS155C
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4.49 Device Capabilities Register 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.50 Device Control Register 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.51 Device Status Register 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.52 Link Capabilities Register 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.53 Link Control Register 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.54 Link Status Register 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.55 Serial-Bus Data Register 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.56 Serial-Bus Word Address Register 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.57 Serial-Bus Slave Address Register 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.58 Serial-Bus Control and Status Register 74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.59 GPIO Control Register 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.60 GPIO Data Register 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.61 Control and Diagnostic Register 0 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.62 Control and Diagnostic Register 1 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.63 Control and Diagnostic Register 2 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.64 Subsystem Access Register 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.65 General Control Register 80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.66 Clock Control Register 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.67 Clock Mask Register 83. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.68 Clock Run Status Register 84. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.69 Arbiter Control Register 85. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.70 Arbiter Request Mask Register 86. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.71 Arbiter Time-Out Status Register 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.72 Serial IRQ Mode Control Register 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.73 Serial IRQ Edge Control Register 89. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.74 Serial IRQ Status Register 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 PCI Express Extended Configuration Space 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Advanced Error Reporting Capability ID Register 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Next Capability Offset/Capability Version Register 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Uncorrectable Error Status Register 94. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 Uncorrectable Error Mask Register 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 Uncorrectable Error Severity Register 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 Correctable Error Status Register 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 Correctable Error Mask Register 98. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 Advanced Error Capabilities and Control Register 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 Header Log Register 99. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Secondary Uncorrectable Error Status Register 100. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Secondary Uncorrectable Error Mask Register 101. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Secondary Uncorrectable Error Severity Register 102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13 Secondary Error Capabilities and Control Register 103. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14 Secondary Header Log Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15 Virtual Channel Capability ID Register 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16 Next Capability Offset/Capability Version Register 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.17 Port VC Capability Register 1 105. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.18 Port VC Capability Register 2 106. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.19 Port VC Control Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.20 Port VC Status Register 107. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 VC Resource Capability Register (VC0) 108. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.22 VC Resource Control Register (VC0) 109. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
April 2007 Revised October 2008 SCPS155C
v
Page 5
Contents
5.23 VC Resource Status Register (VC0) 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.24 VC Resource Capability Register (VC1) 110. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.25 VC Resource Control Register (VC1) 111. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.26 VC Resource Status Register (VC1) 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.27 VC Arbitration Table 112. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.28 Port Arbitration Table (VC1) 113. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Memory-Mapped TI Proprietary Register Space 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Device Control Map ID Register 114. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Revision ID Register 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Upstream Isochrony Capabilities Register 115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Upstream Isochrony Control Register 116. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Upstream Isochronous Window 0 Control Register 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Upstream Isochronous Window 0 Base Address Register 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 Upstream Isochronous Window 0 Limit Register 117. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 Upstream Isochronous Window 1 Control Register 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.9 Upstream Isochronous Window 1 Base Address Register 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.10 Upstream Isochronous Window 1 Limit Register 118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.11 Upstream Isochronous Window 2 Control Register 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.12 Upstream Isochronous Window 2 Base Address Register 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.13 Upstream Isochronous Window 2 Limit Register 119. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.14 Upstream Isochronous Window 3 Control Register 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.15 Upstream Isochronous Window 3 Base Address Register 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.16 Upstream Isochronous Window 3 Limit Register 120. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.17 GPIO Control Register 121. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.18 GPIO Data Register 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.19 Serial-Bus Data Register 122. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.20 Serial-Bus Word Address Register 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.21 Serial-Bus Slave Address Register 123. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.22 Serial-Bus Control and Status Register 124. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.23 Serial IRQ Mode Control Register 125. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.24 Serial IRQ Edge Control Register 126. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.25 Serial IRQ Status Register 127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Electrical Characteristics 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges † 129. . . . . . . . . . . . . . . . . . . . .
7.2 Recommended Operation Conditions 129. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Nominal Power Consumption 130. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4 PCI Express Differential Transmitter Output Ranges 131. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 PCI Express Differential Receiver Input Ranges 132. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6 PCI Express Differential Reference Clock Input Ranges 135. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7 Electrical Characteristics Over Recommended Operating Conditions (PCI Bus) 136. . . . . . . . . . .
7.8 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O) 136. . . . . . . . . . .
7.9 PCI Clock Timing Requirements Over Recommended Operating Conditions 137. . . . . . . . . . . . . .
7.10 PCI Bus Timing Requirements Over Recommended Operating Conditions 137. . . . . . . . . . . . . . . .
7.11 PCI Bus Parameter Measurement Information 138. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 PCI Bus Parameter Measurement Information 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Glossary 140. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Mechanical Data 141. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
April 2007 Revised October 2008SCPS155C
Page 6
List of Figures
Figure Page
2−1 XIO2000A GZZ/ZZZ MicroStar BGATM Package (Bottom View) 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 XIO2000A ZHH Microstar BGA Package (Bottom View) 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 XIO2000A Block Diagram 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 Power-Up Sequence 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Power-Down Sequence 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 3-State Bidirectional Buffer 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 PCI Bus Timing 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Type 0 Configuration Transaction Address Phase Encoding 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Type 1 Configuration Transaction Address Phase Encoding 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 PCI Express Assert_INTx Message 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 PCI Express Deassert_INTx Message 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 PCI Express PME Message 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Starting A Locked Sequence 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Continuing A Locked Sequence 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 Terminating A Locked Sequence 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 Serial EEPROM Application 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Serial-Bus Start/Stop Conditions and Bit Transfers 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 Serial-Bus Protocol Acknowledge 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 Serial-Bus Protocol—Byte Write 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18 Serial-Bus Protocol—Byte Read 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−19 Serial-Bus Protocol—Multibyte Read 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1 Load Circuit And Voltage Waveforms 137 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−2 CLK Timing Waveform 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−3 PRST Timing Waveforms 139. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−4 Shared Signals Timing Waveforms 139 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
April 2007 Revised October 2008 SCPS155C
vii
Page 7
Tables
List of Tables
Table Page
2−1 XIO2000A GZZ/ZZZ Terminals Sorted Alphanumerically 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 XIO2000A ZHH Terminals Sorted Alphanumerically 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 XIO2000A Signal Names Sorted Alphabetically 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 Power Supply Terminals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 Ground Terminals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 Combined Power Outputs 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 PCI Express Terminals 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 Clock Terminals 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 PCI System Terminals 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 Reserved Terminals 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Miscellaneous Terminals 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 Bridge Reset Options 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 Initial Flow Control Credit Advertisements 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Messages Supported by the Bridge 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 IRQ Interrupt to MSI Message Mapping 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Classic PCI Arbiter Registers 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Port Number to PCI Bus Device Mapping 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 128-Phase, WRR Time-Based Arbiter Registers 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 PCI Isochronous Windows 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Hardware-Fixed, Round-Robin Arbiter Registers 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 32-phase, WRR Arbiter Registers 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Type 0 Configuration Transaction IDSEL Mapping 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Interrupt Mapping In The Code Field 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 EEPROM Register Loading Map 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 Registers Used To Program Serial-Bus Devices 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Clocking In Low Power States 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 Classic PCI Configuration Register Map 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Command Register Description 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Status Register Description 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Class Code and Revision ID Register Description 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Device Control Base Address Register Description 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 I/O Base Register Description 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 I/O Limit Register Description 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Secondary Status Register Description 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 Memory Base Register Description 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 Memory Limit Register Description 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Prefetchable Memory Base Register Description 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 Prefetchable Memory Limit Register Description 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 Prefetchable Base Upper 32-Bit Register Description 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 Prefetchable Limit Upper 32-Bit Register Description 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 I/O Base Upper 16-Bit Register Description 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−16 I/O Limit Upper 16-Bit Register Description 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 Bridge Control Register Description 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 Power Management Capabilities Register Description 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 Power Management Control/Status Register Description 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 Power Management Bridge Support Extension Register Description 61 . . . . . . . . . . . . . . . . . . . . . . . .
4−21 MSI Message Control Register Description 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
April 2007 Revised October 2008SCPS155C
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Table Page
4−22 MSI Message Lower Address Register Description 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−23 MSI Message Data Register Description 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−24 PCI Express Capabilities Register Description 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−25 Device Capabilities Register Description 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−26 Device Control Register Description 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−27 Device Status Register Description 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−28 Link Capabilities Register Description 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−29 Link Control Register Description 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−30 Link Status Register Description 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−31 Serial-Bus Slave Address Register Description 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−32 Serial-Bus Control and Status Register Description 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−33 GPIO Control Register Description 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−34 GPIO Data Register Description 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−35 Control and Diagnostic Register 0 Description 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−36 Control and Diagnostic Register 1 Description 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−37 Control and Diagnostic Register 2 Description 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−38 Subsystem Access Register Description 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−39 General Control Register Description 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−40 Clock Control Register Description 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−41 Clock Mask Register Description 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−42 Clock Run Status Register Description 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−43 Arbiter Control Register Description 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−44 Arbiter Request Mask Register Description 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−45 Arbiter Time-Out Status Register Description 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−46 Serial IRQ Mode Control Register Description 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−47 Serial IRQ Edge Control Register Description 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−48 Serial IRQ Status Register Description 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 PCI Express Extended Configuration Register Map 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Uncorrectable Error Status Register Description 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3 Uncorrectable Error Mask Register Description 95 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 Uncorrectable Error Severity Register Description 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−5 Correctable Error Status Register Description 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6 Correctable Error Mask Register Description 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7 Advanced Error Capabilities and Control Register Description 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8 Secondary Uncorrectable Error Status Register Description 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 Secondary Uncorrectable Error Mask Register Description 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10 Secondary Uncorrectable Error Severity Register Description 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 Secondary Error Capabilities and Control Register Description 103 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 Secondary Header Log Register Description 104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 Port VC Capability Register 1 Description 105 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 Port VC Capability Register 2 Description 106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−15 Port VC Control Register Description 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−16 Port VC Status Register Description 107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−17 VC Resource Capability Register (VC0) Description 108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−18 VC Resource Control Register (VC0) Description 109 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−19 VC Resource Status Register (VC0) Description 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−20 VC Resource Capability Register (VC1) Description 110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−21 VC Resource Control Register (VC1) Description 111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
April 2007 Revised October 2008 SCPS155C
ix
Page 9
Tables
Table Page
5−22 VC Resource Status Register (VC1) Description 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−23 VC Arbitration Table 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−24 VC Arbitration Table Entry Description 112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−25 Port Arbitration Table 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−26 Port Arbitration Table Entry Description 113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Device Control Memory Window Register Map 114 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Upstream Isochronous Capabilities Register Description 115 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 Upstream Isochrony Control Register Description 116 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 Upstream Isochronous Window 0 Control Register Description 117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−5 Upstream Isochronous Window 1 Control Register Description 118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−6 Upstream Isochronous Window 2 Control Register Description 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7 Upstream Isochronous Window 3 Control Register Description 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−8 GPIO Control Register Description 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−9 GPIO Data Register Description 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−10 Serial-Bus Slave Address Register Description 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−11 Serial-Bus Control and Status Register Description 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−12 Serial IRQ Mode Control Register Description 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−13 Serial IRQ Edge Control Register Description 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−14 Serial IRQ Status Register Description 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
x
April 2007 Revised October 2008SCPS155C
Page 10
1 XIO2000A Features
Features
D Full x1 PCI Express Throughput
D Fully Compliant with PCI Express to
PCI/PCI-X Bridge Specification,
Revision 1.0
D Fully Compliant with PCI Express Base
Specification, Revision 1.0a
D Fully Compliant with PCI Local Bus
Specification, Revision 2.3
D Extended Virtual Channel (VC) Support
Includes a Second VC for
Quality-of-Service and Isochronous
Applications
D PCI Express Advanced Error Reporting
Capability Including ECRC Support
D Support for D1, D2, D3
, and D3
hot
cold
D Active State Link Power Management
Saves Power When Packet Activity on the
PCI Express Link is Idle, Using Both L0s
and L1 States
D Wake Event and Beacon Support
D Error Forwarding Including PCI Express
Data Poisoning and PCI Bus Parity Errors
D Utilizes 100-MHz Differential PCI Express
Common Reference Clock or 125-MHz
Single-Ended, Reference Clock
D Robust Pipeline Architecture To Minimize
Transaction Latency
D Full PCI Local Bus 66-MHz/32-Bit
Throughput
D Support for Six Subordinate PCI Bus
Masters with Internal Configurable, 2-Level
Prioritization Scheme
D Low Power Design (<350 mW) Ensures
Ease of Implementation
D XIO2000AI Supports Industrial
Temperatures at 33-MHz Bus Speeds
D Two Package Options: 15 mm x 15 mm and
12 mm x 12 mm
D Internal PCI Arbiter Supporting Up to 6
External PCI Masters
D Advanced VC Arbitration Options Include
VC1 Strict Priority, Hardware-Fixed
Round-Robin, and 32-Phase, Weighted
Round-Robin
D Advanced PCI Bus Port Arbitration Options
Include 128-phase, Weighted Round-Robin
Time-Based and 128-phase, Weighted
Round-Robin Aggressive Time-Based
D Advanced PCI Isochronous Windows for
Memory Space Mapping to a Specified
Traffic Class
D Advanced PCI Express Message Signaled
Interrupt Generation for Serial IRQ
Interrupts from CardBus Applications
D External PCI Bus Arbiter Option
D PCI Bus LOCK Support
D Clock Run and Power Override Support
D Six Buffered PCI Clock Outputs (33 MHz or
66 MHz)
D PCI Bus Interface 3.3-V and 5.0-V (33 MHz
only at 5.0 V) Tolerance Options
D Integrated AUX Power Switch Drains V
Power Only When Main Power Is Off
AUX
D Eight 3.3-V, Multifunction, General-Purpose
I/O Terminals
D Memory-Mapped EEPROM Serial-Bus
Controller Supporting PCI Express Power
Budget/Limit Extensions for Add-In Cards
D Compact Footprint, 201-Ball, GZZ
MicroStar
Lead-Free 201-Ball, ZZZ MicroStar
175-Ball ZHC MicroStar BGA; or 175-Ball
ZHH MicroStar BGA
TM
BGA (XIO2000A only),
TM
BGA;
T able 1−1.
Figure 1−1.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
April 2007 Revised October 2008 SCPS155C
1
Page 11
Introduction
2 Introduction
The Texas Instruments XIO2000A is a PCI Express to PCI local bus translation bridge that provides full PCI
Express and PCI local bus functionality and performance.
2.1 Description
The XIO2000A is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI
Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge simultaneously
supports up to eight posted and four nonposted transactions for each enabled virtual channel (VC). For
upstream traffic, up to six posted and four nonposted transactions are simultaneously supported for each VC.
The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 1.0a.
The PCI Express interface supports a x1 link operating at full 250 MB/s packet throughput in each direction
simultaneously. Two independent VCs are supported. The second VC is optimized for isochronous traffic
types and quality-of-service (QoS) applications. Also, the bridge supports the advanced error reporting
capability including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental
firmware or software is required to fully utilize both of these features.
Robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors are
detected, then packet poisoning is supported for both upstream and downstream operations.
The PCI local bus is fully compliant with the PCI Local Bus Specification (Revision 2.3) and associated
programming model. Also, the bridge supports the standard PCI-to-PCI bridge programming model.
The PCI bus interface is 32-bit and can operate at either 33 MHz or 66 MHz. Also, the PCI interface provides
fair arbitration and buffered clock outputs for up to 6 subordinate devices. The bridge has advanced VC
arbitration and PCI port arbitration features for upstream traffic. When these arbitration features are fully
utilized, bridge throughput performance may be tuned for a variety of complex applications.
Power management (PM) features include active state link PM, PME mechanisms, the beacon and wake
protocols, and all conventional PCI D-states. If the active state link PM is enabled, then the link automatically
saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and PME-to-ACK
messages are supported. Standard PCI bus power management features provide several low power modes,
which enable the host system to further reduce power consumption.
The bridge has additional capabilities including, but not limited to, serial IRQ with MSI messages, serial
EEPROM, power override, clock run, and PCI bus LOCK
(GPIOs) are provided for further system control and customization.
2.2 Related Documents
• PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
• PCI Express Base Specification, Revision 1.0a
• PCI Express Card Electromechanical Specification, Revision 1.0a
• PCI Local Bus Specification, Revision 2.3
• PCI-to-PCI Bridge Architecture Specification, Revision 1.2
• PCI Bus Power Management Interface Specification, Revision 1.1 or 1.2
• PCI Mobile Design Guide, Revision 1.1
• Serialized IRQ Support for PCI Systems, Revision 6.0
• PCI Express Jitter and BER White Paper
. Also, eight general-purpose inputs and outputs
2.3 Trademarks
• PCI Express is a trademark of PCI-SIG
• TI and MicroStar BGA are trademarks of Texas Instruments
• Other trademarks are the property of their respective owners
2
April 2007 Revised October 2008SCPS155C
Page 12
2.4 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are
listed below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary
field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a
12-bit hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number are
assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, GRST
logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. Differential signal names end with P, N, +, or − designators. The P or + designators signify the positive
signal associated with the differential pair . The N or − designators signify the negative signal associated
with the differential pair.
6. RSVD indicates that the referenced item is reserved.
7. The power and ground signals in Figure 2−1 are not subscripted to aid in readability.
8. In Sections 4 through 6, the configuration space for the bridge is defined. For each register bit, the software
access method is identified in an access column. The legend for this access column includes the following
entries:
r – read access by software
u – updates by the bridge internal hardware
w – write access by software
c – clear an asserted status bit with a write-back of 1b by software
Introduction
), then this indicates the
2.5 Document History
REVISION
DATE
05/2004 − Product preview
08/2005 A Initial release
REVISION
NUMBER
REVISION COMMENTS
2.6 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
XIO2000A PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
XIO2000A PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
XIO2000A PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
XIO2000A PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
XIO2000AI PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
XIO2000AI PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
XIO2000AI PCI-Express to PCI Bridge 3.3-V, 5.0-V tolerant PCI bus I/Os with
3.3-V and 1.5-V power terminals
201-terminal GZZ MicroStar
201-terminal ZZZ (Lead-Free)
MicroStar PBGA
175-terminal ZHH (Lead-Free)
MicroStar PBGA
175-terminal ZHC (Lead-Free)
MicroStar PBGA
201-terminal ZZZ (Lead-Free)
MicroStar PBGA
175-terminal ZHH (Lead-Free)
MicroStar PBGA
175-terminal ZHC (Lead-Free)
MicroStar PBGA
PBGA
April 2007 Revised October 2008 SCPS155C
3
Page 13
Introduction
2.7 Terminal Assignments
The XIO2000A is available in either a 201-ball GZZ/ZZZ MicroStarTM BGA or a 175−ball ZHH/ZHC Microstar
package. The XIO2000AI is available in a 201-ball ZZZ MicroStar BGA or a 175-ball ZHH MicroStar package.
Figure 2−1 shows a terminal diagram of the GZZ/ZZZ package, and Table 2−1 lists the GZZ/ZZZ terminals
sorted alphanumerically.
Figure 2−2 shows a terminal diagram of the ZHH package, and Table 2−2 lists the ZHH package terminals
sorted alphanumerically.
Figure 2−3 shows a terminal diagram of the ZHC package, and Table 2−3 lists the ZHC package terminals
sorted alphanumerically.
Table 2−4 shows the terminals by the alphabetically sorted signal names for both packages.
4
April 2007 Revised October 2008SCPS155C
Page 14
Introduction
1234567891011121314151617
GPIO1 //
U
INTC PRST LOCK
PWR_
GPIO3 GPIO6 GPIO7 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
OVRD
T INTB INTD SERIRQ
GPIO0 //
CLKRUN
R M66EN INTA VSS VDD_33 VSS
GPIO2
GPIO5 //
SDA
GPIO4 //
SCL
RSVD RSVD RSVD RSVD RSVD VDD_33 RSVD RSVD RSVD
RSVD RSVD VSS VSS VSS VSS VDD_33 RSVD VSS
P AD30 AD31 CLK VDD_15 VSS VDD_33 VDD_33 VDD_33 VDD_15 RSVD RSVD
N AD28 AD29 VSS RSVD RSVD GRST
M AD26 AD27 VDD_33 PME WAKE
VDD_33
L AD23 C/BE[3] AD24 AD25 VSS VSS VSS VSS VSS
K AD20 AD21 AD22 VSS VSS VSS VSS VSS VSS
J VCCP AD19 AD18 VDD_15 VSS VSS VSS VSS VSS
H C/BE[2] AD17 AD16 VDD_33 VSS VSS VSS VSS VSS
G FRAME IRDY TRDY VSS VSS VSS VSS VSS VSS VSSA
_COMB
VDD_33
VDDA_15VDDA_
VSSA
IO
VDDA_33VDD_33
_AUX
15
VDD_
VSSA TXN TXP
15
VDDA_
15
VDD_15
_COMB
REF0_
REF1_
PCIE
PCIE
_COMB
VSSA PERST
VSSA VSS
VSS
F DEVSEL STOP PERR VSSA VSSA
VDDA_
E SERR PAR VDD_33 VSSA RXN RXP
CLK
OUT6
GNT5
VDDA_
33
CLKRUN
_EN
EXT_
ARB_EN
RSVD RSVD
REF
CLK−
VSSA
REFCLK
_SEL
REF
CLK+
D C/BE[1] AD15 VSS AD3 VSS VDD_15 VDD_33 VSS
C AD14 AD13 AD8 VSS VDD_33 AD2
B AD12 AD10 C/BE[0] AD7 AD5 AD1 REQ0
A AD11 AD9 VCCP AD6 AD4 AD0 GNT0 GNT1 GNT2
CLK
REQ1 REQ2 GNT3 GNT4 VDD_33 VSS
OUT0
CLK
CLK
OUT1
REQ3 REQ4 REQ5
OUT2
CLK
OUT3
CLK
OUT4
CLK
OUT5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Figure 2−1. XIO2000A GZZ MicroStar BGA Package,
XIO2000A/XIO2000AI ZZZ MicroStar BGA Package(Bottom View)
15
April 2007 Revised October 2008 SCPS155C
5
Page 15
Introduction
Table 2−1. GZZ/ZZZ Terminals Sorted Alphanumerically
BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME
A02 AD11 C17 REFCLK+ H10 V
A03 AD9 D01 C/BE[1] H11 V
A04 V
A05 AD6 D03 V
A06 AD4 D07 AD3 H16 TXN
A07 AD0 D08 V
A08 GNT0 D09 V
A09 GNT1 D10 V
A10 GNT2 D11 V
A11 CLKOUT3 D15 V
A12 CLKOUT4 D16 RSVD J07 V
A13 CLKOUT5 D17 RSVD J08 V
A14 GNT5 E01 SERR J09 V
A15 EXT_ARB_EN E02 PAR J10 V
A16 REFCLK_SEL E03 V
B01 AD12 E15 V
B03 AD10 E16 RXN J15 V
B04 C/BE[0] E17 RXP J16 V
B05 AD7 F01 DEVSEL J17 PERST
B06 AD5 F02 STOP K01 AD20
B07 AD1 F03 PERR K02 AD21
B08 REQ0 F15 V
B09 CLKOUT1 F16 V
B10 CLKOUT2 F17 V
B11 REQ3 G01 FRAME K08 V
B12 REQ4 G02 IRDY K09 V
B13 REQ5 G03 TRDY K10 V
B14 CLKOUT6 G04 V
B15 CLKRUN_EN G07 V
B17 V
C01 AD14 G09 V
C02 AD13 G10 V
C04 AD8 G11 V
C05 V
C06 V
C07 AD2 G16 V
C08 CLKOUT0 G17 V
C09 REQ1 H01 C/BE[2] L08 V
C10 REQ2 H02 AD17 L09 V
C11 GNT3 H03 AD16 L10 V
C12 GNT4 H04 V
C13 V
C14 V
C16 REFCLK− H09 V
CCP
SSA
SS
DD_33
DD_33
SS
D02 AD15 H14 V
H15 V
H17 TXP
J01 V
J02 AD19
J03 AD18
J04 V
J11 V
J14 V
K03 AD22
K04 V
K07 V
K11 V
K14 V
K15 V
K16 V
K17 V
L01 AD23
L02 C/BE[3]
L03 AD24
L04 AD25
L07 V
L11 V
L14 V
L15 V
L16 REF0_PCIE
G08 V
G14 V
G15 V
H07 V
H08 V
SS
SS
DD_15
DD_33
SS
DDA_33
DD_33
SSA
SSA
SSA
DDA_15
SS
SS
SS
SS
SS
SS
SSA
DDA_15
SSA
SS
DD_33
SS
SS
SS
SS
SS
DD_15
SSA
CCP
DD_15
SS
SS
SS
SS
SS
DDA_15
DDA_15
SSA
SS
SS
SS
SS
SS
SS
DD_33_AUX
DDA_33
DD_33_COMB
SS
SS
SS
SS
SS
SS
DD_33_COMBIO
SSA
6
April 2007 Revised October 2008SCPS155C
Page 16
Introduction
Table 2−1. GZZ/ZZZ Terminals Sorted Alphanumerically (Continued)
BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME
L17 REF1_PCIE P17 RSVD T09 RSVD
M01 AD26 R01 M66EN T10 RSVD
M02 AD27 R02 INTA T11 RSVD
M03 V
M15 PME R05 V
M16 WAKE R06 V
M17 V
N01 AD28 R08 RSVD T17 RSVD
N02 AD29 R09 RSVD U02 INTC
N03 V
N15 RSVD R11 V
N16 RSVD R12 V
N17 GRST R13 V
P01 AD30 R14 V
P02 AD31 R16 RSVD U08 GPIO7
P03 CLK R17 V
P07 V
P08 V
P09 V
P10 V
P11 V
P15 V
P16 RSVD T08 RSVD U16 RSVD
DD_33
DD_15_COMB
SS
DD_15
SS
DD_33
DD_33
DD_33
DD_15
R04 V
R07 GPIO4 // SCL T15 RSVD
R10 V
T01 INTB U10 RSVD
T03 INTD U11 RSVD
T04 SERIRQ U12 RSVD
T05 GPIO0 // CLKRUN U13 RSVD
T06 GPIO2 U14 RSVD
T07 GPIO5 // SDA U15 RSVD
SS
DD_33
SS
SS
SS
SS
SS
DD_33
SS
T12 RSVD
T13 V
T14 RSVD
U03 PRST
U04 LOCK
U05 GPIO1 // PWR_OVRD
U06 GPIO3
U07 GPIO6
U09 RSVD
DD_33
April 2007 Revised October 2008 SCPS155C
7
Page 17
Introduction
1234567891011121314
LOCKPRST
P
INTB INTC SERIRQ GPIO2 GPIO5 // SDA VDD_15
N
M66EN INTA INTD GPIO3
M
AD31 CLK VDD_15 PME GRST
L
AD26 AD27 AD28 VDD_33
K
AD23 AD24 AD25
J J
AD19 AD21 AD20 AD22
H H
VCCP VDD_15 VSSA TXN
G
FRAME C/BE[2] VSS
F F
F
TRDY R
E
LOCKPRST
C/BE[3] VDDA_33 VDD_33_ REF1_PCIE
AD17 AD18
DEVSEL STOP IRDY RXN RXP
GPIO0//
CLKRUN
GPIO1//
PWR_OVER
C
GPIO4 // SCL VSSA RSVD
G
G VSS VDD_33
VDD_33
VDD_33
VDD_33 VDD_33
VSS VSS VSS
VSS VSS VSS
VDD_33AD16
VSS VSS
VSSRSVD VSS RSVDGPIO7AD30 AD29
VSS
VSS
VDD_33VSS VSS
RSVD
VDD_33VDD_33
VDD_33VDD_33
VSSA WAKE
VDDA_15
RSVDRSVDRSVDRSVDRSVDRSVDRSVD
VDD_33_
COMBIO
AUX
PERST VDDA_15
VSSA TXP
V
VSSAVDDA_15
VSS
VDD_15_
COMB
RSVDRSVDRSVDRSVDRSVDRSVDRSVD
RSVDRSVDRSVDRSVDRSVDGPIO6
REF0_PCIE
VDD_33_
COMB
VDD_15VSSVDDA_15VSSA
P
P
N
N
M
M
L
L
K
K
J
H
G
G
F
E
E
SERR PAR PERR AD1 CLKOUT0 GNT4
D D
C/BE[1]
C
AD13 AD12 AD10 AD6 AD4C/BE[0]
B B
A
AD15 GNT0 REQ2 GNT5 REFCLK+
AD11 AD9 AD5 AD2 AD0 REQ1 CLKOUT2
AD14 AD8 AD7 AD3 GNT1
VDD_33 VDD_33 VDD_33VDD_15
REQ0 CLKOUT1
VCCP REFCLK_SEL
CLKOUT3 VSSA RSVD RSVD
VDDA_33 REFCLK−GNT3
GNT5
GNT3
CLKOUT4 CLKOUT5 VSSA
EXT_ARB_EN CLKRUN_EN
REQ4REQ3 CLKOUT6
REQ5
1234567891011121314
Figure 2−2. XIO2000A/XIO2000AI ZHH Microstar BGA Package (Bottom View)
D
C
C
B
A
A
8
April 2007 Revised October 2008SCPS155C
Page 18
Introduction
Table 2−2. ZHH Terminals Sorted Alphanumerically
BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME
A02 AD11 D04 V
A03 AD9 D05 V
A04 V
A05 AD5 D07 CLKOUT0 H06 V
A06 AD2 D08 V
A07 AD0 D09 V
A08 REQ1 D10 CLKOUT3 H09 V
A09 CLKOUT2 D11 GNT4 H11 V
A10 REQ3 D12 V
A11 REQ4 D13 RSVD H13 V
A12 REQ5 D14 RSVD H14 V
A13 CLKOUT6 E01 TRDY J01 AD23
A14 REFCLK_SEL E02 DEVSEL J02 C/BE[3]
B01 AD13 E03 STOP J03 AD24
B02 AD12 E04 IRDY J04 AD25
B03 AD10 E11 V
B04 C/BE[0] E12 V
B05 AD6 E13 RXN J08 V
B06 AD4 E14 RXP J09 V
B07 REQ0 F01 FRAME J11 V
B08 CLKOUT1 F02 C/BE[2] J12 V
B09 GNT2 F03 AD16 J13 REF1_PCIE
B10 CLKOUT4 F04 V
B11 CLKOUT5 F06 V
B12 EXT_ARB_EN F07 V
B13 CLKRUN_EN F08 V
B14 V
C01 C/BE[1] F11 V
C02 AD15 F12 V
C03 AD14 F13 V
C04 AD8 F14 V
C05 AD7 G01 V
C06 AD3 G02 AD17 L02 AD30
C07 GNT0 G03 AD18 L03 CLK
C08 GNT1 G04 V
C09 REQ2 G06 V
C10 GNT3 G07 V
C11 GNT5 G08 V
C12 V
C13 REFCLK+ G11 V
C14 REFCLK− G12 V
D01 SERR G13 TXN L11 V
D02 PAR G14 TXP L12 PME
D03 PERR H01 AD19 L13 GRST
CCP
SSA
DDA_33
D06 AD1 H04 AD22
F09 V
G09 V
DD_33
DD_33
DD_15
DD_33
SSA
DDA_15
SSA
DD_33
SS
SS
SS
DD_33
SSA
DDA_15
SS
DD_15
CCP
DD_15
SS
SS
SS
SS
SSA
SSA
H02 AD21
H03 AD20
SS
H07 V
H08 V
H12 PERST
J06 V
J07 V
J14 REF0_PCIE
K01 AD26
K02 AD27
K03 AD28
K04 V
K11 V
K12 V
K13 V
K14 WAKE
L01 AD31
L04 AD29
L05 V
L06 GPIO7
L07 RSVD
L08 V
L09 V
L10 RSVD
SS
SS
SS
DDA_15
DDA_15
DD_33_COMB
DD_33
DD_33
SS
SS
DDA_33
DD_33_AUX
DD_33
SSA
DD_33_COMBIO
DD_15_COMB
DD_15
DD_33
SS
SS
April 2007 Revised October 2008 SCPS155C
9
Page 19
Introduction
Table 2−2. ZHH Terminals Sorted Alphanumerically (Continued)
BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME
L14 RSVD N01 INTB P02 LOCK
M01 M66EN N02 INTC P03 GPIO0 // CLKRUN
M02 INTA N03 SERIRQ P04 GPIO1 // PWR_OVER
M03 INTD N04 GPIO2 P05 GPIO4 // SCL
M04 GPIO3 N05 GPIO5 // SDA P06 RSVD
M05 GPIO6 N06 RSVD P07 RSVD
M06 RSVD N07 RSVD P08 RSVD
M07 RSVD N08 RSVD P09 RSVD
M08 V
M09 V
M10 V
M11 V
M12 RSVD N13 V
M13 RSVD N14 RSVD
M14 RSVD P01 PRST
SS
DD_33
DD_33
DD_33
N09 RSVD P10 RSVD
N10 RSVD P11 RSVD
N11 RSVD P12 RSVD
N12 V
DD_15
SS
P13 V
P14 RSVD
SSA
10
April 2007 Revised October 2008SCPS155C
Page 20
Introduction
ABCDEFGH JKLMNP
14
13
12
CLKOUT4
11
10
9
CLKOUT2 REQ3
8
CLKOUT1 REQ1
7
6
5
REFCLK–VSSA
CLKRUN_EN VDDA_33 RXP RSVD
GNT5
GNT4
GNT2
AD0 CLKOUT0
AD1 AD2
AD4 AD5 AD6 AD8
REQ5 EXT_ARB_EN
GNT3
REQ2
REQ0
REFCLK+
CLKOUT6
CLKOUT5 VDD_33
GNT1
GNT0
RSVD
VDDA_15
RSVD
REFCLK_SEL
CLKOUT3
VDD_15
VDD_33AD3
RXN RSVD RSVD
VSS
VDD_15_
COMB
RSVD
VSSA
VDDA_15
VSSA
VDD_33 VSS
VSS VSS VSS
VSS VSS VSS
VSS
VSSA
VDDA_15
VDD_33_
COMB
VSS VSS
REF1_PCIEVDDA_15TXNVSS
VDD_33_
COM_IO
VDDA_33REQ4
VDD_33
VDD_33VSS VSS
WAKEREF0_PCIEVDD_33_AUXPERSTTXPVDD_15
RSVD
VSSA
VDD_33
VDD_33
VDD_33
RSVD
GPIO7
VDD_15
PME
VDD_15
VSSVSSAVSSAVSSA
RSVD
VSS
VSS
RSVD RSVD
GPIO6
GPIO2 GPIO5 // SDA
RSVD
RSVD
RSVDRSVD
RSVD
RSVD
RSVD
RSVDGRST
VDD_33
VSS
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
14
13
12
11
10
9
8
7
6
5
AD31
GPIO0
/CLKRUN
INTD
M66EN
GPIO3 GPIO4/SCL
SERIRQ
INTCINTA
INTB
4
3
2
1
AD7
AD9
AD11
VCCP
AD10
AD12
AD13
C/BE(0)
AD14
AD15
PERR
VDD_33
STOP
DEVSEL
PAR
C/BE(1)
SERR
IRDY
FRAME
VDD_33
TRDY
C/BE(2)
AD16
VDD_15
AD17
VCCP
AD18
AD22
AD20
AD19 AD23
AD24
AD25
AD28
AD29
AD26
VDD_33
CLK
AD30AD27C/BE(3)AD21
ABCDEFGH JKLMNP
Figure 2−3. XIO2000A/XIO2000AI ZHC Microstar BGA Package (Bottom View)
GPIO1/
PWR_OVER
LOCK
PRST
4
3
2
1
April 2007 Revised October 2008 SCPS155C
11
Page 21
Introduction
Table 2−3. ZHC Terminal Names Sorted Alphanumerically
BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME
A02 AD11 D04 VDD_33 H02 AD21
A03 AD9 D05 AD8 H03 AD20
A04 AD7 D06 VDD_33 H04 AD22
A05 AD4 D07 CLKOUT0 H06 VSS
A06 AD1 D08 VDD_15 H07 VSS
A07 AD0 D09 CLKOUT3 H08 VSS
A08 CLKOUT1 D10 VDD_33 H09 VSS
A09 CLKOUT2 D11 REFCLK_SEL H11 VDDA_15
A10 GNT2 D12 RSVD H12 VDD_33_COMB
A11 CLKOUT4 D13 VDDA_15 H13 VDDA_15
A12 GNT4 D14 RSVD H14 PERST
A13 GNT5 E01 FRAME J01 AD23
A14 VSSA E02 IRDY J02 C/BE(3)
B01 AD13 E03 SERR J03 AD25
B02 AD12 E04 C/BE[1] J04 AD24
B03 AD10 E11 VDDA_15 J06 VDD_33
B04 VCCP E12 VSSA J07 VDD_33
B05 AD5 E13 RXP J08 VSS
B06 AD2 E14 RXN J09 VSS
B07 REQ0 F01 AD16 J11 VDDA_33
B08 REQ1 F02 C/BE[2] J12 VDD_33_COMB_IO
B09 REQ2 F03 TRDY J13 REF1_PCIE
B10 GNT3 F04 VDD_33 J14 VDD_33_AUX
B11 REQ4 F06 VSS K01 AD26
B12 REQ5 F07 VSS K02 AD27
B13 CLKRUN_EN F08 VSS K03 AD29
B14 REFCLK− F09 VDD_33 K04 AD28
C01 PERR F11 VSSA K11 VSSA
C02 AD15 F12 VSSA K12 RSVD
C03 AD14 F13 VSS K13 VDD_15_COMB
C04 C/BE[0] F14 VDD_15 K14 REF0_PCIE
C05 AD6 G01 AD18 L01 AD31
C06 AD3 G02 VCCP L02 AD30
C07 GNT0 G03 AD17 L03 CLK
C08 GNT1 G04 VDD_15 L04 VDD_33
C09 REQ3 G06 VSS L05 VDD_15
C10 CLKOUT5 G07 VSS L06 GPIO7
C11 CLKOUT6 G08 VSS L07 RSVD
C12 EXT_ARB_EN G09 VSS L08 VDD_33
C13 VDDA_33 G11 VSSA L09 VDD_33
C14 REFCLK+ G12 VSSA L10 VDD_33
D01 DEVSEL G13 TXN L11 VSSA
D02 STOP G14 TXP L12 RSVD
D03 PAR H01 AD19 L13 GRST
12
April 2007 Revised October 2008SCPS155C
Page 22
Introduction
Figure 2−3. ZHC Terminal Names Sorted Alphanumarically (Continued)
BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME BGA BALL # SIGNAL NAME
L14 WAKE N01 INTB P02 LOCK
M01 M66EN N02 INTC P03 GPIO1 // PWR_OVER
M02 INTA N03 SERIRQ P04 GPIO4 // SCL
M03 INTD N04 GPIO3 P05 RSVD
M04 GPIO0 // CLKRUN N05 GPIO5 // SDA P06 RSVD
M05 GPIO2 N06 RSVD P07 RSVD
M06 GPIO6 N07 RSVD P08 RSVD
M07 RSVD N08 RSVD P09 RSVD
M08 VSS N09 RSVD P10 RSVD
M09 VSS N10 RSVD P11 VSS
M10 RSVD N11 RSVD P12 VDD_33
M11 RSVD N12 RSVD P13 RSVD
M12 VSS N13 VDD_15 P14 RSVD
M13 RSVD N14 RSVD
M14 PME P01 PRST
April 2007 Revised October 2008 SCPS155C
13
Page 23
Introduction
Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically
SIGNAL NAME
AD0 A07 A07 A07 CLKOUT5 A13 C10 B11
AD1 B07 A06 D06 CLKOUT6 B14 C11 A13
AD2 C07 B06 A06 CLKRUN_EN B15 B13 B13
AD3 D07 C06 C06 DEVSEL F01 D01 E02
AD4 A06 A05 B06 EXT_ARB_EN A15 C12 B12
AD5 B06 B05 A05 FRAME G01 E01 F01
AD6 A05 C05 B05 GNT0 A08 C07 C07
AD7 B05 A04 C05 GNT1 A09 C08 C08
AD8 C04 D05 C04 GNT2 A10 A10 B09
AD9 A03 A03 A03 GNT3 C11 B10 C10
AD10 B03 B03 B03 GNT4 C12 A12 D11
AD11 A02 A02 A02 GNT5 A14 A13 C11
AD12 B01 B02 B02 GPIO0 // CLKRUN T05 M04 P03
AD13 C02 B01 B01 GPIO1 // PWR_OVRD U05 P03 P04
AD14 C01 C03 C03 GPIO2 T06 M05 N04
AD15 D02 C02 C02 GPIO3 U06 N04 M04
AD16 H03 F01 F03 GPIO4 // SCL R07 P04 P05
AD17 H02 G03 G02 GPIO5 // SDA T07 N05 N05
AD18 J03 G01 G03 GPIO6 U07 M06 M05
AD19 J02 H01 H01 GPIO7 U08 L06 L06
AD20 K01 H03 H03 GRST N17 L13 L13
AD21 K02 H02 H02 INTA R02 M02 M02
AD22 K03 H04 H04 INTB T01 N01 N01
AD23 L01 J01 J01 INTC U02 N02 N02
AD24 L03 J04 J03 INTD T03 M03 M03
AD25 L04 J03 J04 IRDY G02 E02 E04
AD26 M01 K01 K01 LOCK U04 P02 P02
AD27 M02 K02 K02 M66EN R01 M01 M01
AD28 N01 K04 K03 PAR E02 D03 D02
AD29 N02 K03 L04 PERR F03 C01 D03
AD30 P01 L02 L02 PERST J17 H14 H12
AD31 P02 L01 L01 PME M15 M14 L12
C/BE[0] B04 C04 B04 PRST U03 P01 P01
C/BE[1] D01 E04 C01 REF0_PCIE L16 K14 J14
C/BE[2] H01 F02 F02 REF1_PCIE L17 J13 J13
C/BE[3] L02 J02 J02 REFCLK_SEL A16 D11 A14
CLK P03 L03 L03 REFCLK− C16 B14 C14
CLKOUT0 C08 D07 D07 REFCLK+ C17 C14 C13
CLKOUT1 B09 A08 B08 REQ0 B08 B07 B07
CLKOUT2 B10 A09 A09 REQ1 C09 B08 A08
CLKOUT3 A11 D09 D10 REQ2 C10 B09 C09
CLKOUT4 A12 A11 B10 REQ3 B11 C09 A10
GZZ/ZZZ
BALL #
ZHC
BALL #
ZHH
BALL #
SIGNAL NAME
GZZ/ZZZ
BALL #
ZHC
BALL #
BALL #
ZHH
14
April 2007 Revised October 2008SCPS155C
Page 24
Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
REQ4 B12 B11 A11 V
REQ5 B13 B12 A12 V
RSVD D16 D12 D13 V
RSVD D17 D14 D14 V
RSVD N15 K12 L07 V
RSVD N16 L07 L10 V
RSVD P16 L12 L14 V
RSVD P17 M07 M14 V
RSVD R08 M10 M06 V
RSVD R09 M11 P07 V
RSVD R16 M13 N14 V
RSVD T08 N06 M12 V
RSVD T09 N07 M07 V
RSVD T10 N08 M13 V
RSVD T11 N09 N06 V
RSVD T12 N10 N08 V
RSVD T14 N11 N09 V
RSVD T15 N12 N10 V
RSVD T17 N14 N11 V
RSVD U09 P05 P06 V
RSVD U10 P06 N07 V
RSVD U11 P07 P08 V
RSVD U12 P08 P09 V
RSVD U13 P09 P10 V
RSVD U14 P10 P11 V
RSVD U15 P13 P12 V
RSVD U16 P14 P14 V
RXN E16 E14 E13 V
RXP E17 E13 E14 V
SERIRQ T04 N03 N03 V
SERR E01 E03 D01 V
STOP F02 D02 E03 V
TRDY G03 F03 E01 V
TXN H16 G13 G13 V
TXP H17 G14 G14 V
V
CCP
V
CCP
V
DD_15
V
DD_15
V
DD_15
V
DD_15
V
DD_15
GZZ/ZZZ
BALL #
A04 B04 A04 V
J01 G02 G01 V
D09 D08 D08 V
H14 F14 F14 V
J04 G04 G04 V
P07 L05 L05 V
P15 N13 N12 V
ZHC
BALL #
ZHH
BALL #
SIGNAL NAME
DD_15_COMB
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33
DD_33_AUX
DD_33_COMB
DD_33_COMBIO
DDA_15
DDA_15
DDA_15
DDA_15
DDA_33
DDA_33
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
Introduction
GZZ/ZZZ
BALL #
M17 K13 K13
C06 D04 D04
C13 D06 D05
D10 D10 D09
E03 F04 F04
H04 F09 F09
M03 J06 J06
P09 J07 J07
P10 L04 K04
P11 L08 L08
R05 L09 M09
R14 L10 M10
T13 P12 M11
K14 J14 J12
K16 H12 H14
L14 J12 K12
F17 D13 E11
G15 E11 F12
J14 H11 H11
J15 H13 H13
D15 C13 C12
K15 J11 J11
C05 F06 F06
C14 F07 F07
D03 F08 F08
D08 F13 F13
D11 G06 G06
G04 G07 G07
G17 G08 G08
K04 G09 G09
K17 H06 H06
N03 H07 H07
P08 H08 H08
R04 H09 H09
R06 J08 J08
R10 J09 J09
R11 M08 L09
R12 M09 L11
R13 M12 M08
R17 P11 N13
G07
G08
ZHC
BALL #
ZHH
BALL #
April 2007 Revised October 2008 SCPS155C
15
Page 25
Introduction
SIGNAL NAME
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
Table 2−4. XIO2000A/XIO2000AI Signal Names Sorted Alphabetically (Continued)
GZZ/ZZZ
BALL #
G09 V
G10 V
G11 V
H07 V
H08 V
H09 V
H10 V
H11 V
J07 V
J08 V
J09 V
J10 V
J11 V
K07 V
K08 V
K09 WAKE M16 L14 K14
K10
ZHC
BALL #
ZHH
BALL #
SIGNAL NAME
SS
SS
SS
SS
SS
SS
SSA
SSA
SSA
SSA
SSA
SSA
SSA
SSA
SSA
GZZ/ZZZ
BALL #
K11
L07
L08
L09
L10
L11
B17 A14 B14
E15 E12 D12
F15 F11 E12
F16 F12 F11
G14 G11 G11
G16 G12 G12
H15 K11 K11
J16 L11 P13
L15
ZHC
BALL #
ZHH
BALL #
2.8 Terminal Descriptions
Table 2−5 through Table 2−12 give a description of the terminals. These terminals are grouped in tables by
functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.
The following list describes the different input/output cell types that appear in the terminal description tables:
• HS DIFF IN = High speed differential input.
• HS DIFF OUT = High speed differential output.
• PCI BUS = PCI bus 3-state bidirectional buffer with 3.3-V or 5.0-V clamp rail.
• LV CMOS = 3.3-V low voltage CMOS input or output with 3.3-V clamp rail.
• BIAS = Input/output terminals that generate a bias voltage to determine a driver’s operating current.
• Feed through = these terminals connect directly to macros within the part and not through an input or
output cell.
• PWR = Power terminal
• GND = Ground terminal
16
April 2007 Revised October 2008SCPS155C
Page 26
SIGNAL
V
CCP
V
DD_15
V
DDA_15
V
DD_33
V
DD_33_AUX
V
DDA_33
SIGNAL
V
SS
V
SS
V
SSA
Table 2−5. Power Supply Terminals
GZZ/ZZZ
BALL #
A04, J01 B04, G02 A04, G01 PWR
D09, H14, J04,
P07, P15
F17, J14, J15,
G15
C06, C13, D10,
E03, H04, M03,
P09, P10, P11,
R05, R14, T13
K14 J14 J12 PWR
D15, K15 C13, J11 C12, J11 PWR Pi filter 3.3-V analog power terminal
ZHC
BALL #
D08, F14, G04,
L05, N13
D13, E11, H11,
H13
D04, D06, D10,
F04, F09, J06,
J07, L04, L08,
L09, L10, P12
ZHH
BALL #
D08, F14, G04,
L05, N12
E11, F12, H11,
H13
D04, D05, D09,
F04, F09, J06,
J07, K04, L08,
M09, M10, M11
I/O
TYPE
PWR
PWR Pi filter 1.5-V analog power terminal
PWR
EXTERNAL
PARTS
Bypass
capacitors
Bypass
capacitors
Bypass
capacitors
Bypass
capacitors
5.0-V or 3.3-V PCI bus clamp voltage
to set maximum I/O voltage tolerance
of the secondary PCI bus signals
1.5-V digital core power terminals
3.3-V digital I/O power terminals
3.3-V auxiliary power terminal
Note: This terminal is connected to
VSS through a pulldown resistor if no
auxiliary supply is present.
DESCRIPTION
Table 2−6. Ground Terminals
GZZ/ZZZ
BALL #
C05, C14, D03, D08, D11,
G04, G17, K04, K17, N03,
P08, R04, R06, R10, R11,
R12, R13, R17
G07, G08, G09, G10, G11,
H07, H08, H09, H10, H11,
J07, J08, J09, J10, J11,
K07, K08, K09, K10, K11,
L07, L08, L09, L10, L11
B17, E15, F15, F16, G14,
G16, H15, J16, L15
F06, F07, F08, F13, G06,
G07, G08, G09, H06, H07,
H08, H09, J08, J09, M08,
A14, E12, F11, F12, G11,
ZHC
BALL #
F06, F07, F08, F13, G06,
G07, G08, G09, H06, H07,
H08, H09, J08, J09, L09,
M09, M12, P11
GND
B14, D12, E12, F11, G11,
G12, K11, L11
ZHH
BALL #
L11, M08, N13
G12, K11, P13
I/O
TYPE
GND Digital ground terminals
Ground terminals for
thermally-enhanced
package
GND Analog ground terminal
Introduction
DESCRIPTION
Table 2−7. Combined Power Outputs
SIGNAL
V
DD_15_COMB
V
DD_33_COMB
V
DD_33_COMBIO
April 2007 Revised October 2008 SCPS155C
GZZ/ZZZ
BALL #
M17 K13 K13
K16 H12 H14
L14 J12 K12
ZHC
BALL #
ZHH
BALL #
I/O
TYPE
Feed
through
Feed
through
Feed
through
EXTERNAL
PARTS
Bypass
capacitors
Bypass
capacitors
Bypass
capacitors
DESCRIPTION
Internally-combined 1.5-V main and V
external bypass capacitor filtering. Supplies all internal
1.5-V circuitry powered by V
Caution: Do not use this terminal to supply external power
to other devices.
Internally-combined 3.3-V main and V
external bypass capacitor filtering. Supplies all internal
3.3-V circuitry powered by V
Caution: Do not use this terminal to supply external power
to other devices.
Internally-combined 3.3-V main and V
external bypass capacitor filtering. Supplies all internal
3.3-V input/output circuitry powered by V
Caution: Do not use this terminal to supply external power
to other devices.
AUX
AUX
.
.
power output for
AUX
power output for
AUX
power output for
AUX
.
AUX
17
Page 27
Introduction
Table 2−8. PCI Express Terminals
GZZ/
SIGNAL
PERST J17 H14 H12 I
REF0_PCIE
REF1_PCIE
RXP
RXN
TXP
TXN
WAKE M16 L14 K14 O
ZZZ
BALL #
L16
L17
E17
E16
H17
H16
ZHC
BALL #
K14
J13
E13
E14
G14
G13
ZHH
BALL #
J14
J13
E14
E13
G14
G13
I/O
TYPE
I/O BIAS −
DO
CELL
TYPE
LV
HS
HS
LV
V
COMBIO
V
COMBIO
CMOS
DI
DIFF IN
DIFF
OUT
CMOS
CLAMP
RAIL
DD_33_
V
SS
V
DD_15
DD_33_
EXTERNAL
PARTS
−
External
resistor
−
Series
capacitors
−
DESCRIPTION
PCI Express reset input. The PERST
signal identifies when the system power is
stable and generates an internal power on
reset.
Note: The PERST
hysteresis.
External reference resistor + and −
terminals for setting TX driver current. An
external resistor is connected between
terminals L16 and L17.
High-speed receive pair. RXP and RXN
comprise the differential receive pair for the
single PCI Express lane supported.
High-speed transmit pair. TXP and TXN
comprise the differential transmit pair for
the single PCI Express lane supported.
Wake is an active low signal that is driven
low to reactivate the PCI Express link
hierarchy’s main power rails and reference
clocks.
Note: Since WAKE
buffer, a system side pullup resistor is
required.
input buffer has
is an open-drain output
18
April 2007 Revised October 2008SCPS155C
Page 28
Table 2−9. Clock Terminals
SIGNAL
REFCLK_SEL A16 D11 A14 I
REFCLK+ C17 C14 C13 DI
REFCLK− C16 B14 C14 DI
CLK P03 L03 L03 I
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUT6
GZZ/ZZZ
BALL #
C08
B09
B10
A11
A12
A13
B14
ZHC
BALL #
D07
A08
A09
D09
A11
C10
C11
ZHH
BALL #
D07
B08
A09
D10
B10
B11
A13
I/O
TYPE
Introduction
CELL
TYPE
CMOS
DIFF
DIFF
PCI
Bus
O
PCI
Bus
LV
HS
IN
HS
IN
CLAMP
RAIL
V
DD_33
V
DD_33
V
DD_33
V
CCP
V
CCP
EXTERNAL
PARTS
Pullup or
pulldown
resistor
−
Capacitor to
VSS for
single-ended
mode
−
−
DESCRIPTION
Reference clock select. This
terminal selects the reference
clock input.
0 = 100-MHz differential
common reference clock
used.
1 = 125-MHz single-ended,
reference clock used.
Reference clock. REFCLK+ and
REFCLK− comprise the
differential input pair for the
100-MHz system reference
clock. For a single-ended,
125-MHz system reference
clock, use the REFCLK+ input.
Reference clock. REFCLK+ and
REFCLK− comprise the
differential input pair for the
100-MHz system reference
clock. For a single-ended,
125-MHz system reference
clock, attach a capacitor from
REFCLK− to VSS.
PCI clock input. This is the clock
input to the PCI bus core.
PCI clock outputs. These clock
outputs are used to clock the
PCI bus. If the bridge PCI bus
clock outputs are used, then
CLKOUT6 must be connected to
the CLK input.
April 2007 Revised October 2008 SCPS155C
19
Page 29
Introduction
Table 2−10. PCI System Terminals
SIGNAL
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE[3]
C/BE[2]
C/BE[1]
C/BE[0]
DEVSEL F01 D01 E02 I/O
FRAME G01 E01 F01 I/O
GNT5
GNT4
GNT3
GNT2
GNT1
GNT0
INTA
INTB
INTC
INTD
IRDY G02 E02 E04 I/O
GZZ/ZZZ
BALL #
P02
P01
N02
N01
M02
M01
L04
L03
L01
K03
K02
K01
J02
J03
H02
H03
D02
C01
C02
B01
A02
B03
A03
C04
B05
A05
B06
A06
D07
C07
B07
A07
L02
H01
D01
B04
A14
C12
C11
A10
A09
A08
R02
T01
U02
T03
ZHC
BALL #
L01
L02
K03
K04
K02
K01
J03
J04
J01
H04
H02
H03
H01
G01
G03
F01
C02
C03
B01
B02
A02
B03
A03
D05
A04
C05
B05
A05
C06
B06
A06
A07
J02
F02
E04
C04
A13
A12
B10
A10
C08
C07
M02
N01
N02
M03
ZHH
BALL #
L01
L02
L04
K03
K02
K01
J04
J03
J01
H04
H02
H03
H01
G03
G02
F03
C02
C03
B01
B02
A02
B03
A03
C04
C05
B05
A05
B06
C06
A06
D06
A07
J02
F02
C01
B04
C11
D11
C10
B09
C08
C07
M02
N01
N02
M03
TYPE
I/O
I/O
I/O
O
CELL
TYPE
PCI
Bus
PCI
Bus
PCI
Bus
PCI
Bus
PCI
Bus
PCI
I
Bus
PCI
Bus
CLAMP
RAIL
V
CCP
V
CCP
V
CCP
V
CCP
V
CCP
V
CCP
V
CCP
EXTERNAL
PARTS
− PCI address data lines
− PCI command byte enables
Pullup
resistor per
PCI spec
Pullup
resistor per
PCI spec
−
Pullup
resistor per
PCI spec
Pullup
resistor per
PCI spec
PCI device select
PCI frame
PCI grant outputs. These signals
are used for arbitration when the
PCI bus is the secondary bus and
an external arbiter is not used.
GNT0
bridge when an external arbiter is
used.
PCI interrupts A−D. These signals
are interrupt inputs to the bridge on
the secondary PCI bus.
PCI initiator ready
DESCRIPTION
is used as the REQ for the
20
April 2007 Revised October 2008SCPS155C
Page 30
Table 2−10. PCI System Terminals (Continued)
SIGNAL
PAR E02 D03 D02 I/O
PERR F03 C01 D03 I/O
PME M15 M14 L12 I
REQ5
REQ4
REQ3
REQ2
REQ1
REQ0
PRST U03 P01 P01 O
SERR E01 E03 D01 I/O
STOP F02 D02 E03 I/O
TRDY G03 F03 E01 I/O
GZZ/ZZZ
BALL #
B13
B12
B11
C10
C09
B08
ZHC
BALL #
B12
B11
C09
B09
B08
B07
ZHH
BALL #
A12
A11
A10
C09
A08
B07
I/O
TYPE
Introduction
CELL
TYPE
PCI
Bus
PCI
Bus
CMOS
I
PCI
Bus
PCI
Bus
PCI
Bus
PCI
Bus
PCI
Bus
LV
CLAMP
RAIL
V
CCP
V
CCP
V
DD_33_
COMBIO
V
CCP
V
CCP
V
CCP
V
CCP
V
CCP
EXTERNAL
PARTS
− PCI bus parity
Pullup
resistor per
PCI spec
Pullup
resistor per
PCI spec
If unused, a
weak pullup
resistor per
PCI spec
−
Pullup
resistor per
PCI spec
Pullup
resistor per
PCI spec
Pullup
resistor per
PCI spec
PCI parity error
PCI power management event. This
terminal may be used to detect PME
events from a PCI device on the
secondary bus.
Note: The PME
hysteresis.
PCI request inputs. These signals are
used for arbitration on the secondary PCI
bus when an external arbiter is not used.
REQ0
when an external arbiter is used.
PCI reset. This terminal is an output to
the secondary PCI bus.
PCI system error
PCI stop
PCI target ready
DESCRIPTION
input buffer has
is used as the GNT for the bridge
Table 2−11. Reserved Terminals
SIGNAL
RSVD
RSVD R16 N12 N14 I Must be connected to V
RSVD
April 2007 Revised October 2008 SCPS155C
GZZ/ZZZ
BALL #
N15, N16,
P16, R08,
T08, T10, T11,
T12, T14,
T15, T17,
U09, U11,
U12, U13,
U14, U15,
U16
D16, D17,
P17, R09,
T09, U10
ZHC
BALL #
K12, L07, L12,
M10, M11,
M13, N06,
N08, N09,
N10, N11,
P05, P06,
P08, P09,
P10, P13, P14
D12, D14,
M07, N07,
N14, P07
ZHH
BALL #
L07, L10, L14,
M06, M12,
M13, N06,
N08, N09,
N10, N11,
P06, P08,
P09, P10,
P11, P12, P14
D13, D14,
M14, P07,
M07, N07
I/O
TYPE
O Reserved, do not connect to external signals.
I Must be connected to VSS.
DESCRIPTION
.
DD_33
21
Page 31
Introduction
Table 2−12. Miscellaneous Terminals
GZZ/
SIGNAL
BALL
CLKRUN_EN B15 B13 B13 I
EXT_ARB_EN A15 C12 B12 I
GPIO0 //
CLKRUN
GPIO1 //
PWR_OVRD
GPIO2 T06 M05 N04 I/O
GPIO3 U06 N04 M04 I/O
ZHC
ZZZ
BALL
T05 M04 P03 I/O
U05 P03 P04 I/O
ZHH
BALL
I/O
TYPE
CELL
TYPE
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
CLAMP
RAIL
V
DD_33
V
DD_33
V
DD_33
V
DD_33
V
DD_33
V
DD_33
EXTERNAL
PARTS
Optional
pullup
resistor
Optional
pullup
resistor
Optional
pullup
resistor
−
−
−
DESCRIPTION
Clock run enable
0 = Clock run support disabled
1 = Clock run support enabled
Note: The CLKRUN_EN input buffer has an internal
active pulldown.
External arbiter enable
0 = Internal arbiter enabled
1 = External arbiter enabled
Note: The EXT_ARB_EN input buffer has an internal
active pulldown.
General-purpose I/O 0/clock run. This terminal
functions as a GPIO controlled by bit 0 (GPIO0_DIR)
in the GPIO control register (see Section 4.59) or the
clock run terminal. This terminal is used as clock run
input when the bridge is placed in clock run mode.
Note: In clock run mode, an external pullup resistor
is required to prevent the CLKRUN
floating.
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 1/power override. This terminal
functions as a GPIO controlled by bit 1 (GPIO1_DIR)
in the GPIO control register (see Section 4.59) or the
power override output terminal. GPIO1 becomes
PWR_OVRD when bits 22:20 (POWER_OVRD) in
the general control register are set to 001b or 011b
(see Section 4.65).
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 2. This terminal functions as a
GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO
control register (see Section 4.59).
Note: When PERST
be a 1b to enable the PCI Express 1.0a compatibility
mode.
Note: This terminal has an internal active pullup
resistor.
General-purpose I/O 3. This terminal functions as a
GPIO controlled by bit 3 (GPIO3_DIR) in the GPIO
control register (see Section 4.59).
Note: This terminal has an internal active pullup
resistor.
is deasserted, this terminal must
signal from
GPIO4 // SCL R07 P04 P05 I/O
22
LV
CMOS
V
DD_33
Optional
pullup
resistor
GPIO4 or serial-bus clock. This terminal functions as
serial-bus clock if a pullup resistor is detected on
SDA. If a pulldown resistor is detected on SDA, this
terminal functions as GPIO4.
Note: In serial-bus mode, an external pullup resistor
is required to prevent the SCL signal from floating.
Note: This terminal has an internal active pullup
resistor.
April 2007 Revised October 2008SCPS155C
Page 32
Table 2−12. Miscellaneous Terminals (Continued)
GZZ
SIGNAL
GPIO5 //
SDA
GPIO6 U07 M06 M05 I/O
GPIO7 U08 L06 L06 I/O
GRST N17 L13 L13 I
LOCK U04 P02 P02 I/O
M66EN R01 M01 M01 I
SERIRQ T04 N03 N03 I/O
ZZZ
BALL
T07 N05 N05 I/O
ZHC
BALL
ZHH
BALL
I/O
TYPE
CELL
TYPE
LV
CMOS
LV
CMOS
LV
CMOS
LV
CMOS
PCI
Bus
PCI
Bus
PCI
Bus
CLAMP
RAIL
V
DD_33
V
DD_33
V
DD_33
V
DD_33_
COMBIO
V
CCP
V
CCP
V
CCP
EXTERNAL
PARTS
Pullup or
Pulldown
resistor
−
−
−
Pullup
resistor per
PCI spec
Pullup
resistor per
PCI spec
Pullup or
pulldown
resistor
Introduction
DESCRIPTION
GPIO5 or serial-bus data. This terminal
functions as serial-bus data if a pullup
resistor is detected on SDA. If a pulldown
resistor is detected on SDA, this terminal
functions as GPIO5.
Note: In serial-bus mode, an external
pullup resistor is required to prevent the
SDA signal from floating.
General-purpose I/O 6. This terminal
functions as a GPIO controlled by bit 6
(GPIO6_DIR) in the GPIO control register
(see Section 4.59).
Note: This terminal has an internal active
pullup resistor.
General-purpose I/O 7. This terminal
functions as a GPIO controlled by bit 7
(GPIO7_DIR) in the GPIO control register
(see Section 4.59).
Note: This terminal has an internal active
pullup resistor.
Global reset input. Asynchronously resets
all logic in device, including sticky bits and
power management state machines.
Note: The GRST
hysteresis and an internal active pullup.
This terminal functions as PCI LOCK when
bit 12 (LOCK_EN) is set in the general
control register (see Section 4.65).
Note: In lock mode, an external pullup
resistor is required to prevent the LOCK
signal from floating.
66-MHz mode enable
0 = Secondary PCI bus and clock outputs
operate at 33 MHz
1 = Secondary PCI bus and clock outputs
operate at 66 MHz
Note: If the PCI bus clock is always 33
MHz, then this terminal is connected to
VSS.
Note: The XIO2000AI industrial
temperature device does not support 66
MHz operation so for the XIO2000AI, this
pin must be grounded for proper operation.
Serial IRQ interface. This terminal
functions as a serial IRQ interface if a
pullup is detected when PERST is
deasserted. If a pulldown is detected, then
the serial IRQ interface is disabled.
input buffer has both
April 2007 Revised October 2008 SCPS155C
23
Page 33
Feature/Protocol Descriptions
3 Feature/Protocol Descriptions
This chapter provides a high-level overview of all significant device features. Figure 3−1 shows a simplified
block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the PCI
Express interface and the PCI bus interface is located at the bottom of the diagram.
PCI Express
Transmitter
Power
Mgmt
Clock
Generator
Reset
Controller
Figure 3−1. XIO2000A Block Diagram
3.1 Power-Up/-Down Sequencing
The bridge contains both 1.5-V and 3.3-V power terminals. In addition, a V
D3
requirements. The following power-up and power-down sequences describe how power is applied to these
terminals.
In addition, the bridge has three resets: PERST
described in Section 3.2. The following power-up and power-down sequences describe how PERST
to the bridge.
The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down sequence
and is included in the following power-up and power-down descriptions.
state. The clamping voltage (V
cold
PCI Express
Receiver
GPIO
Configuration and
Memory Register
PCI Bus Interface
) can be either 3.3-V or 5.0-V, depending on the PCI bus interface
CCP
AUX
Serial
EEPROM
Serial IRQ
supply exists to support the
, GRST, and an internal power-on reset. These resets are fully
is applied
3.1.1 Power-Up Sequence
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages.
3. Apply V
4. Apply a stable PCI Express reference clock.
5. To meet PCI Express specification requirements, PERST
delay requirements are satisfied:
− Wait a minimum of 100 µs after applying a stable PCI Express reference clock. The 100-µs limit
satisfies the requirement for stable device clocks by the deassertion of PERST.
− Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable
power by the deassertion of PERST
24
clamp voltage.
CCP
cannot be deasserted until the following two
.
April 2007 Revised October 2008SCPS155C
Page 34
See the power-up sequencing diagram in Figure 3−2.
Feature/Protocol Descriptions
V
DD_15
V
DDA_15
V
DD_33
V
DDA_33
V
CCP
REFCLK
PERST
and
and
100 µs
100 ms
3.1.2 Power-Down Sequence
1. Assert PERST to the device.
2. Remove the reference clock.
3. Remove V
4. Remove 3.3-V and 1.5-V voltages.
Please see the power-down sequencing diagram in Figure 3−3. If the V
powered after a system shutdown, then the bridge power-down sequence is exactly the same as shown in
Figure 3−3.
clamp voltage.
CCP
Figure 3−2. Power-Up Sequence
DD_33_AUX
terminal is to remain
April 2007 Revised October 2008 SCPS155C
25
Page 35
Feature/Protocol Descriptions
V
V
V
V
REFCLK
DD_15
DDA_15
DD_33
DDA_33
V
CCP
PERST
and
and
3.2 Bridge Reset Features
There are five bridge reset options that include internally-generated power-on reset, resets generated by
asserting input terminals, and software-initiated resets that are controlled by sending a PCI Express hot reset
or setting a configuration register bit. Table 3−1 identifies these reset sources and describes how the bridge
responds to each reset.
Figure 3−3. Power-Down Sequence
26
April 2007 Revised October 2008SCPS155C
Page 36
Feature/Protocol Descriptions
Table 3−1. Bridge Reset Options
RESET OPTION XIO2000A FEATURE RESET RESPONSE
Bridge
internally-generated
power-on reset
Global reset input
GRST
(N17)
PCI Express reset input
PERST
(J17)
PCI Express training
control hot reset
PCI bus reset
PRST
(U03)
During a power-on cycle, the bridge asserts an internal
reset and monitors the V
When this terminal reaches 90% of the nominal input
voltage specification, power is considered stable. After
stable power, the bridge monitors the PCI Express
reference clock (REFCLK) and waits 10 µs after active
clocks are detected. Then, internal power-on reset is
deasserted.
When GRST is asserted low, an internal power-on
reset occurs. This reset is asynchronous and functions
during both normal power states and V
states.
This bridge input terminal is used by an upstream PCI
Express device to generate a PCI Express reset and to
signal a system power good condition.
When PERST
internal PCI Express reset as defined in the PCI
Express specification.
When PERST
power good condition is assumed by the bridge.
Note: The system must assert PERST
removed, before REFCLK is removed, or before
REFCLK becomes unstable.
The bridge responds to a training control hot reset
received on the PCI Express interface. After a training
control hot reset, the PCI Express interface enters the
DL_DOWN state.
System software has the ability to assert and deassert
the PRST
This terminal is the PCI bus reset.
is asserted low, the bridge generates an
transitions from low to high, a system
terminal on the secondary PCI bus interface.
DD_15_COMB
(M17) terminal.
power
AUX
before power is
When the internal power-on reset is asserted, all
control registers, state machines, sticky register bits,
and power management state machines are initialized
to their default state.
In addition, the bridge asserts PCI bus reset (PRST
When GRST is asserted low, all control registers, state
machines, sticky register bits, and power management
state machines are initialized to their default state.
In addition, the bridge asserts PCI bus reset (PRST
When the rising edge of GRST
samples the state of all static control inputs and latches
the information internally. If an external serial EEPROM
is detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link
is started. The bridge starts link training within 80 ms
after GRST
When PERST is asserted low, all control register bits
that are not sticky are reset. Within the configuration
register maps, the sticky bits are indicated by the
symbol. Also, all state machines that are not
associated with sticky functionality or V
management are reset.
In addition, the bridge asserts PCI bus reset (PRST
When the rising edge of PERST
samples the state of all static control inputs and latches
the information internally. If an external serial EEPROM
is detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link
is started. The bridge starts link training within 80 ms
after PERST
In the DL_DOWN state, all remaining configuration
register bits and state machines are reset. All
remaining bits exclude sticky bits and EEPROM
loadable bits. All remaining state machines exclude
sticky functionality, EEPROM functionality, and V
power management.
Within the configuration register maps, the sticky bits
are indicated by the
loadable bits are indicated by the † symbol.
In addition, the bridge asserts PCI bus reset (PRST
When bit 6 (SRST) in the bridge control register at
offset 3Eh (see Section 4.29) is asserted, the bridge
asserts the PRST terminal. A 0 in the SRST bit
deasserts the PRST
is deasserted.
is deasserted.
k
symbol and the EEPROM
terminal.
occurs, the bridge
power
AUX
occurs, the bridge
).
).
k
).
AUX
).
3.3 PCI Express Interface
3.3.1 External Reference Clock
The bridge requires either a differential, 100-MHz common clock reference or a single-ended, 125-MHz clock
reference. The selected clock reference must meet all PCI Express Electrical Specification requirements for
frequency tolerance, spread spectrum clocking, and signal electrical characteristics.
April 2007 Revised October 2008 SCPS155C
27
Page 37
Feature/Protocol Descriptions
If the REFCLK_SEL (A16) input is connected to VSS, then a differential, 100-MHz common clock reference
is expected by the bridge. If the A16 terminal is connected to V
reference is expected by the bridge.
When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is
connected to the REFCLK+ (C17) terminal. The REFCLK− (C16) terminal is connected to one side of an
external capacitor with the other side of the capacitor connected to V
When using a single-ended reference clock, care must be taken to ensure interoperability from a system jitter
standpoint. The PCI Express Base Specification does not ensure interoperability when using a differential
reference clock commonly used in PC applications along with a single-ended clock in a noncommon clock
architecture. System jitter budgets will have to be verified to ensure interoperability. See the PCI Express Jitter
and BER White Paper from the PCI-SIG.
3.3.2 Beacon
The bridge supports the PCI Express in-band beacon feature. Beacon is driven on the upstream PCI Express
link by the bridge to request the reapplication of main power when in the L2 link state. To enable the beacon
feature, bit 10 (BEACON_ENABLE) in the general control register at offset D4h is asserted. See Section 4.65,
General Control Register, for details.
, then a single-ended, 125-MHz clock
DD_33
.
SS
If the bridge is in the L2 link state and beacon is enabled, when a secondary PCI bus device asserts PME
then the bridge outputs the beacon signal on the upstream PCI Express link. The beacon signal frequency
is approximately 500 kHz ± 50% with a differential peak-to-peak amplitude of 500 mV and no de-emphasis.
Once the beacon is activated, the bridge continues to send the beacon signal until main power is restored as
indicated by PERST
going inactive. At this time, the beacon signal is deactivated.
3.3.3 Wake
The bridge supports the PCI Express sideband WAKE feature. WAKE is an active low signal driven by the
bridge to request the reapplication of main power when in the L2 link state. Since WAKE
output, a system-side pullup resistor is required to prevent the signal from floating.
When the bridge is in the L2 link state and PME
signal is asserted low as a wakeup mechanism. Once W AKE is asserted, the bridge drives the signal low until
main power is restored as indicated by PERST
3.3.4 Initial Flow Control Credits
The bridge flow control credits are initialized using the rules defined in the PCI Express Base Specification.
Table 3−2 identifies the initial flow control credit advertisement for the bridge. The initial advertisement is
exactly the same when a second virtual channel (VC) is enabled.
Table 3−2. Initial Flow Control Credit Advertisements
CREDIT TYPE INITIAL ADVERTISEMENT
Posted request headers (PH) 8
Posted request data (PD) 128
Nonposted header (NPH) 4
Nonposted data (NPD) 4
Completion header (CPLH) 0 (infinite)
Completion data (CPLD) 0 (infinite)
,
is an open-collector
is received from a device on the secondary PCI bus, the WAKE
going inactive. At this time, WAKE is deasserted.
3.3.5 PCI Express Message Transactions
PCI Express messages are both initiated and received by the bridge. Table 3−3 outlines message support
within the bridge.
28
April 2007 Revised October 2008SCPS155C
Page 38
MESSAGE SUPPORTED BRIDGE ACTION
Assert_INTx Yes Transmitted upstream
Deassert_INTx Yes Transmitted upstream
PM_Active_State_Nak Yes Received and processed
PM_PME Yes Transmitted upstream
PME_Turn_Off Yes Received and processed
PME_TO_Ack Yes Transmitted upstream
ERR_COR Yes Transmitted upstream
ERR_NONFATAL Yes Transmitted upstream
ERR_FATAL Yes Transmitted upstream
Unlock Yes Received and processed
Set_Slot_Power_Limit Yes Received and processed
Hot plug messages No Discarded
Advanced switching messages No Discarded
Vendor defined type 0 No Unsupported request
Vendor defined type 1 No Discarded
All supported message transactions are processed per the PCI Express Base Specification.
3.4 PCI Bus Interface
Feature/Protocol Descriptions
Table 3−3. Messages Supported by the Bridge
3.4.1 I/O Characteristics
Figure 3−4 shows a 3-state bi-directional buffer that represents the I/O cell design for the PCI bus. Section
7.7, Electrical Characteristics over Recommended Operating Conditions, provides the electrical
characteristics of the PCI bus I/O cell.
NOTE: The PCI bus interface on the bridge meets the ac specifications of the PCI Local Bus
Specification. Additionally, PCI bus terminals (input or I/O) must be held high or low to prevent
them from floating.
3.4.2 Clamping Voltage
In the bridge, the PCI bus I/O drivers are powered from the V
to input signals with 5.0-V peak-to-peak amplitudes.
For PCI bus interfaces operating at 66 MHz, all devices are required to output only 3.3-V peak-to-peak signal
amplitudes. For PCI bus interfaces operating at 33-MHz, devices may output either 3.3-V or 5.0-V
peak-to-peak signal amplitudes. The bridge accommodates both signal amplitudes.
V
Tied for Open Drain
OE
CCP
Pad
Figure 3−4. 3-State Bidirectional Buffer
DD_33
power rail. Plus, the I/O driver cell is tolerant
Each PCI bus I/O driver cell has a clamping diode connected to the V
from excessive input voltage. If the PCI signaling is 3.3-V, then V
supply. If the PCI signaling is 5.0 V, then V
April 2007 Revised October 2008 SCPS155C
(A04, J01) is connected to a 5.0-V power supply.
CCP
(A04, J01) is connected to a 3.3-V power
CCP
voltage rail that protects the cell
CCP
29
Page 39
Feature/Protocol Descriptions
The PCI bus signals attached to the V
• In Table 2−9, Clock Terminals, the terminal names include CLK and CLKOUT6:0.
• In Table 2−10, PCI System Terminals, all terminal names except for PME
• In Table 2−12, Miscellaneous Terminals, the terminal names include SERIRQ, M66EN, and LOCK.
3.4.3 PCI Bus Clock Run
The bridge supports the clock run protocol as specified in the PCI Mobile Design Guide. When the clock run
protocol is enabled, the bridge assumes the role of the central resource master.
To enable the clock run function, terminal B15 (CLKRUN_EN) is asserted high. Then, terminal T05 (GPIO0)
is enabled as the CLKRUN
from floating. To verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock
run status register at offset DAh (see Section 4.68) is read.
Since the bridge has several unique features associated with the PCI bus interface, the system designer must
consider the following interdependencies between these features and the CLKRUN
1. If the system designer chooses to generate the PCI bus clock externally, then the CLKRUN mode of the
bridge must be disabled. The central resource function within the bridge only operates as a CLKRUN
master and does not support the CLKRUN slave mode.
2. If the central resource function has stopped the PCI bus clocks, then the bridge still detects INTx state
changes and will generate and send PCI Express messages upstream.
clamping voltage are identified in the following list:
CCP
signal. An external pullup resistor must be provided to prevent the CLKRUN signal
feature:
3. If the serial IRQ interface is enabled and the central resource function has stopped the PCI bus clocks,
then any PCI bus device that needs to report an IRQ interrupt asserts CLKRUN
4. When a PCI bus device asserts CLKRUN
minimum of 512 cycles.
5. If the serial IRQ function detects an IRQ interrupt, then the central resource function keeps the PCI bus
clocks running until the IRQ interrupt is cleared by software.
6. If the central resource function has stopped the PCI bus clocks and the bridge receives a downstream
transaction that is forwarded to the PCI bus interface, then the bridge asserts CLKRUN to start the bus
clocks.
7. The central resource function is reset by PCI bus reset (PRST) assuring that clocks are present during
PCI bus resets.
3.4.4 PCI Bus External Arbiter
The bridge supports an external arbiter for the PCI bus. Terminal A15 (EXT_ARB_EN), when asserted high,
enables the use of an external arbiter.
When an external arbiter is enabled, GNT0 is connected to the external arbiter as the REQ for the bridge.
Likewise, REQ0
All internal port arbitration features are disabled when an external arbiter is enabled. 128-phase, weighted
round-robin (WRR) time-based arbitration, bus parking, arbiter time-out, tier select, and request masking
modes have no effect if an external arbiter is enabled.
is connected to the external arbiter as the GNT for the bridge.
to start the bus clocks.
, the central resource function turns on PCI bus clocks for a
30
April 2007 Revised October 2008SCPS155C
Page 40
3.4.5 MSI Messages Generated from the Serial IRQ Interface
When properly configured, the bridge converts PCI bus serial IRQ interrupts into PCI Express message
signaled interrupts (MSI). classic PCI configuration register space is provided to enable this feature. The
following list identifies the involved configuration registers:
1. Command register at offset 04h, bit 2 (MASTER_ENB) is asserted (see Section 4.3).
2. MSI message control register at offset 62h, bits 0 (MSI_EN) and 6:4 (MM_EN) enable single and multiple
MSI messages, respectively (see Section 4.38).
3. MSI message address register at offsets 64h and 68h specifies the message memory address. A nonzero
address value in offset 68h initiates 64-bit addressing (see Section 4.40).
4. MSI message data register at offset 6Ch specifies the system interrupt message (see Section 4.41).
5. Serial IRQ mode control register at offset E0h specifies the serial IRQ bus format (see Section 4.72).
6. Serial IRQ edge control register at offset E2h selects either level or edge mode interrupts (see
Section 4.73).
7. Serial IRQ status register at offset E4h reports level mode interrupt status (see Section 4.74).
A PCI Express MSI is generated based on the settings in the serial IRQ edge control register. If the system
is configured for edge mode, then an MSI message is sent when the corresponding serial IRQ interface
sample phase transitions from low to high. If the system is configured for level mode, then an MSI message
is sent when the corresponding IRQ status bit in the serial IRQ status register changes from low to high.
The bridge has a dedicated SERIRQ terminal (T04) for all PCI bus devices that support serialized interrupts.
This SERIRQ interface is synchronous to the PCI bus clock input (CLK) frequency. The bridge always
generates a 17-phase serial IRQ stream. Internally, the bridge detects only 16 IRQ interrupts, IRQ0 frame
through IRQ15 frame. The IOCHCK
generates an IRQ interrupt or MSI message.
frame is not monitored by the serial IRQ state machine and never
Feature/Protocol Descriptions
The multiple message enable (MM_EN) field determines the number of unique MSI messages that are sent
upstream on the PCI Express link. From 1 message to 16 messages, in powers of 2, are selectable. If fewer
than 16 messages are selected, then the mapping from IRQ interrupts to MSI messages is aliased. Table 3−4
illustrates the IRQ interrupt to MSI message mapping based on the number of enabling messages.
Table 3−4. IRQ Interrupt to MSI Message Mapping
IRQ INTERRUPT
IRQ0 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #0
IRQ1 MSI MSG #0 MSI MSG #1 MSI MSG #1 MSI MSG #1 MSI MSG #1
IRQ2 MSI MSG #0 MSI MSG #0 MSI MSG #2 MSI MSG #2 MSI MSG #2
IRQ3 MSI MSG #0 MSI MSG #1 MSI MSG #3 MSI MSG #3 MSI MSG #3
IRQ4 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #4 MSI MSG #4
IRQ5 MSI MSG #0 MSI MSG #1 MSI MSG #1 MSI MSG #5 MSI MSG #5
IRQ6 MSI MSG #0 MSI MSG #0 MSI MSG #2 MSI MSG #6 MSI MSG #6
IRQ7 MSI MSG #0 MSI MSG #1 MSI MSG #3 MSI MSG #7 MSI MSG #7
IRQ8 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #8
IRQ9 MSI MSG #0 MSI MSG #1 MSI MSG #1 MSI MSG #1 MSI MSG #9
IRQ10 MSI MSG #0 MSI MSG #0 MSI MSG #2 MSI MSG #2 MSI MSG #10
IRQ11 MSI MSG #0 MSI MSG #1 MSI MSG #3 MSI MSG #3 MSI MSG #11
IRQ12 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #4 MSI MSG #12
IRQ13 MSI MSG #0 MSI MSG #1 MSI MSG #1 MSI MSG #5 MSI MSG #13
IRQ14 MSI MSG #0 MSI MSG #0 MSI MSG #2 MSI MSG #6 MSI MSG #14
IRQ15 MSI MSG #0 MSI MSG #1 MSI MSG #3 MSI MSG #7 MSI MSG #15
1 MESSAGE
ENABLED
2 MESSAGES
ENABLED
4 MESSAGES
ENABLED
8 MESSAGES
ENABLED
16 MESSAGES
ENABLED
April 2007 Revised October 2008 SCPS155C
31
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Feature/Protocol Descriptions
The MSI message format is compatible with the PCI Express request header format for 32-bit and 64-bit
memory write transactions. The system message and message number fields are included in bytes 0 and 1
of the data payload.
3.4.6 PCI Bus Clocks
The bridge has seven PCI bus clock outputs and one PCI bus clock input. Up to six PCI bus devices are
supported by the bridge.
Terminal R01 (M66EN) selects the operating frequency of the PCI bus clock outputs. When this input is
asserted high, the PCI bus clocks operate at 66-MHz. When this input is deasserted low, the PCI bus clocks
operate at 33-MHz. The clock control register at offset D8h provides 7 control bits to individually enable or
disable each PCI bus clock output (see Section 4.66). The register default is enabled for all 7 outputs.
The PCI bus clock (CLK) input provides the clock to the internal PCI bus core and serial IRQ core. When the
internal PCI bus clock source is selected, PCI bus clock output 6 (CLKOUT6) is connected to the PCI bus clock
input (CLK). When an external PCI bus clock source is selected, the external clock source is connected to the
PCI bus clock input (CLK). For external clock mode, all seven CLKOUT6:0 terminals must be disabled using
the clock control register at offset D8h (see Section 4.66).
3.5 Quality of Service and Isochronous Features
The bridge has standard and advanced features that provide a robust solution for quality-of-service (QoS) and
isochronous applications. These features are best described by divided them into the following three
categories:
• PCI port arbitration. PCI port arbitration determines which bus master is granted the next transaction cycle
on the PCI bus. The three PCI port arbitration options are the classic PCI arbiter, the 128-phase, WRR
time-based arbiter, and the 128-phase, WRR aggressive time-based arbiter. The power-up register
default is the classic PCI arbiter. The advanced time-based arbiter features are provided to support
isochronous applications.
• PCI isochronous windows. There are four separate windows that allow PCI bus-initiated memory
transactions to be labeled with a PCI Express traffic class (TC) beyond the default TC0. Each window
designates a range of PCI memory space that is mapped to a specified TC label. The power-up register
default is all four windows disabled.
• PCI Express extended VC with VC arbitration. With an extended VC, system software can map a particular
TC to a specific VC. The differentiated traffic on the second VC then uses dedicated system resources
to support a QoS environment. VC arbitration is provided to gate traffic to the upstream PCI Express link.
The three VC arbitration options include strict priority, hardware-fixed round-robin, and 32-phase WRR.
The power-up register default is strict priority with the second VC disabled.
32
When configuring these standard and advanced features, the following rules must be followed:
1. The default mode is classic PCI arbiter with the PCI isochronous windows disabled and the second VC
disabled. The bridge performs default PCI bus arbitration without any arbiter-related configuration register
setup.
2. If a second VC is enabled, then at least one PCI isochronous window must be configured to map upstream
transactions to the second VC.
3. If a second VC is enabled, then any VC arbiter option interacts with any PCI port arbiter option.
4. To enable the PCI isochronous windows it is not required to enable a second VC. The memory space to
traffic mapping always uses VC0 for all upstream traffic.
5. When programming the upstream isochronous window base and limit registers, the 32-bit base/limit
address must be DWORD aligned and the limit address must be greater than the base address.
The following sections describe in detail the standard and advanced bridge features for QoS and isochronous
applications.
April 2007 Revised October 2008SCPS155C
Page 42
3.5.1 PCI Port Arbitration
The internal PCI port arbitration logic supports up to six external PCI bus devices plus the bridge. Three options
exist when configuring the bridge arbiter for these seven bus devices: classic PCI arbiter, 128-phase, WRR
time-based arbiter, and 128-phase, WRR aggressive time-based arbiter.
3.5.1.1 Classic PCI Arbiter
The classic PCI arbiter is configured through the classic PCI configuration space at offset DCh. Table 3−5
identifies and describes the registers associated with classic PCI arbitration mode.
Table 3−5. Classic PCI Arbiter Registers
PCI OFFSET REGISTER NAME DESCRIPTION
Classic PCI configuration
register DCh
Classic PCI configuration
register DDh
Classic PCI configuration
register DEh
Arbiter control
(see Section 4.69)
Arbiter request mask
(see Section 4.70)
Arbiter time-out status
(see Section 4.71)
Contains a two-tier priority scheme for the bridge and six PCI bus devices. The bridge
defaults to the high priority tier. The six PCI bus devices default to the low priority tier. A
bus parking control bit (bit 7, PARK) is provided.
Six mask bits provide individual control to block each PCI Bus REQ input. Bit 7
(ARB_TIMEOUT) in the arbiter request mask register enables generating timeout
status if a PCI device does not respond within 16 PCI bus clocks. Bit 6 (AUTO_MASK)
in the arbiter request mask register automatically masks a PCI bus REQ
does not respond after GNT
automatically generated mask.
When bit 7 (ARB_TIMEOUT) in the arbiter request mask register (see Section 4.70) is
asserted, timeout status for each PCI bus device is reported in this register.
is issued. The AUTO_MASK bit is cleared to disable any
Feature/Protocol Descriptions
if the device
3.5.1.2 128-Phase, WRR Time-Based Arbiter
The 128-phase, WRR time-based arbiter is configured through the PCI express VC extended configuration
space at offset 150h and the device control memory window register map.
The 128-phase, WRR time-based arbiter periodically asserts GNT to a PCI master device based on entries
within a port arbitration table. There are actually two port arbitration tables within the bridge. The first table
is accessed through the PCI Express VC extended configuration register space using configuration read/write
transactions. The second table is internal and is used by the PCI bus arbiter to make GNT
configuration register load function exists to transfer the contents of the configuration register table to the
internal table.
The port arbitration table uses a 4-bit field to identify the secondary bus master that receives GNT
phase of the time-based WRR arbitration. For the arbiter to recognize a bus master REQ
software must allocate at least three consecutive phases to the same port number.
Table 3−6 defines the mapping relationship of the PCI bus devices to a port number in the port arbitration table.
Table 3−6. Port Number to PCI Bus Device Mapping
PORT NUMBER GNT PCI DEVICE
0000b Internal GNT for PCI master state machine Internal REQ from PCI master state machine
0001b External GNT0 External REQ0
0010b External GNT1 External REQ1
0011b External GNT2 External REQ2
0100b External GNT3 External REQ3
0101b External GNT4 External REQ4
0110b External GNT5 External REQ5
0111b−1111b Reserved −
decisions. A
during each
and to generate GNT,
April 2007 Revised October 2008 SCPS155C
33
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Feature/Protocol Descriptions
To enable the 128-phase, WRR time-based arbiter, two configuration registers must be written. Bit 1
(PORTARB_LEVEL_1_EN) in the upstream isochrony control register at offset 04h (see Section 6.4) within
the device control memory window register map must be asserted. The VC1 resource control register at offset
170h within the PCI Express VC extended configuration space has a PORT_ARB_SELECT field that must
be set to 100b (see Section 5.22).
Table 3−7 identifies and describes the registers associated with 128-phase, WWR time-based arbitration
mode.
Table 3−7. 128-Phase, WRR Time-Based Arbiter Registers
REGISTER OFFSET REGISTER NAME DESCRIPTION
PCI Express VC extended
configuration registers
1C0h to 1FCh
PCI Express VC extended
configuration register 170h
PCI Express VC extended
configuration register 176h
Device control memory
window register 04h
Port arbitration table
(see Section 5.28)
VC1 resource control
(see Section 5.25)
VC1 resource status
(see Section 5.26)
Upstream isochrony
control (see Section 6.4)
16-doubleword sized configuration registers that are the registered version of the
128-phase, WRR port arbitration table. Each port arbitration table entry is a 4-bit
field.
Bits 19:17 (PORT_ARB_SELECT) equal to 100b define the port arbitration
mechanism as 128-phase WRR.
Bit 16 (LOAD_PORT_TABLE), when written with a 1b, transfers the port arbitration
table configuration register values to the internal registers used by the PCI bus
arbiter.
Bit 0 (PORT_TABLE_STATUS) equal to 1b indicates that the port arbitration table
configuration registers were updated but not loaded into the internal arbitration
table.
Bit 1 (PORTARB_LEVEL_1_EN) must be asserted to enable the 128-phase, WRR
time-based arbiter.
3.5.1.3 128-Phase, WRR Aggressive Time-Based Arbiter
The last option for PCI port arbitration is 128-phase, WRR aggressive time-based arbitration mode. This
arbitration mode performs the same as isochronous mode arbitration, but with one difference. When an
isochronous timing event occurs, the PCI bus arbiter deliberately stops a secondary bus master in the middle
of the transaction to assure that isochrony is preserved. The register setup for this arbitration option is the
same as the 128-phase, WRR time-based arbiter option with the following addition. Bit 2
(PORTARB_LEVEL_2_EN) in the device control memory window upstream isochrony control register at of fset
04h must be asserted (see Section 6.4).
3.5.2 PCI Isochronous Windows
The bridge has four separate windows that allow PCI bus-initiated memory transactions to be labeled with a
PCI Express traffic class (TC) beyond the default TC0. Each window designates a range of PCI memory space
that is mapped to a specified TC label. This advance feature is configured through the device control memory
window register map.
Table 3−8 identifies and describes the registers associated with isochronous arbitration mode.
Table 3−8. PCI Isochronous Windows
REGISTER OFFSET REGISTER NAME DESCRIPTION
Device control memory
window register 08h
Device control memory
window register 0Ch
Device control memory
window register 10h
Upstream isochronous window 0
control (see Section 6.5)
Upstream isochronous window 0
base address (see Section 6.6)
Upstream isochronous window 0
limit address (see Section 6.7)
Bits 3:1 (ISOC_WINDOW_EN) indicate that memory addresses within the
base and limit addresses are mapped to a specific traffic class ID.
Bit 0 (TC_ID) identifies the specific traffic class ID.
Note: Memory-mapped register space exists for four upstream windows.
Only window 0 is included in this table.
Window 0 base address
Window 0 limit address
34
April 2007 Revised October 2008SCPS155C
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3.5.3 PCI Express Extended VC With VC Arbitration
When a second VC is enabled, the bridge has three arbitration options that determine which VC is granted
access to the upstream PCI Express link. These three arbitration modes include strict priority, hardware-fixed
round-robin, and 32-phase WRR. The default mode is strict priority. For all three arbitration modes, if the
second VC is disabled, then VC0 is always granted.
To map upstream transactions to the extended VC, the following registers must be programmed:
1. Bit 0 (ISOC_ENABLE) is asserted in the upstream isochrony control register at device control memory
window register offset 04h (see Section 6.4).
2. At least one PCI isochronous window register set must be programmed. Please see Section 3.5.2 for a
description on how to program this advanced feature.
3. The traffic class ID selected for the PCI isochronous window(s) must be assigned to the extended VC.
This is accomplished by asserting the corresponding bit in the TC_VC_MAP field in the VC resource
control register (VC1) at PCI Express extended register offset 170h (see Section 5.25).
4. The extended VC must be enabled. This is accomplished by asserting bit 31 (VC_EN) and programming
bits 26:24 (VC_ID) in the VC resource control register (VC1) at PCI Express extended register offset 170h.
3.5.3.1 Strict Priority Arbitration Mode
Strict priority arbitration always grants VC1 traffic over VC0 traffic. If the traffic on VC1 uses 100% of the
upstream link bandwidth, then VC0 traffic is blocked. This mode is enabled when bit 25
(STRICT_PRIORITY_EN) in the general control register at offset D4h equals 1b (see Section 4.65).
Feature/Protocol Descriptions
For applications that require QoS or isochronous operation, this arbitration mode is recommended. In this
mode, all traffic on VC1 is assured access to the upstream link and VC0 traffic is best ef fort with a lower priority.
3.5.3.2 Hardware-Fixed, Round-Robin Arbitration
Hardware-fixed, round-robin arbitration alternates between VC0 and the second VC. Over an extended period
of time, if both VCs are heavily loaded with equal data payloads, each VC is granted approximately 50% of
the upstream link bandwidth. The PCI configuration registers described in Table 3−9 configure the
hardware-fixed, round-robin arbitration mode.
Table 3−9. Hardware-Fixed, Round-Robin Arbiter Registers
PCI OFFSET REGISTER NAME DESCRIPTION
Classic PCI configuration
register D4h
Classic PCI configuration
register 15Ch
General control
(see Section 4.65)
Port VC control
(see Section 5.19)
Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,
round-robin or 32-phase, WRR arbitration mode.
Bits 3:1 (VC_ARB_SELECT) equal to 000b enables hardware-fixed,
round-robin arbitration mode.
3.5.3.3 32-Phase, WRR Arbitration Mode
When the second upstream VC is enabled, the VC arbiter selects the next PCI Express upstream link
transaction based on entries within a VC arbitration table. There are actually two VC arbitration tables within
the bridge. The first table is accessed through the extended PCI Express configuration register space using
configuration read/write transactions. The second table is internal and is used by the VC arbiter to make
selection decisions. A configuration register load function exists to transfer the contents of the configuration
register table to the internal table.
The VC arbitration table uses a 4-bit field to identify the VC that is selected during each arbiter cycle. Bits 2:0
of this 4-bit field are loaded with the VC_ID assigned to each VC. For the arbiter to recognize a VC request,
the software must allocate only 1 phase to the same VC_ID.
The PCI configuration registers described in Table 3−10 configure the 32-phase, WRR arbitration mode.
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Feature/Protocol Descriptions
Table 3−10. 32-phase, WRR Arbiter Registers
PCI OFFSET REGISTER NAME DESCRIPTION
Classic PCI configuration
register D4h
PCI Express VC extended
configuration register 15Ch
PCI Express VC extended
configuration register 15Eh
PCI Express VC extended
configuration registers 180h
to 18Ch
General control
(see Section 4.65)
Port VC control
(see Section 5.19)
Port VC status
(see Section 5.20)
VC arbitration table
(see Section 5.27)
Bit 25 (STRICT_PRIORITY_EN) equal to 0b enables either hardware-fixed,
round-robin or 32-phase, WRR arbitration mode.
Bit 0 (LOAD_VC_TABLE) when written with a 1b transfers the VC arbitration table
configuration register values to the internal registers used by the VC arbiter.
Bits 3:1 (VC_ARB_SELECT) equal to 001b enables 32-phase, WRR arbitration
mode.
Bit 0 (VC_TABLE_STATUS) equal to 1b indicates that the VC arbitration table
configuration registers were updated but not loaded into the internal arbitration
table.
4-doubleword sized configuration registers that are the registered version of the
32-phase, WRR VC arbitration table. Each VC arbitration table entry is a 4-bit field.
3.5.4 128-Phase, WRR PCI Port Arbitration Timing
This section includes a timing diagram that illustrates the 128-phase, WRR time-based arbiter timing for the
bridge and three PCI bus devices. This timing diagram assumes aggressive mode since the transfer
associated with device #1 is stopped to start a device #0 transfer. The PCI bus cycle where device #1 is
stopped is indicated by the ‡ symbol. Device #1 then waits until its next port arbitration table cycle to finish
the transfer.
The signal waveforms associated with bridge REQ
, bridge GNT, ISOC reference clock, and port arbitration
table entry are internal to the bridge. These internal bridge signals are included here to help clarify the
operation of the PCI port arbiter in 128-phase, WRR time-based arbitration mode. The remaining REQ
, GNT,
and PCI bus signals are all external to the bridge.
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Bridge
REQ
REQ0
REQ1
REQ2
Bridge
GNT
GNT0
GNT1
Feature/Protocol Descriptions
GNT2
Isoc Ref
Clock
Port Arb
Table
PCI Bus
330002222111133300022221
Bridge
Device 1
‡
Figure 3−5. PCI Bus Timing
3.6 Configuration Register Translation
PCI Express configuration register transactions received by the bridge are decoded based on the transaction’s
destination ID. These configuration transactions can be broken into three subcategories: type 0 transactions,
type 1 transactions that target the secondary bus, and type 1 transactions that target a downstream bus other
than the secondary bus.
PCI Express type 0 configuration register transactions always target the configuration space and are never
passed on to the secondary interface.
Type 1 configuration register transactions that target a device on the secondary bus are converted to type 0
configuration register transactions on the PCI bus. Figure 3−6 shows the address phase of a type 0
configuration transaction on the PCI bus as defined by the PCI specification.
Device 0
Device 2
Bridge Device 1
31 16 15 11 10 8 7 2 1 0
IDSEL Reserved
Function
Number
Register Number 0 0
Figure 3−6. Type 0 Configuration Transaction Address Phase Encoding
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Feature/Protocol Descriptions
In addition, the bridge converts the destination ID device number to one of the AD[31:16] lines as the IDSEL
signal. The implemented IDSEL signal mapping is shown in Table 3−11.
Table 3−11. Type 0 Configuration Transaction IDSEL Mapping
DEVICE
NUMBER
00000 0000 0000 0000 0001
00001 0000 0000 0000 0010
00010 0000 0000 0000 0100
00011 0000 0000 0000 1000
00100 0000 0000 0001 0000
00101 0000 0000 0010 0000
00110 0000 0000 0100 0000
00111 0000 0000 1000 0000
01000 0000 0001 0000 0000
01001 0000 0010 0000 0000
01010 0000 0100 0000 0000
01011 0000 1000 0000 0000
01100 0001 0000 0000 0000
01101 0010 0000 0000 0000
01110 0100 0000 0000 0000
01111 1000 0000 0000 0000
1xxxx 0000 0000 0000 0000
AD[31:16]
Type 1 configuration registers transactions that target a downstream bus other then the secondary bus are
output on the PCI bus as type 1 PCI configuration transactions. Figure 3−7 shows the address phase of a type
1 configuration transaction on the PCI bus as defined by the PCI specification.
31 24 23 16 15 11 10 8 7 2 1 0
Reserved Bus Number Device Number
Function
Number
Register Number 0 1
Figure 3−7. Type 1 Configuration Transaction Address Phase Encoding
3.7 PCI Interrupt Conversion to PCI Express Messages
The bridge converts interrupts from the PCI bus sideband interrupt signals to PCI Express interrupt messages.
PCI Express Assert_INTx messages are generated when one of the PCI bus INT[A:D]
transitions low. The requester ID portion of the Assert_INTx message uses the value stored in the primary bus
number register (see Section 4.1 1 ) a s the bus number, 0 as the device number , and 0 as the function number.
The tag field for each Assert_INTx message is 00h. The lower two bits in the code field indicate the asserted
interrupt signal.
PCI Express Deassert_INTx messages are generated when one of the PCI bus INT[A:D]
transitions high. The requester ID portion of the Deassert_INTx message uses the value stored in the primary
bus number register as the bus number, 0 as the device number, and 0 as the function number. The Tag field
for each Deassert_INTx message is 00h. The lower two bits in the code field indicate the deasserted interrupt
signal.
Table 3−12, Figure 3−8, and Figure 3−9 illustrate the format for both the assert and deassert INTx messages.
input terminals
input terminals
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Byte 0>
R
R
Reserved
R
Byte 4>
Requester ID
Tag
Byte 8>
Reserved
Byte 0>
R
R
Reserved
R
Byte 4>
Requester ID
Tag
Reserved
Byte 0>
R
R
Reserved
R
Byte 4>
Requester ID
Tag
Reserved
Byte 12>
Byte 8>
Byte 12>
Feature/Protocol Descriptions
Table 3−12. Interrupt Mapping In The Code Field
INTERRUPT CODE FIELD
INTA 00
INTB 01
INTC 10
INTD 11
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Fmt Type
0 1 1 0 1 0 0
TC
0 0 0
T
E Attr
D P 0 0
Length
0 0 0 0 0 0 0 0 0 0
Code
0 0 1 0 0 0 x x
Figure 3−8. PCI Express ASSERT_INTX Message
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Fmt Type
0 1 1 0 1 0 0
TC
0 0 0
T
E Attr
D P 0 0
Length
0 0 0 0 0 0 0 0 0 0
Code
0 0 1 0 0 1 x x
Figure 3−9. PCI Express DEASSERT_INTX Message
3.8 PME Conversion to PCI Express Messages
When the PCI bus PME input transitions low, the bridge generates and sends a PCI Express PME message
upstream. The requester ID portion of the PME message uses the stored value in the secondary bus number
register as the bus number, 0 as the device number, and 0 as the function number. The Tag field for each PME
message is 00h. A PME message is sent periodically until the PME
Figure 3−10 illustrates the format for a PCI Express PME message.
+0 +1 +2 +3
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Fmt Type
0 1 1 0 0 0 0
Byte 8>
Byte 12>
Figure 3−10. PCI Express PME Message
TC
0 0 0
T
E Attr
D P 0 0
signal transitions high.
Length
0 0 0 0 0 0 0 0 0 0
Code
0 0 0 1 1 0 0 0
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Feature/Protocol Descriptions
3.9 PCI Express To PCI Bus Lock Conversion
The bus-locking protocol defined in the PCI Express Base Specification and PCI Local Bus Specification is
provided on the bridge as an additional compatibility feature. The PCI bus LOCK
that is enabled by setting bit 12 in the general control register at of fset D4h. See Section 4.65, General Control
Register, for details.
NOTE:The use of LOCK is only supported by PCI-Express to PCI Bridges in the downstream
direction (away from the root complex).
PCI Express locked-memory read request transactions are treated the same as PCI Express memory read
transactions except that the bridge returns a completion for a locked-memory read. Also, the bridge uses the
PCI LOCK
When a PCI Express locked-memory read request transaction is received and the bridge is not already locked,
the bridge arbitrates for use of the LOCK
terminal is high, then the bridge drives the LOCK terminal low after the address phase of the first
locked-memory read transaction to take ownership of LOCK
during the address phase of locked transactions. If the bridge receives GNT
then the bridge deasserts its REQ
use of LOCK
protocol when initiating the memory read transaction on the PCI bus.
terminal by asserting REQ. If the bridge receives GNT and the LOCK
and waits until LOCK is high and the bus is idle before re-arbitrating for the
.
CLK
signal is a dedicated output
. The bridge continues to assert LOCK except
and the LOCK terminal is low,
FRAME
LOCK
AD
IRDY
TRDY
DEVSEL
DataAddress
Figure 3−11. Starting A Locked Sequence
Once the bridge has ownership of LOCK
, the bridge initiates the lock read as a memory read transaction on
the PCI bus. When the target of the locked-memory read returns data, the bridge is considered locked and
all transactions not associated with the locked sequence are blocked by the bridge.
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CLK
FRAME
LOCK
Feature/Protocol Descriptions
AD
IRDY
TRDY
DEVSEL
DataAddress
Figure 3−12. Continuing A Locked Sequence
Because PCI Express does not have a unique locked-memory write request packet, all PCI Express memory
write requests that are received while the bridge is locked are considered part of the locked sequence and
are transmitted to PCI as locked-memory write transactions. In addition, all traffic mapped to VC1 is allowed
to pass.
The bridge terminates the locked sequence when an unlock message is received from PCI Express and all
previous locked transactions have been completed.
CLK
FRAME
LOCK
IRDY
Figure 3−13. Terminating A Locked Sequence
In the erroneous case that a normal downstream memory read request is received during a locked sequence,
the bridge responds with an unsupported request completion status. Please note that this condition must
never occur, because the PCI Express specification requires the root complex to block normal memory read
requests at the source. All locked sequences that end successfully or with an error condition must be
immediately followed by an unlock message. This unlock message is required to return the bridge to a known
unlocked state.
3.10 Two-Wire Serial-Bus Interface
The bridge provides a two-wire serial-bus interface to load subsystem identification information and specific
register defaults from an external EEPROM. The serial-bus interface signals (SCL and SDA) are shared with
two of the GPIO terminals (4 and 5). If the serial bus interface is enabled, then the GPIO4 and GPIO5 terminals
are disabled. If the serial bus interface is disabled, then the GPIO terminals operate as described in
Section 3.13.
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Feature/Protocol Descriptions
3.10.1 Serial-Bus Interface Implementation
To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising edge
of PERST
is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see Section 4.58) is set.
Software may disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If no external
EEPROM is required, then the serial-bus interface is permanently disabled by attaching a pulldown resistor
to the SDA signal.
The bridge implements a two-terminal serial interface with 1 clock signal (SCL) and 1 data signal (SDA). The
SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both are open-drain
signals and require pullup resistors. The bridge is a bus master device and drives SCL at approximately
60 kHz during data transfers and places SCL in a high-impedance state (0 frequency) during bus idle states.
The serial EEPROM is a bus slave device and must acknowledge a slave address equal to A0h. Figure 3−14
illustrates an example application implementing the two-wire serial bus.
or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup resistor. If one
V
Serial
EEPROM
A0
A1A2SCL
SDA
DD_33
XIO2000A
GPIO4 // SCL
GPIO5 // SDA
Figure 3−14. Serial EEPROM Application
3.10.2 Serial-Bus Interface Protocol
All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a start
condition, which is signaled when the SDA line transitions to the low state while SCL is in the high state, as
illustrated in Figure 3−15. The end of a requested data transfer is indicated by a stop condition, which is
signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3−15. Data on
SDA must remain stable during the high state of the SCL signal, as changes on the SDA signal during the high
state of SCL are interpreted as control signals, that is, a start or stop condition.
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SDA
SCL
Feature/Protocol Descriptions
Start
Condition
Stop
Condition
Change of
Data Allowed
Data Line Stable,
Data Valid
Figure 3−15. Serial-Bus Start/Stop Conditions and Bit Transfers
Data is transferred serially in 8-bit bytes. During a data transfer operation, the exact number of bytes that are
transmitted is unlimited. However, each byte must be followed by an acknowledge bit to continue the data
transfer operation. An acknowledge (ACK) is indicated by the data byte receiver pulling the SDA signal low,
so that it remains low during the high state of the SCL signal. Figure 3−16 illustrates the acknowledge protocol.
SCL From
Master
SDA Output
By Transmitter
SDA Output
By Receiver
123 789
Figure 3−16. Serial-Bus Protocol Acknowledge
The bridge performs three basic serial-bus operations: single byte reads, single byte writes, and multibyte
reads. The single byte operations occur under software control. The multibyte read operations are performed
by the serial EEPROM initialization circuitry immediately after a PCI Express reset. See Section 3.10.3,
Serial-Bus EEPROM Application, for details on how the bridge automatically loads the subsystem
identification and other register defaults from the serial-bus EEPROM.
Figure 3−17 illustrates a single byte write. The bridge issues a start condition and sends the 7-bit slave device
address and the R/W
command bit is equal to 0b. A 0b in the R/W command bit indicates that the data transfer
is a write. The slave device acknowledges if it recognizes the slave address. If no acknowledgment is received
by the bridge, then bit 1 (SB_ERR) is set in the serial-bus control and status register (PCI offset B3h, see
Section 4.58). Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment
is expected. Then the bridge delivers the data byte MSB first and expects a final acknowledgment before
issuing the stop condition.
Slave Address Word Address
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
R/W
S/P = Start/Stop ConditionA = Slave Acknowledgement
b7 b6 b4b5 b3 b2 b1 b0 A P
Data Byte
Figure 3−17. Serial-Bus Protocol—Byte Write
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Feature/Protocol Descriptions
Figure 3−18 illustrates a single byte read. The bridge issues a start condition and sends the 7-bit slave device
address and the R/W
slave address. Next, the EEPROM word address is sent by the bridge, and another slave acknowledgment
is expected. Then, the bridge issues a restart condition followed by the 7-bit slave address and the R/W
command bit is equal to 1b (read). Once again, the slave device responds with an acknowledge. Next, the
slave device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the bridge responds with no
acknowledge (logic high) indicating the last data byte. Finally, the bridge issues a stop condition.
command bit is equal to 0b (write). The slave device acknowledges if it recognizes the
Slave Address Word Address
Sb6 b4b5 b3 b2 b1 b0 0 b7 b6 b5 b4 b3 b2 b1 b0AA
Start
A = Slave Acknowledgement
R/W
Sb6 b4b5 b3 b2 b1 b0 1 A
Restart R/W
b7 b6 b4b5 b3 b2 b1 b0 M P
S/P = Start/Stop ConditionM = Master Acknowledgement
Slave Address
Data Byte
Figure 3−18. Serial-Bus Protocol—Byte Read
Figure 3−19 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The
serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes
are transferred. The number of transferred data bytes is controlled by the bridge master. After each data byte,
the bridge master issues acknowledge (logic low) if more data bytes are requested. The transfer ends after
a bridge master no acknowledge (logic high) followed by a stop condition.
Slave Address Word Address
S1 10 00000 00000000AA
S1 10 00001A
Slave Address
Stop
Start
Data Byte 0 M
R/W
Data Byte 1 Data Byte 2 Data Byte 3 M PMM
M = Master Acknowledgement S/P = Start/Stop ConditionA = Slave Acknowledgement
Figure 3−19. Serial-Bus Protocol—Multibyte Read
Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of the
three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this control
bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus protocol.
This feature allows the system designer a second serial-bus protocol option when selecting external EEPROM
devices.
3.10.3 Serial-Bus EEPROM Application
The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3−13.
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R/W
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Table 3−13. EEPROM Register Loading Map
Feature/Protocol Descriptions
SERIAL EEPROM
WORD ADDRESS
00h PCI-Express to PCI bridge function indicator (00h)
01h Number of bytes to download (1Eh)
02h PCI 84h, subsystem vendor ID, byte 0
03h PCI 85h, subsystem vendor ID, byte 1
04h PCI 86h, subsystem ID, byte 0
05h PCI 87h, subsystem ID, byte 1
06h PCI D4h, general control, byte 0
07h PCI D5h, general control, byte 1
08h PCI D6h, general control, byte 2
09h PCI D7h, general control, byte 3
0Ah PCI D8h, clock control
0Bh PCI D9h, clock mask
0Ch Reserved—no bits loaded
0Dh PCI DCh, arbiter control
0Eh PCI DDh, arbiter request mask
0Fh PCI C0h, control and diagnostic register 0 byte 0
10h PCI C1h, control and diagnostic register 0 byte 1
11h PCI C2h, control and diagnostic register 0 byte 2
12h PCI C3h, control and diagnostic register 0 byte 3
13h PCI C4h, control and diagnostic register 1 byte 0
14h PCI C5h, control and diagnostic register 1 byte 1
15h PCI C6h, control and diagnostic register 1 byte 2
16h PCI C7h, control and diagnostic register 1 byte 3
17h PCI C8h, control and diagnostic register 2 byte 0
18h PCI C9h, control and diagnostic register 2 byte 1
19h PCI CAh, control and diagnostic register 2 byte 2
1Ah PCI CBh, control and diagnostic register 2 byte 3
1Bh Reserved—no bits loaded
1Ch Reserved—no bits loaded
1Dh PCI E0h, serial IRQ mode control
1Eh PCI E2h, serial IRQ edge control, byte 0
1Fh PCI E3h, serial IRQ edge control, byte 1
20h End-of-list indicator (80h)
BYTE DESCRIPTION
This format must be explicitly followed for the bridge to correctly load initialization values from a serial
EEPROM. All byte locations must be considered when programming the EEPROM.
The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is internally
hardwired and cannot be changed by the system designer. Therefore, all three hardware address bits for the
EEPROM are tied to V
to achieve this address. The serial EEPROM in the sample application circuit
SS
(Figure 3−14) assumes the 1010b high-address nibble. The lower three address bits are terminal inputs to
the chip, and the sample application shows these terminal inputs tied to V
SS
.
During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is
asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register may
be monitored to verify a successful download.
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Feature/Protocol Descriptions
3.10.4 Accessing Serial-Bus Devices Through Software
The bridge provides a programming mechanism to control serial-bus devices through system software. The
programming is accomplished through a doubleword of PCI configuration space at offset B0h. Table 3−14 lists
the registers that program a serial-bus device through software.
Table 3−14. Registers Used To Program Serial-Bus Devices
PCI OFFSET REGISTER NAME DESCRIPTION
B0h Serial-bus data
(see Section 4.55)
B1h Serial-bus word address
(see Section 4.56)
B2h Serial-bus slave address
(see Section 4.57)
B3h Serial-bus control and status
(see Section 4.58)
To access the serial EEPROM through the software interface, the following steps are performed:
1. The control and status byte is read to verify the EEPROM interface is enabled (SBDETECT asserted) and
not busy (REQBUSY and ROMBUSY deasserted).
2. The serial-bus word address is loaded. If the access is a write, then the data byte is also loaded.
3. The serial-bus slave address and R/W
4. REQBUSY is monitored until this bit is deasserted.
5. SB_ERR is checked to verify that the serial-bus operation completed without error. If the operation is a
read, then the serial-bus data byte is now valid.
Contains the data byte to send on write commands or the received data byte on read
commands.
The content of this register is sent as the word address on byte writes or reads. When bit 7
(PROT_SEL) in the serial-bus control and status register (offset B3h, see Section 4.58) is set
to 1b and the quick command protocol is selected, this word address is ignored.
Write transactions to this register initiate a serial-bus transaction. The slave device address
and the R/W
Serial interface enable, busy, and error status are communicated through this register. In
addition, the protocol-select (PROT_SEL) bit and serial-bus test (SBTEST) bit are
programmed through this register.
command selector are programmed through this register.
command selector byte is written.
3.11 Advanced Error Reporting Registers
In the extended PCI Express configuration space, the bridge supports the advanced error reporting
capabilities structure. For the PCI Express interface, both correctable and uncorrectable error status is
provided. For the PCI bus interface, secondary uncorrectable error status is provided. All uncorrectable status
bits have corresponding mask and severity control bits. For correctable status bits, only mask bits are
provided.
Both the primary and secondary interfaces include first error pointer and header log registers. When the first
error is detected, the corresponding bit position within the uncorrectable status register is loaded into the first
error pointer register. Likewise, the header information associated with the first failing transaction is loaded
into the header log. To reset this first error control logic, the corresponding status bit in the uncorrectable status
register is cleared by a writeback of 1b.
For systems that require high data reliability, ECRC is fully supported on the PCI Express interface. The
primary side advanced error capabilities and control register has both ECRC generation and checking enable
control bits. When the checking bit is asserted, all received TLPs are checked for a valid ECRC field. If the
generation bit is asserted, then all transmitted TLPs contain a valid ECRC field.
3.12 Data Error Forwarding Capability
The bridge supports the transfer of data errors in both directions.
If a downstream PCI Express transaction with a data payload is received that targets the PCI bus and the EP
bit is set indicating poisoned data, then the bridge must ensure that this information is transferred to the PCI
bus. To do this, the bridge forces a parity error on each PCI bus data phase by inverting the parity bit calculated
for each double-word of data.
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If the bridge is the target of a PCI transaction that is forwarded to the PCI Express interface and a data parity
error is detected, then this information is passed to the PCI Express interface. To do this, the bridge sets the
EP bit in the upstream PCI Express header.
3.13 General-Purpose I/O Interface
Up to eight general-purpose input/output (GPIO) terminals are provided for system customization. These
GPIO terminals are 3.3-V tolerant.
The exact number of GPIO terminals varies based on implementing the clock run, power override, and serial
EEPROM interface features. These features share four of the eight GPIO terminals. When any of the three
shared functions are enabled, the associated GPIO terminal is disabled.
All eight GPIO terminals are individually configurable as either inputs or outputs by writing the corresponding
bit in the GPIO control register at offset B4h. A GPIO data register at offset B6h exists to either read the logic
state of each GPIO input or to set the logic state of each GPIO output. The power-up default state for the GPIO
control register is input mode.
3.14 Set Slot Power Limit Functionality
The PCI Express Specification provides a method for devices to limit internal functionality and save power
based on the value programmed into the captured slot power limit scale (CSPLS) and capture slot power limit
value (CSPLV) fields of the PCI Express device capabilities register at offset 94h. See Section 4.49, Device
Capabilities Register , for details. The bridge writes these fields when a set slot power limit message is received
on the PCI Express interface.
Feature/Protocol Descriptions
After the deassertion of PERST
device capabilities register with the minimum power scale (MIN_POWER_SCALE) and minimum power value
(MIN_POWER_VALUE) fields in the general control register at offset D4h. See Section 4.65, General Control
Register, for details. If the CSPLS and CSPLV fields are less than the MIN_POWER_SCALE and
MIN_POWER_VALUE fields, respectively , then the bridge takes the appropriate action that is defined below.
The power usage action is programmable within the bridge. The general control register includes a 3-bit
PWR_OVRD field. This field is programmable to the following five options:
1. Ignore slot power limit fields
2. Assert the PWR_OVRD terminal (U05)
3. Disable secondary clocks as specified by the clock mask register at offset D9h.
4. Disable secondary clocks as specified by the clock mask register and assert the PWR_OVRD terminal
5. Respond with unsupported request to all transactions except type 0/1 configuration transactions and set
slot power limit messages
, the bridge compares the information in the CSPLS and CSPLV fields of the
3.15 PCI Express and PCI Bus Power Management
The bridge supports both software-directed power management and active state power management through
standard PCI configuration space. Software-directed registers are located in the power management
capabilities structure located at offset 50h. Active state power management control registers are located in
the PCI Express capabilities structure located at offset 90h.
During software-directed power management state changes, the bridge initiates link state transitions to L1 or
L2/L3 after a configuration write transaction places the device in a low power state. The power management
state machine is also responsible for gating internal clocks based on the power state. Table 3−15 identifies
the relationship between the D-states and bridge clock operation.
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Feature/Protocol Descriptions
PCI express reference clock input (REFCLK) On On On On/Off
PCI clock input (CLK) On Off Off Off
Secondary PCI bus clock outputs (CLKOUT6:0) On On On On/Off
The link power management (LPM) state machine manages active state power by monitoring the PCI Express
transaction activity . If no transactions are pending and the transmitter has been idle for at least the minimum
time required by the PCI Express Specification, then the LPM state machine transitions the link to either the
L0s or L1 state. By reading the bridge’s L0s and L1 exit latency in the link capabilities register, the system
software may make an informed decision relating to system performance versus power savings. The ASLPMC
field in the link control register provides an L0s-only option, L1-only option, or both L0s and L1 option.
Finally, the bridge generates the PM_Active_State_Nak Message if a PM_Active_State_Request_L1 DLLP
is received on the PCI Express interface and the link cannot be transitioned to L1.
Table 3−15. Clocking In Low Power States
CLOCK SOURCE D0/L0 D1/L1 D2/L1 D3/L2/L3
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4 Classic PCI Configuration Space
The programming model of the XIO2000A PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI
bridge programming model. The PCI configuration map uses the type 1 PCI bridge header.
Classic PCI Configuration Space
All bits marked with a
power-on reset. All bits marked with a † are reset by a PCI Express reset (PERST
k
are sticky bits and are reset by a global reset (GRST) or the internally-generated
), a GRST, or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST
GRST
, or the internally-generated power-on reset.
Table 4−1. Classic PCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 000h
Status Command 004h
Class code Revision ID 008h
BIST Header type Latency timer Cache line size 00Ch
Device control base address 010h
Reserved 014h
Secondary latency timer Subordinate bus number Secondary bus number Primary bus number 018h
Secondary status I/O limit I/O base 01Ch
Memory limit Memory base 020h
Prefetchable memory limit Prefetchable memory base 024h
Prefetchable base upper 32 bits 028h
Prefetchable limit upper 32 bits 02Ch
I/O limit upper 16 bits I/O base upper 16 bits 030h
Reserved Capabilities pointer 034h
Reserved 038h
Bridge control Interrupt pin Interrupt line 03Ch
Reserved 040h−04Ch
Power management capabilities Next item pointer PM CAP ID 050h
PM data PMCSR_BSE Power management CSR 054h
Reserved 058h−05Ch
MSI message control Next item pointer MSI CAP ID 060h
MSI message address 064h
MSI upper message address 068h
Reserved MSI message data 06Ch
Reserved 070h−07Ch
Reserved Next item pointer SSID/SSVID CAP ID 080h
Subsystem ID† Subsystem vendor ID† 084h
Reserved 088h−08Ch
PCI Express capabilities register Next item pointer PCI Express capability ID 090h
Device capabilities 094h
Device status Device control 098h
Link capabilities 09Ch
Link status Link control 0A0h
Reserved 0A4h−0ACh
Serial-bus control and
status†
†
One or more bits in this register are reset by a PCI Express reset (PERST
Serial-bus slave address† Serial-bus word address† Serial-bus data† 0B0h
), a GRST, or the internally-generated power-on reset.
,
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Classic PCI Configuration Space
Table 4−1. PCI Express Configuration Register Map (Continued)
GPIO data† GPIO control† 0B4h
Reserved Clock run status† Clock mask† Clock control† 0D8h
Reserved Arbiter time-out status Arbiter request mask† Arbiter control† 0DCh
Serial IRQ edge control† Reserved Serial IRQ mode control† 0E0h
Reserved Serial IRQ status 0E4h
†
One or more bits in this register are reset by a PCI Express reset (PERST
4.1 Vendor ID Register
This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas Instruments.
PCI register offset: 00h
Register type: Read-only
Default value: 104Ch
REGISTER NAME OFFSET
Reserved 0B8h−0BCh
Control and diagnotic register 0† 0C0h
Control and diagnotic register 1† 0C4h
Control and diagnotic register 2† 0C8h
Reserved 0CCh
Subsystem access† 0D0h
General control† 0D4h
Reserved 0E8h−0FCh
), a GRST, or the internally-generated power-on reset.
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0
4.2 Device ID Register
This 16-bit read-only register contains the value 8231h, which is the device ID assigned by TI for the bridge.
PCI register offset: 02h
Register type: Read-only
Default value: 8231h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 0 0 0 0 0 1 0 0 0 1 1 0 0 0 1
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4.3 Command Register
The command register controls how the bridge behaves on the PCI Express interface. See Table 4−2 for a
complete description of the register contents.
PCI register offset: 04h
Register type: Read-only, Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−2. Command Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:11 RSVD R Reserved. Returns 00000b when read.
10 INT_DISABLE R
9 FBB_ENB R
8 SERR_ENB RW
7 STEP_ENB R
6 PERR_ENB RW
5 VGA_ENB R
4 MWI_ENB RW
3 SPECIAL R
2 MASTER_ENB RW
1 MEMORY_ENB RW
0 IO_ENB RW
INTx disable. This bit enables device specific interrupts. Since the bridge does not generate any
internal interrupts, this bit is read-only 0b.
Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;
therefore, this bit returns 0b when read.
SERR enable bit. When this bit is set, the bridge can signal fatal and nonfatal errors on the PCI
Express interface on behalf of SERR
0 = Disable the reporting of nonfatal errors and fatal errors (default)
1 = Enable the reporting of nonfatal errors and fatal errors
Address/data stepping control. The bridge does not support address/data stepping, and this bit is
hardwired to 0b.
Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Section 4.4) in
response to a received poisoned TLP from PCI Express. A received poisoned TLP is forwarded
with bad parity to conventional PCI regardless of the setting of this bit.
0 = Disables the setting of the master data parity error bit (default)
1 = Enables the setting of the master data parity error bit
VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore, this bit
returns 0b when read.
Memory write and invalidate enable. When this bit is set, the bridge translates PCI Express
memory write requests into memory write and invalidate transactions on the PCI interface.
0 = Disable the promotion to memory write and invalidate (default)
1 = Enable the promotion to memory write and invalidate
Special cycle enable. The bridge does not respond to special cycle transactions; therefore, this
bit returns 0b when read.
Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on the PCI
Express interface.
0 = PCI Express interface cannot initiate transactions. The bridge must disable the response
to memory and I/O transactions on the PCI interface (default).
1 = PCI Express interface can initiate transactions. The bridge can forward memory and I/O
transactions from PCI secondary interface to the PCI Express interface.
Memory space enable. Setting this bit enables the bridge to respond to memory transactions on
the PCI Express interface.
0 = PCI Express receiver cannot process downstream memory transactions and must
respond with an unsupported request (default)
1 = PCI Express receiver can process downstream memory transactions. The bridge can
forward memory transactions to the PCI interface.
I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the PCI
Express interface.
0 = PCI Express receiver cannot process downstream I/O transactions and must respond
with an unsupported request (default)
1 = PCI Express receiver can process downstream I/O transactions. The bridge can forward
I/O transactions to the PCI interface.
assertions detected on the PCI bus.
Classic PCI Configuration Space
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4.4 Status Register
The status register provides information about the PCI Express interface to the system. See Table 4−3 for a
complete description of the register contents.
PCI register offset: 06h
Register type: Read-only, Read/Clear
Default value: 0010h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Table 4−3. Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Detected parity error. This bit is set when the PCI Express interface receives a poisoned TLP. This
bit is set regardless of the state of bit 6 (PERR_ENB) in the command register (offset 04h, see
15 PAR_ERR RCU
14 SYS_ERR RCU
13 MABORT RCU
12 TABORT_REC RCU
11 TABORT_SIG RCU
10:9 PCI_SPEED R DEVSEL timing. These bits are read-only 00b, because they do not apply to PCI Express.
8 DATAPAR RCU
7 FBB_CAP R
6 RSVD R Reserved. Returns 0b when read.
5 66MHZ R
4 CAPLIST R
3 INT_STATUS R
2:0 RSVD R Reserved. Returns 000b when read.
Section 4.3).
0 = No parity error detected
1 = Parity error detected
Signaled system error. This bit is set when the bridge sends an ERR_FATAL or ERR_NONFATAL
message and bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set.
0 = No error signaled
1 = ERR_FATAL or ERR_NONFATAL signaled
Received master abort. This bit is set when the PCI Express interface of the bridge receives a
completion-with-unsupported-request status.
0 = Unsupported request not received on the PCI Express interface
1 = Unsupported request received on the PCI Express interface
Received target abort. This bit is set when the PCI Express interface of the bridge receives a
completion-with-completer-abort status.
0 = Completer abort not received on the PCI Express interface
1 = Completer abort received on the PCI Express interface
Signaled target abort. This bit is set when the PCI Express interface completes a request with
completer abort status.
0 = Completer abort not signaled on the PCI Express interface
1 = Completer abort signaled on the PCI Express interface
Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset 04h,
see Section 4.3) is set and the bridge receives a completion with data marked as poisoned on the
PCI Express interface or poisons a write request received on the PCI Express interface.
0 = No uncorrectable data error detected on the primary interface
1 = Uncorrectable data error detected on the primary interface
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express device
and is hardwired to 0b.
66-MHz capable. This bit does not have a meaningful context for a PCI Express device and is
hardwired to 0b.
Capabilities list. This bit returns 1b when read, indicating that the bridge supports additional PCI
capabilities.
Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only 0b since
the bridge does not generate any interrupts internally.
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Classic PCI Configuration Space
4.5 Class Code and Revision ID Register
This read-only register categorizes the base class, subclass, and programming interface of the bridge. The
base class is 06h, identifying the device as a bridge. The subclass is 04h, identifying the function as a
PCI-to-PCI bridge, and the programming interface is 00h. Furthermore, the TI device revision is indicated in
the lower byte (03h). See Table 4−4 for a complete description of the register contents.
PCI register offset: 08h
Register type: Read-only
Default value: 0604 0003
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Table 4−4. Class Code and Revision ID Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:24 BASECLASS R Base class. This field returns 06h when read, which classifies the function as a bridge device.
23:16 SUBCLASS R Subclass. This field returns 04h when read, which classifies the function as a PCI-to-PCI bridge.
15:8 PGMIF R Programming interface. This field returns 00h when read.
7:0 CHIPREV R Silicon revision. This field returns the silicon revision of the function.
4.6 Cache Line Size Register
This read/write cache line size register is used by the bridge to determine how much data to prefetch when
handling delayed read transactions. The value in this register must be programmed to a power of 2. Any written
odd value (bit 0 = 1b) or value greater than 32 DWORDs is treated as 0 DWORDs.
PCI register offset: 0Ch
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.7 Primary Latency Timer Register
This read-only register has no meaningful context for a PCI Express device and returns the value 00h when
read.
PCI register offset: 0Dh
Register type: Read-only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.8 Header Type Register
This read-only register indicates that this function has a type one PCI header. Bit 7 of this register is 0b
indicating that the bridge is a single-function device.
PCI register offset: 0Eh
Register type: Read-only
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
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Classic PCI Configuration Space
4.9 BIST Register
Since the bridge does not support a built-in self test (BIST), this read-only register returns the value of 00h
when read.
PCI register offset: 0Fh
Register type: Read-only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.10 Device Control Base Address Register
This register programs the memory base address that acesses the device control registers. By default, this
register is read only. If bit 5 of the Control and Diagnostic Register 2 (offset C8h) is set, then the bits 31:12
of this register become read/write. See Table 4−5 for a complete description of the register contents.
PCI register offset: 10h
Register type: Read-only, Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−5. Device Control Base Address Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Memory base address. The memory address field for the bridge uses 20 read/write bits indicating
31:12 ADDRESS R,R/W
11:4 RSVD R Reserved. These bits are read-only and return 00h when read.
3 PRE_FETCH R Prefetchable. This bit is read-only 0b indicating that this memory window is not prefetchable.
2:1 MEM_TYPE R
0 MEM_IND R Memory space indicator. This field returns 0b indicating that memory space is used.
that 4096 bytes is the amount of memory space that is reserved. These bits are read only if
Register C8h bit 5 is clear. If bit 5 is set, then these bits become Read/Write.
Memory type. This field is read-only 00b indicating that this window can be located anywhere in the
32-bit address space.
4.11 Primary Bus Number Register
This read/write register specifies the bus number of the PCI bus segment that the PCI Express interface is
connected to.
PCI register offset: 18h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
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4.12 Secondary Bus Number Register
This read/write register specifies the bus number of the PCI bus segment that the PCI interface is connected
to. The bridge uses this register to determine how to respond to a type 1 configuration transaction.
PCI register offset: 19h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.13 Subordinate Bus Number Register
This read/write register specifies the bus number of the highest number PCI bus segment that is downstream
of the bridge. The bridge uses this register to determine how to respond to a type 1 configuration transaction.
PCI register offset: 1Ah
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Classic PCI Configuration Space
4.14 Secondary Latency Timer Register
This read/write register specifies the secondary bus latency timer for the bridge, in units of PCI clock cycles.
PCI register offset: 1Bh
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.15 I/O Base Register
This read/write register specifies the lower limit of the I/O addresses that the bridge forwards downstream.
See Table 4−6 for a complete description of the register contents.
PCI register offset: 1Ch
Register type: Read-only, Read/Write
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
Table 4−6. I/O Base Register Description
BIT FIELD NAME ACCESS DESCRIPTION
I/O base. Defines the bottom address of the I/O address range that determines when to forward I/O
transactions from one interface to the other. These bits correspond to address bits [15:12] in the
7:4 IOBASE RW
3:0 IOTYPE R I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.
I/O address. The lower 12 bits are assumed to be 000h. The 16 bits corresponding to address bits
[31:16] of the I/O address are defined in the I/O base upper 16 bits register (offset 30h, see
Section 4.24).
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Classic PCI Configuration Space
4.16 I/O Limit Register
This read/write register specifies the upper limit of the I/O addresses that the bridge forwards downstream.
See Table 4−7 for a complete description of the register contents.
PCI register offset: 1Dh
Register type: Read-only, Read/Write
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
Table 4−7. I/O Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
I/O limit. Defines the top address of the I/O address range that determines when to forward I/O
transactions from one interface to the other. These bits correspond to address bits [15:12] in the
7:4 IOLIMIT RW
3:0 IOTYPE R I/O type. This field is read-only 1h indicating that the bridge supports 32-bit I/O addressing.
I/O address. The lower 12 bits are assumed to be FFFh. The 16 bits corresponding to address bits
[31:16] of the I/O address are defined in the I/O limit upper 16 bits register (offset 32h, see
Section 4.25).
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4.17 Secondary Status Register
The secondary status register provides information about the PCI bus interface. See T able 4−8 for a complete
description of the register contents.
PCI register offset: 1Eh
Register type: Read-only, Read/Clear
Default value: 02X0h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 1 0 1 0 x 0 0 0 0 0
Table 4−8. Secondary Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15 PAR_ERR RCU Detected parity error. This bit reports the detection of an uncorrectable address, attribute, or data
14 SYS_ERR RCU Received system error. This bit is set when the bridge detects an SERR assertion.
13 MABORT RCU Received master abort. This bit is set when the PCI interface of the bridge reports the detection of
12 TABORT_REC RCU Received target abort. This bit is set when the PCI interface of the bridge receives a target abort.
11 TABORT_SIG RCU Signaled target abort. This bit reports the signaling of a target abort termination by the bridge when
10:9 PCI_SPEED R DEVSEL timing. These bits are 01b indicating that this is a medium speed decoding device.
8 DATAPAR RCU Master data parity error. This bit is set if the bridge is the bus master of the transaction on the PCI
7 FBB_CAP R Fast back-to-back capable. This bit returns a 1b when read indicating that the secondary PCI
6 RSVD R Reserved. Returns 0b when read.
5 66MHZ R 66-MHz capable. The bridge can operate at a maximum CLK frequency of 66 MHz; therefore, this
4:0 RSVD R Reserved. Returns 00000b when read.
error by the bridge on its secondary interface. This bit must be set when any of the following three
conditions are true:
• The bridge detects an uncorrectable address or attribute error as a potential target.
• The bridge detects an uncorrectable data error when it is the target of a write transaction.
• The bridge detects an uncorrectable data error when it is the master of a read transaction
(immediate read data).
The bit is set irrespective of the state of bit 0 (PERR_EN) in the bridge control register at offset 3Eh
(see Section 4.29).
0 = Uncorrectable address, attribute, or data error not detected on secondary interface
1 = Uncorrectable address, attribute, or data error detected on secondary interface
0 = No error asserted on the PCI interface
1 = SERR
a master abort termination by the bridge when it is the master of a transaction on its secondary
interface.
0 = Master abort not received on the PCI interface
1 = Master abort received on the PCI interface
0 = Target abort not received on the PCI interface
1 = Target abort received on the PCI interface
it responds as the target of a transaction on its secondary interface.
0 = Target abort not signaled on the PCI interface
1 = Target abort signaled on the PCI interface
bus, bit 0 (PERR_EN) in the bridge control register (offset 3Eh see Section 4.29) is set, and the
bridge either asserts PERR on a read transaction or detects PERR asserted on a write transaction.
0 = No data parity error detected on the PCI interface
1 = Data parity error detected on the PCI interface
interface of bridge supports fast back-to-back transactions.
bit reflects the state of the M66EN terminal.
asserted on the PCI interface
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4.18 Memory Base Register
This read/write register specifies the lower limit of the memory addresses that the bridge forwards
downstream. See Table 4−9 for a complete description of the register contents.
PCI register offset: 20h
Register type: Read-only, Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−9. Memory Base Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Memory base. Defines the lowest address of the memory address range that determines when to
15:4 MEMBASE RW
3:0 RSVD R Reserved. Returns 0h when read.
forward memory transactions from one interface to the other. These bits correspond to address bits
[31:20] in the memory address. The lower 20 bits are assumed to be 00000h.
4.19 Memory Limit Register
This read/write register specifies the upper limit of the memory addresses that the bridge forwards
downstream. See Table 4−10 for a complete description of the register contents.
PCI register offset: 22h
Register type: Read-only, Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−10. Memory Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Memory limit. Defines the highest address of the memory address range that determines when to
15:4 MEMLIMIT RW
3:0 RSVD R Reserved. Returns 0h when read.
forward memory transactions from one interface to the other. These bits correspond to address bits
[31:20] in the memory address. The lower 20 bits are assumed to be FFFFFh.
4.20 Prefetchable Memory Base Register
This read/write register specifies the lower limit of the prefetchable memory addresses that the bridge forwards
downstream. See Table 4−11 for a complete description of the register contents.
PCI register offset: 24h
Register type: Read-only, Read/Write
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 4−11. Prefetchable Memory Base Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Prefetchable memory base. Defines the lowest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
15:4 PREBASE RW
3:0 64BIT R
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
00000h. The prefetchable base upper 32 bits register (offset 28h, see Section 4.22) specifies
bits [63:32] of the 64-bit prefetchable memory address.
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
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4.21 Prefetchable Memory Limit Register
This read/write register specifies the upper limit of the prefetchable memory addresses that the bridge
forwards downstream. See Table 4−12 for a complete description of the register contents.
PCI register offset: 26h
Register type: Read-only, Read/Write
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 4−12. Prefetchable Memory Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Prefetchable memory limit. Defines the highest address of the prefetchable memory address range
that determines when to forward memory transactions from one interface to the other. These bits
15:4 PRELIMIT RW
3:0 64BIT R
correspond to address bits [31:20] in the memory address. The lower 20 bits are assumed to be
FFFFFh. The prefetchable limit upper 32 bits register (offset 2Ch, see Section 4.23) specifies bits
[63:32] of the 64-bit prefetchable memory address.
64-bit memory indicator. These read-only bits indicate that 64-bit addressing is supported for this
memory window.
4.22 Prefetchable Base Upper 32-Bit Register
This read/write register specifies the upper 32 bits of the prefetchable memory base register. See Table 4−13
for a complete description of the register contents.
PCI register offset: 28h
Register type: Read/Write
Default value: 0000 0000h
Classic PCI Configuration Space
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−13. Prefetchable Base Upper 32-Bit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Prefetchable memory base upper 32 bits. Defines the upper 32 bits of the lowest address of the
31:0 PREBASE RW
prefetchable memory address range that determines when to forward memory transactions
downstream.
4.23 Prefetchable Limit Upper 32-Bit Register
This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See Table 4−14
for a complete description of the register contents.
PCI register offset: 2Ch
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−14. Prefetchable Limit Upper 32-Bit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the
31:0 PRELIMIT RW
prefetchable memory address range that determines when to forward memory transactions
downstream.
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Classic PCI Configuration Space
4.24 I/O Base Upper 16-Bit Register
This read/write register specifies the upper 16 bits of the I/O base register. See Table 4−15 for a complete
description of the register contents.
PCI register offset: 30h
Register type: Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−15. I/O Base Upper 16-Bit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
I/O base upper 16 bits. Defines the upper 16 bits of the lowest address of the I/O address range
15:0 IOBASE RW
that determines when to forward I/O transactions downstream. These bits correspond to address
bits [31:20] in the I/O address. The lower 20 bits are assumed to be 00000h.
4.25 I/O Limit Upper 16-Bit Register
This read/write register specifies the upper 16 bits of the I/O limit register. See Table 4−16 for a complete
description of the register contents.
PCI register offset: 32h
Register type: Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−16. I/O Limit Upper 16-Bit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
I/O limit upper 16 bits. Defines the upper 16 bits of the top address of the I/O address range that
15:0 IOLIMIT RW
determines when to forward I/O transactions downstream. These bits correspond to address
bits [31:20] in the I/O address. The lower 20 bits are assumed to be FFFFFh.
4.26 Capabilities Pointer Register
This read-only register provides a pointer into the PCI configuration header where the PCI power management
block resides. Since the PCI power management registers begin at 50h, this register is hardwired to 50h.
PCI register offset: 34h
Register type: Read-only
Default value: 50h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 1 0 1 0 0 0 0
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4.27 Interrupt Line Register
This read/write register is programmed by the system and indicates to the software which interrupt line the
bridge has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not yet
been assigned to the function. Since the bridge does not generate interrupts internally, this register is a scratch
pad register.
PCI register offset: 3Ch
Register type: Read/Write
Default value: FFh
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 1 1 1 1 1 1 1 1
4.28 Interrupt Pin Register
The interrupt pin register is read-only 00h indicating that the bridge does not generate internal interrupts. While
the bridge does not generate internal interrupts, it does forward interrupts from the secondary interface to the
primary interface.
PCI register offset: 3Dh
Register type: Read-only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Classic PCI Configuration Space
4.29 Bridge Control Register
The bridge control register provides extensions to the command register that are specific to a bridge. See
Table 4−17 for a complete description of the register contents.
PCI register offset: 3Eh
Register type: Read-only, Read/Write, Read/Clear
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−17. Bridge Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:12 RSVD R Reserved. Returns 0h when read.
11 DTSERR RW Discard timer SERR enable. Applies only in conventional PCI mode. This bit enables the bridge to
10 DTSTATUS RCU Discard timer status. This bit indicates if a discard timer expires and a delayed transaction is
generate either an ERR_NONFATAL (by default) or ERR_FATAL transaction on the primary
interface when the secondary discard timer expires and a delayed transaction is discarded from a
queue in the bridge. The severity is selectable only if advanced error reporting is supported.
0 = Do not generate ERR_NONFATAL or ERR_FATAL on the primary interface as a result of
the expiration of the secondary discard timer. Note that an error message can still be sent if
advanced error reporting is supported and bit 10 (DISCARD_TIMER_MASK) in the
secondary uncorrectable error mask register (offset 130h, see Section 5.11) is clear
(default).
1 = Generate ERR_NONFATAL or ERR_FATAL on the primary interface if the secondary
discard timer expires and a delayed transaction is discarded from a queue in the bridge
discarded.
0 = No discard timer error
1 = Discard timer error
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Classic PCI Configuration Space
Table 4−17. Bridge Control Register Description (Continued)
BIT FIELD NAME ACCESS DESCRIPTION
9 SEC_DT RW Selects the number of PCI clocks that the bridge waits for a master on the secondary interface to
8 PRI_DEC R Primary discard timer. This bit has no meaning in PCI Express and is hardwired to 0b.
7 FBB_EN RW Fast back-to-back enable. This bit allows software to enable fast back-to-back transactions on the
6 SRST RW Secondary bus reset. This bit is set when software wishes to reset all devices downstream of the
5 MAM RW Master abort mode. This bit controls the behavior of the bridge when it receives a master abort or
4 VGA16 RW VGA 16-bit decode. This bit enables the bridge to provide full 16-bit decoding for VGA I/O
3 VGA RW VGA enable. This bit modifies the response by the bridge to VGA compatible addresses. If this bit
repeat a delayed transaction request. The counter starts once the delayed completion (the
completion of the delayed transaction on the primary interface) has reached the head of the
downstream queue of the bridge (i.e., all ordering requirements have been satisfied and the bridge
is ready to complete the delayed transaction with the initiating master on the secondary bus). If the
master does not repeat the transaction before the counter expires, then the bridge deletes the
delayed transaction from its queue and sets the discard timer status bit.
0 = The secondary discard timer counts 215 PCI clock cycles (default)
1 = The secondary discard timer counts 210 PCI clock cycles
secondary PCI interface.
0 = Fast back-to-back transactions are disabled (default)
1 = Secondary interface fast back-to-back transactions are enabled
bridge. Setting this bit causes the PRST
0 = Secondary interface is not in reset state (default)
1 = Secondary interface is in the reset state
an unsupported request.
0 = Do not report master aborts. Returns FFFF FFFFh on reads and discards data on writes
(default).
1 = Respond with an unsupported request on PCI Express when a master abort is received on
PCI. Respond with target abort on PCI when an unsupported request completion on PCI
Express is received. This bit also enables error signaling on master abort conditions on
posted writes.
addresses. This bit only has meaning if the VGA enable bit is set.
0 = Ignore address bits [15:10] when decoding VGA I/O addresses (default)
1 = Decode address bits [15:10] when decoding VGA I/O addresses
is set, then the bridge decodes and forwards the following accesses on the primary interface to the
secondary interface (and, conversely, block the forwarding of these addresses from the secondary
to primary interface):
terminal on the secondary interface to be asserted.
• Memory accesses in the range 000A 0000h to 000B FFFFh
• I/O addresses in the first 64 KB of the I/O address space (address bits [31:16] are 0000h) and
where address bits [9:0] are in the range of 3B0h to 3BBh or 3C0h to 3DFh (inclusive of ISA
address aliases – address bits [15:10] may possess any value and are not used in the decoding)
If this bit is set, then forwarding of VGA addresses is independent of the value of bit 2 (ISA), the I/O
address and memory address ranges defined by the I/O base and limit registers, the memory base
and limit registers, and the prefetchable memory base and limit registers of the bridge. The
forwarding of VGA addresses is qualified by bits 0 (IO_ENB) and 1 (MEMORY_ENB) in the
command register (offset 04h, see Section 4.3).
0 = Do not forward VGA compatible memory and I/O addresses from the primary to secondary
interface (addresses defined above) unless they are enabled for forwarding by the defined
I/O and memory address ranges (default)
1 = Forward VGA compatible memory and I/O addresses (addresses defined above) from the
primary interface to the secondary interface (if the I/O enable and memory enable bits are
set) independent of the I/O and memory address ranges and independent of the ISA enable
bit
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Classic PCI Configuration Space
Table 4−17. Bridge Control Register Description (Continued)
BIT FIELD NAME ACCESS DESCRIPTION
2 ISA RW ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This applies only to
1 SERR_EN RW SERR enable. This bit controls forwarding of system error events from the secondary interface to
I/O addresses that are enabled by the I/O base and I/O limit registers and are in the first 64 KB of
PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is set, then the bridge blocks any
forwarding from primary to secondary of I/O transactions addressing the last 768 bytes in each
1 KB block. In the opposite direction (secondary to primary), I/O transactions are forwarded if they
address the last 768 bytes in each 1K block.
0 = Forward downstream all I/O addresses in the address range defined by the I/O base and
I/O limit registers (default)
1 = Forward upstream ISA I/O addresses in the address range defined by the I/O base and I/O
limit registers that are in the first 64 KB of PCI I/O address space (top 768 bytes of each
1-KB block)
the primary interface. The bridge forwards system error events when:
• This bit is set
• Bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set
• SERR is asserted on the secondary interface
0 = Disable the forwarding of system error events (default)
1 = Enable the forwarding of system error events
0 PERR_EN RW Parity error response enable. Controls the bridge’s response to data, uncorrectable address, and
attribute errors on the secondary interface. Also, the bridge always forwards data with poisoning,
from conventional PCI to PCI Express on an uncorrectable conventional PCI data error, regardless
of the setting of this bit.
0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface
(default)
1 = Enable uncorrectable address, attribute, and data error detection and reporting on the
secondary interface
4.30 Capability ID Register
This read-only register identifies the linked list item as the register for PCI power management. The register
returns 01h when read.
PCI register offset: 50h
Register type: Read-only
Default value: 01h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1
4.31 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 60h pointing to the MSI capabilities registers.
PCI register offset: 51h
Register type: Read-only
Default value: 60h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 1 1 0 0 0 0 0
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Classic PCI Configuration Space
4.32 Power Management Capabilities Register
This read-only register indicates the capabilities of the bridge related to PCI power management. See
Table 4−18 for a complete description of the register contents.
PCI register offset: 52h
Register type: Read-only
Default value: 0602h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0
Table 4−18. Power Management Capabilities Register Description
BIT FIELD NAME ACCESS DESCRIPTION
PME support. This 5-bit field indicates the power states from which the bridge may assert PME.
15:11 PME_SUPPORT R
10 D2_SUPPORT R This bit returns a 1b when read, indicating that the function supports the D2 device power state.
9 D1_SUPPORT R This bit returns a 1b when read, indicating that the function supports the D1 device power state.
8:6 AUX_CURRENT R
5 DSI R
4 RSVD R Reserved. Returns 0b when read.
3 PME_CLK R PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.
2:0 PM_VERSION R
Because the bridge never generates a PME
is read-only and returns 00000b.
3.3 V
generate PME
Device specific initialization. This bit returns 0b when read, indicating that the bridge does not
require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
Power management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register
(offset D4h, see Section 4.65) is 0b, then this field returns 010b indicating revision 1.1
compatibility. If PCI_PM_VERSION_CTRL is 1b, then this field returns 011b indicating revision
1.2 compatibility.
auxiliary current requirements. This field returns 000b since the bridge does not
AUX
from D3
cold
.
except on a behalf of a secondary device, this field
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4.33 Power Management Control/Status Register
This register determines and changes the current power state of the bridge. No internal reset is generated
when transitioning from the D3
state to the D0 state. See Table 4−19 for a complete description of the
hot
register contents.
PCI register offset: 54h
Register type: Read-only, Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−19. Power Management Control/Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15 PME_STAT R PME status. This bit is read-only and returns 0b when read.
14:13 DATA_SCALE R
12:9 DATA_SEL R
8 PME_EN RW
7:4 RSVD R Reserved. Returns 0h when read.
3 NO_SOFT_RESET R
2 RSVD R Reserved. Returns 0b when read.
1:0 PWR_STATE RW
Data scale. This 2-bit field returns 00b when read since the bridge does not use the data
register.
Data select. This 4-bit field returns 0h when read since the bridge does not use the data
register.
PME enable. This bit has no function and acts as scratchpad space. The default value for this
bit is 0b.
No soft reset. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register (offset D4h,
see Section 4.65) is 0b, then this bit returns 0b for compatibility with version 1.1 of the PCI
Power Management Specification. If PCI_PM_VERSION_CTRL is 1b, then this bit returns 1b
indicating that no internal reset is generated and the device retains its configuration context
when transitioning from the D3
Power state. This 2-bit field determines the current power state of the function and sets the
function into a new power state. This field is encoded as follows:
00 = D0 (default)
01 = D1
10 = D2
11 = D3
hot
state to the D0 state.
hot
4.34 Power Management Bridge Support Extension Register
Classic PCI Configuration Space
This read-only register indicates to host software what the state of the secondary bus will be when the bridge
is placed in D3. See Table 4−20 for a complete description of the register contents.
PCI register offset: 56h
Register type: Read-only
Default value: 40h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 1 0 0 0 0 0 0
Table 4−20. Power Management Bridge Support Extension Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Bus power/clock control enable. This bit indicates to the host software if the bus secondary clocks
are stopped when the bridge is placed in D3. The state of the BPCC bit is controlled by bit 11
7 BPCC R
6 BSTATE R B2/B3 support. This bit is read-only 1b indicating that the bus state in D3 is B2.
5:0 RSVD R Reserved. Returns 00 0000b when read.
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(BPCC_E) in the general control register (offset D4h, see Section 4.65).
0 = The secondary bus clocks are not stopped in D3
1 = The secondary bus clocks are stopped in D3
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Classic PCI Configuration Space
4.35 Power Management Data Register
The read-only register is not applicable to the bridge and returns 00h when read.
PCI register offset: 57h
Register type: Read-only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.36 MSI Capability ID Register
This read-only register identifies the linked list item as the register for message signaled interrupts capabilities.
The register returns 05h when read.
PCI register offset: 60h
Register type: Read-only
Default value: 05h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 0 1
4.37 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 80h pointing to the subsystem ID capabilities registers.
PCI register offset: 61h
Register type: Read-only
Default value: 80h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 1 0 0 0 0 0 0 0
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4.38 MSI Message Control Register
This register controls the sending of MSI messages. See Table 4−21 for a complete description of the register
contents.
PCI register offset: 62h
Register type: Read-only, Read/Write
Default value: 0088h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0
Table 4−21. MSI Message Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved. Returns 00h when read.
7 64CAP R
6:4 MM_EN RW
3:1 MM_CAP R
0 MSI_EN RW
64-bit message capability. This bit is read-only 1b indicating that the bridge supports 64-bit MSI
message addressing.
Multiple message enable. This bit indicates the number of distinct messages that the bridge is
allowed to generate.
000 = 1 message (default)
001 = 2 messages
010 = 4 messages
011 = 8 messages
100 = 16 messages
101 = Reserved
110 = Reserved
111 = Reserved
Multiple message capabilities. This field indicates the number of distinct messages that bridge is
capable of generating. This field is read-only 100b indicating that the bridge can signal 1 interrupt
for each IRQ supported on the serial IRQ stream up to a maximum of 16 unique interrupts.
MSI enable. This bit enables MSI interrupt signaling. MSI signaling must be enabled by software
for the bridge to signal that a serial IRQ has been detected.
0 = MSI signaling is prohibited (default)
1 = MSI signaling is enabled
Classic PCI Configuration Space
4.39 MSI Message Lower Address Register
This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is
detected. See Table 4−22 for a complete description of the register contents.
PCI register offset: 64h
Register type: Read-only, Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−22. MSI Message Lower Address Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:2 ADDRESS RW System specified message address
1:0 RSVD R Reserved. Returns 00b when read.
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Classic PCI Configuration Space
4.40 MSI Message Upper Address Register
This register contains the upper 32 bits of the address that a MSI message writes to when a serial IRQ is
detected. If this register contains 0000 0000h, then 32-bit addressing is used; otherwise, 64-bit addressing
is used.
PCI register offset: 68h
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.41 MSI Message Data Register
This register contains the data that software programmed the bridge to send when it send a MSI message.
See Table 4−23 for a complete description of the register contents.
PCI register offset: 6Ch
Register type: Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−23. MSI Message Data Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:4 MSG RW
3:0 MSG_NUM RW
System specific message. This field contains the portion of the message that the bridge forwards
unmodified.
Message number. This portion of the message field may be modified to contain the message
number is multiple messages are enable. The number of bits that are modifiable depends on the
number of messages enabled in the message control register.
1 message = No message data bits can be modified (default)
2 messages = Bit 0 can be modified
4 messages = Bits 1:0 can be modified
8 messages = Bits 2:0 can be modified
16 messages = Bits 3:0 can be modified
4.42 Capability ID Register
This read-only register identifies the linked list item as the register for subsystem ID and subsystem vendor
ID capabilities. The register returns 0Dh when read.
PCI register offset: 80h
Register type: Read-only
Default value: 0Dh
68
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 1 1 0 1
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4.43 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 90h pointing to the PCI Express capabilities registers.
PCI register offset: 81h
Register type: Read-only
Default value: 90h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 1 0 0 1 0 0 0 0
4.44 Subsystem Vendor ID Register
This register, used for system and option card identification purposes, may be required for certain operating
systems. This read-only register is initialized through the EEPROM and can be written through the subsystem
alias register. This register is reset by a PCI Express reset (PERST
power-on reset.
PCI register offset: 84h
Register type: Read-only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Classic PCI Configuration Space
), a GRST, or the internally-generated
4.45 Subsystem ID Register
This register, used for system and option card identification purposes, may be required for certain operating
systems. This read-only register is initialized through the EEPROM and can be written through the subsystem
alias register. This register is reset by a PCI Express reset (PERST
power-on reset.
PCI register offset: 86h
Register type: Read-only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.46 PCI Express Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express capabilities. The register
returns 10h when read.
PCI register offset: 90h
Register type: Read-only
Default value: 10h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 0 0
), a GRST, or the internally-generated
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Classic PCI Configuration Space
4.47 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 00h indicating no additional capabilities are supported.
PCI register offset: 91h
Register type: Read-only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.48 PCI Express Capabilities Register
This read-only register indicates the capabilities of the bridge related to PCI Express. See Table 4−24 for a
complete description of the register contents.
PCI register offset: 92h
Register type: Read-only
Default value: 0071h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1
Table 4−24. PCI Express Capabilities Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:14 RSVD R Reserved. Returns 00b when read.
13:9 INT_NUM R
8 SLOT R Slot implemented. This bit is not valid for the bridge and is read-only 0b.
7:4 DEV_TYPE R
3:0 VERSION R Capability version. This field returns 1h indicating revision 1 of the PCI Express capability.
Interrupt message number. This field is used for MSI support and is implemented as read-only
00000b in the bridge.
Device/port type. This read-only field returns 7h indicating that the device is a PCI Express-to-PCI
bridge.
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Classic PCI Configuration Space
4.49 Device Capabilities Register
The device capabilities register indicates the device specific capabilities of the bridge. See Table 4−25 for a
complete description of the register contents.
PCI register offset: 94h
Register type: Read-only
Default value: 0000 0D82
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0
Table 4−25. Device Capabilities Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:28 RSVD R Reserved. Returns 0h when read.
27:26 CSPLS RU Captured slot power limit scale. The value in this field is programmed by the host by issuing a
25:18 CSPLV RU Captured slot power limit value. The value in this field is programmed by the host by issuing a
17:15 RSVD R Reserved. Returns 000b when read.
14 PIP R Power indicator present. This bit is hardwired to 0b indicating that a power indicator is not
13 AIP R Attention indicator present. This bit is hardwired to 0b indicating that an attention indicator is not
12 ABP R Attention button present. This bit is hardwired to 0b indicating that an attention button is not
11:9 EP_L1_LAT RU Endpoint L1 acceptable latency. This field indicates the maximum acceptable latency for a
8:6 EP_L0S_LAT RU Endpoint L0s acceptable latency. This field indicates the maximum acceptable latency for a
5 ETFS R Extended tag field supported. This field indicates the size of the tag field not supported.
4:3 PFS R Phantom functions supported. This field is read-only 00b indicating that function numbers are not
2:0 MPSS R Maximum payload size supported. This field indicates the maximum payload size that the device
Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 9:8 are
written to this field. The value in this field specifies the scale used for the slot power limit.
00 = 1.0x
01 = 0.1x
10 = 0.01x
11 = 0.001x
Set_Slot_Power_Limit message. When a Set_Slot_Power_Limit message is received, bits 7:0 are
written to this field. The value in this field in combination with the slot power limit scale value
(bits 27:26) specifies the upper limit of power supplied to the slot. The power limit is calculated by
multiplying the value in this field by the value in the slot power limit scale field.
implemented.
implemented.
implemented.
transition from L1 to L0 state. This field can be programmed by writing to the L1_LATENCY field
(bits 15:13) in the general control register (offset D4h, see Section 4.65). The default value for this
field is 110b which indicates a range from 32 µs to 64 µs. This field cannot be programmed to be
less than the latency for the PHY to exit the L1 state.
transition from L0s to L0 state. This field can be programmed by writing to the L0s_LATENCY field
(bits 18:16) in the general control register (offset D4h, see Section 4.65). The default value for this
field is 110b which indicates a range from 2 µs to 4 µs. This field cannot be programmed to be less
than the latency for the PHY to exit the L0s state.
used for phantom functions.
can support for TLPs. This field is encoded as 010b indicating the maximum payload size for a TLP
is 512 bytes.
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Classic PCI Configuration Space
4.50 Device Control Register
The device control register controls PCI Express device specific parameters. See Table 4−26 for a complete
description of the register contents.
PCI register offset: 98h
Register type: Read-only, Read/Write
Default value: 2800h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Table 4−26. Device Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Configuration retry status enable. When this read/write bit is set to 1b, the bridge returns a
completion with completion retry status on PCI Express if a configuration transaction forwarded
15 CFG_RTRY_ENB RW
14:12 MRRS RW
11 ENS RW
k
10
9 PFE R
8 ETFE R
7:5 MPS RW
4 ERO R
APPE RW
k This bit is sticky and must retain its value when the bridge is powered by V
to the secondary interface did not complete within the implementation specific time-out period.
When this bit is set to 0b, the bridge does not generate completions with completion retry status
on behalf of configuration transactions. The default value of this bit is 0b.
Maximum read request size. This field is programmed by host software to set the maximum size
of a read request that the bridge can generate. The bridge uses this field in conjunction with the
cache line size register (offset 0Ch, see Section 4.6) to determine how much data to fetch on a
read request. This field is encoded as:
000 = 128B
001 = 256B
010 = 512B (default)
011 = 1024B
100 = 2048B
101 = 4096B
110 = Reserved
111 = Reserved
Enable no snoop. Controls the setting of the no snoop flag within the TLP header for upstream
memory transactions mapped to any traffic class mapped to a virtual channel (VC) other than
VC0 through the upstream decode windows.
0 = No snoop field is 0b
1 = No snoop field is 1b (default)
Auxiliary power PM enable. This bit has no effect in the bridge.
0 = AUX power is disabled (default)
1 = AUX power is enabled
Phantom function enable. Since the bridge does not support phantom functions, this bit is
read-only 0b.
Extended tag field enable. Since the bridge does not support extended tags, this bit is read-only
0b.
Maximum payload size. This field is programmed by host software to set the maximum size of
posted writes or read completions that the bridge can initiate. This field is encoded as:
000 = 128B (default)
001 = 256B
010 = 512B
011 = 1024B
100 = 2048B
101 = 4096B
110 = Reserved
111 = Reserved
Enable relaxed ordering. Since the bridge does not support relaxed ordering, this bit is read-only
0b.
.
AUX
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Table 4−26. Device Control Register Description (Continued)
BIT FIELD NAME ACCESS DESCRIPTION
Unsupported request reporting enable. If this bit is set, then the bridge sends an ERR_NONFATAL
3 URRE RW
2 FERE RW
1 NFERE RW
0 CERE RW
message to the root complex when an unsupported request is received.
0 = Do not report unsupported requests to the root complex (default)
1 = Report unsupported requests to the root complex
Fatal error reporting enable. If this bit is set, then the bridge is enabled to send ERR_FATAL
messages to the root complex when a system error event occurs.
0 = Do not report fatal errors to the root complex (default)
1 = Report fatal errors to the root complex
Nonfatal error reporting enable. If this bit is set, then the bridge is enabled to send
ERR_NONFATAL messages to the root complex when a system error event occurs.
0 = Do not report nonfatal errors to the root complex (default)
1 = Report nonfatal errors to the root complex
Correctable error reporting enable. If this bit is set, then the bridge is enabled to send ERR_COR
messages to the root complex when a system error event occurs.
0 = Do not report correctable errors to the root complex (default)
1 = Report correctable errors to the root complex
4.51 Device Status Register
The device status register provides PCI Express device specific information to the system. See Table 4−27
for a complete description of the register contents.
Classic PCI Configuration Space
PCI register offset: 9Ah
Register type: Read-only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−27. Device Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:6 RSVD R Reserved. Returns 00 0000 0000b when read.
5 PEND RU
4 APD RU
3 URD RCU
2 FED RCU Fatal error detected. This bit is set by the bridge when a fatal error is detected.
1 NFED RCU Nonfatal error detected. This bit is set by the bridge when a nonfatal error is detected.
0 CED RCU Correctable error detected. This bit is set by the bridge when a correctable error is detected.
Transaction pending. This bit is set when the bridge has issued a nonposted transaction that has
not been completed.
AUX power detected. This bit indicates that AUX power is present.
0 = No AUX power detected
1 = AUX power detected
Unsupported request detected. This bit is set by the bridge when an unsupported request is
received.
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Classic PCI Configuration Space
4.52 Link Capabilities Register
The link capabilities register indicates the link specific capabilities of the bridge. See Table 4−28 for a complete
description of the register contents.
PCI register offset: 9Ch
Register type: Read-only
Default value: 0002 XC11h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 x x x 1 1 0 0 0 0 0 1 0 0 0 1
Table 4−28. Link Capabilities Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:24 PORT_NUM R
23:18 RSVD R Reserved. Returns 00 0000b when read.
17:15 L1_LATENCY R
14:12 L0S_LATENCY R
11:10 ASLPMS R
9:4 MLW R
3:0 MLS R
Port number. This field indicates port number for the PCI Express link. This field is read-only 00h
indicating that the link is associated with port 0.
L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the L0
state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.53) equals 1b for a common
clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of this field is determined by bits 20:18
(L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see Section 4.62).
For an asynchronous reference clock, the value of this field is determined by bits 17:15
(L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see Section 4.62).
L0s exit latency. This field indicates the time that it takes to transition from the L0s state to the L0
state. Bit 6 (CCC) in the link control register (offset A0h, see Section 4.53) equals 1b for a common
clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of 011b indicates that the L1 exit latency falls between
256 ns to less than 512 ns.
For an asynchronous reference clock, the value of 100b indicates that the L1 exit latency falls
between 512 ns to less than 1 µs.
Active state link PM support. This field indicates the level of active state power management that
the bridge supports. The value 11b indicates support for both L0s and L1 through active state
power management.
Maximum link width. This field is encoded 00 0001b to indicate that the bridge only supports a 1x
PCI Express link.
Maximum link speed. This field is encoded 1h to indicate that the bridge supports a maximum link
speed of 2.5 Gb/s.
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4.53 Link Control Register
The link control register controls link specific behavior. See Table 4−29 for a complete description of the
register contents.
PCI register offset: A0h
Register type: Read-only, Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−29. Link Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved. Returns 00h when read.
Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets and an
7 ES RW
6 CCC RW
5 RL R Retrain link. This bit has no function and is read-only 0b.
4 LD R Link disable. This bit has no function and is read-only 0b.
3 RCB RW
2 RSVD R Reserved. Returns 0b when read.
1:0 ASLPMC RW
extra TS2 when exiting from L1 prior to entering to L0.
0 = Normal synch (default)
1 = Extended synch
Common clock configuration. When this bit is set, it indicates that the bridge and the device at the
opposite end of the link are operating with a common clock source. A value of 0b indicates that the
bridge and the device at the opposite end of the link are operating with separate reference clock
sources. The bridge uses this common clock configuration information to report the L0s and L1 exit
latencies.
0 = Reference clock is asynchronous (default)
1 = Reference clock is common
Read completion boundary. This bit is an indication of the RCB of the root complex. The state of
this bit has no affect on the bridge, since the RCB of the bridge is fixed at 128 bytes.
0 = 64 bytes (default)
1 = 128 bytes
Active state link PM control. This field enables and disables the active state PM.
00 = Active state PM disabled (default)
01 = L0s entry enabled
10 = L1 entry enabled
11 = L0s and L1 entry enabled
Classic PCI Configuration Space
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Classic PCI Configuration Space
4.54 Link Status Register
The link status register indicates the current state of the PCI Express link. See Table 4−30 for a complete
description of the register contents.
PCI register offset: A2h
Register type: Read-only
Default value: X011h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 x 0 0 0 0 0 0 0 1 0 0 0 1
Table 4−30. Link Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:13 RSVD R Reserved. Returns 000b when read.
Slot clock configuration. This bit indicates that the bridge uses the same physical reference clock
that the platform provides on the connector. If the bridge uses an independent clock irrespective of
12 SCC R
11 LT R Link training. This bit has no function and is read-only 0b.
10 TE R Retrain link. This bit has no function and is read-only 0b.
9:4 NLW R Negotiated link width. This field is read-only 00 0001b indicating the lane width is 1x.
3:0 LS R Link speed. This field is read-only 1h indicating the link speed is 2.5 Gb/s.
the presence of a reference on the connector, then this bit must be cleared.
0 = Independent 125-MHz reference clock is used
1 = Common 100-MHz reference clock is used
4.55 Serial-Bus Data Register
The serial-bus data register reads and writes data on the serial-bus interface. Write data is loaded into this
register prior to writing the serial-bus slave address register (offset B2h, see Section 4.57) that initiates the
bus cycle. When reading data from the serial bus, this register contains the data read after bit 5 (REQBUSY)
of the serial-bus control and status register (offset B3h, see Section 4.58) is cleared. This register is reset by
a PCI Express reset (PERST
), a GRST, or the internally-generated power-on reset.
PCI register offset: B0h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.56 Serial-Bus Word Address Register
The value written to the serial-bus word address register represents the word address of the byte being read
from or written to the serial-bus device. The word address is loaded into this register prior to writing the
serial-bus slave address register (offset B2h, see Section 4.57) that initiates the bus cycle. This register is reset
by a PCI Express reset (PERST
PCI register offset: B1h
Register type: Read/Write
Default value: 00h
), a GRST, or the internally-generated power-on reset.
76
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
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4.57 Serial-Bus Slave Address Register
The serial-bus slave address register indicates the slave address of the device being targeted by the serial-bus
cycle. This register also indicates if the cycle is a read or a write cycle. Writing to this register initiates the cycle
on the serial interface. See Table 4−31 for a complete description of the register contents.
PCI register offset: B2h
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4−31. Serial-Bus Slave Address Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7:1† SLAVE_ADDR RW
0† RW_CMD RW
†
These bits are reset by a PCI Express reset (PERST
Serial-bus slave address. This 7-bit field is the slave address for a serial-bus read or write
transaction. The default value for this field is 000 0000b.
Read/write command. This bit determines if the serial-bus cycle is a read or a write cycle.
0 = A single byte write is requested (default)
1 = A single byte read is requested
), a GRST, or the internally-generated power-on reset.
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Classic PCI Configuration Space
4.58 Serial-Bus Control and Status Register
The serial-bus control and status register controls the behavior of the serial-bus interface. This register also
provides status information about the state of the serial bus. See Table 4−32 for a complete description of the
register contents.
PCI register offset: B3h
Register type: Read-only, Read/Write, Read/Clear
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4−32. Serial-Bus Control and Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Protocol select. This bit selects the serial-bus address mode used.
7† PROT_SEL RW
6 RSVD R Reserved. Returns 0b when read.
5† REQBUSY RU
4† ROMBUSY RU
3† SBDETECT RWU
2† SBTEST RW
1† SB_ERR RCU
0† ROM_ERR RCU
†
These bits are reset by a PCI Express reset (PERST
0 = Slave address and word address are sent on the serial-bus (default)
1 = Only the slave address is sent on the serial-bus
Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle is in
progress.
0 = No serial-bus cycle
1 = Serial-bus cycle in progress
Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the bridge is
downloading register defaults from a serial EEPROM.
0 = No EEPROM activity
1 = EEPROM download in progress
Serial EEPROM detected. This bit enables the serial-bus interface. The value of this bit controls
whether the GPIO4//SCL and GPIO5//SDA terminals are configured as GPIO signals or as
serial-bus signals. This bit is automatically set to 1b when a serial EEPROM is detected.
Note: A serial EEPROM is only detected once following PERST
0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL and
GPIO5//SDA terminals are configured as GPIO signals.
1 = EEPROM present, EEPROM load process takes place. GPIO4//SCL and GPIO5//SDA
terminals are configured as serial-bus signals.
Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source for the
serial interface clock.
0 = Serial-bus clock at normal operating frequency ~ 60 kHz (default)
1 = Serial-bus clock frequency increased for test purposes ~ 4 MHz
Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus cycle.
0 = No error
1 = Serial-bus error
Serial EEPROM load error. This bit is set when an error occurs while downloading registers from a
serial EEPROM.
0 = No error
1 = EEPROM load error
), a GRST, or the internally-generated power-on reset.
.
78
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4.59 GPIO Control Register
This register controls the direction of the eight GPIO terminals. This register has no effect on the behavior of
GPIO terminals that are enabled to perform secondary functions. The secondary functions share GPIO0
(CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). See Table 4−33 for a complete
description of the register contents.
PCI register offset: B4h
Register type: Read-only, Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−33. GPIO Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved. Returns 00h when read.
GPIO 7 data direction. This bit selects whether GPIO7 is in input or output mode.
7† GPIO7_DIR RW
6† GPIO6_DIR RW
5† GPIO5_DIR RW
4† GPIO4_DIR RW
3† GPIO3_DIR RW
2† GPIO2_DIR RW
1† GPIO1_DIR RW
0† GPIO0_DIR RW
†
These bits are reset by a PCI Express reset (PERST
0 = Input (default)
1 = Output
GPIO 6 data direction. This bit selects whether GPIO6 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 5 data direction. This bit selects whether GPIO5 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 4 data direction. This bit selects whether GPIO4 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 3 data direction. This bit selects whether GPIO3 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 2 data direction. This bit selects whether GPIO2 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 1 data direction. This bit selects whether GPIO1 is in input or output mode.
0 = Input (default)
1 = Output
GPIO 0 data direction. This bit selects whether GPIO0 is in input or output mode.
0 = Input (default)
1 = Output
), a GRST, or the internally-generated power-on reset.
Classic PCI Configuration Space
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79
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Classic PCI Configuration Space
4.60 GPIO Data Register
This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO
terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary
functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO4 (SCL), and GPIO5 (SDA). The default
value at power up depends on the state of the GPIO terminals as they default to general-purpose inputs. See
Table 4−34 for a complete description of the register contents.
PCI register offset: B6h
Register type: Read-only, Read/Write
Default value: 00XXh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 x x x x x x x x
Table 4−34. GPIO Data Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved. Returns 00h when read.
7† GPIO7_DATA RW
6† GPIO6_DATA RW
5† GPIO5_DATA RW
4† GPIO4_DATA RW
3† GPIO3_DATA RW
2† GPIO2_DATA RW
1† GPIO1_DATA RW
0† GPIO0_DATA RW
†
These bits are reset by a PCI Express reset (PERST
GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of GPIO7
when in output mode.
GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of GPIO6
when in output mode.
GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of GPIO5
when in output mode.
GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of GPIO4
when in output mode.
GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of GPIO3
when in output mode.
GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of GPIO2
when in output mode.
GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of GPIO1
when in output mode.
GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of GPIO0
when in output mode.
), a GRST, or the internally-generated power-on reset.
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4.61 Control and Diagnostic Register 0
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−35 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset: C0h
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−35. Control and Diagnostic Register 0 Description
BIT FIELD NAME ACCESS DESCRIPTION
31:24† PRI_BUS_NUM R This field contains the captured primary bus number
23:19†
18:16 RSVD R Reserved. Returns 000b when read.
15:14† RSVD RW
13:12 RSVD R Reserved. Returns 00b when read.
11:8† RSVD RW
5:4†
†
These bits are reset by a PCI Express reset (PERST
PRI_DEVICE_
NUM
7 RSVD R Reserved. Returns 0b when read.
6† PREFETCH_4X RW
UP_REQ_BUF
_VALUE
UP_REQ_BUF
3†
2†
1† RSVD RW
0 RSVD R Reserved. Returns 0b when read.
_CTRL
CFG_ACCESS
_MEM_REG
R This field contains the captured primary device number
Reserved. Bits 15:14 default to 00b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 00b.
Reserved. Bits 11:8 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
Prefetch 4X enable. This bit sets the prefetch behavior for upstream memory read multiple
transactions. If bit 24 (FORCE_MRM) in the general control register (offset D4h, see Section 4.65)
is set, then all upstream memory read transactions will prefetch the indicated number of cache lines.
If bit 19 (READ_PREFETCH_DIS) in the general control register (offset D4h, see Section 4.65) is
set, then this bit has no effect and only 1 DWORD will be fetched.
0 = The bridge will prefetch up to 2 cache lines, as defined in the cache line size register (offset
0Ch, see Section 4.6) for upstream memory read multiple (MRM) transactions (default)
1 = The bridge device will prefetch up to 4 cache lines, as defined in the cache line size register
(offset 0Ch, see Section 4.6) for upstream memory read multiple (MRM) transactions.
PCI upstream req−res buffer threshold value. The value in this field controls the buffer space that
must be available for the bridge to accept a PCI bus transaction. If the cache line size is not valid,
then the bridge will use 8 DW for calculating the threshold value
RW
RW
RW
00 = 1 Cacheline + 4 DW (default)
01 = 1 Cacheline + 8 DW
10 = 1 Cacheline + 12 DW
11 = 2 Cachelines + 4 DW
PCI upstream req-res buffer threshold control. This bit enables the PCI upstream req-res buffer
threshold control mode of the bridge.
0 = PCI upstream req-res buffer threshold control mode disabled (default)
1 = PCI upstream req-res buffer threshold control mode enabled
Configuration access to memory-mapped registers. When this bit is set, the bridge allows
configuration access to memory-mapped configuration registers.
Reserved. Bit 1 defaults to 0b. If this register is programmed via EEPROM or another mechanism,
the value written into this field must be 0b.
), a GRST, or the internally-generated power-on reset.
Classic PCI Configuration Space
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Classic PCI Configuration Space
4.62 Control and Diagnostic Register 1
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−36 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset: C4h
Register type: Read/Write
Default value: 0012 0108h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0
Table 4−36. Control and Diagnostic Register 1 Description
BIT FIELD NAME ACCESS DESCRIPTION
32:21 RSVD R Reserved. Returns 000h when read.
L1 exit latency for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h,
see Section 4.53) is set, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the
link capabilities register (offset 9Ch, see Section 4.52). This field defaults to 100b.
L1 exit latency for common clock. When bit 6 (CCC) of the link control register (offset A0h, see
Section 4.53) is clear, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the link
capabilities register (offset 9Ch, see Section 4.52). This field defaults to 100b.
Reserved. Bits 14:11 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
Secondary bus reset bit mask. When this bit is set, the bridge masks the reset caused by bit 6
(SRST) of the bridge control register (offset 3Eh, see Section 4.29). This bit defaults to 0b.
L1ASPM entry timer. This field specifies the value (in 512-ns ticks) of the L1ASPM entry timer. This
field defaults to 0100b.
L0s entry timer. This field specifies the value (in 62.5-MHz clock ticks) of the L0s entry timer. This
field defaults to 0010b.
Reserved. Bits 1:0 default to 00b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00b.
), a GRST, or the internally-generated power-on reset.
10†
L1_EXIT_LAT_
ASYNC
L1_EXIT_LAT_
COMMON
SBUS_RESET
_MASK
L1ASPM_
TIMER
RW
RW
RW
RW
20:18†
17:15†
14:11† RSVD RW
9:6†
5:2† L0s_TIMER RW
1:0† RSVD RW
†
These bits are reset by a PCI Express reset (PERST
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4.63 Control and Diagnostic Register 2
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−37 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset: C8h
Register type: Read/Write
Default value: 3214 6000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−37. Control and Diagnostic Register 2 Description
BIT FIELD NAME ACCESS DESCRIPTION
31:24†
23:16†
15:13 PHY_REV R PHY revision number
12:8† LINK_NUM RW Link number
7:6 RSVD R Reserved. Returns 00b when read.
5:0 BAROWE RW
4:0† RSVD RW
†
These bits are reset by a PCI Express reset (PERST
N_FTS_
ASYNC_CLK
N_FTS_
COMMON_
CLK
RW
RW
N_FTS for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h, see
Section 4.53) is clear, the value in this field is the number of FTS that are sent on a transition from
L0s to L0. This field shall default to 32h.
N_FTS for common clock. When bit 6 (CCC) of the link control register (offset A0h, see Section
4.53) is set, the value in this field is the number of FTS that are sent on a transition from L0s to L0.
This field defaults to 14h.
BAR 0 Write Enable. When this bit is clear (default), the Base Address at offset 10h is read only
and writes to that register will have no effect. When this bit is set, then bits 31:12 of the Base
Address Register becomes writeable allowing the address of the 4K window to the Memory
Mapped TI Proprietary Registers to be changed.
Reserved. Bits 4:0 default to 00000b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00000b.
), a GRST, or the internally-generated power-on reset.
Classic PCI Configuration Space
4.64 Subsystem Access Register
The contents of this read/write register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 84h and 86h. See Table 4−38 for a complete description of the register contents.
PCI register offset: D0h
Register type: Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−38. Subsystem Access Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:16† SubsystemID RW
15:0† SubsystemVendorID RW
†
These bits are reset by a PCI Express reset (PERST
April 2007 Revised October 2008 SCPS155C
Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI
offset 86h (see Section 4.45).
Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 84h (see Section 4.44).
), a GRST, or the internally-generated power-on reset.
83
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Classic PCI Configuration Space
4.65 General Control Register
This read/write register controls various functions of the bridge. See Table 4−39 for a complete description
of the register contents.
PCI register offset: D4h
Register type: Read-only, Read/Write
Default value: 8206 C000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−39. General Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Configuration retry counter. Configures the amount of time that a configuration request must be retried
on the secondary PCI bus before it may be completed with configuration retry status on the PCI
31:30†
29:28 RSVD R Reserved. Returns 00b when read.
27†
26†
25†
24† FORCE_MRM RW
23†
22:20†
†
These bits are reset by a PCI Express reset (PERST
CFG_RETRY
_CNTR
LOW_POWER
_EN
PCI_PM_
VERSION_
CTRL
STRICT_
PRIORITY_EN
ASPM_CTRL_
DEF_OVRD
POWER_
OVRD
RW
RW
RW
RW
RW
RW
Express side.
00 = 25 µs
01 = 1 ms
10 = 25 ms (default)
11 = 50 ms
Low-power enable. When this bit is set, the half-ampitude, no preemphasis mode for the PCI Express
TX drivers is enabled. The default for this bit is 0b.
PCI power management version control. This bit controls the value reported in bits 2:0 (PM_VERSION)
in the power management capabilities register (offset 52h, see Section 4.32). It also controls the value
of bit 3 (NO_SOFT_RESET) in the power management control/status register (offset 54h, see Section
4.33).
0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power Management 1.1
compliance (default)
1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power Management 1.2
compliance
Strict priority enable. When this bit is set and bits 6:4 (LOW_PRIORITY_COUNT) in the port VC
capability register 1 (offset 154h, see Section 5.17) are 000b, meaning that strict priority VC arbitration
is used, the extended VC always receives priority over VC0 at the PCI Express port.
0 = The default LOW_PRIORITY_COUNT is 001b
1 = The default LOW_PRIORITY_COUNT is 000b (default)
Force memory read multiple
0 = Memory read multiple transactions are disabled (default)
1 = All upstream memory read transactions initiated on the PCI bus are treated as though they
are memory read multiple transactions where prefetching is supported
Active state power management control default override. This bit determines the power-up default for
bits 1:0 (ASLPMC) of the link control register (offset A0h, see Section 4.53) in the PCI Express
capability structure.
0 = Power-on default indicates that active state power management is disabled (00b) (default)
1 = Power-on default indicates that active state power management is enabled for L0s and L1 (11b)
Power override. This bit field determines how the bridge responds when the slot power limit is less
than the amount of power required by the bridge and the devices behind the bridge.
000 = Ignore slot power limit (default)
001 = Assert the PWR_OVRD terminal
010 = Disable secondary clocks selected by the clock mask register
011 = Disable secondary clocks selected by the clock mask register and assert the PWR_OVRD
terminal
100 = Respond with unsupported request to all transactions except for configuration transactions
(type 0 or type 1) and set slot power limit messages
101, 110, 111 = Reserved
), a GRST, or the internally-generated power-on reset.
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Table 4−39. General Control Register Description (Continued)
BIT FIELD NAME ACCESS DESCRIPTION
Classic PCI Configuration Space
READ_
19†
18:16† L0s_LATENCY RW
15:13† L1_LATENCY RW
12† VC_CAP_EN RW
PREFETCH_
DIS
RW
Read prefetch disable. This bit controls the prefetch functionality on PCI memory read transactions.
0 = Prefetch to the next cache line boundary on a burst read (default)
1 = Fetch only a single DWORD on a burst read
L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the L0s
state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 94h, see Section
4.49).
000 = Less than 64 ns
001 = 64 ns up to less than 128 ns
010 = 128 ns up to less than 256 ns
011 = 256 ns up to less than 512 ns
100 = 512 ns up to less than 1 µs
101 = 1 µs up to less than 2 µs
110 = 2 µs to 4 µs (default)
111 = More than 4 µs
L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the L1
state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 94h, see
Section 4.49).
000 = Less than 1 µs
001 = 1 µs up to less than 2 µs
010 = 2 µs up to less than 4 µs
011 = 4 µs up to less than 8 µs
100 = 8 µs up to less than 16 µs
101 = 16 µs up to less than 32 µs
110 = 32 µs to 64 µs (default)
111 = More than 64 µs
VC capability structure enable. This bit enables the VC capability structure by changing the next
offset field of the advanced error reporting capability register at offset 102h.
0 = VC capability structure disabled (offset field = 000h)
1 = VC capability structure enabled (offset field = 150h)
Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are stopped
k
11
k
10
9:8†
7:0†
†
These bits are reset by a PCI Express reset (PERST
BPCC_E RW
BEACON_
ENABLE
MIN_POWER_
SCALE
MIN_POWER_
VALUE
RW
RW
RW
when the bridge is placed in the D3 state. It is assumed that if the secondary bus clocks are required
to be active, that a reference clock continues to be provided on the PCI Express interface.
0 = Secondary bus clocks are not stopped in D3 (default)
1 = Secondary bus clocks are stopped on D3
Beacon enable. This bit controls the mechanism for waking up the physical PCI Express link when in
L2.
0 = WAKE mechanism is used exclusively. Beacon is not used (default).
1 = Beacon and WAKE
Minimum power scale. This value is programmed to indicate the scale of bits 7:0
(MIN_POWER_VALUE).
00 = 1.0x (default)
01 = 0.1x
10 = 0.01x
11 = 0.001x
Minimum power value. This value is programmed to indicate the minimum power requirements. This
value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum power
requirements for the bridge. The default is 00h, because this feature is only usable when the system
implementer adds the PCI devices’ power consumption to the bridge power consumption and
reprograms this field with an EEPROM or the system BIOS.
), a GRST, or the internally-generated power-on reset.
mechanisms are used
k These bits are sticky and must retain their value when the bridge is powered by V
AUX
.
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Classic PCI Configuration Space
4.66 Clock Control Register
This register enables and disables the PCI clock outputs (CLKOUT). See Table 4−40 for a complete
description of the register contents.
PCI register offset: D8h
Register type: Read-only, Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4−40. Clock Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7 RSVD R Reserved. Returns 0b when read.
Clock output 6 disable. This bit disables secondary CLKOUT6.
6† CLOCK6_DISABLE RW
5† CLOCK5_DISABLE RW
4† CLOCK4_DISABLE RW
3† CLOCK3_DISABLE RW
2† CLOCK2_DISABLE RW
1† CLOCK1_DISABLE RW
0† CLOCK0_DISABLE RW
†
These bits are reset by a PCI Express reset (PERST
0 = Clock enabled (default)
1 = Clock disabled
Clock output 5 disable. This bit disables secondary CLKOUT5.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 4 disable. This bit disables secondary CLKOUT4.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 3 disable. This bit disables secondary CLKOUT3.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 2 disable. This bit disables secondary CLKOUT2.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 1 disable. This bit disables secondary CLKOUT1.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 0 disable. This bit disables secondary CLKOUT0.
0 = Clock enabled (default)
1 = Clock disabled
), a GRST, or the internally-generated power-on reset.
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4.67 Clock Mask Register
This register selects which PCI bus clocks are disabled when bits 22:20 (POWER_OVRD) in the general
control register (offset D4h, see Section 4.65) are set to 010h or 011h. This register has no effect on the clock
outputs if the POWER_OVRD bits are not set to 010h or 011h or if the slot power limit is greater than the power
required. See Table 4−41 for a complete description of the register contents.
PCI register offset: D9h
Register type: Read-only, Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4−41. Clock Mask Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7 RSVD R Reserved. Returns 0b when read.
Clock output 6 mask. This bit disables PCI bus CLKOUT6 when the POWER_OVRD bits are set
6† CLOCK6_MASK RW
5† CLOCK5_MASK RW
4† CLOCK4_MASK RW
3† CLOCK3_MASK RW
2† CLOCK2_MASK RW
1† CLOCK1_MASK RW
0† CLOCK0_MASK RW
†
These bits are reset by a PCI Express reset (PERST
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 5 mask. This bit disables PCI bus CLKOUT5 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 4 mask. This bit disables PCI bus CLKOUT4 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 3 mask. This bit disables PCI bus CLKOUT3 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 2 mask. This bit disables PCI bus CLKOUT2 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 1 mask. This bit disables PCI bus CLKOUT1 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
Clock output 0 mask. This bit disables PCI bus CLKOUT0 when the POWER_OVRD bits are set
to 010b or 011b and the slot power limit is exceeded.
0 = Clock enabled (default)
1 = Clock disabled
), a GRST, or the internally-generated power-on reset.
Classic PCI Configuration Space
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Classic PCI Configuration Space
4.68 Clock Run Status Register
The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 4−42
for a complete description of the register contents.
PCI register offset: DAh
Register type: Read-only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4−42. Clock Run Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7:1 RSVD R Reserved. Returns 000 0000b when read.
Secondary clock status. This bit indicates the status of the PCI bus secondary clock outputs.
0† SEC_CLK_STATUS RU
†
This bit is reset by a PCI Express reset (PERST
0 = Secondary clock running
1 = Secondary clock stopped
), a GRST, or the internally-generated power-on reset.
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4.69 Arbiter Control Register
The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier
rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority arbitration
tier. See Table 4−43 for a complete description of the register contents.
PCI register offset: DCh
Register type: Read/Write
Default value: 40h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 1 0 0 0 0 0 0
Table 4−43. Arbiter Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Bus parking mode. This bit determines where the internal arbiter parks the secondary bus.
When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is
7† PARK RW
6† BRIDGE_TIER_SEL RW
5† TIER_SEL5 RW
4† TIER_SEL4 RW
3† TIER_SEL3 RW
2† TIER_SEL2 RW
1† TIER_SEL1 RW
0† TIER_SEL0 RW
†
Thes bits are reset by a PCI Express reset (PERST
cleared, the arbiter parks the bus on the last device mastering the secondary bus.
0 = Park the secondary bus on the last secondary bus master (default)
1 = Park the secondary bus on the bridge
Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration
scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT5 tier select. This bit determines in which tier GNT5 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT4 tier select. This bit determines in which tier GNT4 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT3 tier select. This bit determines in which tier GNT3 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT2 tier select. This bit determines in which tier GNT2 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT1 tier select. This bit determines in which tier GNT1 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
GNT0 tier select. This bit determines in which tier GNT0 is placed in the arbitration scheme.
0 = Lowest priority tier
1 = Highest priority tier (default)
), a GRST, or the internally-generated power-on reset.
Classic PCI Configuration Space
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Classic PCI Configuration Space
4.70 Arbiter Request Mask Register
The arbiter request mask register enables and disables support for requests from specific masters on the
secondary bus. The arbiter request mask register also controls if a request input is automatically masked on
an arbiter time-out. See Table 4−44 for a complete description of the register contents.
PCI register offset: DDh
Register type: Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4−44. Arbiter Request Mask Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Arbiter time-out. This bit enables the arbiter time-out feature. The arbiter time-out is defined as
the number of PCI clocks after the PCI bus has gone idle for a device to assert FRAME
7† ARB_TIMEOUT RW
6† AUTO_MASK RW
5† REQ5_MASK RW
4† REQ4_MASK RW
3† REQ3_MASK RW
2† REQ2_MASK RW
1† REQ1_MASK RW
0† REQ0_MASK RW
†
These bits are reset by a PCI Express reset (PERST
the arbiter assumes the device will not respond.
0 = Arbiter time disabled (default)
1 = Arbiter time-out set to 16 PCI clocks
Automatic request mask. This bit enables automatic request masking when an arbiter time-out
occurs.
0 = Automatic request masking disabled (default)
1 = Automatic request masking enabled
Request 5 (REQ5) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 5.
0 = Use request 5 (default)
1 = Ignore request 5
Request 4 (REQ4) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 4.
0 = Use request 4 (default)
1 = Ignore request 4
Request 3 (REQ3) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 3.
0 = Use request 3 (default)
1 = Ignore request 3
Request 2 (REQ2) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 2.
0 = Use request 2 (default)
1 = Ignore request 2
Request 1 (REQ1) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 1.
0 = Use request 1 (default)
1 = Ignore request 1
Request 0 (REQ0) mask. Setting this bit forces the internal arbiter to ignore requests signal on
request input 0.
0 = Use request 0 (default)
1 = Ignore request 0
), a GRST, or the internally-generated power-on reset.
before
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4.71 Arbiter Time-Out Status Register
The arbiter time-out status register contains the status of each request (request 5–0) time-out. The time-out
status bit for the respective request is set if the device did not assert FRAME
See Table 4−45 for a complete description of the register contents.
PCI register offset: DEh
Register type: Read/Clear
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4−45. Arbiter Time-Out Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7:6 RSVD R Reserved. Returns 00b when read.
Request 5 time-out status
5 REQ5_TO RCU
4 REQ4_TO RCU
3 REQ3_TO RCU
2 REQ2_TO RCU
1 REQ1_TO RCU
0 REQ0_TO RCU
0 = No time-out
1 = Time-out has occurred
Request 4 time-out status
0 = No time-out
1 = Time-out has occurred
Request 3 time-out status
0 = No time-out
1 = Time-out has occurred
Request 2 time-out status
0 = No time-out
1 = Time-out has occurred
Request 1 time-out status
0 = No time-out
1 = Time-out has occurred
Request 0 time-out status
0 = No time-out
1 = Time-out has occurred
Classic PCI Configuration Space
after the arbiter time-out value.
NOTE:If bit 6 (AUTO_MASK) in the arbiter request mask register (offset DDh, see
Section 4.70) is asserted and a PCI bus request time-out is detected, then the request time-out
status bits require a special reset sequence. First, the AUTO_MASK bit must be cleared to
0b. Then, the REQ[5:0]_TO bit will clear after a write-back of 1b.
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