TEXAS INSTRUMENTS VSP2232 Technical data

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VSP2232

SLAS320 – MAY 2001

CCD SIGNAL PROCESSOR

FOR DIGITAL CAMERAS

FEATURES

CCD Signal Processing

D

– Correlated Double Sampling (CDS)
– Programmable Black Level Clamping

D Programmable Gain Amplifier (PGA)

– –6-dB to 42-dB Gain Ranging

D 10-Bit Digital Data Output

– Up to 36-MHz Conversion Rate
– No Missing Codes

D 76-dB Signal-to-Noise Ratio
D Portable Operation

– Low Voltage: 2.7 V to 3.6 V
– Low Power: 130 mW (typ) at 3.0 V
– Standby Mode: 6 mW

VSP2232 block diagram

CLPDM SHP SHD SLOAD SCLK SDATA RESET ADCCK DRV

DESCRIPTION

The VSP2232 is a complete mixed-signal processing IC
for digital cameras that provides signal conditioning and
analog-to-digital conversion for the output of a CCD
array. The primary CCD channel provides correlated
double sampling (CDS) to extract the video information
from the pixels, a –6-dB to 42-dB gain with digital control
for varying illumination conditions, and black level
clamping for an accurate black level reference.

Input signal clamping and offset correction of the input
CDS is also performed. The stable gain control is linear
in dB. Additionally, the black level is quickly recovered
after gain change.

The VSP2232Y is pin-to-pin compatible with the
VSP2262Y (12-bit 20 MHz) one-chip product.

The VSP2232Y is available in a 48-pin LQFP package
and operates from a single 3-V/3.3-V supply.

DDVCC

Input

Clamp

Correlated

Double

Sampling (CDS)

CCD

Output

Signal

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Preblanking

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Optical Black (OB)

Level Clamping

Serial Interface

Programmable
Gain Amplifier

(PGA)

–6 to 42 dB

Reference Voltage Generator

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Analog-to-Digital

Timing Control

Output

Converter

Copyright  2001, Texas Instruments Incorporated

Latch

12-Bit

Digital

Output

B(0–11)

GNDADRVGNDREFPCMREFNBYPMBYPBYPP2CPLOBCOBPBLK

1

VSP2232

SLAS320 – MAY 2001

PACKAGE/ORDERING INFORMATION

PRODUCT

VSP2232Y 48-pin LQFP ZZ340 0_C to 85_C VSP2232Y VSP2232Y 250 pcs. Tray
VSP2232Y 48-pin LQFP ZZ340 0_C to 85_C VSP2232Y VSP2232Y/2K Tape and Reel

†

This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., VSP2232CDR.

PACKAGE

PACKAGE OUTLINE

NUMBER

DEMO BOARD ORDERING INFORMATION

PRODUCT

VSP2232Y DEM-VSP2232Y

pin assignments

48-PIN LQFP PACKAGE

SPECIFIED

TEMPERATURE RANGE

ORDERING NUMBER

(TOP VIEW)

PACKAGE
MARKING

ORDERING

NUMBER

†

TRANSPORT

MEDIA

CC

GNDA

GNDA

35 34 33 32 3136 30

CM

37

REFP
REFN

GNDA
GNDA

RESET
SLOAD

SDATA

SCLK

V

CC

NC
NC

38
39
40
41
42
43
44
45
46
47
48

1

23

B1

B2

B0(LSB)

NC – No internal connection

VCCV

BYPM

BYP

5678

4

B4B5B6B7B8

B3

BYPP2

CCDIN

28 27 2629

9

CC

COBVGNDA

10 11 12

B9

GNDA

25

24
23
22
21
20
19
18
17
16
15
14
13

B10

B11(MSB)

V

CC

CLPDM
SHD
SHP
CLPOB
PBLK
V

CC

GNDA
ADCCK
GNDA
DRVGND
DRV

DD

2

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†

VSP2232

SLAS320 – MAY 2001

Terminal Functions

TERMINAL

NAME NO.

ADCCK 16 DI Master clock, See Note 1
B0(LSB) 1 DO A/D converter output, Bit 0 (LSB)
B1 2 DO A/D converter output, Bit 1
B2 3 DO A/D converter output, Bit 2
B3 4 DO A/D converter output, Bit 3
B4 5 DO A/D converter output, Bit 4
B5 6 DO A/D converter output, Bit 5
B6 7 DO A/D converter output, Bit 6
B7 8 DO A/D converter output, Bit 7
B8 9 DO A/D converter output, Bit 8
B9 10 DO A/D converter output, Bit 9
B10 11 DO A/D converter output, Bit 10
B11(MSB) 12 DO A/D converter output, Bit 11 (MSB)
BYP 31 AO Internal reference C (bypass to ground), See Note 2
BYPM 32 AO Internal reference N (bypass to ground), See Note 3
BYPP2 29 AO Internal reference P (bypass to ground), See Note 3
CCDIN 30 AI CCD signal input
CLPDM 23 DI Dummy pixel clamp pulse (Default = Active low), See Note 4
CLPOB 20 DI Optical black clamp pulse (Default = Active low), See Note 4
CM 37 AO A/D converter common mode voltage (bypass to ground), See Note 2
COB 28 AO Optical black clamp loop reference (bypass to ground), See Note 5
DRV

DD

DRVGND 14 P Digital ground. Exclusively for digital output
GNDA 15, 17, 25, 26, 35, 36,

NC 43, 44 Should be left open
PBLK 19 DI Preblanking

REFN 39 AO A/D converter negative reference (bypass to ground), See Note 2
REFP 38 AO A/D converter positive reference (bypass to ground), See Note 2
RESET 45 DI Asynchronous system reset (active low)
SCLK 48 DI Clock for serial data shift (triggered at the rising edge)
SDATA 47 DI Serial data input
SHP 21 DI CDS reference level sampling pulse (Default = Active low), See Note 4
SHD 22 DI CDS Data level sampling pulse (Default = Active low), See Note 4

†

Designators in TYPE Column: P–power supply and ground, DI–digital input, DO–digital output, AI–analog input, AO–analog output

NOTES: 1. There are two options to drive the A/D converter:

a). External drive mode: The master clock (ADCCK) drives A/D converter directly.
b). Internal drive mode: The clock internally generated by on-chip timing control circuit using SHP and SHD signals drives A/D
converter.

2. BYP, CM, REFN, and REFP should be connected to ground using a bypass capacitor (0.1 µF). Refer to voltage reference for details.

3. BYPM, BYPP2 should be connected to ground using a bypass capacitor with a recommend value of 200 pF to 600 pF. However,
this depends on the application environment. Refer to voltage reference for details.

4. Refer to serial interface for details.

5. COB should be connected to ground using a bypass capacitor with a recommend value of 0.1 µF to 0.22 µF. However , this depends
on the application environment. Refer to optical black level clamp loop for details.

13 P Power supply. Exclusively for digital output

41, 42

TYPE

P Analog ground

High = Normal operation mode
Low = Preblanking mode: Digital output all zero

DESCRIPTION

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VSP2232

†

SLAS320 – MAY 2001

Terminal Functions (continued)

TERMINAL

NAME NO.

SLOAD 46 DI Serial data latch signal (triggered at the rising edge)
V

CC

†

Designators in TYPE column: P–power supply and ground, DI–digital input, DO–digital output, AI–aAnalog input, AO–analog output

18, 24, 27, 33, 34, 40 P Analog power supply

TYPE

DESCRIPTION

detailed description

introduction

The VSP2232 is a complete mixed-signal IC that contains all of the key features associated with the processing
of the CCD imager output signal in a video camera, a digital still camera, a security camera, or similar
applications. A simplified block diagram is shown on the front page of this data sheet. The VSP2232 includes
a correlated double sampler (CDS), a programmable gain amplifier (PGA), an analog-to-digital converter
(ADC), an input clamp, an optical black (OB) level clamp loop, a serial interface, a timing control, and a reference
voltage generator. W e recommend an off-chip emitter follower buffer between the CCD output and the VSP2232
CCDIN input. The PGA gain control, the clock polarity setting, and the operation mode choosing can be made
through the serial interface. All parameters are reset to the default value when the RESET pin goes to low
asynchronously from the clocks.

correlated double sampler (CDS)

The output signal of a CCD imager is sampled twice during one pixel period, one at the reference interval and
the other at the data interval.

Subtracting these two samples, extracts the video information of the pixel as well as removes any noise that
is common—or correlated—to both the intervals.

Thus, a CDS is very important to reduce the reset noise and the low frequency noises that are present on the
CCD output signal. Figure 1 shows the simplified block diagram of the CDS and input clamp.

VSP2232

SHP

C

= 5 pF

(1)

= 5 pF

+

OPA

_

CCD

Output

C

IN

CLPDM

SHP

CCDIN

SHD

REFN (1.25 V)

C

(2)

Figure 1. Simplified Block Diagram of CDS and Input Clamp

The CDS is driven through an off-chip coupling capacitor (C

). AC coupling is strongly recommended because

IN

the DC level of the CCD output signal is usually too high (several volts) for the CDS to work properly . A 0.1-µF
capacitor is recommended for C

, however, it depends on the application environment.

IN

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SLAS320 – MAY 2001

correlated double sampler (CDS) (continued)

Also, an off-chip emitter follower buffer is recommended that can drive more than 10 pF, because the 5 pF of
the sampling capacitor and a few pF of stray capacitance can be seen at the input pin. The analog input signal
range at the CCDIN pin is 1 V

1.5 V.
The reference level is sampled during SHP active period, and the voltage level is held on the sampling capacitor

C

at the trailing edge of SHP. The data level is sampled during SHD active period, and the voltage level is

(1)

held on the sampling capacitor C
the subtraction of these two levels.

The active polarity of SHP/SHD (active high or active low) can be chosen through the serial interface, refer to
serial interface for details. The default value of SHP/SHD is active low . However , right after power on, this value
is unknown. For this reason, it must be set to the appropriate value by using the serial interface, or reset to the
default value by the RESET pin. The description and the timing diagrams in this data sheet are all based on the
polarity of active low (default value).

input clamp and dummy pixel clamp

The buffered CCD output is capacitively coupled to the VSP2232. The purpose of the input clamp is to restore
the dc component of the input signal that was lost with the ac-coupling and establish the desired dc bias point
for the CDS. Figure 1 shows the simplified block diagram of the input clamp. The input level is clamped to the
internal reference voltage REFN (1.25 V) during the dummy pixel interval. More specifically , when both CLPDM
and SHP are active, then the dummy clamp function becomes active. If the dummy pixels and/or the CLPDM
pulse are not available in your system, the CLPOB pulse can be used in place of CLPDM as long as the clamping
takes place during black pixels. In this case, both CPLDM pin (actives as same timing as CLPOB) and SHP
become active during the optical black pixel interval, then the dummy clamp function becomes active.

, and the appropriate common mode voltage for the CDS is around 0.5 V to

P–P

at the trailing edge of SHD. Then, the switched-capacitor amplifier performs

(2)

VSP2232

The active polarity of CLPDM and SHP (active high or active low) can be chosen through the serial interface,
refer to serial interface for details. The default value of CLPDM and SHP is active low. However , right after power
on, this value is unknown. For this reason, it must be set to the appropriate value by using the serial interface,
or reset to the default value by the RESET pin. The description and timing diagrams in this data sheet are all
based on the polarity of active low (default value).

high performance analog-to-digital converter (ADC)

The analog-to-digital converter (ADC) utilizes a fully differential and pipelined architecture. This ADC is well
suited for low voltage operation, low power consumption requirement, and high-speed applications. It assures
10-bit resolution of the output data with no missing code. The VSP2232 includes the reference voltage generator
for the ADC. REFP (positive reference, pin 38), REFN (negative reference, pin 39), and CM (common-mode
voltage, pin 37) should be bypassed to the ground with a 0.1-µF ceramic capacitor. Do not use this voltage
anywhere else in the system because it affects the stability of these reference levels, and then causes ADC
performance degradation. These are analog output pins, so do not apply voltage from the outside.

programmable gain amplifier (PGA)

Figure 2 shows the characteristics of the PGA gain. The PGA provides a gain range of –6 dB to 42 dB, which
is linear in dB. The gain is controlled by a digital code with 10-bit resolution, and it can be settle through the serial
interface, refer to the serial interface section for details. The default value of the gain control code is 128 (PGA
gain = 0 dB). However, right after power on, this value is unknown. For this reason, it must be set to the
appropriate value by using the serial interface, or reset to the default value by the RESET pin.

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VSP2232

SLAS320 – MAY 2001

programmable gain amplifier (PGA) (continued)

50

40

30

20

Gain – dB

10

0

–10

100 200 300 400 500 600 700 800 900 1000

0

Input Code for Gain Control (0 to 1023)

Figure 2. Characteristics of PGA Gain

optical black (OB) level clamp loop

T o extract the video information correctly , the CCD signal must be referenced to a well-established optical black
(OB) level. The VSP2232 has an autocalibration loop to establish the OB level using the optical black pixel
output from the CCD imager. The input signal level of the OB pixels is identified as the real OB level and the
loop should be closed during this period while CLPOB is active. During the effective pixel interval, the reference
level of the CCD output signal is clamped to the OB level by the OB level clamp loop. T o determine the loop-time
constant, an off-chip capacitor is required, and should be connected to the COB (pin 28). The time constant T
is given in equation 1.

T +

ǒ

16384 I

C

(min)

Ǔ

Where:

C is the capacitor value connected to COB, I

is the minimum current (0.15 µA) of the control DAC in the

(min)

OB level clamp loop, and 0.15 µA is equivalent to 1 LSB of the DAC output current. When C is 0.1 µF , then the
time constant T is 40.7 µs. Also, the slew rate (SR) is given in equation 2.

I

SR +

(max)

C

(1)

(2)

Where:

C is the capacitor value connected to COB. I

is the maximum current (153 µA) of the control DAC in the

(max)

OB level clamp loop, and 153 µA is equivalent to 1023 LSB of the DAC output current.

Generally , the OB level clamping at high-speed causes clamp noise (or white streak noise). However, the noise
will decrease by increasing the capacitor size. On the other hand, a larger capacitor requires a much longer time
to restore from the standby mode, or right after the power goes on. Therefore, we recommend a 0.1-µF to

0.22-µF capcitor. However, it depends on the application environment, and making careful adjustments using
the cut-and-try method is recommended.

6

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