TEXAS INSTRUMENTS ULN2003AI Technical data

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D, N, OR PW PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1B
2B
3B
4B
5B
6B
7B

E

1C
2C
3C
4C
5C
6C
7C
COM

FEATURES

• 500-mA-Rated Collector Current (Single

Output)

• High-Voltage Outputs . . . 50 V

• Output Clamp Diodes

• Inputs Compatible With Various Types of

Logic

• Relay-Driver Applications

DESCRIPTION/ORDERING INFORMATION

The ULN2003AI is a high-voltage, high-current
Darlington transistor array. This device consists of
seven npn Darlington pairs that feature high-voltage
outputs with common-cathode clamp diodes for
switching inductive loads. The collector-current rating
of a single Darlington pair is 500 mA. The Darlington
pairs can be paralleled for higher current capability.
Applications include relay drivers, hammer drivers,
lamp drivers, display drivers (LED and gas
discharge), line drivers, and logic buffers.

ULN2003AI

HIGH-VOLTAGE, HIGH-CURRENT

DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

The ULN2003AI has a 2.7-k Ω series base resistor for each Darlington pair for operation directly with TTL or 5-V
CMOS devices.

ORDERING INFORMATION

T

A

PDIP (N) Tube of 425 ULN2003AIN ULN2003AIN

–40 ° C to 105 ° C SOIC (D) ULN2003AI

TSSOP (PW) Reel of 2000 ULN2003AIPWR UN2003AI

PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING

Tube of 40 ULN2003AID
Reel of 2500 ULN2003AIDR

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2003–2005, Texas Instruments Incorporated

www.ti.com

7C

6C

5C

4C

3C

2C

1C

COM

7

6

5

4

3

2

1

7B

6B

5B

4B

3B

2B

1B

10

11

12

13

14

15

16

9

Output
C

COM

E

7.2 kΩ

3 kΩ

2.7 kΩ

Input

B

All resistor values shown are nominal.

ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

LOGIC DIAGRAM

SCHEMATICS (EACH DARLINGTON PAIR)

2

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HIGH-VOLTAGE, HIGH-CURRENT

DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

Absolute Maximum Ratings

at 25 ° C free-air temperature (unless otherwise noted)

V

V

I

T

θ

T
T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

(2) All voltage values are with respect to the emitter/substrate terminal E, unless otherwise noted.
(3) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient

(4) The package thermal impedance is calculated in accordance with JESD 51-7.

Collector-emitter voltage 50 V

CC

Clamp diode reverse voltage
Input voltage

I

Peak collector current
Output clamp current 500 mA

OK

(2)

(3) (4)

Total emitter-terminal current –2.5 A
Operating free-air temperature range –40 105 ° C

A

Package thermal impedance

JA

Operating virtual junction temperature 150 ° C

J

Storage temperature range –65 150 ° C

stg

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

temperature is PD= (TJ(max) – TA)/ θJA. Operating at the absolute maximum TJof 150 ° C can affect reliability.

(1)

MIN MAX UNIT

(2)

D package 73

(3) (4)

N package 67 ° C/W
PW package 108

ULN2003AI

50 V
30 V

500 mA

Electrical Characteristics

TA= 25 ° C

V

I(on)

V

CE(sat)

I

CEX

V

F

I

I(off)

I

I

I

R

C

i

PARAMETER TEST FIGURE TEST CONDITIONS MIN TYP MAX UNIT

IC= 200 mA 2.4

On-state input voltage 5 V

= 2 V IC= 250 mA 2.7 V

CE

IC= 300 mA 3

II= 250 µ A, IC= 100 mA 0.9 1.1

Collector-emitter saturation voltage 4 II= 350 µ A, IC= 200 mA 1 1.3 V

II= 500 µ A, IC= 350 mA 1.2 1.6

Collector cutoff current 1 V

= 50 V, II= 0 50 µ A

CE

Clamp forward voltage 7 IF= 350 mA 1.7 2 V
Off-state input current 2 V

= 50 V, IC= 500 µ A 50 65 µ A

CE

Input current 3 VI= 3.85 V 0.93 1.35 mA
Clamp reverse current 6 VR= 50 V 50 µ A
Input capacitance VI= 0, f = 1 MHz 15 25 pF

3

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ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

Electrical Characteristics

TA= –40 ° C to 105 ° C

PARAMETER TEST FIGURE TEST CONDITIONS MIN TYP MAX UNIT

V

I(on)

V

CE(sat)

I

CEX

V

F

I

I(off)

I

I

I

R

C

i

Switching Characteristics

TA= 25 ° C

t

PLH

t

PHL

V

OH

On-state input voltage 5 V

Collector-emitter saturation voltage 4 II= 350 µ A, IC= 200 mA 1 1.4 V

Collector cutoff current 1 V
Clamp forward voltage 7 IF= 350 mA 1.7 2.2 V
Off-state input current 2 V
Input current 3 VI= 3.85 V 0.93 1.35 mA
Clamp reverse current 6 VR= 50 V 100 µ A
Input capacitance VI= 0, f = 1 MHz 15 25 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Propagation delay time, low- to high-level output See Figure 8 0.25 1 µ s
Propagation delay time, high- to low-level output See Figure 8 0.25 1 µ s
High-level output voltage after switching VS= 50 V, IO≈ 300 mA, See Figure 9 VS– 20 mV

IC= 200 mA 2.7

= 2 V IC= 250 mA 2.9 V

CE

IC= 300 mA 3

II= 250 µ A, IC= 100 mA 0.9 1.2

II= 500 µ A, IC= 350 mA 1.2 1.7

= 50 V, II= 0 100 µ A

CE

= 50 V, IC= 500 µ A 30 65 µ A

CE

Switching Characteristics

TA= –40 ° C to 105 ° C

t
t
V

Propagation delay time, low- to high-level output See Figure 8 1 10 µ s

PLH

Propagation delay time, high- to low-level output See Figure 8 1 10 µ s

PHL

High-level output voltage after switching VS= 50 V, IO≈ 300 mA, See Figure 9 VS– 50 mV

OH

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

4

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PARAMETER MEASUREMENT INFORMATION

Open

V

CE

Open

I

CEX

Figure 1. I

CEX

Test Circuit

Open

V

CE

I

C

I

I(off)

Figure 2. I

I(off)

Test Circuit

Open

Open

I

I(on)

V

I

Figure 3. I

I

Test Circuit

Open

V

CE

I

C

I

I

hFE =

I

C

I

I

NOTE: II is fixed for measuring V

CE(sat)

, variable for

measuring hFE.

Figure 4. hFE, V

CE(sat)

Test Circuit

Open

V

CE

I

C

V

I(on)

Figure 5. V

I(on)

Test Circuit

V

R

Open

I

R

Figure 6. I

R

Test Circuit

I

F

V

F

Open

Figure 7. VF Test Circuit

ULN2003AI

HIGH-VOLTAGE, HIGH-CURRENT

DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

5

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50% 50%

50% 50%

t

PHL

VOLTAGE WA VEFORMS

Input

t

PLH

Figure 8. Propagation Delay-Time Waveforms

Output

Input

Open

V

S

200 Ω

Output

CL = 15 pF
(see Note B)

90% 90%

1.5 V 1.5 V

10% 10%

40 µs

≤10 ns≤5 ns

V

IH

(see Note C)

0 V

V

OH

V

OL

Input

Output

TEST CIRCUIT

VOLTAGE WA VEFORMS

1N3064

2 mH

Pulse

Generator

(see Note A)

NOTES: A. The pulse generator has the following characteristics: PRR = 12.5 kHz, ZO = 50 Ω.

B. CL includes probe and jig capacitance.
C. For testing, VIH = 3 V

Figure 9. Latch-Up Test Circuit and Voltage Waveforms

ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

PARAMETER MEASUREMENT INFORMATION

6

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Figure 10

COLLECTOR-EMITTER

SATURATION VOLTAGE

vs

COLLECTOR CURRENT

(ONE DARLINGTON)

0

IC − Collector Current − mA

2.5

800

0

100 200 300 400 500 600 700

0.5

1

1.5

2

II = 350 µA
II = 500 µA

VCE(sat) − Collector-Emitter Saturation Voltage − V

V

CE(sat)

TA = 25°C

II = 250 µA

2

1.5

1

0.5

700600500400300200100

0

800

2.5

I

C(tot)

− Total Collector Current − mA

0

COLLECTOR-EMITTER

SATURATION VOLTAGE

vs

TOTAL COLLECTOR CURRENT

(TWO DARLINGTONS IN PARALLEL)

VCE(sat) − Collector-Emitter Saturation Voltage − VV

CE(sat)

II = 250 µA

II = 350 µA

II = 500 µA

T

A

= 25°C

COLLECTOR CURRENT

vs

INPUT CURRENT

0

I

I

− Input Current − µA

500

200

0

25 50 75 100 125 150 175

50

100

150

200

250

300

350

400

450

VS = 10 V

VS = 8 V

IC − Collector Current − mA

C

I

RL = 10 Ω
T

A

= 25°C

Figure 12

Figure 11

ULN2003AI

HIGH-VOLTAGE, HIGH-CURRENT

DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

TYPICAL CHARACTERISTICS

7

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Figure 13

0

Duty Cycle − %

600

100

0

10 20 30 40 50 60 70 80 90

100

200

300

400

500

TA = 70°C
N = Number of Outputs

Conducting Simultaneously

N = 7
N = 6

D PACKAGE

MAXIMUM COLLECTOR CURRENT

vs

DUTY CYCLE

N = 5

N = 3

N = 2

N = 1

IC − Maximum Collector Current − mA

C

I

N = 4

Figure 14

Conducting Simultaneously

N = Number of Outputs

500

400

300

200

100

908070605040302010

0

100

600

Duty Cycle − %

0

N = 5

TA = 85°C

N PACKAGE

MAXIMUM COLLECTOR CURRENT

vs

DUTY CYCLE

N = 7

N = 3

N = 2

N = 6

N = 1

IC − Maximum Collector Current − mA

C

I

N = 4

ULN2003AI
HIGH-VOLTAGE, HIGH-CURRENT
DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

THERMAL INFORMATION

8

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Lamp
Test

TTL

Output

V

CC

V

1

2

3

4

5

6

9

10

11

12

13

14

15

16

8

7

Figure 15. TTL to Load

V

CC

V

R

P

1

2

3

4

5

6

9

10

11

12

13

14

15

16

8

TTL

Output

7

Figure 16. Use of Pullup Resistors

to Increase Drive Current

ULN2003AI

HIGH-VOLTAGE, HIGH-CURRENT

DARLINGTON TRANSISTOR ARRAY

SLRS054B – JULY 2003 – REVISED FEBRUARY 2005

APPLICATION INFORMATION

9

PACKAGE OPTION ADDENDUM

www.ti.com

28-Feb-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

ULN2003AID ACTIVE SOIC D 16 40 Pb-Free

ULN2003AIDR ACTIVE SOIC D 16 2500 Pb-Free

ULN2003AIN ACTIVE PDIP N 16 25 Pb-Free

ULN2003AIPW ACTIVE TSSOP PW 16 90 Pb-Free

ULN2003AIPWR ACTIVE TSSOP PW 16 2000 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15

0,05

8

1

A

DIM

6,60
6,20

14

0,10

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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