TEXAS INSTRUMENTS UCD9240 Technical data

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

Digital PWM System Controller

1

FEATURES

2

• Fully Configurable Multi-Output and

Multi-Phase Non-Isolated DC/DC PWM Controller

• Controls Up To Four Voltage Rails and Up To

Eight Phases

• Supports Switching Frequencies Up to 2MHz

With 250 ps Duty-Cycle Resolution

• Up To 1mV Closed Loop Resolution

• Hardware-Accelerated, 3-Pole/3-Zero

Compensator With Non-Linear Gain for Improved Transient Performance

• Supports Multiple Soft-Start and Soft-Stop

Configurations Including Prebias Start-up

• Supports Voltage Tracking, Margining and

Sequencing

• Supports Current and Temperature Balancing

for Multi-Phase Power Stages

• Supports Phase Adding/Shedding for

Multi-Phase Power Stages

• Sync In /Out Pins Align DPWM Clocks

Between Multiple UCD9240 Devices

• Fan Monitoring and Control

• 12-Bit Digital Monitoring of Power Supply

Parameters Including: – Input Current and Voltage – Output Current and Voltage – Temperature at Each Power Stage

• Multiple Levels of Overcurrent Fault

Protection: – External Current Fault Inputs – Analog Comparators Monitor Current

Sense Voltage

– Current Continually Digitally Monitored

• Over and Undervoltage Fault Protection

• Overtemperature Fault Protection

• Enhanced Nonvolatile Memory With Error

Correction Code (ECC)

• Device Operates From a Single Supply With an

Internal Regulator Controller That Allows Operation Over a Wide Supply Voltage Range

• Supported by Fusion Digital Power™

Designer, a Full Featured PC Based Design Tool to Simulate, Configure, and Monitor Power Supply Performance.

APPLICATIONS

• Industrial/ATE

• Networking Equipment

• Telecommunications Equipment

• Servers

• Storage Systems

• FPGA, DSP and Memory Power

DESCRIPTION

The UCD9240 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop management with flash memory and a serial interface to support configurability, monitoring and management.

The UCD9240 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.

To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.

TI has also developed multiple complementary power stage solutions – from discrete drives in the UCD7k family to fully tested power train modules in the PTD family. These solutions have been developed to complement the UCD9k family of system power controllers.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

OPERATING

TEMPERATURE PIN COUNT SUPPLY PACKAGE

RANGE, T

-40 ° C to 110 ° C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ORDERABLE PART TOP SIDE

A

NUMBER MARKING

UCD9240PFCR 80-pin Reel of 1000 QFP UCD9240

UCD9240PFC 80-pin Tray of 119 QFP UCD9240

(1)

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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS

Voltage applied at V33D to DV Voltage applied at V33A to AV Voltage applied to any pin Storage temperature (T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS.

(2)

) – 40 to 150 ° C

STG

(1)

VALUE UNIT

SS

– 0.3 to 3.6 V – 0.3 to 3.6 V – 0.3 to 3.6 V

RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range (unless otherwise noted).

MIN NOM MAX UNIT

V Supply voltage during operation, V33D, V33DIO, V33A 3 3.3 3.6 V T

A

T

J

Operating free-air temperature range – 40 110 ° C Junction temperature 125 ° C

Product Folder Link(s): UCD9240

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

ELECTRICAL CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

SUPPLY CURRENT

I

V33A

I

V33DIO

I

V33D

I

V33D

Supply current mA

INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS

V

V33

3.3-V linear regulator Emitter of NPN transistor 3.25 3.3 3.35 V33FB 3.3-V linear regulator feedback 4 4.6 I

V33FB

Series pass base drive V

Beta Series NPN pass device 40

EXTERNALLY SUPPLIED 3.3 V POWER

V

,

V33D

V

V33DION

V

V33A

Digital 3.3-V power T Analog 3.3-V power T

ERROR AMPLIFIER INPUTS EAPn, EANn

V

CM

V

ERROR

Common mode voltage each pin -0.15 1.6 V

Internal error Voltage range AFE_GAIN field of CLA_GAINS = 0 EAP-EAN Error voltage digital resolution AFE_GAIN field of CLA_Gains = 3 1 mV R

EA

I

OFFSET

Input Impedance Ground reference 0.5 1.5 3 M Ω

Input offset current 1 k Ω source impedence -5 5 µ A

ANALOG INPUTS CS, Vin, TEMP, PMBusADDR

I

BIAS

V

ADDR_OPEN

V

ADDR_SHORT

V

ADC_RANGE

V

OC_THRS

V

OC_RES

Bias current for PMBus Addr pins 9 11 µ A

Voltage indicating open pin AddrSens 0,1 open 2.47 V

Voltage indicating shorted pin AddrSense 0,1 short to ground 0.179 V

Measurment range for voltage

monitoring

Overcurrent comparator threshold

voltage range

Overcurrent comparator threshold

voltage range ADCREF External Reference input (80-pin package) 1.8 V33A V Temp

internal

Int. temperature sense accuracy Over range from 0 ° C to 100 ° C -5 5 ° C INL ADC integral nonlinearity -2.5 2.5 mV I

lkg

R

IN

C

IN

Input leakage current 3V applied to pin 100 nA

Input impedance Ground reference 8 M Ω

Current Sense Input capacitance 10 pF

(1) See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command.

V

= 3.3 V 8 15

V33A

V

= 3.3 V 2 10

V33DIO

V

= 3.3 V 40 45

V33D

V

= 3.3 V storing configuration

V33D

parameters in flash memory TBD

= 12 V 10 mA

VIN

A = 25 ° C

Inputs: VIn, V

(1)

, V

track

temp

3.13 3.47 V

-256 256 mV

50 55

CS-1A, CS-1B, CS-2A, CS-2B 0 2.5 V CS-3A, CS-3B, CS-4A, CS-4B

Inputs: CS-1A, CS-2A, CS-3A, CS-4A 0.032 2 V

Inputs: CS-1A, CS-2A, CS-3A, CS-4A 31.25 mV

V

Product Folder Link(s): UCD9240

UCD9240

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ELECTRICAL CHARACTERISTICS (continued)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

DIGITAL INPUTS/OUTPUTS

V

OL

V

OH

V

IH

V

IL

Low-level output voltage IOH= 6 mA

High-level output voltage IOH= -6 mA

High-level input voltage V

Low-level input voltage V

V33DIO V33DIO

(2)

, V

(3)

, V

= 3 V V

V33DIO

V

= 3 V V

V33DIO

33DIO

-0.6V = 3V 2.1 V = 3.5 V 1.1 V

FAN CONTROL INPUTS/OUTPUTS

T

PWM_PERIOD

DUTY

PWM

DUTY

RES

Tach

RANGE

Tach

RES

t

MIN

FAN-PWM period 156 kHz FAN-PWM duty cycle range 0% 100% Duty cycle resolution 1%

FAN-TACH range 30 300k RPM

For 1 Tach pulse per revolution. At 2,

3, or 4 pulse/rev, divide by that value FAN-TACH resolution For 1 Tach pulse per revolution 30 RPM FAN-TACH minimum pulse width Either positive or negative polarity 150 µ s

SYSTEM PERFORMANCE

V

commanded to be 1V, at 25 ° C

V

Ref

Setpoint Reference Accuracy -10 10 mV

Setpoint Reference Accuracy over temeprature

V

DiffOffset

t

Delay

F

SW

Differential offset between gain setetings

Digital Compensator Delay

(5)

Switching Frequency 15.260 2000 kHz

ref

AFEgain = 4, 1V input to EAP/N

measured at output of the EADC

(4)

-40 ° C to 125 ° C -20 20 mV

AFEgain = 4 compared to

AFEgain = 1, 2, or 8

-4 4 mV

(6)

208

Duty Max and Min Duty Cycle Configured via PMBus 0% 100% VDDSlew Minimum V t

retention

Write_Cycles TJ= 25 ° C 20 K cycles

Retention of configuration parameters TJ= 25 ° C 100 Years Number of nonvolatile erase/write

cycles

slew rate V

DD

slew rate between 2.3V and 2.9V 0.25 V/ms

DD

(2) The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop

specified.

(3) The maximum total current current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum

voltage drop specified. (4) With default device caliibration. PMBus calibration can be used to improve the regulation tolerance. (5) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay must be

accounted for when calculating the system dynamic response. (6) The PMBus command: EADC_SAMPLE_TRIGGER defines the start of the 32ns ADC sample window. So the minimum

EAD_SAMPLE_TRIGGER time is 208 + 32 = 240 ns.

Dgnd

+0.25

ns

Product Folder Link(s): UCD9240

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

ADC MONITORING INTERVALS AND RESPONSE TIMES

The ADC operates in a continuous conversion sequence that measures each rail ' s output voltage, each power stage ' s ouput current, plus four other variables (external temperature, Internal temperature, input voltage and current, and tracking input voltage). The length of the sequence is determined by the number of output rails (NumRails) and total output power stages (NumPhases) configured for use. The time to complete the monitoring sampling sequence is give by the formula:

t

ADC_SEQ

t

ADC

t

ADC_Seq

The most recent ADC conversion results are periodically converted into the proper measurement units (volts, amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The monitoring operates asynchronously to the ADC, at intervals shown in the table below.

t

Vout

t

Iout

t

Vin

t

Iin

t

TEMP

t

Ibal

t

FanTach

Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC sequence interval. Once a fault condition is detected, some additional time is required to determine the correct action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following table lists the worse-case fault response times.

t

, t

OVF

UVF

t

, t

OVF

UVF

t

, t

OVF

UVF

t

, t

OCF

UCF

t

, t

OCF

UCF

t

, t

OCF

UCF

t

OTF

(1) During a STORE_DEFAULT_ALL command, which stores the entire configuration to nonvolatile memory, the fault detection latency can

be up to 10 ms. (2) Because the current measurement is averaged with a smoothing filter, the response time to an Overcurrent condition depends on a

combination of the time constant ( τ ) from Table 4 , the recent measurement history, and how much the measured value exceeds the

overcurrent limit.

= t

× (NumRAILS + NumPHASE + 4)

ADC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC single-sample time 3.89 µ s

Min = 1 Rail + 1 Phase = 4 = 6

ADC sequencer interval 27.75 74 µ s

samples Max = 4 Rails + 8 Phases + 4 = 16

samples

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage monitoring interval 200 µ s Output current monitoring interval µ s

200 ×

N

Rails

Input voltage monitoring interval 2 ms Input current monitoring interval 2 ms Temeprature monitoring interval 800 ms Output current balancing interval 2 ms Fan speed monitoring interval 1000 ms

PARAMETER TEST CONDITIONS MAX TIME UNIT

Over/under voltage fault response time during Normal regulation, no PMBus activity, normal operation 8 stages enabled

Over/under voltage fault response time, during data During data logging to nonvolatile logging memory

Over/under voltage fault response time, when tracking or sequencing enable

Over/under current fault response time during normal operation N

Over/under current fault response time, during data 600 + (600 x logging N

(1)

During tracking and soft-start ramp. 400 µ s Normal regulation, no PMBus activity,

8 stages enabled µ s 75% to 125% current step

During data logging to nonvolatile memory µ s 75% to 125% current step

300 µ s

800 µ s

(2)

100 + (600 x

)

Rails

)

Rails

Over/under current fault response time, when During tracking and soft start ramp 300 + (600 x tracking or sequencing enable 75% to 125% current step N

Overtemperature fault response time 5 s

Temperature rise of 10 ° C/sec, OT threshold = 100 ° C

)

Rails

µ s

Product Folder Link(s): UCD9240

UCD9240

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HARDWARE FAULT DETECTION LATENCY

The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.

PARAMETER TEST CONDITIONS MAX TIME UNIT

t

FAULT

t

CLF-A

t

CLF-B

PMBUS/SMBUS/I

Time to disable DPWM output base on active FAULT pin signal

High level on FAULT pin µ s

Time to disable the DPWM A output based on internal Step change in CS voltage from 0v to Switch analog comparator 2.5V Cycles

Time to disable all remaining DPWM and SRE outputs configured to drive a voltage rail after a CLF-A event µ s occurs

2

C

Step change in CS voltage from 0V to

2.5V

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus are shown below.

I2C/SMBus/PMBus Timing Characteristics

TA= – 40 ° C to 85 ° C, 3V < V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

SMB

f

I2C

t

(BUF)

t

(HD:STA)

t

(SU:STA)

t

(SU:STO)

t

(HD:DAT)

t

(SU:DAT)

t

(TIMEOUT)

t

(LOW)

t

(HIGH)

t

(LOW:SEXT)

t

FALL

t

RISE

(1) The UCD9240 times out when any clock low exceeds t (2) t

(HIGH)

in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). (3) t

(LOW:SEXT)

(4) Rise time t (5) Fall time t

SMBus/PMBus operating frequency Slave mode; SMBC 50% duty cycle 10 1000 kHz I C operating frequency Slave mode; SCL 50% duty cycle 10 1000 kHz

Bus free time between start and stop 4.7 µ s Hold time after (repeated) start 0.26 µ s Repeated start setup timed 0.26 µ s Stop setup time 0.26 µ s Data hold time Receive mode 0 ns Data setup time 50 ns Error signal/detect See Clock low period 0.5 µ s Clock high period See Cumulative clock low slave extend time See Clock/data fall time See Clock/data rise time See

, max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9110 that is

is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

= V

RISE

VILMAX

= 0.9 V

FALL

< 3.6V, typical values at TA= 25 ° C and V

DD

(TIMEOUT)

to (VILMAX – 0.15)

DD

– 0.15) to (V

+ 0.15)

VIHMIN

= 2.5 V (Unless otherwise noted)

CC

(1)

(2) (3) (4) (5)

.

15 + 3 ×

NumPhases

4

10 + 3 ×

NumPhases

35 µ s

0.26 50 µ s 25 µ s

120 ns 120 ns

Product Folder Link(s): UCD9240

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

The coefficients of the filter sections are generated through modeling the power stage and load in the Power+ Designer tool. Several banks of filter coefficients can be downloaded to the device that can automatically switch them based on the power stage operation.

Figure 1. I2C/SMBus/PMBus Timing in Extended Mode Diagram

Product Folder Link(s): UCD9240

Compensator

3P/3Z IIR

12-bit

ADC

250 ksps

Osc

ARM-7 core

PMBus

EAp4

EAn4

EAp3

EAn3

EAp2

EAn2

AddrSens0 AddrSens1

CS-1A CS-1B CS-2A CS-2B CS-3A CS-3B CS-4A CS-4B Vin/Iin Vtrack

Temp

V33x

xGnd

Analog Front End

(AFE)

Analog Front End

(AFE)

Analog Front End

(AFE)

Ref

ADC 6 bit

IIR

3P/3Z

Err

Amp

EAp1

EAn1

Coeff.

Regs

CompensatorAnalog Front End

ADCref

POR/BOR

DPWM-1A

Ref 1

Analog Comparators

OC PWM-1A

DPWM-1B

FAULT-1A FAULT-1B

DPWM-2A DPWM-2B

FAULT-2A FAULT-2B

DPWM-3A DPWM-3B

FAULT-3A FAULT-3B

DPWM-4A DPWM-4B

FAULT-4A FAULT-4B

PMBus-Clk PMBus-Data PMBus-Alert PMBus-Cntl PowerGood (TMS)

SYNC-IN (TDI) SYNC -OUT (TDO)

5

6

BPCap

SRE-4B SRE-4A SRE-3B SRE-3A SRE-2B SRE-2A SRE-1B SRE-1A

SRE

Control

Compensator

3P/3Z IIR

Compensator

3P/3Z IIR

Flash

Memory with

ECC

Diff

Amp

Fusion Power Peripheral 4

Fusion Power Peripheral 3

Fusion Power Peripheral 2

Fusion Power Peripheral 1

Internal

Temp Sense

3.3V reg.

controller

& 1.8V

regulator

Ref 2

Ref 3

Ref 4

Digital

High Res

PWM

Digital

High Res

PWM

Digital

High Res

PWM

Digital

High Res

PWM

Mux

Control

TMUX0 TMUX1 TMUX2

OC PWM-2A

OC PWM-3A

OC PWM-4A

Fan

Control

FAN-TACH (TCK) FAN-PWM

/RESET

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

FUNCTIONAL BLOCK DIAGRAM

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Product Folder Link(s): UCD9240

58

46

45

7

44

47

9

62 63

64 65 66

67 68

69

EAp1 EAn1

EAp2 EAn2

EAp3 EAn3 EAp4

EAn4

AddrSen0 AddrSen1

CS-1A (COMP1) CS-2A (COMP2)

CS-3A (COMP3) CS-4A (COMP4)

CS-1B CS-2B

CS-3B CS-4B Vin/Iin

Vtrack Temp

Aux-in (AD13) Aux-in (AD14) ADCref

77 76

75

4 3

2

79 78 74

73

5 6

7

72 71

1

DPWM-1A DPWM-1B

DPWM-2A DPWM-2B DPWM-3A

DPWM-3B DPWM-4A

DPWM-4B

21 22 23

24 25

26 27 28

SRE-1A SRE-1B SRE-2A

SRE-2B SRE-3A

SRE-3B SRE-4A SRE-4B

FAULT-1A FAULT-1B

FAULT-2A FAULT-2B

FAULT-3A FAULT-3B

FAULT-4A FAULT-4B

12 11

51 37

38 52

33 50

PMBus-Clk PMBus-Data

PMBus-Alert PMBus-Ctrl

PowerGood

19 20

35 36 49

V33FB

V33A

V33D

V33DIO-1

V33DIO-2

BPCa p

70

58

57

8

56

59

A -1

VSS

A -2

VSS

A

-3

VSS

D -1

VSS

D

-2

VSS

D -3

VSS

61

60

80

9

34

55

/RESET

13

48 47 46

45 44

14

15 16

17 18

29 41 42

43

TMUX-0 TMUX-1

TMUX-2

39 40

54

SYNC-IN

SYNC-OUT

FAN-PWM

FAN-TACH

DiagLED

31 30

53 32 10

UCD9240-64pin UCD9240-80pin

50 51

52 53 54

55 56

57

EAp1 EAn1

EAp2 EAn2

EAp3 EAn3 EAp4

EAn4

AddrSens0 AddrSens1

CS-1A (COMP1) CS-2A (COMP2)

CS-3A (COMP3) CS-4A (COMP4)

CS-1B CS-2B

Vin/Iin Vtrack Temp

61 60

59

3 2

1

63 62

4 5

6

DPWM-1A DPWM-1B

DPWM-2A DPWM-2B DPWM-3A

DPWM-4A

17 18 19

20 21

23

SRE-1A SRE-1B

SRE-2A SRE-2B

SRE-3A SRE-4A

FAULT-1A FAULT-1B

FAULT-2A FAULT-2B

FAULT-3A FAULT-4A

22 24

33 35 29

30

PMBus-Clk PMBus-Data

PMBus-Alert PMBus-Ctrl

PowerGood (TMS)

15 16

27 28

39

V33FB

V33A

V33D

V33DIO-1

V33DIO-2

BPCa p

A -1

VSS

A -2

VSS

A -3

VSS

D

-1

VSS

D -2

VSS

D

-3

VSS

49

48

64

8

26

43

/RESET

9

/TRST

TRCK

40 10

11 12

13 14

25 34

TMUX-0 TMUX-1 TMUX-2

31 32

42

FAN-PWM

FAN-TACH (TCK)

SYNC-IN (TDI)

SYNC-OUT (TDO)

41 36

38 37

/TRST

TMS

TDI

TDO TCK

TRCK

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

The UCD9240 is available in a plastic 64-pin QFN package (RGC) and an 80-pin TQFP package (PFC).

Figure 2. UCD9240 Pin Assignment

Product Folder Link(s): UCD9240

Commutation

logic

FLT

PWM

SRE

CS

PTD08A020W

50 51 52 53 54 55 56 57

EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4

AddrSens0 AddrSens1 CS-1A (COMP1) CS-2A (COMP2) CS-3A (COMP3) CS-4A (COMP4) CS-1B CS-2B Vin/Iin Vtrack Temp

61 60 59

3 2

1 63 62

4

5

6

DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-4A

17 18 19 20 21 23

SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-4A

FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-4A

22 24 33 35 29 30

PMBus-Clk PMBus-Data PMBus-Alert PMBus-Ctrl PowerGood (TMS)

15 16 27 28 39

V33FB

V33A

V33D

V33DIO-1

V33DIO-2

BPCap

584645744

47

Agnd-1

Agnd-2

Agnd-3

Dgnd-1

Dgnd-2

Dgnd-3

494864826

43

/RESET

9

SYNC-IN (TDI)

SYNC-OUT (TDO)

38 37

11 12 13 14 25 34

TMUX-0 TMUX-1 TMUX-2

31 32 42

FLT

PWM

SRE

CS

UCD72xx Driver

PTD08A010W

FLT

PWM

SRE

CS

PTD08A010W

FLT

PWM

SRE

CS

PTD08A010W

FLT

PWM

SRE

CS

PTD08A010W

FLT

PWM

SRE

CS

+Vsens-rail4

-Vsens-rail4

+Vsens-rail1

-Vsens-rail1

+Vsens-rail2

-Vsens-rail2

+Vsens-rail3

-Vsens-rail3

+Vsens-rail1

-Vsens-rail1

+Vsens-rail2

-Vsens-rail2

+Vsens-rail3

-Vsens-rail3

+Vsens-rail4

-Vsens-rail4

Vin

TLV1117-ADJ

VoutVin

+8V

Sync-in Sync-out

CD74HC4051

Temp-rail1A Temp-rail1B Temp-rail2A Temp-rail2B Temp-rail3A Temp-rail4A

13 14 15 12

1

5

2

4

+3.3V

Com

S2 S1 S0

-EN

+3.3V

CS-rail2B

CS-rail2A

CS-rail3A

CS-rail4A

CS-rail1A

CS-rail1A CS-rail2A CS-rail3A CS-rail4A CS-rail1B CS-rail2B

Vtrack

FCX491A

A0 A1 A2 A3 A4 A5 A6 A7

FAN-PWM

FAN-TACH (TCK)

41 36

FAN-PWM FAN-Tach

CS-rail1B

temp

sensor

Temp-rail1A

Temp-rail1B

Temp-rail2A

Temp-rail2B

Temp-rail3A

Temp-rail4A

82.5k

15k

0.1u

10k

4.7u

0.1u

10u

1.10k

5.49k

4.7u

40 10

/TRST

RCK

10k

3

9 10 11 6

16

8

10k

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

TYPICAL APPLICATION SCHEMATIC

Figure 3 shows the UCD9240 power supply controller as part of a system that provides the regulation of four

independent power supplies. The loop for each power supply is created by the respective voltage outputs feeding into the differential voltage error ADC (EADC) inputs, and completed by DPWM outputs feeding into the gate drivers for each power stage.

The ± V configured as part of the rail. (See more detail on page 19, " Flexible Rail/Power Stage Configuration " .)

rail signals must be routed to the EAp/EAn input that matches the number of the lowest DPWM

sense

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Figure 3. Typical Application Schematic

Product Folder Link(s): UCD9240

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

PIN DESCRIPTIONS

64-PIN PACKAGE 80-PIN PACKAGE

PIN NO. SIGNAL PIN NO. SIGNAL

50 EAp1 62 EAp1 AI Error analog, differential voltage. Positive channel #1 input. 51 EAn1 63 EAn1 AI Error analog, differential voltage. Negative channel #1 input. 52 EAp2 64 EAp2 AI Error analog, differential voltage. Positive channel #2 input. 53 EAn2 65 EAn2 AI Error analog, differential voltage. Negative channel #2 input. 54 EAp3 66 EAp3 AI Error analog, differential voltage. Positive channel #3 input. 55 EAn3 67 EAn3 AI Error analog, differential voltage. Negative channel #3 input. 56 EAp4 68 EAp4 AI Error analog, differential voltage. Positive channel #4 input. 57 EAN4 69 EAn4 AI Error analog, differential voltage. Negative channel #4 input.

61 AddrSens0 77 AddrSens0 AI PMBus address sense. Least significant address bits 60 AddrSens1 76 AddrSens1 AI PMBus address sense. Most significant address bits 59 CS-1A 75 CS-1A AI Power stage 1A current sense input. Analog comparator 1

3 CS-2A 4 CS-2A AI Power stage 2A current sense input. Analog comparator 2 2 CS-3A 3 CS-3A AI Power stage 3A current sense input. Analog comparator 3

1 CS-4A 2 CS-4A AI Power stage 4A current sense input. Analog comparator 4 63 CS-1B 79 CS-1B AI Power stage 1B current sense input 62 CS-2B 78 CS-2B AI Power stage 2B current sense input

– CS-3B 74 CS-3B AI Power stage 3B current sense input

– CS-4B 73 CS-4B AI Power stage 4B current sense input

4 Vin/ I

in

5 Vin/ I

in

5 VTRACK 6 VTRACK AI Voltage tracking

6 Temp 7 Temp AI Temperature sense input

Aux-in Aux-in

– 72 AI Unused analog input -- Tie to ground with 10 k Ω resistor

(AD13) (AD13) Aux-in Aux-in

– 71 AI Unused analog input -- Tie to ground with 10 k Ω reisistor

(AD14) (AD14)

– ADCref 1 ADCref AI ADC Decoupling Capacitor -- Tie 0.1 µ F cap to ground

I/O DESCRIPTION

Error Amplifier Differential Analog Inputs

Analog Inputs

AI Input supply sense, alternates between Vinand I

in

Digital PWM Outputs

17 dPWM-1A 21 dPWM-1A O DPWM 1A output 18 dPWM-1B 22 dPWM-1B O DPWM 1B output 19 dPWM-2A 23 dPWM-2A O DPWM 2A output 20 dPWM-2B 24 dPWM-2B O DPWM 2B output 21 dPWM-3A 25 dPWM-3A O DPWM 3A output

26 dPWM-3B O DPWM 3B output

23 dPWM-4A 27 dPWM-4A O DPWM 4A output

28 dPWM-4B O DPWM 4B output

External Fault Inputs

11 FAULT-1A 15 FAULT-1A I External fault input 1A 12 FAULT-1B 16 FAULT-1B I External fault input 1B 13 FAULT-2A 17 FAULT-2A I External fault input 2A 14 FAULT-2B 18 FAULT-2B I External fault input 2B 25 FAULT-3A 29 FAULT-3A I External fault input 3A

41 FAULT-3B I External fault input 3B

34 FAULT-4A 42 FAULT-4A I External fault input 4A

43 FAULT-4B I External fault input 4B

Product Folder Link(s): UCD9240

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

PIN DESCRIPTIONS (continued)

64-PIN PACKAGE 80-PIN PACKAGE

PIN NO. SIGNAL PIN NO. SIGNAL

22 SRE-1A 12 SRE-1A O Synchronous rectifier enable 1A 24 SRE-1B 11 SRE-1B O Synchronous rectifier enable 1B 33 SRE-2A 51 SRE-2A O Synchronous rectifier enable 2A 35 SRE-2B 37 SRE-2B O Synchronous rectifier enable 2B 29 SRE-3A 38 SRE-3A O Synchronous rectifier enable 3A

52 SRE-3B O Synchronous rectifier enable 3B

30 SRE-4A 33 SRE-4A O Synchronous rectifier enable 4A

50 SRE-4B O Synchronous rectifier enable 4B

31 TMUX-0 39 TMUX-0 O Temperature multiplexer select S0

9 RESET 13 RESET I Active low device reset input 32 TMUX-1 40 TMUX-1 O Temperature multiplexer select S1 42 TMUX-2 54 TMUX-2 O Temperature multiplexer select S2 41 FAN-PWM 53 FAN-PWM O Fan control PWM output 39 PowerGood 49 PowerGood O Power good signal (multiplexed with TMS on 64-pin package) 36 FAN-Tach 32 FAN-Tach I Fan tachometer input (multiplexed with TCK on 64-pin package)

37 Sync_Out 30 Sync_Out O 38 Sync_In 31 Sync_In I Synchronization input to DPWM (multiplexed with TDI on 64-pin package)

10 diag LED O Diagnostic LED

I/O DESCRIPTION

Synchronous Rectification Enable Outputs

Miscellaneous Digital I/O

Synchronization output from DPWM (multiplexed with TDO on 64-pin package)

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PMBus Communications Interface

15 PMBus_Clk 19 PMBus_Clk I/O PMBus Clk (Must have pullup to 3.3 V) 16 PMBus_Data 20 PMBus_Data I/O PMBus Data (Must have pullup to 3.3 V) 27 PMBus_Alert 35 PMBus_Alert O PMBUS Alert 28 PMBus_Cntrl 36 PMBus_Cntrl I PMBUS Cntl

JTAG

10 TRCK 14 TRCK O Test return clock 36 TCK 44 TCK I Test clock (multiplexed with FAN-Tach (TCK) on 64-pin package) 37 TDO 45 TDO O Test data out (multiplexed with Sync_Out (TDO) on 64-pin package)

38 TDI 46 TDI I

39 TMS 47 TMS I/O

Test data in -- tie to Vdd with 10 k Ω resistor (multiplexed with Sync_In (TDI) on 64-pin package)

Test mode select -- tie to Vdd with 10 k Ω resistor (multiplexed with PowerGood (TMS) on 64-pin package)

40 TRST 48 TRST I/O Test reset -- tie to ground with 10 k Ω resistor

Input Power and Grounds

58 V33FB 70 V33FB I 3.3-V linear regulatorfFeedback connection 46 V33A 58 V33A I Analog 3.3-V supply 45 V33D 57 V33D I Digital core 3.3-V supply

7 V33DIO 8 V33DIO I Digital I/O 3.3-V supply 44 V33DIO 56 V33DIO I Digital I/O 3.3-V supply 47 BPCap 59 BPCap I 1.8-V bypass capacitor connection 49 AV 48 AV 64 AV

SS SS SS

61 AV 60 AV 80 AV

SS SS SS

I Analog ground I Analog ground I Analog ground

Product Folder Link(s): UCD9240

Vdd

10uA

I

BIAS

To12 -bit ADC

Resistorto setPMBus

Address

On/OffControl

AddrSens0, AddrSens1

pins

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

PIN DESCRIPTIONS (continued)

64-PIN PACKAGE 80-PIN PACKAGE

PIN NO. SIGNAL PIN NO. SIGNAL

8 DV 26 DV 43 DV

SS SS SS

9 DV 34 DV 55 DV

SS SS SS

I/O DESCRIPTION

I Digital ground I Digital ground I Digital ground

FUNCTIONAL OVERVIEW

The UCD9240 contains four fusion power peripherals (FPP). Each FPP can be configured to regulated up to four DC/DC converter outputs. There are eight PWM outputs that can be assigned to drive the coverter outputs. Each FPP can be configured to drive from one of the eight power stages. Each FPP consists of:

• A differential input error voltage amplifier.

• A 10-bit DAC used to set the output regulation reference voltage.

• A fast ADC with programmable input gain to digitally measure the error voltage.

• A dedicated 3-pole/3-zero digital filter to compensate the error voltage.

• A digital PWM (DPWM) engine that generates the PWM pulse width based on the compensator output.

Each controller is configured through a PMBus serial interface.

PMBus Interface

The PMBus is a serial interface specifically designed to support power management. It is based on the SMBus interface that is built on the I2C physical specification. The UCD9240 supports revision 1.1 of the PMBus standard. Wherever possible, standard PMBus commands are used to support the function of the device. For unique features of the UCD9240, MFR_SPECIFIC commands are defined to configure or activate those features. These commands are defined in the UCD92xx PMBUS Command Reference.

The UCD9240 is PMBus compliant, in accordance with the "Compliance" section of the PMBus specification. The firmware is also compliant with the SMBus 1.1 specification, including support for the SMBus ALERT function. The hardware can support either 100 kHz, 400 kHz, or 1 MHz PMBus operation.

Resistor Programmed PMBus Address Decode

Two pins are allocated to decode the PMBus address. At power-up, the device applies a bias current to each address detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is calculated as follows:

Where bin(V

The address bins are defined so that each bin is a constant ratio of the previous bin. This method maintains the width of each bin relative to the tolerance of the standard 1% resistors. The ratio betweens bins is 1.30.

PMBus Address = 12 × bin(V

) is the address bin for one of 12 address as shown in Table 1 .

AD0x

) + bin(V

AD01

)

AD00

Figure 4. PMBus Address Detection Method

Product Folder Link(s): UCD9240

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

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Table 1. PMBus Address Bins

V

PMBus ADDRESS

open 2.226 3.300 –

11 1.746 2.255 200 10 1.342 1.746 154

9 1.030 1.341 118 8 0.792 1.030 90.9 7 0.609 0.792 69.8 6 0.468 0.608 53.6 5 0.359 0.467 41.2 4 0.276 0.358 31.6 3 0.212 0.275 24.3 2 0.162 0.211 18.7 1 0.125 0.162 14.3 0 0.098 0.124 11

short 0 0.097 –

PMBus VOLTAGE RANGE (V)

MIN MAX

PMBus

PMBus RESISTANCE (k Ω )

R

PMBus

A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the PMBus address to default to address 126. A high impedance (open) on either address pin that produces a voltage above the maximum voltage also causes the PMBus address to default to address 126.

The PMBus address can be set to any value ranging from 1 to 126, except address 12. Address 0 is not used because it is the SMBus General Call address; address 12 is reserved for the PMBus alert response. Also, it is recommended that address 11 not be used by this device or any other device that shares the PMBus with it, since it is used in manufacturing to program the device. Further, address 127 cannot be used by this device or any other device that shares the PMBus with it, since the address is reserved by this device for device manufacturing test.

Finally, it is recommended that address 126 not be used for any devices on the PMBus, since this is the address that the UCD9240 defaults to if the address lines are shorted to ground or left open. If any other UCD9240 has a short or open on its address lines, then its address would conflict with the (programmed) address 126.

Product Folder Link(s): UCD9240

V33FB

V33A

V33D

V33DIO-1

V33DIO-2

BPCap

0.1u

10k0

Vin

4.7u

0.1u

FCX491A

UCD9240

To Power Stage

+3.3V

+1.8V

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

Table 2. PMBus Address Assignment Rules

ADDRESS STATUS REASON

0 Prohibited SMBus generall address call

1-10 Avaliable

11 Avoid Causes confilcts with other devices during program flash updates. 12 Prohibited PMBus alert response protocol

13-125 Avaliable

126 Avoid Default value; may cause conflicts with other devices. 127 Prohibited Used by TI manufacturing for device tests.

JTAG Interface

The JTAG interface can provide an alternate interface for programming the device. It is disabled by default in order to enable the fan, sync, and power good status pins with which it is multiplexed. There are three conditions under which the JTAG interface is enabled:

1. When the ROM_MODE PMBus command is issued.

2. On power-up if the Data Flash is blank. This allows JTAG to be used for writing the configuration parameters to a programmed device with no PMBus interaction.

3. When an invalid address is detected at power-up. By shorting one of the address pins to ground, an invalid address can be generated that enables JTAG.

Bias Supply Generator (Series Regulator Controller)

Internally, the circuits in the UCD92XX require 3.3V to operate. This can be provided directly on the V33x pins, or it can be generated from the power supply input voltage using an internal series regulator and an external transistor. The requirements for the external transistor are that it be an NPN device with a beta of at least 40.

Figure 3 shows the typical application using the external series pass transistor. The base of the transistor is

driven by a 10k Ω resistor to Vin and a transconduction amplifier whose output is on the VD33FB pin. The NPN emitter becomes the 3.3 V supply for the chip and requires a bypass capacitor of 4 to 5 µ F.

Some circuits in the device require 1.8V that is generated internally from the 3.3V supply. This voltage requires a

0.1 to 1 µ F bypass capacitor from BPCap to ground.

Figure 5. Series-Pass 3.3V Regulator Controller I/O

Power On Reset

Product Folder Link(s): UCD9240

The UCD9240 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the POR circuit detects the V33D rise. When V33D is greater than VRESET, the device initiates the UVLO or startup-delay sequence. At the end of the delay sequence, the device begins normal operation, as defined by the downloaded device PMBus configuration.

VOUT_M ARGIN_HIGH

VOUT_CAL_O FFSET

VOUT_MARGIN_LOW

VOUT_COMMAND

+

Limiter

VOUT_ SCALE_ LOOP

“Reference Voltage Equivalent”

OPERATION

Com mand

VOUT_MAX

3:1

Mux

EApx

EAnx

6-bitresult

eADC

VrefDAC

CPU

PMBus

G

AFE

= 1, 2, 4 or 8

Vead

G

eADC

= 8mV/LSB

Vref = 1.563 mV/LSB

+

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

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External Reset

The device can be forced into the reset state by an external circuit connected to the RESET pin. A logic low voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a pull up resistor to

3.3V is recommended.

Output Voltage Adjustment

The nominal output voltage is programmed by a combination of PMBus commands: VOUT_COMMAND, VOUT_CAL_OFFSET, and VOUT_MAX. Their relationship is shown in Figure 6 . Output voltage margining is configured by the VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands. The OPERATION command selects between the nominal output voltage and either of the margin voltages. The OPERATION command also includes an option to suppress certain voltage faults and warnings while operating at the margin settings.

For a complete description of the commands supported by the UCD9240 see the UCD92xx PMBUS Command Reference. Each of these commands can also be issued from the Texas Instruments Fusion Digital Power™ Designer program. This Graphical User Interface (GUI) PC program issues the appropriate commands to configure the UCD9240 device.

Analog Front End (AFE)

The UCD9240 senses the power supply output voltage differentially through the EAP and EAN pins. The error amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage sense signals. The fully differential nature of the error amplifier also ensures low offset performance.

The output voltage is sampled at a programmable time (set by the EADC_SAMPLE_TRIGGER PMBus

Figure 6. PMBus Voltage Adjustment Methods

Figure 7. Analog Front End Block Diagram

Product Folder Link(s): UCD9240

EAp

EAn

V

OUT

R

1

R

IN

I

OFF

R

2

2 1 2

1 2 1 2

= +

æ ö æ ö

+ + + +

ç ÷ ç ÷ è ø è ø

EA OUT O FF

IN IN

R R R

V V I

R R R R

R R

1

2

1

=

æ ö

- + ±

ç ÷ è ø

EA

OUT EA OFF

IN

R V

R

V V R I

R

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by the Vref DAC as shown in Figure 7 . The resulting error voltage is then amplified by a programmable gain circuit before the error voltage is converted to a digital value by the flash ADC. This programmable gain is configured through the PMBus and affects the dynamic range and resolution of the sensed error voltage as shown in

Table 3 .

Table 3. Analog Front End Resolution

AFE GAIN DIGITAL ERROR VOLTAGE DYNAMIC RANGE (mV)

1 8 -256 to 248 2 4 -128 to 124 4 2 -64 to 62 8 1 -32 to 31

EFFECTIVE ADC RESOLUTION

(mV)

The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This allows the user to trade-off resolution and dynamic range for each operational mode.

The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time. However, its range is limited as shown in Table 3 . If the output voltage is different from the reference by more than this, the EADC reports a saturated value at -32 LSBs or 31 LSBs. The UCD9240 overcomes this limitation by adjusting the setpoint DAC up or down in order to bring the error voltage out of saturation. In this way, the effective range of the ADC is extended. When the EADC saturates, the setpoint DAC is slewed at a rate of 0.156 V/ms, referred to the EA differential inputs.

To obtain the best possible accuracy, the input resistance and offset current on the device should be considered when calculating the gain of a voltage divider between the output voltage and the EA sense inputs of the UCD9240. The input resistance and input offset current are specified in the parametric tables in this datasheet.

The effect of the offset current can be reduced by making the resistance of the divider network low. R1 should be between 1k Ω and 5k Ω . Then R2, the lower divider resistor, can be calculated as:

Digital Compensator

Each voltage rail controller in the UCD9240 includes a digital compensator. The compensator consists of a nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (IIR) filter section cascaded with a first order IIR filter section.

Figure 8. Input Offset Equivalent Circuit

Product Folder Link(s): UCD9240

Nonlinear Gain Block

Threshold

logic

Gain 0

Gain 1

Gain 2

Gain 3

Gain 4

eADC

Limit 0

Limit 3

Limit 2

Limit 1

z

-1

+

X

B01

z

-1

X

B11XB21

+

Clamp z

-1

z

-1

X

+

A11 A21

z

-1

X

+

B12

z

-1

Clamp

X

A21

2nd Order Filter Section

1st Order Filter Section

Duty out

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

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The Texas Instruments Fusion Digital Power™ Designer development tool can be used to assist in defining the compensator coefficients. The design tool allows the compensator to be described in terms of the pole frequencies, zero frequencies and gain desired for the control loop. In addition, the Fusion Digital Power™ Designer can be used to characterize the power stage so that the compensator coefficients can be chosen based on the total loop gain for each feedback system. The coefficients of the filter sections are generated through modeling the power stage and load.

Additionally, the UCD9240 has three banks of filter coefficients: Bank-0 is used during the soft start/stop ramp or tracking; Bank-1 is used while in regulation mode; and Bank-2 is used when the measured output current is below the configured light load threshold.

The compensator also allows the minimum and maximum duty cycle to be programmed. This again is done by issuing a PMBus command to the device.

Figure 9. Digital Compensator

The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from zero. Typically Limit 0 and Limit 1 would be configured with negative values between -1 and -32 and Limit 2 and Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to be symmetric. For example, the four limit registers could all be set to positive values causing the Gain 0 value to set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages.

The cascaded 1st order filter section is used to generated the third zero and third pole.

DPWM Engine

The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty cycle as a digital number representing a value from 0 to 1 This duty cycle value is multiplied by the configured period to generate a comparator threshold value. This threshold is compared against the high speed switching period counter to generate the desired DPWM pulse width. This is shown in Figure 10 . The resolution of the duty period is nominally 250 picoseconds.

Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the SYNC_IN and SYNC_OUT pins. Configuration of the synchronization function is done through a MFR_SPECIFIC PMBus command. See the DPWM Synchronization section for more details.

Product Folder Link(s): UCD9240

high

res

ramp

counter

Clk

reset

Switchperiod

Currentbalanceadj

Compensatoroutput

(calculateddutycycle)

EADCtrigger threshold

PWMgatedrive

output

SysClk

SyncIn

EADC

trigger

SyncOut

S

R

DPWMEngine(1of4)

3

13

=

rail-rail spread SW

t t

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

Figure 10. DPWM Engine

The switching frequency is set by issuing the FREQUENCY_SWITCH PMBus command.

Flexible Rail/Power Stage Configuration

The UCD9240 can control up to four rails, each of which can comprise a programmable number of power stages. Constraints on the mapping of power stages to rails are described in detail in the UCD92xx PMBus Command Reference under the PHASE_INFO command.

While there is significant flexibility in terms of mapping power stages to output rails, the differential voltage feedback signals (EAP/EAN) cannot be re-mapped through any commands, and therefore, must be connected to the proper input on the circuit board. Because the EADC sample trigger for a given front end stage is derived from the ramp timer of the first (lowest numbered) DPWM on the rail, the system must ensure that the number of the EADC and the number of the first DPWM match. For example, consider a two rail configuration in which 4 power stages (1A, 2A, 1B and 2B) are assigned to the first rail and 2 power stages (3A and 4A) to the second. The first DPWM on the first rail is 1; its voltage feedback must be through EAP1/EAN1. The first DPWM on the second rail is 3; its voltage feedback must be through EAP3/EAN3. (In this configuration EAP2/EAN2 and EAP4/EAN4 are unused and are disabled to reduce unnecessary power consumption.)

DPWM Phase Distribution

The number of voltage rails is configured using the PHASE_INFO PMBus command. The UCD9240 automatically synchronizes the first power stage of each voltage rail. The phase (in time) of each 1st power stage is shifted by an amount in order to minimize input current ripple. The amount that each 1st power stage is shifted is:

The ratio 3/13 is chosen because it is close to 1/4, but it is a prime ratio. This should ensure that any configuration of rails and power stages should not have the leading edge of the DPWM signal aligned.

The PHASE_INFO PMBus command is also used to configure the number of power stages driving each voltage rail. When multiple power stages are configured to drive a voltage rail, the UCD9240 automatically distributes the phase of each DPWM output to minimize ripple. This is accomplished by setting the rising edge of each DPWM pulse to be separated by:

Where tSWis the period of the rail with the fastest switching frequency.

Product Folder Link(s): UCD9240

=

SW

phase-phase spread

Phases

t

N

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

Where tSWis the switching period and N

is the number of power stages driving a voltage rail.

Phases

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DPWM Synchronization

DPWM synchronization provides a method to link the timing between rails on two distinct devices at the switching rate; i.e., two rails on different devices can be configured to run at the same frequency and sync forcing them not to drift from each other. (Note that within a single device, because all rails are driven off a common clock there is no need for an internal sync because rails wont drift.)

The PMBus SYNC_IN_OUT command sets which rails (if any) should follow the sync input, and which rail (if any) should drive the sync output.

For rails that are following the sync input, the DPWM ramp timer for that output is reset when the sync input goes high. This allows the slave device to sync to inputs that are either faster or slower than it is. On the fast side, there is no limit to how much faster the input is compared to the defined frequency of the rail; when the pulse comes in, the timer is reset and the frequencies are locked. This is the standard mode of operation - setting the slave to run slower, and letting the sync speed it up.

If the slave rail is running fast, the sync pulse resets the counter after the DPWM output has already been turned on. Resetting the counter at this point results in a larger duty cycle for that period. Because the system is closed loop; however, the controller reacts by decreasing the commanded control effort, with the result being a regulated rail synchronized to a slower master. Synchronizing to the slower master does have a limit however. If the master is slow enough that the DPWM output has sufficient time to output the entire command pulse before the sync input arrives, the result is a double pulse. This is likely an undesirable mode of operation.

The Sync Input and Output Configuration Word set by the PMBus command consists of two bytes. The upper byte (sync_out) controls which rail drives the sync output signal (0=DWPM1, 1=DPWM2, 2=DPWM3, 3=DPWM4. Any other value disables sync_out). The lower byte (sync_in) determines which rail(s) respond to the sync input signal (each bit represents one rail - note that multiple rails can be synchronized to the input). The DPWM period is aligned to the sync input. For more information, see the UCD92xx PMBUS Command Reference.

Note that once a rail is synchronized to an external source, the rail-to-rail spacing that attempts to minimize input current ripple are lost. Rail-to-rail spacing can only be restored by power cycling or issuing a SOFT_RESET command.

Phase Shedding at Light Current Load

By issuing LIGHT_LOAD_LIMIT_LOW, LIGHT_LOAD_LIMIT_HIGH, and LIGHT_LOAD_CONFIG commands, the UCD9240 can be configured to shed (disable) power stages when at light load. When this feature is enabled, the device disables the configured number of power stages when the average current drops below the specified LIGHT_LOAD_LIMIT_LOW. In addition, a separate set of compensation coefficients can be loaded into the digital compensator when entering a light load condition.

Phase Adding at Normal Current Load

After shedding phases, if the current load is increased past the LIGHT_LOAD_LIMIT_HIGH threshold, all phases are re-enabled. If the compensator was configured for light load, the normal load coefficients are restored as well. See the UCD92xx PMBUS Command Reference for more information.

Output Current Measurment

Pins CS-1A, CS-1B, CS-2A, CS-2B, CS-3A, CS-3B, CS-4A, and CS-4B are used to measure either output current or inductor current in each of the controlled power stages. PMBus commands IOUT_CAL_GAIN and IOUT_CAL_OFFSET are used to calibrate each measurement. See the UCD92xx PMBus Command Reference for specifics on configuring this voltage to current conversion.

When the measured current is outside the range of either the overcurrent or undercurrent threshold, a FAULT is

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10 100 1.0k 10k 100k

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UCD9240

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declared and the UCD9240 performs the PMBus configured fault recovery. ADC current measurements are digitally averaged before they are compared against the FAULT threshold. The output current is measured at a rate of one output rail per 200 microseconds. The current measurements are then passed through a smoothing filter to reduce noise on the signal and prevent false errors. The output of the smoothing filter asymptotically approaches the input value with a time constant that is approximately 3.5 times the sampling interval.

Table 4. Output Current Filter Times Constants

NUMBER OF OUTPUT RAILS FILTER TIME CONSTANTS (ms)

1 200 0.7 2 400 1.4 3 600 2.1 4 800 2.8

OUTPUT CURRENT SAMPLING

INTERVALS ( µ s)

For example, with a single rail, the filter has the transfer function characteristics (Figure 11 ) that shows the signal magnitude at the output of the averaging filter due to a sine wave input for a range of frequencies. This plot includes an RC analog low pass network, with a corner frequency of 3 kHz, on the current sense inputs.

This averaged current measurement is used for output current fault detection; see “ Overcurrent Detection, ” below.

In response to a PMBus request for a current reading, the device returns an average current value. When the UCD9240 is configured to drive a multi-phase power converter, the device adds the average current measurement for each of the power stages tied to a power rail.

Figure 11. Averaging Filter for Current Monitoring

Output Current Balancing

When the UCD9240 is configured to drive multiple power stage circuits from one compensator, current balancing is implemented by adjusting each gate drive output pulse width to correct for current imbalance between the connected power stage sections. The UCD9240 balances the current by monitoring the current at the CS analog input for each power stage and then adding a current balance adjustment value to the DPWM ramp threshold value for each power stage.

When there is more than one power stage connected to the voltage rail, the device continually determines which stage has the highest measured current and which stage has the lowest measured current. To balance the currents while maintaining a constant total current, the adjustment value for the power stage with the lowest current is increased by the same amount as the adjustment value for the power stage with the highest current is decreased. A slight modification to this algorithm is made to keep the adjustment values positive in order to ensure that a positive DPWM duty cycle is commanded under all conditions.

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( )

1 2 1

1 e

t

-

æ ö ç ÷

= + - -

ç ÷ è ø

smoothed

t

I t

I I I

2 1

2

lnt

æ ö

-

=

ç ÷

-

è ø

lag

limit

I I

t

I I

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

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Overcurrent Detection

Several mechanisms are provided to sense output current fault conditions. This allows for the design of power systems with multiple layers of protection.

1. A logic high signal on the FAULT input causes a hardware interrupt to the internal CPU. The CPU then determines which DPWM outputs are configured to be associated with the voltage rail that contained the fault and disables those DPWM and SRE outputs. This process takes about 14 microseconds. An integrated gate driver such as the UCD7230 can be used to generate the FAULT signal. The UCD7230 monitors the voltage drop across the high side FET and if it exceeds a resistor/voltage programmed threshold, the UCD7230 activates its fault output. The FAULT input can be disabled by reconfiguring the FAULT pin to be a sequencing pin.

2. Inputs CS-1A, CS-2A, CS-3A and CS-4A each drive an internal analog comparator. These comparators can be used to detect the voltage output of a current sense circuit. Each comparator has a separate PMBus configurable threshold. This threshold is set by issuing the FAST_OC_FAULT_LIMIT command. Though the command is specified in amperes, the hardware threshold is programmed with a value between 31mV and 2V in 64 steps. The conversion from amperes to volts is accomplished by issuing the IOUT_CAL_GAIN command. When the current sense voltage exceeds the configured threshold the corresponding DPWM and SRE outputs are driven low on the voltage rail with the fault.

3. Each Current Sense input to the UCD9240 is also monitored by the 12-bit ADC. Each measured value is scaled using the IOUT_CAL_GAIN and IOUT_CAL_OFFSET commands. The currents for each power stage configured as part of a voltage rail are summed and compared to the OC limit set by the IOUT_OC_FAULT_LIMIT command. The action taken when a fault is detected is defined by the IOUT_OC_FAULT_RESPONSE command.

Because the current measurement is averaged with a smoothing filter, the response time to an Overcurrent condition depends on a combination of the time constant ( τ ) from Table 4 , the recent measurement history, and how much the measured value exceeds the overcurrent limit. When the current steps from a current (I1) that is less than the limit to a higher current (I2) that is greater than the limit, the output of the smoothing filter is:

At the point when I

smoothed

exceeds the limit, the smoothing filter lags time, t

is:

lag

The worst case response time to an overcurrent condition is the sum of the sampling interval (Table 4 ) and the smoothing filter lag, t

from the equation above.

lag

Current Foldback Mode

When the measured output current exceeds the value specified by the IOUT_OC_FAULT_LIMIT command, the UCD9240 attempts to continue to operate by reducing the output voltage in order to maintain the output current at the value set by IOUT_OC_FAULT_LIMIT. This continues indefinitely as long as the output voltage remains above the minimum value specified by IOUT_OC_LV_FAULT_LIMIT. If the output voltage is pulled down to less than that value, the device shuts down, if programmed to do so by the IOUT_OC_LV_FAULT_RESPONSE command.

(3)

(4)

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CD74HC4051

Temp-rail1A Temp-rail1B Temp-rail2A Temp-rail2B Temp-rail3A Temp-rail4A

13 14 15 12

1 5 2 4

+3.3V

Com

S2 S1 S0

-EN

A0 A1 A2 A3 A4 A5 A6 A7

Temp

TMUX2 TMUX1 TMUX0

3

9 10 11 6

16

8

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

Input Voltage and Current Monitoring

The Vin/Iin pin on the UCD9240 monitors the input voltage and current. To measure both input voltage and input current, an external multiplexer is required. If measurement of only the input voltage, and not input current, is desired, then a multiplexer is not needed, see Figure 3 . The multiplexer is switched between voltage and current using the TMUX-0 signal. (This signal is the LSB of the temperature mux select signals, so the TMUX-0 signal is connected both to the temperature multiplexer as well as the voltage/current multiplexer). The Vin/Iin pin is monitored using the internal 12-bit ADC and so has a dynamic range of 0 to 2.5V. The fault thresholds for the input voltage are set using the VIN_OV_FAULT_LIMIT and VIN_UV_FAULT_LIMIT commands. The scaling for Vin is set using the VIN_SCALE_MONITOR command, and the scaling for Iin is set using the IIN_SCALE_MONITOR command.

Temperature Monitoring

Both the internal device temperature and up to eight external temperatures are monitored by the UCD9240. The controller supports multiple PMBus commands related to temperature, including READ_TEMPERATURE_1, which reads the internal temperature, READ_TEMPERATURE_2, which reads the external power stage temperatures, OT_FAULT_LIMIT, which sets the over temperature fault limit, and OT_FAULT_RESPONSE, which defines the action to take when the configured limit is exceeded.

If more than one external temperature is to be measured, the UCD9240 provides analog multiplexer select pins (TMUX0-2) to allow up to 8 external temperatures to be measured. The output of the multiplexer is routed to the Temp pin. The controller cycles through each of the power stage temperature measurement signals. The signal from the external temperature sensor is expected to be a linear voltage proportional to temperature. The PMBus commands TEMPERATURE_CAL_GAIN and TEMPERATURE_CAL_OFFSET are used to scale the measured temperature-dependent voltage to ° C. The inputs to the multiplexer should be mapped without any gap. For example, if only one power stage is wired to each DPWM, the four temperature signals should be wired to the first four multiplexer input.

The UCD9240 monitors temperature using the 12-bit monitor ADC, sampling each temperature in turn with a 800 ms sample period. These measurements are smoothed by a digital filter, similar to that used to smooth the output current measurements. The filter has a time constant 15.5 times the sample interval, or 12.4 s (15.5 × 800 ms = 12.4 seconds). This filtering reduces the probability of false fault detections.

Figure 12. Temperature Mux (4-rail, 6-phase Example)

Temperature Balancing

Temperature balancing between phases is performed by adjusting the current such that cooler phases draw a larger share of the current. Temperature balancing occurs slowly (the loop runs at a 10 Hz rate), and only when the phase currents exceeds the PMBus settable TEMP_BALANCE_IMIN. This minimum current threshold prevents the controller from "winding up" and forcing one phase to carry all the current under a low-load condition, when the total current may be insufficient to significantly affect phase temperatures.

Soft Start, Soft Stop Ramp Sequence

The UCD9240 performs soft start and soft stop ramps under closed loop control. Performing a start or stop ramp or tracking is considered a separate operational mode. The other operational modes are normal regulation and light load regulation. Each operational mode can be configured to have an independent loop gain and compensation. Each set of loop gain coefficients is called a "bank" and is configured using the CLA_GAINS PMBus command.

Product Folder Link(s): UCD9240

2 4 6 8 10 14 16120

–0.2

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olts

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PWMbeginsherewithpre-bias

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

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Start ramps are performed by waiting for the configured start delay TON_DELAY and then ramping the internal reference toward the commanded reference voltage at the rate specified by the TON_DELAY time. The DPWM and SRE outputs are enabled when the internal ramp reference equals the preexisting voltage (pre-bias) on the output and the calculated DPWM pulse width exceeds the pulse width specified by DRIVER_MIN_PULSE. This ensures that a constant ramp rate is maintained, and that the ramp is completed at the same time it would be if there were not a pre-bias condition.

The operation of soft-stop ramps depends on how the voltage rail is configured. If PAGE_ISOLATED is set to 1 through the PAGE_ISOLATED PMBus command, the controller assumes that it is the only device driving the voltage rail, and the soft-stop ramp is performed with SRE enabled until the voltage associated with the configured minimum supported pulse width is reached. If PAGE_ISOLATED is set to 0, the controller assumes that multiple power stages may be supplying the voltage rail and SRE is disabled at the beginning of the soft-stop ramp. Figure 13 shows the operation of soft-start ramps and soft-stop ramps.

Figure 13. Start and Stop Ramps

When a voltage rail is in its idle state, the DPWM and SRE outputs are disabled, and the differential voltage on the EAP/EAN pins are monitored by the controller. During idle the setpoint DAC is adjusted to minimize the error voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the start ramp from that voltage with a minimum of disturbance. This is done by calculating the duty cycle that is required to match the measured voltage on the rail. Nominally this is calculated as Vin / Vout; however, to allow for losses and offsets in the system, PREBIAS_GAIN and PREBIAS_OFFSET can be used for fine tuning. If the pre-bias voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the DRIVER_MIN_PULSE PMBus command, then the start ramp is delayed until the internal ramp reference voltage has increased to the point where the required duty cycle exceeds the specified minimum duty.

Once a soft start/stop ramp has begun, the output is controlled by adjusting the setpoint DAC at a fixed rate and allowing the digital compensator control engine to generate a duty cycle based on the error. The setpoint DAC adjustments are made at a rate of 10 kHz and are based on the TON_RISE or TOFF_FALL PMBus configuration parameters.

Although the presence of a pre-bias voltage or a specified minimum DPWM pulse width affects the time when the DPWM and SRE signals become active, the time from when the controller starts processing the turn-on command to the time when it reaches regulation is TON_DELAY plus TON_RISE, regardless of the pre-bias or minimum duty cycle.

During a normal ramp (i.e. no tracking, no current limiting events and no EADC saturation), the setpoint slews at a pre-calculated rate based on the commanded output voltage and TON_RISE. Under closed loop control, the compensator follows this ramp up to the regulation point.

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Because the EADC in the controller has a limited range, it may saturate due to a large transient during a start/stop ramp. If this occurs, the controller overrides the calculated setpoint ramp value, and adjust the reference DAC in the direction to minimize the error. It continues to step the reference DAC in this direction until the EADC comes out of saturation. Once it is out of saturation, the start ramp continues, but from this new setpoint voltage; and therefore, has an impact on the ramp time.

Input UV Lockout

The normal operation supply lock-out voltage thresholds are configured with the VIN_ON and VIN_OFF commands. When input supply voltage drops below the value set by VIN_OFF, the device starts a normal soft stop ramp. When the input supply voltage drops below the voltage set by VIN_UV_FAULT_LIMIT, the device performs per the configuration using the VIN_UV_FAULT_RESPONSE command. For example, when the bias supply for the controller is derived from another source, the response code can be set to "Continue" or "Continue with delay," and the controller attempts to finish the soft stop ramp. If the bias voltages for the controller and gate driver are uncertain below some voltage, the user can set the UV fault limit to that voltage and specify the response code to be "shut down immediately" disabling all DPWM and SRE outputs. If VIN_OFF sets the voltage at which the output voltage soft-stop ramp is initiated, and VIN_UV_FAULT_LIMIT sets the voltage where power conversion is stopped.

Voltage Tracking

Each voltage rail can be configured to operate in a tracking mode. When a voltage rail is configured to track another voltage rail, it adjusts the setpoint to follow the master, which can be either another internal rail or the external Vtrack pin. As in standard non-tracking mode, a target Vout is still specified for the voltage rail. If the tracking input exceeds this target, the tracking voltage rail stops following the master signal, switch to regulation gains, and regulate at the target voltage. When the tracking input drops back below the target (with 20 mV of hysteresis), tracking gains is re-loaded, and the voltage rail follows the tracking reference. Note that the target can be set above the range of the tracking input, forcing the voltage rail to always remain in tracking mode.

During tracking, the setpoint DAC is permitted to change only as fast as is possible without inducing the EADC to saturate. This limit may be reached if the master ramps at an extremely fast rate, or if the master is at a significantly different voltage when the rail is turned on. As in normal regulation, a current limit (current foldback) or the detection of the EADC saturating forces the rail to temporarily deviate from the tracking reference.

The PMBus command TRACKING_SOURCE is available to enable tracking mode and select the master to track. The tracking mode is set individually for each rail, allowing each rail to have a different master, multiple rails to share a master, or some rails to track while others remain independent. Additionally, TRACKING_SCALE_MONITOR permits tracking at voltage with a fixed ratio to a master voltage. For example, a ratio of 0.5 causes the rail to regulate at one half of the master ’ s voltage.

Sequencing

There are three methods to squence voltage rails controlled by the UCD9240 that allow for a variety of system sequencing configurations. Each of these options is configurable in the GUI. These methods include:

1. Use the PMBus to set the soft start/stop parameters for each rail. Multiple start/stop sequences may be triggered simultaneously. Each voltage rail performs its sequencing in an open-loop manner. If any rail fails to complete its sequence, all other rails are unaffected.

2. Daisy-chain the Power Good output signal from one controller to the PMBus-CTRL input on another.

3. Use the GPIO_SEQ_CONFIG command to assign dependencies between rails, or to configure unused pins as sequencing control inputs or sequencing status outputs.

Method 1: Each rail has programmable delay times, TON_DELAY and TOFF_DELAY, before beginning a soft start ramp or a soft stop ramp, and programmable ramp times, TON_RISE and TOFF_FALL determine how long the ramp takes. These PMBus commands are defined in the UCD92xx PMBUS Command Reference. The parameters can also be configured using the Fusion Digital Power™ Designer GUI (see

http://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html ). The configurable times can be

used to program a time based sequence for each voltage rail. Using this method each rail ramps independently and completes the ramp regardless of the success of the other rails.

The start/stop sequence is initiated for a single rail by the PMBus-CTRL pin or via the PMBus using the OPERATION or ON_OFF_CONTROL commands.

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The start/stop sequence may be initiated simultaneously for multiple rails within the same controller by configuring each rail to respond to the PMBus-CTRL pin. Alternatively, after setting the PMBus PAGE variable to 255, subsequent OPERATION or ON_OFF_CONTROL commands applies to all rails at the same time.

To simultaneously initiate start/stop sequences in multiple controllers, a common PMBus-CTRL signal can be fed into each controller. Alternatively, the PMBus Group Command Protocol may be used to send separate commands to multiple controllers. All the commands are sent in one continuous transmission and wait for the final STOP signal in order to start executing their commands simultaneously.

Method 2: The Power Good pin can be used to coordinate multiple controllers by running the Power Good pin output from one controller to the PMBus-CTRL input pin of another. This imposes a master/slave relationship between multiple devices. During startup, the slave controllers initiates their start sequences after the master completes its start sequence and reaches its regulation voltage. During shut-down, as soon as the master starts its shut-down sequence, the shut-down signals to its slaves.

Unlike Method 1, a shut-down on one or more rails on the master can initiate shut-downs of the slave devices. The master shut-downs can initiate intentionally or by a fault condition.

The PMBus specification implies that the Power Good signal is active when ALL the rails in a controller are above their power-good “ on ” threshold setting. The UCD9240 allows the Power Good pin to be reprogrammed using the GPIO_SEQ_CONFIG command so that the pin responds to a desired subset of rails.

This method works to coordinate multiple controllers, but it does not enforce interdependency between rails within a single controller.

Method 3: Using the GPIO_SEQ_CONFIG command, several sequencing options can be configured using undedicated pins for input/output. As many as four pins can be configured as inputs, and as many as eight as outputs. The outputs can be open-drain or actively driven with selectable polarity.

Each rail can be configured to respond to a combination of the power-good status of other internal rails and/or the state of sequencing input pins. The output pins can be configured to reflect the power-good status of a combination of rails, or to one of several status indicators including power-good, an Overcurrent warning, or the “ open-drain outputs valid ” signal.

When using the output signals for sequencing, they may be routed to sequencing control inputs or to the PMBus-CTRL inputs on other controllers.

Once each rail ’ s input dependencies are configured, the rail responds to those input pins or internal rails. Like method 2, shut-downs on one rail or controller can initiate shut-downs of other rails or controllers. Unlike method 2, GPIO_SEQ_CONFIG offers much more flexibility in assigning relationships between multiple rails within a single controller or between multiple controllers. It is possible for each controller to be both a master and a slave to another controller.

GPIO_SEQ_CONFIG allows the configuration of fault relationships such that a fault on one rail can result in the shut down of any selection of rails in addition to the rail at fault. These fault interactions are not constrained to a single master/slave relationship; for example, a system can be configured such that a fault on any rail shuts down all rails. If the fault response of the failing rail is to shut down immediately, all dependent rails follow suit and shuts down immediately regardless of their programmed response code.

Each rail can be optionally configured to monitor a sequencing input pin for a specified period of time after it turns on and reaches its power good threshold. If the programmable timeout is reached before the input pin state matches its defined logic level, the rail is shut down, and a status error posted. This feature could be used, for example, to ensure that an LDO on the board did turn on when the main system voltage came up. Each rail is enabled independently of the other rails and has a unique timeout value; a single input pin is used as the timeout source.

The setup of the GPIO_SEQ_CONFIG command is aided by the use of the Fusion Digital Power™ Designer, which graphically displays relationships between rails and provides intuitive controls to allocate and configure available resources.

The following pins are available for use as GPIO or sequencing control, provided they are not being used for their primary purpose:

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PIN NAME 80-PIN 64-PIN

DPWM-1A IN/OUT IN/OUT DPWM-1B IN/OUT IN/OUT DPWM-2A IN/OUT IN/OUT DPWM-2B IN/OUT IN/OUT DPWM-3A IN/OUT IN/OUT DPWM-3B IN/OUT – DPWM-4A IN/OUT IN/OUT DPWM-4B IN/OUT –

FAULT-1A IN/OUT IN/OUT FAULT-1B IN/OUT IN/OUT FAULT-2A IN/OUT IN/OUT FAULT-2B IN/OUT IN/OUT FAULT-3A IN/OUT IN/OUT FAULT-3B IN/OUT – FAULT-4A IN/OUT IN/OUT FAULT-4B IN/OUT –

SRE-1A IN/OUT IN/OUT SRE-1B IN/OUT IN/OUT SRE-2A IN/OUT IN/OUT SRE-2B IN/OUT IN/OUT SRE-3A IN/OUT IN/OUT SRE-3B IN/OUT – SRE-4A IN/OUT IN/OUT SRE-4B IN/OUT – POWER_GOOD IN/OUT IN/OUT FAN_TACH IN/OUT IN/OUT FAN_PWM IN DIAG_LED IN

(1) The FAN_PWM and Diag_LED pins are outputs when configured for their primary purpose. When

configured for sequencing, they may be used only as inputs.

(1) (1)

(1)

IN

–

Fan Control

The UCD9240 can control one fan as defined in the PMBus standard. When enabled, the FAN-PWM control output provides a 156 kHz digital signal, with a duty cycle that is set based on the FAN_COMMAND_1 PMBus command. The duty cycle can be set from 0% to 100% with 1% resolution.

The FAN-TACH input counts the number of transitions in the tachometer output from the fan in each 1 second interval. The fan speed may be read by issuing the READ_FAN_SPEED_1 command. The speed is returned in RPMs.

Different fans may output from one to four tachometer pulses per revolution. The FAN_CONFIG_1_2 command is used to set the number of tachometer pulses per revolution. The same command is used to indicate whether a fan is attached.

The UCD9240 can report fan speed faults when the fan speed is too slow for 5 consecutive seconds. The fan speed fault limit is set by the FAN_SPEED_FAULT_LIMIT command. The status is checked by issuing the STATUS_FAN_1_2 command. See the UCD92xx PMBUS Command Reference for a complete description of each command.

Product Folder Link(s): UCD9240

+

1k31k0

1u

FAN-PWM

FAN-TACH

12V

FAN

33k2

0.1u

TIP31A

TS321

10k0

3.3V

UCD9240

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Figure 14. Example Fan Control Circuit

Non-volatile Memory Error Correction Coding

The UCD9240 uses Error Correcting Code (ECC) to improve data integrity and provide high reliability storage of Data Flash contents. ECC uses dedicated hardware to generate extra check bits for the user data as it is written into the Flash memory. This adds an additional six bits to each 32-bit memory word stored into the Flash array. These extra check bits, along with the hardware ECC algorithm, allow for any single bit error to be detected and corrected when the Data Flash is read.

APPLICATION INFORMATION

Calculation of Open Loop Gain Using the UCD9240

When designing a power supply it is necessary to determine the stability of the closed loop system. The usual way to do this is to determine the open loop gain versus frequency and from the open loop gain determine the gain margin and phase margin. Figure 15 shows a block diagram of a complete control loop using the UDC9240. Each component of the loop gain that is a function of frequency is labeled "Gx". Constant gain components are labeled "Kx".

CONSTANT GAIN COMPONENTS DESCRIPTION

G

plant

G

div

K

AFE

K

EADC

G

delay

Knonlinear Nonlinear function gain. Gain for the limit interval that contains zero error.

G

CLA2

G

CLA1

K

PWM

Transfer function for the power stage circuit consisting of the FET switches, LC output filter and load.

Transfer function for the VOUT sense divider and its capacitive filter network. Analog fron-end amplifier gain. Gain of the 6-bit EADC in units of LSBs/V Phase shift due to the delays in the control loop.

Transfer function of the second order filter section of the compensator. Transfer function of the first order filter section of the compensator. Accounts for the bit resolution of the input to the DPWM

Product Folder Link(s): UCD9240

Power Stage

Gplant(f)

Gdiv(f)

K

AFE

K

EADC

K

nonlinear

G

CLA2

G

CLA1

K

PWM

+

Vout

Vin

G

delay

V

ref

DAC

divider

UCD9240

CPU

PMBus

Power Stage

Vout

divider

R

1

R

2

C

2

EAn

EAp

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

Figure 15. Loop Gain Contributions

Several of the gain blocks are programmable. They are configured by issuing a CLA_GAINS command over the PMBus. The syntax for this command is shown in the UCD92xx PMBUS Command Reference. These gains can also be configured using the Fusion Digital Power™ Designer PC program.

Automatic System Identification ( Auto-ID™)

By using digital circuits to create the control function for a switch-mode power supply, additional features can be implemented. One of those features is the measurement of the open loop gain and stability margin of the power supply without the use of external test equipment. This capability is called automatic system identification or Auto-ID™. To identify the frequency response, the UCD9240 internally synthesizes a sine wave signal and injects it into the loop at the set point DAC. This signal excites the system, and the closed-loop response to that excitation can be measured at another point in the loop. The UCD9240 measures the response to the excitation at the output of the digital compensator. From the closed-loop response, the open-loop transfer function is calculated. The open-loop transfer function may be calculated from the closed-loop response.

Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can be divided out of the measured open-loop gain. In this way the UCD9240 can accurately measure the power stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and send the measurement data back to a host through the PMBus interface without the need for external test equipment. Details of the Auto-ID™ PMBus measurement commands can be found in the UCD92xx PMBus Command Reference.

EAp/EAn Voltage Sense Filtering

Conditioning should be provided on the EAp and EAn signals. Figure 16 shows a divider network between the output voltage and the voltage sense input to the controller. The resistor divider is used to bring the output voltage within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the signal conditioned by the low-pass filter formed by R1 and C2.

Figure 16. EAp/EAn Input Network

Product Folder Link(s): UCD9240

1 2

1

= = = =

- +

P P EA

P

OU T

R R V R R

R R where K and R

K K V R R

2

1

2 0.35p=´ ´ ´

SW P

C

F R

UCD9240

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As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly across an output capacitor, and route the positive and negative differential sense signals as a balanced pair of traces or as a twisted pair cable back to the controller. Put the divider network close to the controller. This ensures that there is a low impedance driving the differential voltage sense signal from the voltage rail output back to the controller. The resistance of the divider network is a trade-off between power loss and minimizing interference susceptibility. A parallel resistance of 1k to 4k Ω is a good compromise.

It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter, the corner frequency should be 35% to 40% of the switching frequency. Then the capacitor is calculated as:

Current Sense Input FIltering

Each power stage current is monitored by the device at the CS pins. There are 4 "A" channel pins and 2 or 4 "B" channel pins (64 or 80 pin package). The B channels monitor the current with a 12-bit ADC and samples each current sense voltage in turn. The A channels monitor the current with the same12-bit ADC and also monitor the current with a digitally programmable analog comparator.

Because the current sense signal is digitally sampled, it should be conditioned with an RC network acting as an anti-alias filter. Since the sample rate for the CS inputs is 1/ TIout, a good cutoff frequency for the RC network is from 2 kHz to 3 kHz.

Output Voltage Margining

The UCD9240 supports Voltage Margining using the PMBus VOUT_MARGIN_HIGH and VOUT_MARGIN_LOW commands in conjunction with the OPERATION command. The margin voltages can be configured at device configuration and saved into Data Flash. The output can be commanded to switch between Margin High, Nominal, and Margin Low using bits [3:2] of the OPERATION command.

Calibration

To optimize the operation of the UCD9240, PMBus commands are supplied to enable fine calibration of output voltage, output current, and temperature measurements. The supported commands and related calibration formulas may be found in the UCD92xx PMBUS Command Reference.

Product Folder Link(s): UCD9240

PACKAGE OPTION ADDENDUM

www.ti.com

15-Sep-2008

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

UCD9240PFC ACTIVE TQFP PFC 80 96 Green (RoHS &

no Sb/Br)

UCD9240PFCR ACTIVE TQFP PFC 80 1000 Green (RoHS &

no Sb/Br) UCD9240RGCR PREVIEW VQFN RGC 64 2000 TBD Call TI Call TI UCD9240RGCT PREVIEW VQFN RGC 64 250 TBD Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

16-Aug-2008

*All dimensions are nominal

Device Package

Type

UCD9240PFCR TQFP PFC 80 1000 330.0 24.4 15.0 15.0 2.0 20.0 24.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

16-Aug-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

UCD9240PFCR TQFP PFC 80 1000 346.0 346.0 41.0

Pack Materials-Page 2

MECHANICAL DATA

MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996

PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK

80

61

1,05 0,95

0,50

60

0,27 0,17

41

1

9,50 TYP

12,20

SQ

11,80

14,20

SQ

13,80

20

0,08

21

40

M

0,13 NOM

Gage Plane

0,25

0,05 MIN

0,75 0,45

0°–7°

1,20 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

Seating Plane

0,08

4073177/B 11/96

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TEXAS INSTRUMENTS UCD9240 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

ADC MONITORING INTERVALS AND RESPONSE TIMES

HARDWARE FAULT DETECTION LATENCY

I2C/SMBus/PMBus Timing Characteristics

FUNCTIONAL BLOCK DIAGRAM

TYPICAL APPLICATION SCHEMATIC

FUNCTIONAL OVERVIEW

PMBus Interface

Resistor Programmed PMBus Address Decode

JTAG Interface

Bias Supply Generator (Series Regulator Controller)

Power On Reset

External Reset

Output Voltage Adjustment

Analog Front End (AFE)

Digital Compensator

DPWM Engine

Flexible Rail/Power Stage Configuration

DPWM Phase Distribution

DPWM Synchronization

Phase Shedding at Light Current Load

Phase Adding at Normal Current Load

Output Current Measurment

Output Current Balancing

Overcurrent Detection

Current Foldback Mode

Input Voltage and Current Monitoring

Temperature Monitoring

Temperature Balancing

Soft Start, Soft Stop Ramp Sequence

Input UV Lockout

Voltage Tracking

Sequencing

Fan Control

Non-volatile Memory Error Correction Coding

APPLICATION INFORMATION

Calculation of Open Loop Gain Using the UCD9240

EAp/EAn Voltage Sense Filtering

Current Sense Input FIltering

Output Voltage Margining

Calibration