TEXAS INSTRUMENTS UCD9240 Technical data

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

Digital PWM System Controller

1

FEATURES

2

• Fully Configurable Multi-Output and

Multi-Phase Non-Isolated DC/DC PWM Controller

• Controls Up To Four Voltage Rails and Up To

Eight Phases

• Supports Switching Frequencies Up to 2MHz

With 250 ps Duty-Cycle Resolution

• Up To 1mV Closed Loop Resolution

• Hardware-Accelerated, 3-Pole/3-Zero

Compensator With Non-Linear Gain for Improved Transient Performance

• Supports Multiple Soft-Start and Soft-Stop

Configurations Including Prebias Start-up

• Supports Voltage Tracking, Margining and

Sequencing

• Supports Current and Temperature Balancing

for Multi-Phase Power Stages

• Supports Phase Adding/Shedding for

Multi-Phase Power Stages

• Sync In /Out Pins Align DPWM Clocks

Between Multiple UCD9240 Devices

• Fan Monitoring and Control

• 12-Bit Digital Monitoring of Power Supply

Parameters Including: – Input Current and Voltage – Output Current and Voltage – Temperature at Each Power Stage

• Multiple Levels of Overcurrent Fault

Protection: – External Current Fault Inputs – Analog Comparators Monitor Current

Sense Voltage

– Current Continually Digitally Monitored

• Over and Undervoltage Fault Protection

• Overtemperature Fault Protection

• Enhanced Nonvolatile Memory With Error

Correction Code (ECC)

• Device Operates From a Single Supply With an

Internal Regulator Controller That Allows Operation Over a Wide Supply Voltage Range

• Supported by Fusion Digital Power™

Designer, a Full Featured PC Based Design Tool to Simulate, Configure, and Monitor Power Supply Performance.

APPLICATIONS

• Industrial/ATE

• Networking Equipment

• Telecommunications Equipment

• Servers

• Storage Systems

• FPGA, DSP and Memory Power

DESCRIPTION

The UCD9240 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop management with flash memory and a serial interface to support configurability, monitoring and management.

The UCD9240 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.

To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.

TI has also developed multiple complementary power stage solutions – from discrete drives in the UCD7k family to fully tested power train modules in the PTD family. These solutions have been developed to complement the UCD9k family of system power controllers.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

OPERATING

TEMPERATURE PIN COUNT SUPPLY PACKAGE

RANGE, T

-40 ° C to 110 ° C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ORDERABLE PART TOP SIDE

A

NUMBER MARKING

UCD9240PFCR 80-pin Reel of 1000 QFP UCD9240

UCD9240PFC 80-pin Tray of 119 QFP UCD9240

(1)

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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS

Voltage applied at V33D to DV Voltage applied at V33A to AV Voltage applied to any pin Storage temperature (T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS.

(2)

) – 40 to 150 ° C

STG

(1)

VALUE UNIT

SS

– 0.3 to 3.6 V – 0.3 to 3.6 V – 0.3 to 3.6 V

RECOMMENDED OPERATING CONDITIONS

Over operating free-air temperature range (unless otherwise noted).

MIN NOM MAX UNIT

V Supply voltage during operation, V33D, V33DIO, V33A 3 3.3 3.6 V T

A

T

J

Operating free-air temperature range – 40 110 ° C Junction temperature 125 ° C

Product Folder Link(s): UCD9240

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

ELECTRICAL CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

SUPPLY CURRENT

I

V33A

I

V33DIO

I

V33D

I

V33D

Supply current mA

INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS

V

V33

3.3-V linear regulator Emitter of NPN transistor 3.25 3.3 3.35 V33FB 3.3-V linear regulator feedback 4 4.6 I

V33FB

Series pass base drive V

Beta Series NPN pass device 40

EXTERNALLY SUPPLIED 3.3 V POWER

V

,

V33D

V

V33DION

V

V33A

Digital 3.3-V power T Analog 3.3-V power T

ERROR AMPLIFIER INPUTS EAPn, EANn

V

CM

V

ERROR

Common mode voltage each pin -0.15 1.6 V

Internal error Voltage range AFE_GAIN field of CLA_GAINS = 0 EAP-EAN Error voltage digital resolution AFE_GAIN field of CLA_Gains = 3 1 mV R

EA

I

OFFSET

Input Impedance Ground reference 0.5 1.5 3 M Ω

Input offset current 1 k Ω source impedence -5 5 µ A

ANALOG INPUTS CS, Vin, TEMP, PMBusADDR

I

BIAS

V

ADDR_OPEN

V

ADDR_SHORT

V

ADC_RANGE

V

OC_THRS

V

OC_RES

Bias current for PMBus Addr pins 9 11 µ A

Voltage indicating open pin AddrSens 0,1 open 2.47 V

Voltage indicating shorted pin AddrSense 0,1 short to ground 0.179 V

Measurment range for voltage

monitoring

Overcurrent comparator threshold

voltage range

Overcurrent comparator threshold

voltage range ADCREF External Reference input (80-pin package) 1.8 V33A V Temp

internal

Int. temperature sense accuracy Over range from 0 ° C to 100 ° C -5 5 ° C INL ADC integral nonlinearity -2.5 2.5 mV I

lkg

R

IN

C

IN

Input leakage current 3V applied to pin 100 nA

Input impedance Ground reference 8 M Ω

Current Sense Input capacitance 10 pF

(1) See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command.

V

= 3.3 V 8 15

V33A

V

= 3.3 V 2 10

V33DIO

V

= 3.3 V 40 45

V33D

V

= 3.3 V storing configuration

V33D

parameters in flash memory TBD

= 12 V 10 mA

VIN

A = 25 ° C

Inputs: VIn, V

(1)

, V

track

temp

3.13 3.47 V

-256 256 mV

50 55

CS-1A, CS-1B, CS-2A, CS-2B 0 2.5 V CS-3A, CS-3B, CS-4A, CS-4B

Inputs: CS-1A, CS-2A, CS-3A, CS-4A 0.032 2 V

Inputs: CS-1A, CS-2A, CS-3A, CS-4A 31.25 mV

V

Product Folder Link(s): UCD9240

UCD9240

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ELECTRICAL CHARACTERISTICS (continued)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

DIGITAL INPUTS/OUTPUTS

V

OL

V

OH

V

IH

V

IL

Low-level output voltage IOH= 6 mA

High-level output voltage IOH= -6 mA

High-level input voltage V

Low-level input voltage V

V33DIO V33DIO

(2)

, V

(3)

, V

= 3 V V

V33DIO

V

= 3 V V

V33DIO

33DIO

-0.6V = 3V 2.1 V = 3.5 V 1.1 V

FAN CONTROL INPUTS/OUTPUTS

T

PWM_PERIOD

DUTY

PWM

DUTY

RES

Tach

RANGE

Tach

RES

t

MIN

FAN-PWM period 156 kHz FAN-PWM duty cycle range 0% 100% Duty cycle resolution 1%

FAN-TACH range 30 300k RPM

For 1 Tach pulse per revolution. At 2,

3, or 4 pulse/rev, divide by that value FAN-TACH resolution For 1 Tach pulse per revolution 30 RPM FAN-TACH minimum pulse width Either positive or negative polarity 150 µ s

SYSTEM PERFORMANCE

V

commanded to be 1V, at 25 ° C

V

Ref

Setpoint Reference Accuracy -10 10 mV

Setpoint Reference Accuracy over temeprature

V

DiffOffset

t

Delay

F

SW

Differential offset between gain setetings

Digital Compensator Delay

(5)

Switching Frequency 15.260 2000 kHz

ref

AFEgain = 4, 1V input to EAP/N

measured at output of the EADC

(4)

-40 ° C to 125 ° C -20 20 mV

AFEgain = 4 compared to

AFEgain = 1, 2, or 8

-4 4 mV

(6)

208

Duty Max and Min Duty Cycle Configured via PMBus 0% 100% VDDSlew Minimum V t

retention

Write_Cycles TJ= 25 ° C 20 K cycles

Retention of configuration parameters TJ= 25 ° C 100 Years Number of nonvolatile erase/write

cycles

slew rate V

DD

slew rate between 2.3V and 2.9V 0.25 V/ms

DD

(2) The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop

specified.

(3) The maximum total current current, IOHmax and IOLmax, for all outputs combined, should not exceed 48 mA to hold the maximum

voltage drop specified. (4) With default device caliibration. PMBus calibration can be used to improve the regulation tolerance. (5) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay must be

accounted for when calculating the system dynamic response. (6) The PMBus command: EADC_SAMPLE_TRIGGER defines the start of the 32ns ADC sample window. So the minimum

EAD_SAMPLE_TRIGGER time is 208 + 32 = 240 ns.

Dgnd

+0.25

ns

Product Folder Link(s): UCD9240

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

ADC MONITORING INTERVALS AND RESPONSE TIMES

The ADC operates in a continuous conversion sequence that measures each rail ' s output voltage, each power stage ' s ouput current, plus four other variables (external temperature, Internal temperature, input voltage and current, and tracking input voltage). The length of the sequence is determined by the number of output rails (NumRails) and total output power stages (NumPhases) configured for use. The time to complete the monitoring sampling sequence is give by the formula:

t

ADC_SEQ

t

ADC

t

ADC_Seq

The most recent ADC conversion results are periodically converted into the proper measurement units (volts, amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The monitoring operates asynchronously to the ADC, at intervals shown in the table below.

t

Vout

t

Iout

t

Vin

t

Iin

t

TEMP

t

Ibal

t

FanTach

Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC sequence interval. Once a fault condition is detected, some additional time is required to determine the correct action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following table lists the worse-case fault response times.

t

, t

OVF

UVF

t

, t

OVF

UVF

t

, t

OVF

UVF

t

, t

OCF

UCF

t

, t

OCF

UCF

t

, t

OCF

UCF

t

OTF

(1) During a STORE_DEFAULT_ALL command, which stores the entire configuration to nonvolatile memory, the fault detection latency can

be up to 10 ms. (2) Because the current measurement is averaged with a smoothing filter, the response time to an Overcurrent condition depends on a

combination of the time constant ( τ ) from Table 4 , the recent measurement history, and how much the measured value exceeds the

overcurrent limit.

= t

× (NumRAILS + NumPHASE + 4)

ADC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC single-sample time 3.89 µ s

Min = 1 Rail + 1 Phase = 4 = 6

ADC sequencer interval 27.75 74 µ s

samples Max = 4 Rails + 8 Phases + 4 = 16

samples

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage monitoring interval 200 µ s Output current monitoring interval µ s

200 ×

N

Rails

Input voltage monitoring interval 2 ms Input current monitoring interval 2 ms Temeprature monitoring interval 800 ms Output current balancing interval 2 ms Fan speed monitoring interval 1000 ms

PARAMETER TEST CONDITIONS MAX TIME UNIT

Over/under voltage fault response time during Normal regulation, no PMBus activity, normal operation 8 stages enabled

Over/under voltage fault response time, during data During data logging to nonvolatile logging memory

Over/under voltage fault response time, when tracking or sequencing enable

Over/under current fault response time during normal operation N

Over/under current fault response time, during data 600 + (600 x logging N

(1)

During tracking and soft-start ramp. 400 µ s Normal regulation, no PMBus activity,

8 stages enabled µ s 75% to 125% current step

During data logging to nonvolatile memory µ s 75% to 125% current step

300 µ s

800 µ s

(2)

100 + (600 x

)

Rails

)

Rails

Over/under current fault response time, when During tracking and soft start ramp 300 + (600 x tracking or sequencing enable 75% to 125% current step N

Overtemperature fault response time 5 s

Temperature rise of 10 ° C/sec, OT threshold = 100 ° C

)

Rails

µ s

Product Folder Link(s): UCD9240

UCD9240

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HARDWARE FAULT DETECTION LATENCY

The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.

PARAMETER TEST CONDITIONS MAX TIME UNIT

t

FAULT

t

CLF-A

t

CLF-B

PMBUS/SMBUS/I

Time to disable DPWM output base on active FAULT pin signal

High level on FAULT pin µ s

Time to disable the DPWM A output based on internal Step change in CS voltage from 0v to Switch analog comparator 2.5V Cycles

Time to disable all remaining DPWM and SRE outputs configured to drive a voltage rail after a CLF-A event µ s occurs

2

C

Step change in CS voltage from 0V to

2.5V

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus are shown below.

I2C/SMBus/PMBus Timing Characteristics

TA= – 40 ° C to 85 ° C, 3V < V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

SMB

f

I2C

t

(BUF)

t

(HD:STA)

t

(SU:STA)

t

(SU:STO)

t

(HD:DAT)

t

(SU:DAT)

t

(TIMEOUT)

t

(LOW)

t

(HIGH)

t

(LOW:SEXT)

t

FALL

t

RISE

(1) The UCD9240 times out when any clock low exceeds t (2) t

(HIGH)

in progress. This specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0]=0). (3) t

(LOW:SEXT)

(4) Rise time t (5) Fall time t

SMBus/PMBus operating frequency Slave mode; SMBC 50% duty cycle 10 1000 kHz I C operating frequency Slave mode; SCL 50% duty cycle 10 1000 kHz

Bus free time between start and stop 4.7 µ s Hold time after (repeated) start 0.26 µ s Repeated start setup timed 0.26 µ s Stop setup time 0.26 µ s Data hold time Receive mode 0 ns Data setup time 50 ns Error signal/detect See Clock low period 0.5 µ s Clock high period See Cumulative clock low slave extend time See Clock/data fall time See Clock/data rise time See

, max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9110 that is

is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

= V

RISE

VILMAX

= 0.9 V

FALL

< 3.6V, typical values at TA= 25 ° C and V

DD

(TIMEOUT)

to (VILMAX – 0.15)

DD

– 0.15) to (V

+ 0.15)

VIHMIN

= 2.5 V (Unless otherwise noted)

CC

(1)

(2) (3) (4) (5)

.

15 + 3 ×

NumPhases

4

10 + 3 ×

NumPhases

35 µ s

0.26 50 µ s 25 µ s

120 ns 120 ns

Product Folder Link(s): UCD9240

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

The coefficients of the filter sections are generated through modeling the power stage and load in the Power+ Designer tool. Several banks of filter coefficients can be downloaded to the device that can automatically switch them based on the power stage operation.

Figure 1. I2C/SMBus/PMBus Timing in Extended Mode Diagram

Product Folder Link(s): UCD9240

Compensator

3P/3Z IIR

12-bit

ADC

250 ksps

Osc

ARM-7 core

PMBus

EAp4

EAn4

EAp3

EAn3

EAp2

EAn2

AddrSens0 AddrSens1

CS-1A CS-1B CS-2A CS-2B CS-3A CS-3B CS-4A CS-4B Vin/Iin Vtrack

Temp

V33x

xGnd

Analog Front End

(AFE)

Analog Front End

(AFE)

Analog Front End

(AFE)

Ref

ADC 6 bit

IIR

3P/3Z

Err

Amp

EAp1

EAn1

Coeff.

Regs

CompensatorAnalog Front End

ADCref

POR/BOR

DPWM-1A

Ref 1

Analog Comparators

OC PWM-1A

DPWM-1B

FAULT-1A FAULT-1B

DPWM-2A DPWM-2B

FAULT-2A FAULT-2B

DPWM-3A DPWM-3B

FAULT-3A FAULT-3B

DPWM-4A DPWM-4B

FAULT-4A FAULT-4B

PMBus-Clk PMBus-Data PMBus-Alert PMBus-Cntl PowerGood (TMS)

SYNC-IN (TDI) SYNC -OUT (TDO)

5

6

BPCap

SRE-4B SRE-4A SRE-3B SRE-3A SRE-2B SRE-2A SRE-1B SRE-1A

SRE

Control

Compensator

3P/3Z IIR

Compensator

3P/3Z IIR

Flash

Memory with

ECC

Diff

Amp

Fusion Power Peripheral 4

Fusion Power Peripheral 3

Fusion Power Peripheral 2

Fusion Power Peripheral 1

Internal

Temp Sense

3.3V reg.

controller

& 1.8V

regulator

Ref 2

Ref 3

Ref 4

Digital

High Res

PWM

Digital

High Res

PWM

Digital

High Res

PWM

Digital

High Res

PWM

Mux

Control

TMUX0 TMUX1 TMUX2

OC PWM-2A

OC PWM-3A

OC PWM-4A

Fan

Control

FAN-TACH (TCK) FAN-PWM

/RESET

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

FUNCTIONAL BLOCK DIAGRAM

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Product Folder Link(s): UCD9240

58

46

45

7

44

47

9

62 63

64 65 66

67 68

69

EAp1 EAn1

EAp2 EAn2

EAp3 EAn3 EAp4

EAn4

AddrSen0 AddrSen1

CS-1A (COMP1) CS-2A (COMP2)

CS-3A (COMP3) CS-4A (COMP4)

CS-1B CS-2B

CS-3B CS-4B Vin/Iin

Vtrack Temp

Aux-in (AD13) Aux-in (AD14) ADCref

77 76

75

4 3

2

79 78 74

73

5 6

7

72 71

1

DPWM-1A DPWM-1B

DPWM-2A DPWM-2B DPWM-3A

DPWM-3B DPWM-4A

DPWM-4B

21 22 23

24 25

26 27 28

SRE-1A SRE-1B SRE-2A

SRE-2B SRE-3A

SRE-3B SRE-4A SRE-4B

FAULT-1A FAULT-1B

FAULT-2A FAULT-2B

FAULT-3A FAULT-3B

FAULT-4A FAULT-4B

12 11

51 37

38 52

33 50

PMBus-Clk PMBus-Data

PMBus-Alert PMBus-Ctrl

PowerGood

19 20

35 36 49

V33FB

V33A

V33D

V33DIO-1

V33DIO-2

BPCa p

70

58

57

8

56

59

A -1

VSS

A -2

VSS

A

-3

VSS

D -1

VSS

D

-2

VSS

D -3

VSS

61

60

80

9

34

55

/RESET

13

48 47 46

45 44

14

15 16

17 18

29 41 42

43

TMUX-0 TMUX-1

TMUX-2

39 40

54

SYNC-IN

SYNC-OUT

FAN-PWM

FAN-TACH

DiagLED

31 30

53 32 10

UCD9240-64pin UCD9240-80pin

50 51

52 53 54

55 56

57

EAp1 EAn1

EAp2 EAn2

EAp3 EAn3 EAp4

EAn4

AddrSens0 AddrSens1

CS-1A (COMP1) CS-2A (COMP2)

CS-3A (COMP3) CS-4A (COMP4)

CS-1B CS-2B

Vin/Iin Vtrack Temp

61 60

59

3 2

1

63 62

4 5

6

DPWM-1A DPWM-1B

DPWM-2A DPWM-2B DPWM-3A

DPWM-4A

17 18 19

20 21

23

SRE-1A SRE-1B

SRE-2A SRE-2B

SRE-3A SRE-4A

FAULT-1A FAULT-1B

FAULT-2A FAULT-2B

FAULT-3A FAULT-4A

22 24

33 35 29

30

PMBus-Clk PMBus-Data

PMBus-Alert PMBus-Ctrl

PowerGood (TMS)

15 16

27 28

39

V33FB

V33A

V33D

V33DIO-1

V33DIO-2

BPCa p

A -1

VSS

A -2

VSS

A -3

VSS

D

-1

VSS

D -2

VSS

D

-3

VSS

49

48

64

8

26

43

/RESET

9

/TRST

TRCK

40 10

11 12

13 14

25 34

TMUX-0 TMUX-1 TMUX-2

31 32

42

FAN-PWM

FAN-TACH (TCK)

SYNC-IN (TDI)

SYNC-OUT (TDO)

41 36

38 37

/TRST

TMS

TDI

TDO TCK

TRCK

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

The UCD9240 is available in a plastic 64-pin QFN package (RGC) and an 80-pin TQFP package (PFC).

Figure 2. UCD9240 Pin Assignment

Product Folder Link(s): UCD9240

Commutation

logic

FLT

PWM

SRE

CS

PTD08A020W

50 51 52 53 54 55 56 57

EAp1 EAn1 EAp2 EAn2 EAp3 EAn3 EAp4 EAn4

AddrSens0 AddrSens1 CS-1A (COMP1) CS-2A (COMP2) CS-3A (COMP3) CS-4A (COMP4) CS-1B CS-2B Vin/Iin Vtrack Temp

61 60 59

3 2

1 63 62

4

5

6

DPWM-1A DPWM-1B DPWM-2A DPWM-2B DPWM-3A DPWM-4A

17 18 19 20 21 23

SRE-1A SRE-1B SRE-2A SRE-2B SRE-3A SRE-4A

FAULT-1A FAULT-1B FAULT-2A FAULT-2B FAULT-3A FAULT-4A

22 24 33 35 29 30

PMBus-Clk PMBus-Data PMBus-Alert PMBus-Ctrl PowerGood (TMS)

15 16 27 28 39

V33FB

V33A

V33D

V33DIO-1

V33DIO-2

BPCap

584645744

47

Agnd-1

Agnd-2

Agnd-3

Dgnd-1

Dgnd-2

Dgnd-3

494864826

43

/RESET

9

SYNC-IN (TDI)

SYNC-OUT (TDO)

38 37

11 12 13 14 25 34

TMUX-0 TMUX-1 TMUX-2

31 32 42

FLT

PWM

SRE

CS

UCD72xx Driver

PTD08A010W

FLT

PWM

SRE

CS

PTD08A010W

FLT

PWM

SRE

CS

PTD08A010W

FLT

PWM

SRE

CS

PTD08A010W

FLT

PWM

SRE

CS

+Vsens-rail4

-Vsens-rail4

+Vsens-rail1

-Vsens-rail1

+Vsens-rail2

-Vsens-rail2

+Vsens-rail3

-Vsens-rail3

+Vsens-rail1

-Vsens-rail1

+Vsens-rail2

-Vsens-rail2

+Vsens-rail3

-Vsens-rail3

+Vsens-rail4

-Vsens-rail4

Vin

TLV1117-ADJ

VoutVin

+8V

Sync-in Sync-out

CD74HC4051

Temp-rail1A Temp-rail1B Temp-rail2A Temp-rail2B Temp-rail3A Temp-rail4A

13 14 15 12

1

5

2

4

+3.3V

Com

S2 S1 S0

-EN

+3.3V

CS-rail2B

CS-rail2A

CS-rail3A

CS-rail4A

CS-rail1A

CS-rail1A CS-rail2A CS-rail3A CS-rail4A CS-rail1B CS-rail2B

Vtrack

FCX491A

A0 A1 A2 A3 A4 A5 A6 A7

FAN-PWM

FAN-TACH (TCK)

41 36

FAN-PWM FAN-Tach

CS-rail1B

temp

sensor

Temp-rail1A

Temp-rail1B

Temp-rail2A

Temp-rail2B

Temp-rail3A

Temp-rail4A

82.5k

15k

0.1u

10k

4.7u

0.1u

10u

1.10k

5.49k

4.7u

40 10

/TRST

RCK

10k

3

9 10 11 6

16

8

10k

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

TYPICAL APPLICATION SCHEMATIC

Figure 3 shows the UCD9240 power supply controller as part of a system that provides the regulation of four

independent power supplies. The loop for each power supply is created by the respective voltage outputs feeding into the differential voltage error ADC (EADC) inputs, and completed by DPWM outputs feeding into the gate drivers for each power stage.

The ± V configured as part of the rail. (See more detail on page 19, " Flexible Rail/Power Stage Configuration " .)

rail signals must be routed to the EAp/EAn input that matches the number of the lowest DPWM

sense

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Figure 3. Typical Application Schematic

Product Folder Link(s): UCD9240

UCD9240

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......................................................................................................................................................... SLUS766B – JULY 2008 – REVISED AUGUST 2008

PIN DESCRIPTIONS

64-PIN PACKAGE 80-PIN PACKAGE

PIN NO. SIGNAL PIN NO. SIGNAL

50 EAp1 62 EAp1 AI Error analog, differential voltage. Positive channel #1 input. 51 EAn1 63 EAn1 AI Error analog, differential voltage. Negative channel #1 input. 52 EAp2 64 EAp2 AI Error analog, differential voltage. Positive channel #2 input. 53 EAn2 65 EAn2 AI Error analog, differential voltage. Negative channel #2 input. 54 EAp3 66 EAp3 AI Error analog, differential voltage. Positive channel #3 input. 55 EAn3 67 EAn3 AI Error analog, differential voltage. Negative channel #3 input. 56 EAp4 68 EAp4 AI Error analog, differential voltage. Positive channel #4 input. 57 EAN4 69 EAn4 AI Error analog, differential voltage. Negative channel #4 input.

61 AddrSens0 77 AddrSens0 AI PMBus address sense. Least significant address bits 60 AddrSens1 76 AddrSens1 AI PMBus address sense. Most significant address bits 59 CS-1A 75 CS-1A AI Power stage 1A current sense input. Analog comparator 1

3 CS-2A 4 CS-2A AI Power stage 2A current sense input. Analog comparator 2 2 CS-3A 3 CS-3A AI Power stage 3A current sense input. Analog comparator 3

1 CS-4A 2 CS-4A AI Power stage 4A current sense input. Analog comparator 4 63 CS-1B 79 CS-1B AI Power stage 1B current sense input 62 CS-2B 78 CS-2B AI Power stage 2B current sense input

– CS-3B 74 CS-3B AI Power stage 3B current sense input

– CS-4B 73 CS-4B AI Power stage 4B current sense input

4 Vin/ I

in

5 Vin/ I

in

5 VTRACK 6 VTRACK AI Voltage tracking

6 Temp 7 Temp AI Temperature sense input

Aux-in Aux-in

– 72 AI Unused analog input -- Tie to ground with 10 k Ω resistor

(AD13) (AD13) Aux-in Aux-in

– 71 AI Unused analog input -- Tie to ground with 10 k Ω reisistor

(AD14) (AD14)

– ADCref 1 ADCref AI ADC Decoupling Capacitor -- Tie 0.1 µ F cap to ground

I/O DESCRIPTION

Error Amplifier Differential Analog Inputs

Analog Inputs

AI Input supply sense, alternates between Vinand I

in

Digital PWM Outputs

17 dPWM-1A 21 dPWM-1A O DPWM 1A output 18 dPWM-1B 22 dPWM-1B O DPWM 1B output 19 dPWM-2A 23 dPWM-2A O DPWM 2A output 20 dPWM-2B 24 dPWM-2B O DPWM 2B output 21 dPWM-3A 25 dPWM-3A O DPWM 3A output

26 dPWM-3B O DPWM 3B output

23 dPWM-4A 27 dPWM-4A O DPWM 4A output

28 dPWM-4B O DPWM 4B output

External Fault Inputs

11 FAULT-1A 15 FAULT-1A I External fault input 1A 12 FAULT-1B 16 FAULT-1B I External fault input 1B 13 FAULT-2A 17 FAULT-2A I External fault input 2A 14 FAULT-2B 18 FAULT-2B I External fault input 2B 25 FAULT-3A 29 FAULT-3A I External fault input 3A

41 FAULT-3B I External fault input 3B

34 FAULT-4A 42 FAULT-4A I External fault input 4A

43 FAULT-4B I External fault input 4B

Product Folder Link(s): UCD9240

UCD9240

SLUS766B – JULY 2008 – REVISED AUGUST 2008 .........................................................................................................................................................

PIN DESCRIPTIONS (continued)

64-PIN PACKAGE 80-PIN PACKAGE

PIN NO. SIGNAL PIN NO. SIGNAL

22 SRE-1A 12 SRE-1A O Synchronous rectifier enable 1A 24 SRE-1B 11 SRE-1B O Synchronous rectifier enable 1B 33 SRE-2A 51 SRE-2A O Synchronous rectifier enable 2A 35 SRE-2B 37 SRE-2B O Synchronous rectifier enable 2B 29 SRE-3A 38 SRE-3A O Synchronous rectifier enable 3A

52 SRE-3B O Synchronous rectifier enable 3B

30 SRE-4A 33 SRE-4A O Synchronous rectifier enable 4A

50 SRE-4B O Synchronous rectifier enable 4B

31 TMUX-0 39 TMUX-0 O Temperature multiplexer select S0

9 RESET 13 RESET I Active low device reset input 32 TMUX-1 40 TMUX-1 O Temperature multiplexer select S1 42 TMUX-2 54 TMUX-2 O Temperature multiplexer select S2 41 FAN-PWM 53 FAN-PWM O Fan control PWM output 39 PowerGood 49 PowerGood O Power good signal (multiplexed with TMS on 64-pin package) 36 FAN-Tach 32 FAN-Tach I Fan tachometer input (multiplexed with TCK on 64-pin package)

37 Sync_Out 30 Sync_Out O 38 Sync_In 31 Sync_In I Synchronization input to DPWM (multiplexed with TDI on 64-pin package)

10 diag LED O Diagnostic LED

I/O DESCRIPTION

Synchronous Rectification Enable Outputs

Miscellaneous Digital I/O

Synchronization output from DPWM (multiplexed with TDO on 64-pin package)

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PMBus Communications Interface

15 PMBus_Clk 19 PMBus_Clk I/O PMBus Clk (Must have pullup to 3.3 V) 16 PMBus_Data 20 PMBus_Data I/O PMBus Data (Must have pullup to 3.3 V) 27 PMBus_Alert 35 PMBus_Alert O PMBUS Alert 28 PMBus_Cntrl 36 PMBus_Cntrl I PMBUS Cntl

JTAG

10 TRCK 14 TRCK O Test return clock 36 TCK 44 TCK I Test clock (multiplexed with FAN-Tach (TCK) on 64-pin package) 37 TDO 45 TDO O Test data out (multiplexed with Sync_Out (TDO) on 64-pin package)

38 TDI 46 TDI I

39 TMS 47 TMS I/O

Test data in -- tie to Vdd with 10 k Ω resistor (multiplexed with Sync_In (TDI) on 64-pin package)

Test mode select -- tie to Vdd with 10 k Ω resistor (multiplexed with PowerGood (TMS) on 64-pin package)

40 TRST 48 TRST I/O Test reset -- tie to ground with 10 k Ω resistor

Input Power and Grounds

58 V33FB 70 V33FB I 3.3-V linear regulatorfFeedback connection 46 V33A 58 V33A I Analog 3.3-V supply 45 V33D 57 V33D I Digital core 3.3-V supply

7 V33DIO 8 V33DIO I Digital I/O 3.3-V supply 44 V33DIO 56 V33DIO I Digital I/O 3.3-V supply 47 BPCap 59 BPCap I 1.8-V bypass capacitor connection 49 AV 48 AV 64 AV

SS SS SS

61 AV 60 AV 80 AV

SS SS SS

I Analog ground I Analog ground I Analog ground

Product Folder Link(s): UCD9240