TEXAS INSTRUMENTS UCD9224 Technical data

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UCD9224

SLVSA35 –JANUARY 2010

Digital PWM System Controller

FEATURES

• Fully Configurable Multi-Output and Multi-

Tool to Simulate, Configure, and Monitor Power Supply Performance

Phase Non-Isolated DC/DC PWM Controller

• Controls Up to 2 Voltage Rails and Up to 4 Phases

• Supports Switching Frequencies Up to 2MHz with 250 ps Duty-Cycle Resolution

• Up To 1mV Closed Loop Resolution

• Hardware-Accelerated, 3-Pole/3-Zero Compensator with Non-Linear Gain for

APPLICATIONS

• Industrial/ATE

• Networking Equipment

• Telecommunications Equipment

• Servers

• Storage Systems

• FPGA, DSP and Memory Power

Improved Transient Performance

• Supports Multiple Soft-Start and Soft-Stop Configurations Including Prebias Start-up

• Supports Voltage Tracking, Margining and Sequencing

• Supports Current and Temperature Balancing for Multi-Phase Power Stages

• Supports Phase Adding/Shedding for Multi-Phase Power Stages

• Sync In/Out Pins Align DPWM Clocks Between Multiple UCD92xx Devices

• 12-Bit Digital Monitoring of Power Supply Parameters Including:

– Input/Output Current and Voltage – Temperature at Each Power Stage

• Multiple Levels of Over-current Fault Protection:

– External Current Fault Inputs – Analog Comparators Monitor Current

Sense Voltage

– Current Continually Digitally Monitored

• Over- and Under-voltage Fault Protection

• Over-temperature Fault Protection

• Enhanced Nonvolatile Memory with Error Correction Code (ECC)

• Device Operates From a Single Supply with an Internal Regulator Controller That Allows

DESCRIPTION

The UCD9224 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop management with flash memory and a serial interface to support configurability, monitoring and management.

The UCD9224 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.

To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.

TI has also developed multiple complementary power stage solutions – from discrete drivers in the UCD7k family to fully tested power train modules in the PTD

Operation Over a Wide Supply Voltage Range family. These solutions have been developed to

• Supported by Fusion Digital Power™ Designer, a Full Featured PC Based Design

complement the UCD9k family of system power controllers.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

UCD9224

SLVSA35 –JANUARY 2010

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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ORDERING INFORMATION

(1)

OPERATING TEMPERATURE ORDERABLE PART PIN COUNT SUPPLY PACKAGE TOP SIDE

RANGE, T

–40°C to 125°C

NUMBER MARKING

UCD9224RGZR 48-pin Reel of 2500 QFN UCD9224 UCD9224RGZT 48-pin Tray of 250 QFN UCD9224

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

VALUE UNIT

Voltage applied at V Voltage applied at V Voltage applied to any pin Storage temperature (T

to DGND1 –0.3 to 3.8 V

33D

to AGND –0.3 to 3.8 V

33A

(2)

) –40 to 150 °C

STG

–0.3 to 3.8 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to GND.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

V Supply voltage during operation, V T

Operating free-air temperature range Junction temperature

(1)

(1) When operating, the UCD9224’s typical power consumption causes a 15°C temperature rise from ambient.

33D

(1)

, V

33DIO

, V

33A

3 3.3 3.6 V

–40 125 °C

125 °C

ELECTRICAL CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

V33A

V33D

INTERNAL REGULATOR CONTROLLER INPUTS/OUTPUTS

33FB

V33FB

Beta Series NPN pass device 40

EXTERNALLY SUPPLIED 3.3 V POWER

33D

33A

Supply current mA

3.3-V linear regulator Emitter of NPN transistor 3.25 3.3 3.6

3.3-V linear regulator feedback 4 4.6 Series pass base drive V

Digital 3.3-V power TA= 25° C 3.0 3.6 V Analog 3.3-V power TA= 25°C 3.0 3.6 V

= 3.3 V 8 15

33A

= 3.3 V 42 55

33D

= 3.3 V storing configuration parameters

33D

in flash memory

= 12 V, curent into V

VIN

pin 10 mA

33FB

53 65

UCD9224

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ELECTRICAL CHARACTERISTICS (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ERROR AMPLIFIER INPUTS EAPn, EANn

ERROR

EAP-EAN Error voltage digital resolution AFE_GAIN field of CLA_GAINS = 3 1 mV R

OFFSET

Vref 10-bit DAC

ref

refres

ANALOG INPUTS CS-1A, CS-1B, CS-2A, CS-3A, Vin/Iin, Temperature, ADDR-0, ADDR-1, Vtrack, ADCref

ADDR_OPEN

ADDR_SHORT

ADC_RANGE

OC_THRS

OC_RES

ADCref External reference input 1.8 V33A V Temp

internal

INL ADC integral nonlinearity –2.5 2.5 mV I

lkg

DIGITAL INPUTS/OUTPUTS

SYSTEM PERFORMANCE

RESET

RefAcc

DiffOffset

Delay

Duty Max and Min duty cycle 0% 100% V33Slew Minimum V33slew rate during power on 0.25 V/ms t

retention

Write_Cycles Number of nonvolatile erase/write cycles TJ= 25°C 20 K cycles

(1) See the UCD92xx PMBus Command Reference for the description of the AFE_GAIN field of CLA_GAINS command. (2) Can be disabled by setting to '0'0 (3) The maximum IOL, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified. (4) The maximum IOH, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified. (5) With default device calibration. PMBus calibration can be used to improve the regulation tolerance

Common mode voltage each pin –0.15 1.848 V Internal error voltage range AFE_GAIN field of CLA_GAINS = 0

(1)

Input Impedance Ground reference 0.5 1.5 3 MΩ Input offset current 1 kΩ source impedence –5 5 µA

Reference voltage setpoint 0 1.6 V Reference voltage resolution 1.56 mV

Voltage indicating open pin ADDR-0, ADDR-1 open 2.37 V Voltage indicating shorted pin ADDR-0, ADDR-1 short to ground 0.36 V

Measurement range for voltage monitoring 0 2.5 V Over-current comparator threshold voltage

(2)

range Over-current comparator threshold voltage

range

Inputs: Vin/Iin, V CS-1B, CS-2A, CS-3A

Inputs: CS-1A, CS-1B, CS-2A, CS-3A 0.032 2 V

Inputs: CS-1A, CS-1B, CS-2A, CS-3A 31.25 mV

track

, V

temperature

CS-1A,

Int. temperature sense accuracy Over range from 0°C to 125°C –5 5 °C

Input leakage current 3V applied to pin 100 nA Input impedance Ground reference 8 MΩ Current Sense Input capacitance 10 pF

Low-level output voltage IOL= 6 mA

High-level output voltage IOH= -6 mA High-level input voltage V

Low-level input voltage V

Voltage where device comes out of reset V

(3)

, V

= 3 V V

33D

(4)

, V

= 3 V V

33D

= 3V 2.1 3.6 V

33D

= 3.5 V 1.4 V

33D

Pin 2.3 2.4 V

33D

Pulse width needed for reset nRESET pin 2 µs

commanded to be 1V at 25°C,

Setpoint reference accuracy –10 10 mV

ref

AFEgain = 4, 1V input to EAP/N measured at output of the EADC

(5)

Setpoint reference accuracy over temperature –40°C to 125°C –20 20 mV Differential offset between gain settings AFEgain = 4 compared to AFEgain = 1, 2, or 8 –4 4 mV

Digital compensator delay 240 switching ns

Switching frequency 15.260 2000 kHz

V33slew rate between 2.3V and 2.9V, V

= V

33A

33D

Retention of configuration parameters TJ= 25°C 100 Years

SLVSA35 –JANUARY 2010

–256 248 mV

DGND1

+0.25

33D

–0.6V

240 + 1

cycle

UCD9224

SLVSA35 –JANUARY 2010

ADC MONITORING INTERVALS AND RESPONSE TIMES

The ADC operates in a continuous conversion sequence that measures each rail's output voltage, each power stage's output current, plus four other variables (external temperature, Internal temperature, input voltage and current, and tracking input voltage). The length of the sequence is determined by the number of output rails (NumRails) and total output power stages (NumPhases) configured for use. The time to complete the monitoring sampling sequence is give by the formula:

ADC_SEQ

ADC

ADC_SEQ

The most recent ADC conversion results are periodically converted into the proper measurement units (volts, amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. The monitoring operates asynchronously to the ADC, at intervals shown in the table below.

Vout

Iout

Vin

Iin

TEMP

Ibal

= t

× (NumRAILS + NumPHASE + 4)

ADC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ADC single-sample time 3.84 µs ADC sequencer interval 23.04 38.4 µs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output voltage monitoring interval 200 µs Output current monitoring interval 200 × NRails µs Input voltage monitoring interval 2 ms Input current monitoring interval 2 ms Temperature monitoring interval 100 ms Output current balancing interval 2 ms

Min = 1 Rail + 1 Phase + 4 = 6 samples Max = 2 Rails + 4 Phases + 4 = 10 samples

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Because the ADC sequencer and the monitoring comparisons are asynchronous to each other, the response time to a fault condition depends on where the event occurs within the monitoring interval and within the ADC sequence interval. Once a fault condition is detected, some additional time is required to determine the correct action based on the FAULT_RESPONSE code, and then to perform the appropriate response. The following table lists the worse-case fault response times.

PARAMETER TEST CONDITIONS MAX TIME UNIT

Over-/under-voltage fault response time during Normal regulation, no PMBus activity, 4 normal operation stages enabled

, t

OVF

, t

OCF

OTF

(1) During a STORE_DEFAULT_ALL command, which stores the entire configuration to nonvolatile memory, the fault detection latency can

be up to 10 ms.

Over-/under-voltage fault response time, during

UVF

data logging Over-/under-voltage fault response time, when

tracking or sequencing enable Over-/under-current fault response time during Normal regulation, no PMBus activity, 4

normal operation stages enabled 75% to 125% current step Over-/under-current fault response time, during During data logging to nonvolatile memory

UCF

data logging 75% to 125% current step Over-/under-current fault response time, when During tracking and soft start ramp 75% to

tracking or sequencing enable 125% current step Over-temperature fault response time 2.5 S

During data logging to nonvolatile memory

During tracking and soft-start ramp. 400 µs

Temperature rise of 10°C/sec, OT threshold = 100°C

(1)

100 + (600 × NRails) µs

300 µs

800 µs

600 + (600 × N

300 + (600 × N

Rails

) µs

UCD9224

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HARDWARE FAULT DETECTION LATENCY

The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.

PARAMETER TEST CONDITIONS MAX UNIT

Time to disable DPWM output based on corresponding 15 + 3 ×

FLT

active FLT pin NumPhases Time to disable the first DPWM output based on internal Step change in CS voltage from 0V to Switch

analog comparator fault 2.5V Cycles

CLF

Time to disable all remaining DPWM and SRE outputs configured for the voltage rail after an internal analog µs comparator fault

High level on FLT pin µs

Step change in CS voltage from 0V to 10 + 3 ×

2.5V NumPhases

PMBUS/SMBUS/I2C

The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus are shown below.

I2C/SMBus/PMBus TIMING CHARACTERISTICS

TA= –40°C to 125°C, 3V < V33< 3.6V, typical values at TA= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SMB

I2C

(BUF)

(HD:STA)

(SU:STA)

(SU:STO)

(HD:DAT)

(SU:DAT)

(TIMEOUT)

(LOW)

(HIGH)

(LOW:SEXT)

FALL

RISE

(1) The UCD9224 times out when any clock low exceeds t(TIMEOUT). (2) t

(HIGH)

in progress.

(3) t

(LOW:SEXT)

(4) Rise time t (5) Fall time t

SMBus/PMBus operating frequency Slave mode; SMBC 50% duty cycle 10 1000 kHz I2C operating frequency Slave mode; SCL 50% duty cycle 10 1000 kHz Bus free time between start and stop 4.7 µs Hold time after (repeated) start 0.26 µs Repeated start setup time 0.26 µs Stop setup time 0.26 µs Data hold time Receive mode 0 ns Data setup time 50 ns Error signal/detect See

(1)

Clock low period 0.5 µs Clock high period See Cumulative clock low slave extend time See Clock/data fall time See Clock/data rise time See

(2) (3) (4) (5)

, max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9224 that is

is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.

= V

RISE

= 0.9 V33to (V

FALL

ILMAX

– 0.15) to (V

ILMAX

IHMIN

– 0.15)

+ 0.15)

SLVSA35 –JANUARY 2010

35 ms

0.26 50 µs 25 ms

120 ns 120 ns

UCD9224

SLVSA35 –JANUARY 2010

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Figure 1. \I2C/SMBus/PMBus Timing in Extended Mode Diagram

Digital

HighRes

PWM

Digital

HighRes

PWM

Digital

HighRes

PWM

Digital

HighRes

PWM

12-bit

ADC

260 ksps

Osc

ARM-7 core

PMBus

EAP2

EAN2

PWR

GND

Analogfrontend

(AFE)

Ref

ADC

6 bit

IIR

3P/3Z

Err

Amp

EAP1

EAN1

Coeff.

Regs

CompensatorAnalogFrontEnd

POR/BOR

Ref 1

AnalogComparators

TRIP1

TRIP2

DPWM-1B

DPWM-2A

DPWM-3A

PMBus-Clk

SYNC-IN SYNC-OUT

BPCAP

TRIP4

SRE-3A

SRE-2A

SRE-1B

SRE-1A

SRE

control

Compensator

3P/3ZIIR

Flash

memorywith

ECC

Diff

Amp

FusionPowerPeripheral 2

FusionPowerPeripheral 1

internal

Tempsense

internal

3.3V &

1.8V

regulator

Ref 2

Ref 4

PMBus-Data

PMBus-Alert

PMBus-Cntl

UCD9224

FLT-1B

DPWM-1A

FLT-1A

ADDR-0 ADDR-1

CS-1A CS-1B CS-2A CS-3A

VIN_IIN

Vtrack

Temperature

TMUX-0 TMUX-1

FLT-2A

FLT-3A

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UCD9224

SLVSA35 –JANUARY 2010

Figure 2. Functional Block Diagram

Temp erat u r e

Vt r ack

UCD9224

RESET

Vin/Iin

FLT-1 B

SRE-1A

PMBus _Data

FLT-2 A

PMBus _CLK

DPWM -1A

DPWM -1B

SEQ- 1

DPWM -2A

SRE-2A

DWPM-3A

PMBu s_Alert

PMBu s_CNTL

SEQ- 2

SRE-1B

TMS

TRST

ADCref

TDI / Sync_In

TDO/ Sync _Out

TCK

PGood

FLT-3 A

DGND 1

AGND 2

EAN2

EAP2

ADDR- 0

CS-2 A

V33FB

FLT-1 A

SRE-3A

ADDR- 1

V33 A

CS-1 A

V33 D

TMUX-0

TMUX-1

EAN1

EAP1

CS-1 B

CS-3 A

AGND 1

BPCap

UCD9224

SLVSA35 –JANUARY 2010

The UCD9224 is available in an 48-pin QFP package (RGZ).

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TYPICAL APPLICATION SCHEMATIC

Figure 4 shows the UCD9224 power supply controller as part of a system that provides the regulation of one

eight-phase power supply. The loop for the power supply is created by the voltage output feeding into the differential voltage error ADC (EADC) input, and completed by DPWM outputs feeding into the gate drivers for each power stage (PTD modules in this example).

The ±VsA and ±VsB signal must be routed to the EAp/EAn input that matches the number of the lowest DPWM configured as part of the rail. (See more detail in Flexible Rail/Power Stage Configuration.)

Figure 3. Pin Assignment Diagram

+3.3 V

Temperature

Vin/Iin

+VsA

-VsA

Vin

Temperature

PTD08D210W

FF-A

PWM-A

SRE-A

Isense-A

Tsense

Vout-A

PGND

AGND

VIN VIN

AGND

Vout-A

FF-B

PWM-B

SRE-B

Isense-B

Vout-B

PGND

Vout-B

PGND

+VsA

+VsB

-VsA

-VsB

+VsB

-VsB +3.3 V

UCD9224

TRST

TMS

TDI/Sync_In

TDO/Sync_Out

FLT-1A

DPWM-1A

SRE-1A

AGND1

V33A

FLT-1B

DPWM-1B

SRE-1B

FLT-2A

DPWM-2A

SRE-2A

FLT-3A

DPWM-3A

SRE-3A

TMUX-0

TMUX-1

TCK

RESET

PMBus_Clock

PMBus_Data

PMBus_Alert

PMBus_Cntl

V33D

BPCAP

AGND2

DGND1

PowerPad

EAP1

ADDR-0

ADDR-1

EAN1

EAP2

EAN2

Vin/Iin

Vtrack

Temperature

CS-1A

CS-1B

CS-2A

CS-3A

V33FB

PGood

ADCref

SEQ-1

SEQ-2

+3.3 V

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UCD9224

SLVSA35 –JANUARY 2010

Figure 4. Typical Application Schematic Using PTD Driver Module

UCD7231

RDLY

VGG

HS_SNS

HS_Gate

ILIM

IOUT

BP3

Vin

AGND

CSP

SRE_Mode

CSN

LS_Gate

SWSRE

FF BST

PWM

PwPd

PGND

VGG_DIS

CD74HC4052

Vcc

1Y0 1Z

Gnd

1Y1

1Y2

1Y3

2Y0

2Y1

2Y2

2Y3

Vin

Temperature

Sensor

Temp_A

UCD7231

RDLY

VGG

HS_SNS

HS_Gate

ILIM

IOUT

BP3

Vin

AGND

CSP

SRE_Mode

CSN

LS_Gate

SWSRE

FF BST

PWM

PwPd

PGND

VGG_DIS

Vin

Temperature

Sensor

Temp_B

UCD7231

RDLY

VGG

HS_SNS

HS_Gate

ILIM

IOUT

BP3

Vin

AGND

CSP

SRE_Mode

CSN

LS_Gate

SWSRE

FF BST

PWM

PwPd

PGND

VGG_DIS

Vin

Temperature

Sensor

Temp_C

UCD7231

RDLY

VGG

HS_SNS

HS_Gate

ILIM

IOUT

BP3

Vin

AGND

CSP

SRE_Mode

CSN

LS_Gate

SWSRE

FF BST

PWM

PwPd

PGND

VGG_DIS

Vin

Temperature

Sensor

Temp_D

Temp_C

Temp_B

Temp_A

Vinput

Iin

+3.3V

Temperature

Vin/Iin

+3.3V

Temperature

Vin/Iin

+Vs1

-Vs1

+Vs1

-Vs1

+Vout1

-Vout1

+3.3V

UCD9224

TRST

TMS

TDI/Sync_In

TDO/Sync_Out

FLT-1A

DPWM-1A

SRE-1A

AGND1

V33A

FLT-1B

DPWM-1B

SRE-1B

FLT-2A

DPWM-2A

SRE-2A

FLT-3A

DPWM-3A

SRE-3A

TMUX-0

TMUX-1

TCK

RESET

PMBus_Clock

PMBus_Data

PMBus_Alert

PMBus_Cntl

V33D

BPCAP

AGND2

DGND1

PowerPad

EAP1

ADDR-0

ADDR-1

EAN1

EAP2

EAN2

Vin/Iin

Vtrack

Temperature

CS-1A

CS-1B

CS-2A

CS-3A

V33FB

PGood

ADCref

SEQ-1

SEQ-2

+3.3V

UCD9224

SLVSA35 –JANUARY 2010

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Figure 5. Typical Application Schematic Using UCD7231 Drivers

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SLVSA35 –JANUARY 2010

PIN DESCRIPTIONS

PIN NO. PIN NAME DESCRIPTION

1 CS-3A Power stage 3A current sense input and input to analog comparator 4 2 CS-1B Power stage 1B current sense input 3 CS-2A Power stage 2A current sense input and input to analog comparator 2 4 Vin/I 5 nRESET Active low device reset input, pullup to 3.3V with 10kΩ resistor 6 FLT-1A External fault input 1A, active high 7 FLT-1B External fault input 1B, active high 8 FLT-2A External fault input 2A, active high

9 SRE-1A Synchronous rectifier enable output 1A, active high 10 PMBus_Clock PMBus Clock, pullup to 3.3V with 2kΩ resistor 11 PMBus_Data PMBus Data, pullup to 3.3V with 2kΩ resistor 12 DPWM-1A Digital Pulse Width Modulator output 1A 13 DPWM-1B Digital Pulse Width Modulator output 1B 14 DPWM-2A Digital Pulse Width Modulator output 2A 15 SRE-2A Synchronous rectifier enable output 2A, active high 16 DPWM-3A Digital Pulse Width Modulator output 3A 17 SRE-3A Synchronous rectifier enable output 3A, active high 18 SRE-1B Synchronous rectifier enable output 1B, active high 19 PMBus_Alert PMBus Alert, pullup to 3.3V with 2kΩ resistor 20 PMBus_Cntl PMBus Control, pullup to 3.3V with 2kΩ resistor 21 SEQ-1 Sequencing Input/Output 22 SEQ-2 Sequencing Input/Output 23 TMUX-0 Temperature multiplexer select output S0, Vin/Iinselect 24 TMUX-1 Temperature multiplexer select output S1 25 FLT-3A External fault input 3A, active high 26 PGood Power Good indication, Active high open-drain output. Pull-up to 3.3V with 10kΩ resistor. 27 TCK JTAG Test clock 28 TDO / Sync_Out JTAG Test data out (muxed with Sync_Out for synchronizing switching frequency across devices) 29 TDI / Sync_In JTAG Test data in (muxed with Sync_In for synchronizing switching frequency across devices) tie to

30 TMS JTAG Test mode select – tie to V33D with 10kΩ resistor 31 nTRST JTAG Test reset – tie to ground with 10kΩ resistor 32 DGND1 Digital ground 33 V33D Digital core 3.3V supply 34 V33A Analog 3.3V supply 35 BPCap 1.8V bypass capacitor connection 36 AGND1 Analog ground 37 EAP1 Error analog, differential voltage. Positive channel #1 input 38 EAN1 Error analog, differential voltage. Negative channel #1 input 39 EAP2 Error analog, differential voltage. Positive channel #2 input 40 EAN2 Error analog, differential voltage. Negative channel #2 input 41 V33FB Connection to the base of the 3.3V linear regulator transistor. (no connect if not using an external

42 CS-1A Power stage 1A current sense input and input to analog comparator 1 43 ADDR-1 Address sense input. Channel 1 44 ADDR-0 Address sense input. Channel 0 45 Vtrack Voltage track input

Input supply sense, alternates between Vinand I

V33D with 10kOhm resistor

transistor)

UCD9224

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