Texas Instruments UCD7201, UCD7201RSAT Datasheet

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FEATURES DESCRIPTION

APPLICATIONS

TYPICAL APPLICATION DIAGRAM (Push-Pull Converter)

Isolation
Amplifier

COMMUNICATION
(Programming & Status Reporting)

141

12

8

VDD

PVDD

CS

10OUT2

3

4

2

5
6

IN1

AGND

3V3

IN2

CLF

7

UCD7201PWP

11OUT1

9PGND

13

NC

ILIM

NC

Bias Supply

Bias Winding

VIN

VOUT

DIGITAL

CONTROLLER

GND

PWMA

ADC4

INTERRUPT or CCR

PWMB

ADC3

VCC

PWM or GPIO

ADC1

ADC2

UCD7201

SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006

Digital Control Compatible Dual Low-Side ±4 Amp MOSFET Drivers with Programmable

Common Current Sense

• Adjustable Current Limit Protection

The UCD7201 is a member of the UCD7K family of
digital control compatible drivers for applications

• 3.3-V, 10-mA Internal Regulator

utilizing digital control techniques or applications

• DSP/µC Compatible Inputs

requiring fast local peak current limit protection.

• Dual ±4-A TrueDrive™ High Current Drivers

The UCD7201 includes dual low-side ±4-A

• 10-ns Typical Rise and Fall Times with 2.2-nF

high-current MOSFET gate drivers. It allows the

Loads

digital power controllers such as UCD9110 or

• 20-ns Input-to-Output Propagation Delay

UCD9501 to interface to the power stage in double
ended topologies. It provides a cycle-by-cycle current

• 25-ns Current Sense-to-Output Propagation

limit function for both driver channels, a

Delay

programmable threshold and a digital output current

• Programmable Current Limit Threshold

limit flag which can be monitored by the host

• Digital Output Current Limit Flag

controller. With a fast cycle-by-cycle current limit
protection, the driver can turn off the power stage in

• 4.5-V to 15-V Supply Voltage Range

the event of an overcurrent condition.

• Rated from -40°C to 105°C

For fast switching speeds, the UCD7201 output

• Lead(Pb)-Free Packaging

stages use the TrueDrive™ output architecture,
which delivers rated current of ±4 A into the gate of a
MOSFET during the Miller plateau region of the

• Digitally Controlled Power Supplies

switching transition. It also includes a 3.3-V, 10-mA

• DC/DC Converters

linear regulator to provide power to the digital
controller.

• Motor Controllers

• Line Drivers

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TrueDrive, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2005–2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

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DESCRIPTION (CONT.)

CONNECTION DIAGRAMS

3V3

IN1

AGND

IN2

16
15
14
13

NC
NC
NC

VDD

RSA−16 PACKAGE

(BOTTOM VIEW)

5
6
7
8

1

CLF
ILM
CS
PGND

2 3 4

12 11 10 9

PVDD

OUT1

OUT2

PGND

1
2
3
4
5
6
7

14
13
12
11
10

9
8

PWP−14 PACKAGE

(TOP VIEW)

NC − No internal connection

NC

3V3

IN1

AGND

IN2
CLF
ILIM

NC
VDD
PVDD
OUT1
OUT2
PGND
CS

UCD7201

SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006

For similar applications requiring direct start-up capability from higher voltages such as the 48-V telecom input
line, the UCD7601 includes a 110-V high-voltage startup circuit.

The UCD7K driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs.
UCD7201 is offered in PowerPAD™ HTSSOP-14 or space-saving QFN-16 packages.

ORDERING INFORMATION

PACKAGED DEVICES

(1) (2)

110-V HV

CURRENT SENSE LIMIT

TEMPERATURE RANGE STARTUP

PowerPAD™ HTSSOP-14

PER CHANNEL

QFN-16 (RSA)

(3)

CIRCUIT

(PWP)

-40°C to 105°C Common No UCD7201PWP UCD7201RSA

(1) These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C

peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.

(2) HTSSOP-14 (PWP) and QFN-16 (RSA), packages are available taped and reeled. Add R suffix to device type (e.g. UCD7201PWPR) to

order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RSA packages.

(3) Contact factory for availability of QFN packaging.

PACKAGING INFORMATION

θ

JC

θ

JA

POWER RATING

DERATING FACTOR,

PACKAGE SUFFIX TA= 70 ° C,

ABOVE 70 ° C (mW/ ° C)

( ° C/W) ( ° C/W)

TJ= 125 ° C (mW)

PowerPAD™

PWP 2.07 37.47

(1)

1470 27

HTSSOP- 14

QFN-16 RSA - - - -

(1) PowerPAD™ soldered to the PWB (TI recommended PWB as defind in TI's application report SLMA002 pg.33) with OLFM.

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ABSOLUTE MAXIMUM RATINGS

(1) (2)

ELECTRICAL CHARACTERISTICS

UCD7201

SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006

SYMBOL PARAMETER UCD7201 UNIT

V

DD

Supply Voltage 16 V

Quiescent 20

I

DD

Supply Current mA

Switching, TA= 25°C, , TJ= 125 ° C, V

DD

= 12 V 200

Output Gate Drive

V

OUT

OUT -1 to PVDD V

Voltage

I

OUT(sink)

4.0

Output Gate Drive

OUT A

Current

I

OUT(source)

-4.0

ISET, CS -0.3 to 3.6

Analog Input

ILIM -0.3 to 3.6 V

Digital I/O’s IN, CLF -0.3 to 3.6

TA= 25°C (PWP-14 package), TJ= 125 ° C 2.67

Power Dissipation W

TA= 25°C (QFN-16 package), TJ= 125 ° C -

Junction Operating

T

J

UCD7201 -55 to 150

Temperature

°C

T

str

Storage Temperature -65 to 150

HBM Human body model 2000

ESD Rating V

CDM Change device model 500
T

SOL

Lead Temperature (Soldering, 10 sec) +300 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.

V

DD

= 12 V, 4.7-µF capacitor from V

DD

to GND, 0.22 µ F from 3V3 to AGND, TA= TJ= -40°C to 105°C, (unless otherwise

noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY SECTION

Supply current, OFF V

DD

= 4.2 V - 200 400 µA

Supply current Outputs not switching IN = LOW - 1.5 2.5 mA

LOW VOLTAGE UNDER-VOLTAGE LOCKOUT

VDD UVLO ON 4.25 4.5 4.75

V

VDD UVLO OFF 4.05 4.25 4.45
VDD UVLO hysteresis 150 250 350 mV

REFERENCE / EXTERNAL BIAS SUPPLY

3V3 initial set point TA= 25°C, I

LOAD

= 0 3.267 3.3 3.333

V

3V3 set point over temperature 3.234 3.3 3.366
3V3 load regulation I

LOAD

= 1 mA to 10 mA, VDD = 5 V - 1 6.6

mV

3V3 line regulation VDD = 4.75 V to 12 V, I

LOAD

= 10 mA - 1 6.6
Short circuit current VDD = 4.75 to 12 V 11 20 35 mA
3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1

V

3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9

INPUT SIGNAL

HIGH, positive-going input threshold

1.65 - 2.08

voltage (VIT+)
LOW negative-going input threshold

1.16 - 1.5 V

voltage (VIT-)
Input voltage hysteresis, (VIT+ -

0.6 - 0.8

VIT-)

3

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UCD7201

SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006

ELECTRICAL CHARACTERISTICS (continued)

V

DD

= 12 V, 4.7-µF capacitor from V

DD

to GND, 0.22 µ F from 3V3 to AGND, TA= TJ= -40°C to 105°C, (unless otherwise

noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Frequency - - 2 MHz

CURRENT LIMIT (ILIM)

ILIM internal current limit threshold ILIM = OPEN 0.51 0.55 0.58
ILIM maximum current limit threshold I

LIM

= 3.3 V 1.05 1.10 1.15

ILIM current limit threshold I

LIM

= 0.75 V 0.700 0.725 0.750

V

ILIM minimum current limit threshold I

LIM

= 0.25 V 0.21 0.23 0.25

CLF output high level CS > I

LIM

, I

LOAD

= -7 mA 2.64 - -

CLF output low level CS ≤ I

LIM

, I

LOAD

= 7 mA - - 0.66

Propagation delay from IN to CLF IN rising to CLF falling after a current limit event - 10 20 ns

CURRENT SENSE COMPARATOR

Bias voltage Includes CS comp offset 5 25 50 mV
Input bias current - –1 - uA
Propagation delay from CS to OUTx

I

LIM

= 0.5 V, measured on OUTx, CS = threshold + 60 mV - 25 40

(1)

ns

Propagation delay from CS to CLF

(1)

I

LIM

= 0.5 V, measured on CLF, CS = threshold + 60 mV - 25 50

CURRENT SENSE DISCHARGE TRANSISTOR

Discharge resistance IN = low, resistance from CS to AGND 10 35 75 Ω

OUTPUT DRIVERS

Source current

(1)

VDD = 12 V, IN = high, OUTx = 5 V 4

Sink current

(1)

VDD = 12 V, IN = low, OUTx = 5 V 4

A

Source current

(1)

VDD = 4.75 V, IN = high, OUTx = 0 2

Sink current

(1)

VDD = 4.75 V, IN = low, OUTx = 4.75 V 3

Rise time, t

R

C

LOAD

= 2.2 nF, VDD = 12 V 10 20

ns

Fall time, t

F

C

LOAD

= 2.2 nF, VDD = 12 V 10 15

Output with VDD < UVLO VDD =1.0 V, I

SINK

= 10 mA 0.8 1.2 V

Propagation delay from IN to OUT1,

C

LOAD

= 2.2 nF, VDD = 12 V, CLK rising 20 35

t

D1

ns

Propagation delay from IN to OUT2,

C

LOAD

= 2.2 nF, VDD = 12 V, CLK falling 20 35

t

D2

(1) Ensured by design. Not 100% tested in production.

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FUNCTIONAL BLOCK DIAGRAM

3

1

4

2

5

6

7

3V3 Regulator

and Reference

UVLO

12

14

11

13

10

9

8

NC

NC

3V3

IN1

AGND

IN2

CLF

ILIM

VDD

PVDD

OUT1

OUT2

PGND

CS

+

S

D

Q

Q R

R

+

25 mV

VIT−

10%

90%

INPUT

OUTPUT

VIT+

t

D1

t

F

t

F

t

D2

UCD7201

SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006

Figure 1. UCD7201

Timing Diagram

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TERMINAL FUNCTIONS

UCD7201

SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006

UCD7201

PIN

I/O FUNCTION

HTSSOP QFN-16

NAME

-14 PIN # PIN #

1 - NC - No Connection

Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA

2 1 3V3 O

of current. Place 0.22 µF of ceramic capacitance from this pin to ground.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up

3 2 IN1 I to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry

from any external noise.

4 3 AGND - Analog ground return.

The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up

5 4 IN2 I to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry

from any external noise.
Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the

6 5 CLF O output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is

latched high until the device receives the next rising edge on the IN pin.
Current limit threshold set pin. The current limit threshold can be set to any value between

7 6 ILIM I

0.25 V and 1.0 V. The default value while open is 0.5 V.
Current sense pin. Fast current limit comparator connected to the CS pin is used to protect

8 7 CS I

the power stage by implementing cycle-by-cycle current limiting.
Power ground return. The pin should be connected very closely to the source of the power

9 8, 9 PGND -

MOSFET.
10 10 OUT2 O The high-current TrueDrive™ driver output.
11 11 OUT1 O The high-current TrueDrive™ driver output.

Supply pin provides power for the output drivers. It is not connected internally to the VDD

12 12 PVDD I

supply rail. The bypass capacitor for this pin should be returned to PGND.

Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to

13 13 VDD I

15 V. Bypass the pin with at least 4.7 µF of capacitance, returned to AGND.

14, 15, No Connection.

14 NC -

16

6

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APPLICATION INFORMATION

Supply Current Sensing and Protection

Reference / External Bias Supply

Input Pin

UCD7201

SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006

The UCD7201 is member of the UCD7K family of If limiting the rise or fall times to the power device is
digital compatible drivers targeting applications desired then an external resistance may be added
utilizing digital control techniques or applications that between the output of the driver and the load device,
require local fast peak current limit protection. which is generally the gate of a power MOSFET.

The UCD7K devices accept a supply range of 4.5 V A very fast current limit comparator connected to the
to 15 V. The device has an internal precision linear CS pin is used to protect the power stage by
regulator that produces the 3V3 output from this implementing cycle-by-cycle current limiting.
VDD input. A separate pin, PVDD, not connected

The current limit threshold may be set to any value

internally to the VDD supply rail provides power for

between 0.25 V and 1.0 V by applying the desired

the output drivers. In all applications the same bus

threshold voltage to the current limit (ILIM) pin. If the

voltage supplies the two pins. It is recommended that

ILIM pin is left floating, the internal current limit

a low value of resistance be placed between the two

threshold will be 0.5 volts. When the CS level is

pins so that the local capacitance on each pin forms

greater than the I

LIM

voltage minus 25 mV, the output

low pass filters to attenuate any switching noise that

of the driver is forced low and the current limit flag

may be on the bus.

(CLF) is set high. The CLF signal is latched high until
Although quiescent VDD current is low, total supply the device receives the next rising edge on either of
current depends on the gate drive output current the IN pins.
required for capacitive load and switching frequency.

When the CS voltage is below I

LIM

, the driver output

Total VDD current is the sum of quiescent VDD

follows the PWM input. The CLF digital output flag

current and the average OUT current. Knowing the

can be monitored by the host controller to determine

operating frequency and the MOSFET gate charge

when a current limit event occurs and to then apply

(Q

G

), average OUT current can be calculated from:

the appropriate algorithm to obtain the desired
I

OUT

= Q

G

x f, where f is frequency. current limit profile (i.e. straight time, fold back,

hickup or latch-off).
For the best high-speed circuit performance, VDD

bypass capacitors are recommended to prevent A benefit of this local protection feature is that the
noise problems. A 4.7-µF ceramic capacitor should UCD7K devices can protect the power stage if the
be located closest to the VDD and the AGND software code in the digital controller becomes
connection. In addition, a larger capacitor with corrupted. If the controller’s PWM output stays high,
relatively low ESR should be connected to the PVDD the local current sense circuit turns off the driver
and PGND pin, to help deliver the high current peaks output when an over-current event occurs. The
to the load. The capacitors should present a low system would then likely go into retry mode because
impedance characteristic for the expected current most DSP and microcontrollers have on-board
levels in the driver application. The use of surface watchdog, brown-out, and other supervisory
mount components for all bypass capacitors is highly peripherals to restart the device in the event that it is
recommended. not operating properly. But these peripherals typically

do not react fast enough to save the power stage.

The UCD7K’s local current limit comparator provides

the required fast protection for the power stage.
All devices in the UCD7K family are capable of

supplying a regulated 3.3-V rail to power various The CS threshold is 25 mV below the I

LIM

voltage. If
types of external loads such as a microcontroller or the user attempts to command zero current while the
an ASIC. The onboard linear voltage regulator is CS pin is at ground the CLF flag will latch high until
capable of sourcing up to 10 mA of current. For the IN pin receives a pulse. At start-up it is
normal operation, place 0.22-µF of ceramic necessary to ensure that the ILIM pin will always be
capacitance between the 3V3 pin to the AGND pin. greater than the CS pin for the handshaking to work

as described below. If for any reason the CS pin
comes to within 25 mV of the ILIM pin during
start-up, then the CLF flag will be latched high and

The input pins are high impedance digital inputs

the digital controller must poll the UCD7K device, by

capable of accepting 3.3-V logic level signals up to 2

sending it a narrow IN pulse. If a fault condition is not

MHz. There is an internal Schmitt Trigger comparator

present the IN pulse will reset the CLF signal to low

which isolates the internal circuitry from any external

indicating that the UCD7K device is ready to process

noise.

power pulses.

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Handshaking Drive Current and Power Requirements

Driver Output

E +

1
2

CV

2

P + CV2 f

Source/Sink Capabilities During Miller Plateau

P + 2.2 nF 122 300 kHz + 0.095 W

I +

P
V

+

0.095 W
12 V

+ 7.9 mA

Operational Waveforms

UCD7201

SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006

The UCD7K family of devices have a built-in The UCD7K family of drivers can deliver high current
handshaking feature to facilitate efficient start-up of into a MOSFET gate for a period of several hundred
the digitally controlled power supply. At start-up the nanoseconds. High peak current is required to turn
CLF flag is held high until all the internal and external the device ON quickly. Then, to turn the device OFF,
supply voltages of the UCD7K device are within their the driver is required to sink a similar amount of
operating range. Once the supply voltages are within current to ground. This repeats at the operating
acceptable limits, the CLF goes low and the device frequency of the power device.
will process input drive signals. The micro-controller

Reference [1] discusses the current required to drive

should monitor the CFL flag at start-up and wait for

a power MOSFET and other capacitive-input

the CLF flag to go LOW before sending power

switching devices.

pulses to the UCD7K device.

When a driver device is tested with a discrete,
capacitive load it is a fairly simple matter to calculate
the power that is required from the bias supply. The

The high-current output stage of the UCD7K device

energy that must be transferred from the bias supply

family is capable of supplying ±4-A peak current

to charge the capacitor is given by:

pulses and swings to both PVDD and PGND. The
driver outputs follow the state of the IN pin provided
that the VDD and 3V3 voltages are above their
respective under-voltage lockout threshold.

where C is the load capacitor and V is the bias

The drive output utilizes Texas Instruments'

voltage feeding the driver.

TrueDrive™ architecture, which delivers rated

There is an equal amount of energy transferred to

current into the gate of a MOSFET when it is most

ground when the capacitor is discharged. This leads

needed, during the Miller plateau region of the

to a power loss given by the following:

switching transition providing efficiency gains.
TrueDrive™ consists of pullup pulldown circuits with

bipolar and MOSFET transistors in parallel. The peak

where f is the switching frequency.

output current rating is the combined current from
the bipolar and MOSFET transistors. This hybrid

This power is dissipated in the resistive elements of

output stage also allows efficient current sourcing at

the circuit. Thus, with no external resistor between

low supply voltages.

the driver and gate, this power is dissipated inside
the driver. Half of the total power is dissipated when

Each output stage also provides a very low

the capacitor is charged, and the other half is

impedance to overshoot and undershoot due to the

dissipated when the capacitor is discharged.

body diode of the external MOSFET. This means
that in many cases, external-schottky-clamp diodes

With V

DD

= 12 V, C

LOAD

= 2.2 nF, and f = 300 kHz,

are not required.

the power loss can be calculated as:

Large power MOSFETs present a large load to the

With a 12-V supply, this would equate to a current of:

control circuitry. Proper drive is required for efficient,
reliable operation. The UCD7K drivers have been
optimized to provide maximum drive to a power
MOSFET during the Miller plateau region of the
switching transition. This interval occurs while the
drain voltage is swinging between the voltage levels

Figure 24 shows the circuit performance achievable

dictated by the power topology, requiring the

with the output driving a 10-nF load at 12-V V

DD

. The

charging/discharging of the drain-gate capacitance

input pulsewidth (not shown) is set to 200 ns to show

with current supplied or removed by the driver

both transitions in the output waveform. Note the

device. See Reference [1]

linear rising and falling edges of the switching
waveforms. This is due to the constant output current
characteristic of TrueDrive™ stage as opposed to
the resistive output impedance of traditional
MOSFET-based gate drivers.

8

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