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FEATURES DESCRIPTION
APPLICATIONS
TYPICAL APPLICATION DIAGRAM (Push-Pull Converter)
Isolation
Amplifier
COMMUNICATION
(Programming & Status Reporting)
141
12
8
VDD
PVDD
CS
10OUT2
3
4
2
5
6
IN1
AGND
3V3
IN2
CLF
7
UCD7201PWP
11OUT1
9PGND
13
NC
ILIM
NC
Bias Supply
Bias Winding
VIN
VOUT
DIGITAL
CONTROLLER
GND
PWMA
ADC4
INTERRUPT or CCR
PWMB
ADC3
VCC
PWM or GPIO
ADC1
ADC2
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
Digital Control Compatible Dual Low-Side ±4 Amp MOSFET Drivers with Programmable
Common Current Sense
• Adjustable Current Limit Protection
The UCD7201 is a member of the UCD7K family of
digital control compatible drivers for applications
• 3.3-V, 10-mA Internal Regulator
utilizing digital control techniques or applications
• DSP/µC Compatible Inputs
requiring fast local peak current limit protection.
• Dual ±4-A TrueDrive™ High Current Drivers
The UCD7201 includes dual low-side ±4-A
• 10-ns Typical Rise and Fall Times with 2.2-nF
high-current MOSFET gate drivers. It allows the
Loads
digital power controllers such as UCD9110 or
• 20-ns Input-to-Output Propagation Delay
UCD9501 to interface to the power stage in double
ended topologies. It provides a cycle-by-cycle current
• 25-ns Current Sense-to-Output Propagation
limit function for both driver channels, a
Delay
programmable threshold and a digital output current
• Programmable Current Limit Threshold
limit flag which can be monitored by the host
• Digital Output Current Limit Flag
controller. With a fast cycle-by-cycle current limit
protection, the driver can turn off the power stage in
• 4.5-V to 15-V Supply Voltage Range
the event of an overcurrent condition.
• Rated from -40°C to 105°C
For fast switching speeds, the UCD7201 output
• Lead(Pb)-Free Packaging
stages use the TrueDrive™ output architecture,
which delivers rated current of ±4 A into the gate of a
MOSFET during the Miller plateau region of the
• Digitally Controlled Power Supplies
switching transition. It also includes a 3.3-V, 10-mA
• DC/DC Converters
linear regulator to provide power to the digital
controller.
• Motor Controllers
• Line Drivers
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TrueDrive, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DESCRIPTION (CONT.)
CONNECTION DIAGRAMS
3V3
IN1
AGND
IN2
16
15
14
13
NC
NC
NC
VDD
RSA−16 PACKAGE
(BOTTOM VIEW)
5
6
7
8
1
CLF
ILM
CS
PGND
2 3 4
12 11 10 9
PVDD
OUT1
OUT2
PGND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PWP−14 PACKAGE
(TOP VIEW)
NC − No internal connection
NC
3V3
IN1
AGND
IN2
CLF
ILIM
NC
VDD
PVDD
OUT1
OUT2
PGND
CS
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
For similar applications requiring direct start-up capability from higher voltages such as the 48-V telecom input
line, the UCD7601 includes a 110-V high-voltage startup circuit.
The UCD7K driver family is compatible with standard 3.3-V I/O ports of DSPs, Microcontrollers, or ASICs.
UCD7201 is offered in PowerPAD™ HTSSOP-14 or space-saving QFN-16 packages.
ORDERING INFORMATION
PACKAGED DEVICES
(1) (2)
110-V HV
CURRENT SENSE LIMIT
TEMPERATURE RANGE STARTUP
PowerPAD™ HTSSOP-14
PER CHANNEL
QFN-16 (RSA)
(3)
CIRCUIT
(PWP)
-40°C to 105°C Common No UCD7201PWP UCD7201RSA
(1) These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C
peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.
(2) HTSSOP-14 (PWP) and QFN-16 (RSA), packages are available taped and reeled. Add R suffix to device type (e.g. UCD7201PWPR) to
order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RSA packages.
(3) Contact factory for availability of QFN packaging.
PACKAGING INFORMATION
θ
JC
θ
JA
POWER RATING
DERATING FACTOR,
PACKAGE SUFFIX TA= 70 ° C,
ABOVE 70 ° C (mW/ ° C)
( ° C/W) ( ° C/W)
TJ= 125 ° C (mW)
PowerPAD™
PWP 2.07 37.47
(1)
1470 27
HTSSOP- 14
QFN-16 RSA - - - -
(1) PowerPAD™ soldered to the PWB (TI recommended PWB as defind in TI's application report SLMA002 pg.33) with OLFM.
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ABSOLUTE MAXIMUM RATINGS
(1) (2)
ELECTRICAL CHARACTERISTICS
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
SYMBOL PARAMETER UCD7201 UNIT
V
DD
Supply Voltage 16 V
Quiescent 20
I
DD
Supply Current mA
Switching, TA= 25°C, , TJ= 125 ° C, V
DD
= 12 V 200
Output Gate Drive
V
OUT
OUT -1 to PVDD V
Voltage
I
OUT(sink)
4.0
Output Gate Drive
OUT A
Current
I
OUT(source)
-4.0
ISET, CS -0.3 to 3.6
Analog Input
ILIM -0.3 to 3.6 V
Digital I/O’s IN, CLF -0.3 to 3.6
TA= 25°C (PWP-14 package), TJ= 125 ° C 2.67
Power Dissipation W
TA= 25°C (QFN-16 package), TJ= 125 ° C -
Junction Operating
T
J
UCD7201 -55 to 150
Temperature
°C
T
str
Storage Temperature -65 to 150
HBM Human body model 2000
ESD Rating V
CDM Change device model 500
T
SOL
Lead Temperature (Soldering, 10 sec) +300 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
V
DD
= 12 V, 4.7-µF capacitor from V
DD
to GND, 0.22 µ F from 3V3 to AGND, TA= TJ= -40°C to 105°C, (unless otherwise
noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY SECTION
Supply current, OFF V
DD
= 4.2 V - 200 400 µA
Supply current Outputs not switching IN = LOW - 1.5 2.5 mA
LOW VOLTAGE UNDER-VOLTAGE LOCKOUT
VDD UVLO ON 4.25 4.5 4.75
V
VDD UVLO OFF 4.05 4.25 4.45
VDD UVLO hysteresis 150 250 350 mV
REFERENCE / EXTERNAL BIAS SUPPLY
3V3 initial set point TA= 25°C, I
LOAD
= 0 3.267 3.3 3.333
V
3V3 set point over temperature 3.234 3.3 3.366
3V3 load regulation I
LOAD
= 1 mA to 10 mA, VDD = 5 V - 1 6.6
mV
3V3 line regulation VDD = 4.75 V to 12 V, I
LOAD
= 10 mA - 1 6.6
Short circuit current VDD = 4.75 to 12 V 11 20 35 mA
3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1
V
3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9
INPUT SIGNAL
HIGH, positive-going input threshold
1.65 - 2.08
voltage (VIT+)
LOW negative-going input threshold
1.16 - 1.5 V
voltage (VIT-)
Input voltage hysteresis, (VIT+ -
0.6 - 0.8
VIT-)
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UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 12 V, 4.7-µF capacitor from V
DD
to GND, 0.22 µ F from 3V3 to AGND, TA= TJ= -40°C to 105°C, (unless otherwise
noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency - - 2 MHz
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold ILIM = OPEN 0.51 0.55 0.58
ILIM maximum current limit threshold I
LIM
= 3.3 V 1.05 1.10 1.15
ILIM current limit threshold I
LIM
= 0.75 V 0.700 0.725 0.750
V
ILIM minimum current limit threshold I
LIM
= 0.25 V 0.21 0.23 0.25
CLF output high level CS > I
LIM
, I
LOAD
= -7 mA 2.64 - -
CLF output low level CS ≤ I
LIM
, I
LOAD
= 7 mA - - 0.66
Propagation delay from IN to CLF IN rising to CLF falling after a current limit event - 10 20 ns
CURRENT SENSE COMPARATOR
Bias voltage Includes CS comp offset 5 25 50 mV
Input bias current - –1 - uA
Propagation delay from CS to OUTx
I
LIM
= 0.5 V, measured on OUTx, CS = threshold + 60 mV - 25 40
(1)
ns
Propagation delay from CS to CLF
(1)
I
LIM
= 0.5 V, measured on CLF, CS = threshold + 60 mV - 25 50
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance IN = low, resistance from CS to AGND 10 35 75 Ω
OUTPUT DRIVERS
Source current
(1)
VDD = 12 V, IN = high, OUTx = 5 V 4
Sink current
(1)
VDD = 12 V, IN = low, OUTx = 5 V 4
A
Source current
(1)
VDD = 4.75 V, IN = high, OUTx = 0 2
Sink current
(1)
VDD = 4.75 V, IN = low, OUTx = 4.75 V 3
Rise time, t
R
C
LOAD
= 2.2 nF, VDD = 12 V 10 20
ns
Fall time, t
F
C
LOAD
= 2.2 nF, VDD = 12 V 10 15
Output with VDD < UVLO VDD =1.0 V, I
SINK
= 10 mA 0.8 1.2 V
Propagation delay from IN to OUT1,
C
LOAD
= 2.2 nF, VDD = 12 V, CLK rising 20 35
t
D1
ns
Propagation delay from IN to OUT2,
C
LOAD
= 2.2 nF, VDD = 12 V, CLK falling 20 35
t
D2
(1) Ensured by design. Not 100% tested in production.
4
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FUNCTIONAL BLOCK DIAGRAM
3
1
4
2
5
6
7
3V3 Regulator
and Reference
UVLO
12
14
11
13
10
9
8
NC
NC
3V3
IN1
AGND
IN2
CLF
ILIM
VDD
PVDD
OUT1
OUT2
PGND
CS
+
S
D
Q
Q R
R
+
25 mV
VIT−
10%
90%
INPUT
OUTPUT
VIT+
t
D1
t
F
t
F
t
D2
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
Figure 1. UCD7201
Timing Diagram
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TERMINAL FUNCTIONS
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
UCD7201
PIN
I/O FUNCTION
HTSSOP QFN-16
NAME
-14 PIN # PIN #
1 - NC - No Connection
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA
2 1 3V3 O
of current. Place 0.22 µF of ceramic capacitance from this pin to ground.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
3 2 IN1 I to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
4 3 AGND - Analog ground return.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
5 4 IN2 I to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the
6 5 CLF O output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is
latched high until the device receives the next rising edge on the IN pin.
Current limit threshold set pin. The current limit threshold can be set to any value between
7 6 ILIM I
0.25 V and 1.0 V. The default value while open is 0.5 V.
Current sense pin. Fast current limit comparator connected to the CS pin is used to protect
8 7 CS I
the power stage by implementing cycle-by-cycle current limiting.
Power ground return. The pin should be connected very closely to the source of the power
9 8, 9 PGND -
MOSFET.
10 10 OUT2 O The high-current TrueDrive™ driver output.
11 11 OUT1 O The high-current TrueDrive™ driver output.
Supply pin provides power for the output drivers. It is not connected internally to the VDD
12 12 PVDD I
supply rail. The bypass capacitor for this pin should be returned to PGND.
Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to
13 13 VDD I
15 V. Bypass the pin with at least 4.7 µF of capacitance, returned to AGND.
14, 15, No Connection.
14 NC -
16
6
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APPLICATION INFORMATION
Supply Current Sensing and Protection
Reference / External Bias Supply
Input Pin
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
The UCD7201 is member of the UCD7K family of If limiting the rise or fall times to the power device is
digital compatible drivers targeting applications desired then an external resistance may be added
utilizing digital control techniques or applications that between the output of the driver and the load device,
require local fast peak current limit protection. which is generally the gate of a power MOSFET.
The UCD7K devices accept a supply range of 4.5 V A very fast current limit comparator connected to the
to 15 V. The device has an internal precision linear CS pin is used to protect the power stage by
regulator that produces the 3V3 output from this implementing cycle-by-cycle current limiting.
VDD input. A separate pin, PVDD, not connected
The current limit threshold may be set to any value
internally to the VDD supply rail provides power for
between 0.25 V and 1.0 V by applying the desired
the output drivers. In all applications the same bus
threshold voltage to the current limit (ILIM) pin. If the
voltage supplies the two pins. It is recommended that
ILIM pin is left floating, the internal current limit
a low value of resistance be placed between the two
threshold will be 0.5 volts. When the CS level is
pins so that the local capacitance on each pin forms
greater than the I
LIM
voltage minus 25 mV, the output
low pass filters to attenuate any switching noise that
of the driver is forced low and the current limit flag
may be on the bus.
(CLF) is set high. The CLF signal is latched high until
Although quiescent VDD current is low, total supply the device receives the next rising edge on either of
current depends on the gate drive output current the IN pins.
required for capacitive load and switching frequency.
When the CS voltage is below I
LIM
, the driver output
Total VDD current is the sum of quiescent VDD
follows the PWM input. The CLF digital output flag
current and the average OUT current. Knowing the
can be monitored by the host controller to determine
operating frequency and the MOSFET gate charge
when a current limit event occurs and to then apply
(Q
G
), average OUT current can be calculated from:
the appropriate algorithm to obtain the desired
I
OUT
= Q
G
x f, where f is frequency. current limit profile (i.e. straight time, fold back,
hickup or latch-off).
For the best high-speed circuit performance, VDD
bypass capacitors are recommended to prevent A benefit of this local protection feature is that the
noise problems. A 4.7-µF ceramic capacitor should UCD7K devices can protect the power stage if the
be located closest to the VDD and the AGND software code in the digital controller becomes
connection. In addition, a larger capacitor with corrupted. If the controller’s PWM output stays high,
relatively low ESR should be connected to the PVDD the local current sense circuit turns off the driver
and PGND pin, to help deliver the high current peaks output when an over-current event occurs. The
to the load. The capacitors should present a low system would then likely go into retry mode because
impedance characteristic for the expected current most DSP and microcontrollers have on-board
levels in the driver application. The use of surface watchdog, brown-out, and other supervisory
mount components for all bypass capacitors is highly peripherals to restart the device in the event that it is
recommended. not operating properly. But these peripherals typically
do not react fast enough to save the power stage.
The UCD7K’s local current limit comparator provides
the required fast protection for the power stage.
All devices in the UCD7K family are capable of
supplying a regulated 3.3-V rail to power various The CS threshold is 25 mV below the I
LIM
voltage. If
types of external loads such as a microcontroller or the user attempts to command zero current while the
an ASIC. The onboard linear voltage regulator is CS pin is at ground the CLF flag will latch high until
capable of sourcing up to 10 mA of current. For the IN pin receives a pulse. At start-up it is
normal operation, place 0.22-µF of ceramic necessary to ensure that the ILIM pin will always be
capacitance between the 3V3 pin to the AGND pin. greater than the CS pin for the handshaking to work
as described below. If for any reason the CS pin
comes to within 25 mV of the ILIM pin during
start-up, then the CLF flag will be latched high and
The input pins are high impedance digital inputs
the digital controller must poll the UCD7K device, by
capable of accepting 3.3-V logic level signals up to 2
sending it a narrow IN pulse. If a fault condition is not
MHz. There is an internal Schmitt Trigger comparator
present the IN pulse will reset the CLF signal to low
which isolates the internal circuitry from any external
indicating that the UCD7K device is ready to process
noise.
power pulses.
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Handshaking Drive Current and Power Requirements
Driver Output
E +
1
2
CV
2
P + CV2 f
Source/Sink Capabilities During Miller Plateau
P + 2.2 nF 122 300 kHz + 0.095 W
I +
P
V
+
0.095 W
12 V
+ 7.9 mA
Operational Waveforms
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
The UCD7K family of devices have a built-in The UCD7K family of drivers can deliver high current
handshaking feature to facilitate efficient start-up of into a MOSFET gate for a period of several hundred
the digitally controlled power supply. At start-up the nanoseconds. High peak current is required to turn
CLF flag is held high until all the internal and external the device ON quickly. Then, to turn the device OFF,
supply voltages of the UCD7K device are within their the driver is required to sink a similar amount of
operating range. Once the supply voltages are within current to ground. This repeats at the operating
acceptable limits, the CLF goes low and the device frequency of the power device.
will process input drive signals. The micro-controller
Reference [1] discusses the current required to drive
should monitor the CFL flag at start-up and wait for
a power MOSFET and other capacitive-input
the CLF flag to go LOW before sending power
switching devices.
pulses to the UCD7K device.
When a driver device is tested with a discrete,
capacitive load it is a fairly simple matter to calculate
the power that is required from the bias supply. The
The high-current output stage of the UCD7K device
energy that must be transferred from the bias supply
family is capable of supplying ±4-A peak current
to charge the capacitor is given by:
pulses and swings to both PVDD and PGND. The
driver outputs follow the state of the IN pin provided
that the VDD and 3V3 voltages are above their
respective under-voltage lockout threshold.
where C is the load capacitor and V is the bias
The drive output utilizes Texas Instruments'
voltage feeding the driver.
TrueDrive™ architecture, which delivers rated
There is an equal amount of energy transferred to
current into the gate of a MOSFET when it is most
ground when the capacitor is discharged. This leads
needed, during the Miller plateau region of the
to a power loss given by the following:
switching transition providing efficiency gains.
TrueDrive™ consists of pullup pulldown circuits with
bipolar and MOSFET transistors in parallel. The peak
where f is the switching frequency.
output current rating is the combined current from
the bipolar and MOSFET transistors. This hybrid
This power is dissipated in the resistive elements of
output stage also allows efficient current sourcing at
the circuit. Thus, with no external resistor between
low supply voltages.
the driver and gate, this power is dissipated inside
the driver. Half of the total power is dissipated when
Each output stage also provides a very low
the capacitor is charged, and the other half is
impedance to overshoot and undershoot due to the
dissipated when the capacitor is discharged.
body diode of the external MOSFET. This means
that in many cases, external-schottky-clamp diodes
With V
DD
= 12 V, C
LOAD
= 2.2 nF, and f = 300 kHz,
are not required.
the power loss can be calculated as:
Large power MOSFETs present a large load to the
With a 12-V supply, this would equate to a current of:
control circuitry. Proper drive is required for efficient,
reliable operation. The UCD7K drivers have been
optimized to provide maximum drive to a power
MOSFET during the Miller plateau region of the
switching transition. This interval occurs while the
drain voltage is swinging between the voltage levels
Figure 24 shows the circuit performance achievable
dictated by the power topology, requiring the
with the output driving a 10-nF load at 12-V V
DD
. The
charging/discharging of the drain-gate capacitance
input pulsewidth (not shown) is set to 200 ns to show
with current supplied or removed by the driver
both transitions in the output waveform. Note the
device. See Reference [1]
linear rising and falling edges of the switching
waveforms. This is due to the constant output current
characteristic of TrueDrive™ stage as opposed to
the resistive output impedance of traditional
MOSFET-based gate drivers.
8
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Thermal Information
Circuit Layout Recommendations
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
Note that the PowerPAD™ is not directly connected
to any leads of the package. However, it is
The useful range of a driver is greatly affected by the
electrically and thermally connected to the substrate
drive power requirements of the load and the thermal
which is the ground of the device. The PowerPad™
characteristics of the device package. In order for a
should be connected to the quiet ground of the
power driver to be useful over a particular
circuit.
temperature range the package must allow for the
efficient removal of the heat produced while keeping
the junction temperature within rated limits. The
UCD7K family of drivers is available in PowerPAD™ In a power driver operating at high frequency, it is
TSSOP and QFN/DFN packages to cover a range of critical to minimize stray inductance to minimize
application requirements. Both have an exposed pad overshoot/undershoots and ringing. The low output
to enhance thermal conductivity from the impedance of these drivers produces waveforms with
semiconductor junction. high di/dt. This tends to induce ringing in the
parasitic inductances. It is advantageous to connect
As illustrated in Reference [2], the PowerPAD™
the driver device close to the MOSFETs. It is
packages offer a leadframe die pad that is exposed
recommended that the PGND and the AGND pins be
at the base of the package. This pad is soldered to
connected to the PowerPad™ of the package with a
the copper on the PC board (PCB) directly
thin trace. It is critical to ensure that the voltage
underneath the device package, reducing the T
JC
potential between these two pins does not exceed
down to 2.07°C/W. The PC board must be designed
0.3 V. The use of schottky diodes on the outputs to
with thermal lands and thermal vias to complete the
PGND and PVDD is recommended when driving
heat removal subsystem, as summarized in
gate transformers.
Reference [3].
9
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Additional Application Circuits
Isolation
Amplifier
COMMUNICATION
(Programming & Status Reporting)
141
13
8
PVDD
VDD
CS
10OUT2
3
4
2
5
6
IN1
AGND
3V3
IN2
CLF
7
UCD7201PWP
11OUT1
9PGND
12
NC
ILIM
NC
Bias Supply
Bias Winding
VIN
VOUT
DIGITAL
CONTROLLER
GND
PWMA
ADC4
INTERRUPT or CCR
PWMB
ADC3
VCC
PWM or GPIO
ADC1
ADC2
CS
XFMR
Gate Drive
Transformer
(3 winding)
15
16
14
2
4
141
13
8
PVDD
VDD
CS
10OUT2
3
4
2
5
6
IN1
AGND
3V3
IN2
CLF
7
UCD7201
11OUT1
9PGND
12
NC
ILIM
NC
Bias Supply
Bias Winding
VIN
VOUT
13
UCC28089
GND
OUTA
OUTB
VDD
DIS
CS
3
1 SYNC
CT
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
Figure 2 shows the UCD7201 in a half-bridge converter design. The digital controller is performing the output
voltage compensation and all supervisory functions. The isolation amplifier is made up of a linear opto-coupler
configured for a gain of 1/10, so the output voltage is transformed to a level comparable with the ADC of the
digital controller.
Figure 2. Half-Bridge Converter
Figure 3 shows the UCD7201 in an analog only implementation of an intermediate bus converter. The ILIM pin
of the UCD7201 is exponentially increased at start-up, which minimizes overshoot on the output voltage. The
UCC28089 is a push-pull controller with fixed dead-time. The UCC28089 operates at a fixed duty cycle close to
100% so the circuit acts like a DC transformer linearly transforming the input voltage via the turns ratio of the
transformer.
Figure 3. Intermediate Bus Converter
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Typical Characteristics
−50 50 125−25 0 25 75 100
3.24
3.26
3.28
3.30
3.32
3.34
3.36
t − Temperature − °C
3V3 − Reference Voltage − V
−50 50
5.0
4.5
2.5
2.0
1.5
0.5
0.0
−25 0 25 75 100
4.0
1.0
3.5
3.0
UVLO on
UVLO off
UVLO hysteresis
t − Temperature − °C
125
V
UVLO
− UVLO Thresholds − V
−50 50 125−25 0 25 75 100
20.0
20.5
21.0
21.5
22.0
22.5
23.0
t − Temperature − °C
I
SHORT_CKT
− Short Circuit Current − mA
VDD = 4.75 V
VDD = 12 V
0 1000 1500500
0
20
40
60
80
100
120
140
160
f − Frequency − kHz
I
DD
− Supply Current − mA
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
UVLO THRESHOLDS 3V3 REFERENCE VOLTAGE
vs vs
TEMPERATURE TEMPERATURE
Figure 4. Figure 5.
3V3 SHORT CIRCUIT CURRENT SUPPLY CURRENT
vs vs
TEMPERATURE FREQUENCY (V
DD
= 5 V)
Figure 6. Figure 7.
11
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0
40
80
120
160
200
240
280
320
0 500
1000
1500
f − Frequency − kHz
I
DD
− Supply Current − mA
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
0
40
80
120
160
200
240
280
0 500
1000
1500
f − Frequency − kHz
I
DD
− Supply Current − mA
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
0
50
100
150
200
250
300
350
400
450
500
0
500
1000
1500
f − Frequency − kHz
I
DD
− Supply Current − mA
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
0
50
100
150
200
250
300
350
400
0
500
1000
1500
f − Frequency − kHz
I
DD
− Supply Current − mA
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
SUPPLY CURRENT SUPPLY CURRENT
vs vs
FREQUENCY (V
DD
= 8 V) FREQUENCY (V
DD
= 10 V)
Figure 8. Figure 9.
SUPPLY CURRENT SUPPLY CURRENT
vs vs
FREQUENCY (V
DD
= 12 V) FREQUENCY (V
DD
= 15 V)
Figure 10. Figure 11.
12
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−50 50 125−25 0 25 75 100
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
16.0
18.0
TJ − Temperature − °C
t
R,
t
F
− Rise and Fall Times − ns
tR = Rise Time
tF = Fall Time
C
LOAD
= 2.2 nF
−50 50 125−25 0 25 75 100
0.0
0.5
1.0
1.5
2.0
2.5
TJ − Temperature − °C
V
INPUT
− Input Voltage − V
Input Rising
Input Falling
5
15
25
35
45
55
65
5 7.5 10 12.5 15
VDD − Supply Voltage − V
t
R
− Rise Time − ns
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
5
10
15
20
25
30
35
40
45
5 7.5 10 12.5 15
VDD − Supply Voltage − V
t
F
− Fall Time − ns
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
INPUT THRESHOLDS OUTPUT RISE TIME AND FALL TIME
vs vs
TEMPERATURE TEMPERATURE (V
DD
= 12 V)
Figure 12. Figure 13.
RISE TIME FALL TIME
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 14. Figure 15.
13
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5
10
15
20
25
5 7.5 10 12.5 15
VDD − Supply Voltage − V
t
PD
− Propagation Delay, Falling − ns
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
0
5
10
15
20
5 7.5 10 12.5 15
VDD − Supply Voltage − V
t
PD
− Propagation Delay, Rising − ns
C
LOAD
= 10 nF
C
LOAD
= 4.7 nF
C
LOAD
= 2.2 nF
C
LOAD
= 1 nF
−50 50 125−25 0 25 75 100
0.51
0.52
0.53
0.54
0.55
0.56
0.57
0.58
0.59
TJ − Temperature − °C
V
CS
− Current Limit Threshold − V
−50 50 125−25 0 25 75 100
0
5
10
15
20
25
30
35
40
TJ − Temperature − °C
t
PD
− CS to OUTx Propagation Delay − ns
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
IN to OUTx PROPAGATION DELAY RISING IN to OUTx PROPAGATION DELAY FALLING
vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
Figure 16. Figure 17.
DEFAULT CURRENT LIMIT THRESHOLD CS TO OUTx PROPAGATION DELAY
vs vs
TEMPERATURE TEMPERATURE
Figure 18. Figure 19.
14
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−50 50 125−25 0 25 75 100
0
5
10
15
20
25
30
35
TJ − Temperature − °C
t
PD
− Propagation Delay − ns
−50 50−25 0 25 75 100
0
5
10
15
20
25
30
35
40
45
50
TJ − Temperature − °C
t
PD
− CS to CLF Propagation Delay − ns
125
t − Time − 40 µs/div
VDD (2 V/div)
OUTx (2 V/div)
3V3 (2 V/div)
t − Time − 40 µs/div
VDD (2 V/div)
OUTx (2 V/div)
3V3 (2 V/div)
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
CS TO CLF PROPAGATION DELAY IN TO OUT PROPAGATION DELAY
vs vs
TEMPERATURE TEMPERATURE
Figure 20. Figure 21.
START-UP BEHAVIOR AT V
DD
= 12 V (INPUT TIED TO SHUT DOWN BEHAVIOR AT V
DD
= 12 V (INPUT TIED TO
3V3) 3V3)
Figure 22. Figure 23.
15
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t − Time − 40 µs/div
VDD (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
t − Time − 40 µs/div
VDD (2 V/div)
3V3 (2 V/div)
OUTx (2 V/div)
t − Time − 40 ns/div
Output Voltage − 2 V/div
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
START-UP BEHAVIOR AT V
DD
= 12 V (INPUT SHORTED SHUT DOWN BEHAVIOR AT V
DD
= 12 V (INPUT SHORTED
TO GND) TO GND)
Figure 24. Figure 25.
OUTPUT RISE AND FALL TIME (V
DD
= 12 V, C
LOAD
= 10
nF)
Figure 26.
16
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REFERENCES
RELATED PRODUCTS
REVISION HISTORY
UCD7201
SLUS645C – FEBRUARY 2005 – REVISED DECEMBER 2006
1. Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.
2. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
3. Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004
TEMPERATURE RANGE CURRENT SENSE LIMIT PER CHANNEL FEATURES
UCD7100 Single Low Side ±4-A Driver with Independent CS 3V3, CS
(1) (2)
UCD7200 Dual Low Side ±4-A Drivers with Independent CS 3V3, CS
(1) (2)
UCD7230 ±4-A Synchronous Buck Driver with CS 3V3, CS
(1) (2)
UCD7500 Single Low Side ±4-A Driver with CS and 110-V High Voltage Startup 3v3, CS, HVS110
(1) (2) (3)
UCD7600 Dual Low Side ±4-A Drivers with Independent CS and 110-V High Voltage Startup 3V3, CS, HVS110
(1) (2) (3)
Dual Low Side ±4-A Drivers with Common CS and 110-V High Voltage Startup 3V3, CCS, HVS110
UCD7601
(1) (4) (3)
UCD9110 Digital Power Controller for High Performance Single-loop Applications
UCD9501 Digital Power Controller for High Performance Multi-Loop Applications
(1) 3V3 = 3.3-V linear regulator.
(2) CS = current sense and current limit function.
(3) HVS110 = 110-V high voltage startup circuit.
(4) CCS = Common current sense and current limit function.
DATE REVISION CHANGE DESCRIPTION
3/4/05 SLUS645 Initial release of preliminary datasheet.
4/1/05 SLUS645A Updated packaging information.
7/14/05 SLUS645B Initial release of production datasheet. Updated specification and application information.
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PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
UCD7201PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
UCD7201PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
UCD7201PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
UCD7201PWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS &
no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
UCD7201RSAR PREVIEW QFN RSA 16 3000 TBD Call TI Call TI
UCD7201RSAT PREVIEW QFN RSA 16 250 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
5-Feb-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
UCD7201PWPR HTSSOP PWP 14 2000 330.0 12.4 6.67 5.4 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCD7201PWPR HTSSOP PWP 14 2000 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
Pack Materials-Page 2
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