Texas Instruments UCC3809PW-1, UCC3809P-1, UCC3809N-2, UCC3809N-1, UCC3809DTR-2 Datasheet

...

Economy Primary Side Controller

application

INFO

available

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

FEATURES

User Programmable Soft Start With

•

Active Low Shutdown

User Programmable Maximum Duty

•

Cycle

Accessible 5V Reference

•

Undervoltage Lockout

•

Operation to 1MHz

•

0.4A Source/0.8A Sink FET Driver

•

Low 100µA Startup Current

•

PART

NUMBER

UCCX809-1 10V 8V UCCX809-2 15V 8V

TURN ON

THRESHOLD

TURN OFF

THRESHOLD

DESCRIPTION

The UCC3809 family of BCDMOS economy low power integrated circuits contains all the control and drive circuitry required for off-line and isolated DC-to-DC fixed frequency current mode switching power supplies with minimal external parts count. Internally implemented circuits include undervoltage lockout featuring startup current less than 100µA, a user ac cessible voltage reference, logic to ensure latched operation, a PWM com parator, and a totem pole output stage to sink or source peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off state.

Oscillator frequency and maximum duty cycle are programmed with two resistors and a capacitor. The UCC3809 family also features full cycle soft start.

The family has UVLO thresholds and hysteresis levels for off-line and DC-to-DC systems as shown in the table to the left.

The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP (N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and MSOP packages make the device ideal for applications where board space and height are at a premium.

TYPICAL APPLICATION DIAGRAM

FEEDBACK

CURRENT

SENSE

START

SLOPE

COMP

DISABLE

NOISE

FILTER

RT1

RT2

+5V

6µA

0.5V

OSC

17.5V

REF

UDG-99036

OUT

VDD

OUT

GND

CLK

PWM LATCH

REF

15/8V 10/8V

UVLO

SLUS166A - NOVEMBER 1999

ABSOLUTE MAXIMUM RATINGS*

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA

VDD

(tpw < 1µs and Duty Cycle < 10%). . . . . . . . –0.4A to 0.8A

OUT

RT1, RT2, SS . . . . . . . . . . . . . . . . . . . . . . –0.3V to REF + 0.3V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –15mA

REF

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C

* Values beyond which damage may occur.

All voltages are with respect to ground unless otherwise stated. Currents are positive into, negative out of the specified termi nal. Consult Packaging Section of Databook for thermal limita tions and considerations of packages.

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

CONNECTION DIAGRAM

SOIC-8, DIL-8 (Top View) D, N and J Packages

TSSOP-8 (Top View) PW Package

RT1

RT2

REF

VDD

OUT

GND

MSOP-8 (Top View) P Package

RT1

RT2

REF

VDD

OUT

GND

ORDERING INFORMATION

Temperature Range Available Packages

UCC1809-X –55°C to +125°C J UCC2809-X –40°C to +85°C N, D, P, PW UCC3809-X 0°C to +70°C N, D, P, PW

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 12V. T

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply Section

VDD Clamp I I

VDD

Starting 100 µA

VDD

Undervoltage Lockout Section

Start Threshold (UCCx809-1) 9.4 10.4 V UVLO Hysteresis (UCCx809-1) 1.65 V Start Threshold (UCCx809-2) 14.0 15.6 V UVLO Hysteresis (UCCx809-2) 6.2 V

Voltage Reference Section

Output Voltage I Line Regulation VDD = 10V to 15V 2 mV Load Regulation I

Comparator Section

Comparator Threshold 0.9 0.95 1 V OUT Propagation Delay (No Load) V

= 10mA 16 17.5 19 V

VDD

No Load 600 900 µA

= 0mA 4.75 5 5.25 V

REF

= 0mA to 5mA 2 mV

REF

Output Off –100 nA

= 0.8V to 1.2V at TR= 10ns 50 100 ns

UCC 809 –

A=TJ

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD = 12V. T

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Soft Start Section

Low VDD = 7.5V, ISS = 200µA 0.2 V

Shutdown Threshold 0.44 0.48 0.52 V

Oscillator Section

Frequency RT1 = 10k, RT2 = 4.32k, CT = 820pF 90 100 110 kHz Frequency Change with Voltage VDD = 10V to 15V 0.1 %/V C

Peak Voltage 3.33 V

Valley Voltage 1.67 V

Peak to Peak Voltage 1.54 1.67 1.80 V

Output Section

Output V Output V Output Low Voltage During UVLO I Minimum Duty Cycle V Maximum Duty Cycle 70 % Rise Time C Fall Time C

Low I

SAT

High I

SAT

VDD = 16V, VSS = 0V; –40°C to +85°C –4.9 –7.0 –9.1 µA VDD = 16V, V

= 80mA (dc) 0.8 1.5 V

OUT

= –40mA (dc), VDD – OUT 0.8 1.5 V

OUT

= 20mA (dc) 1.5 V

OUT

= 2V 0 %

= 1nF 35 ns

OUT

= 1nF 18 ns

OUT

SS = 0V; < –40°C; >+85°C –4.0 –7.0 –10.0 µA

A=TJ

PIN DESCRIPTIONS

FB: This pin is the summing node for current sense

feedback, voltage sense feedback (by optocoupler) and slope compensation. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250Ω on resistance NMOS FET during PWM off time and offers effective leading edge blanking set by the RC time constant of the feedback resistance from current sense resistor to FB input and the high frequency filter capacitor capacitance at this node to GND.

GND: Reference ground and power ground for all functions.

OUT: This pin is the high current power driver output. A minimum series gate resistor of 3.9

is recommended to limit the gate drive current when operating with high bias voltages.

REF: The internal 5V reference output. This reference is buffered and is available on the REF pin. REF should be bypassed with a 0.47µF ceramic capacitor.

RT2: This pin connects to timing resistor RT2 and controls the negative ramp time of the internal oscillator (Tf = 0.74 • (C

+ 27pF) • RT2). The negative threshold

of the internal oscillator is sensed through inactive timing resistor RT1 which connects to pin RT1 and timing capacitor C

SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal 6µA current source. Under normal soft start SS is discharged to at least 0.4V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 5V voltage reference also goes low and I < 100µA.

VDD: The power input connection for this device. This pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1µF ceramic capacitor.

VDD

RT1: This pin connects to timing resistor RT1 and controls the positive ramp time of the internal oscillator (Tr = 0.74 • (C

+ 27pF) • RT1). The positive threshold

of the internal oscillator is sensed through inactive timing resistor RT2 which connects to pin RT2 and timing capacitor C

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