Datasheet UCC3921N, UCC3921DTR, UCC3921D, UCC2921DTR, UCC2921D Datasheet (Texas Instruments)

3/98

FEATURES

• Precision Fault Threshold

• Programmable:

Average Power Limiting, Linear
Current Control, Overcurrent Limit
and Fault Time

• Fault Output Indication Signal

• Automatic Retry Mode or Latched

Operation Mode

• Shutdown Control

• Undervoltage Lockout

• 250µs Glitch Filter on the SDFLTCH

pin

• 8-Pin DIL and SOIC

Latchable Negative Floating Hot Swap Power Manager

BLOCK DIAGRAM

UCC1921
UCC2921
UCC3921

UDG-99052

DESCRIPTION

The UCC3921 family of negative floating hot swap power managers pro­vides complete power management, hot swap, and fault handling capa­bility. The IC is referenced to the negative input voltage and is powered
through an external resistor connected to ground, which is essentially a
current drive as opposed to the traditional voltage drive. The onboard
10V shunt regulator protects the IC from excess voltage and serves as a
reference for programming the maximum allowable output sourcing cur­rent during a fault. All control and housekeeping functions are integrated
and externally programmable. These include the fault current level, maxi­mum output sourcing current, maximum fault time, selection of Retry or
Latched mode, soft start time, and average power limiting. In the event of
a constant fault, the internal timer will limit the on time from less than

0.1% to a maximum of 3% duty cycle. The duty cycle modulation de­pends on the current into PL, which is a function of the voltage across
the FET, thus limiting average power dissipation in the FET. The fault
level is fixed at 50mV across the current sense amplifier to minimize total

(continued)

2

UCC1921
UCC2921
UCC3921

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, TA= 0°C to 70°C for the UCC3921 and –40°C to 85°C

for the UCC2921, and –55°C to 125°C for the UCC1921; I

VDD

= 2mA, CT= 1nF (the minimum allowable value), there is no

resistor connected between the SDFLTCH and VSS pins. TA=TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VDD Section

IDD 12mA
Regulator Voltage I

SOURCE

= 2mA 9 9.5 10.0 V

I

SOURCE

= 10mA 9.15 9.6 10.15 V

UVLO Off Voltage 678V

Fault Timing Section

Overcurrent Threshold T

J

= 25°C 47.5 50 53.5 mV

Over Operating Temperature 46 50 53.5 mV
Overcurrent Input Bias 50 500 nA
CT Charge Current V

CT

= 1V, IPL= 0 –50 –36 –22 µA

Overload Condition, V

SENSE-VIMAX

= 300mV –1.7 –1.2 –0.7 mA
CT Discharge Current VCT= 1V, IPL= 0 0.6 1 1.5 µA
CT Fault Threshold 2.2 2.45 2.6 V
CT Reset Threshold 0.41 0.49 0.57 V
Output Duty Cycle Fault Condition, I

PL

= 0 1.7 2.7 3.7 %

CONNECTION DIAGRAM

DIL-8 , SOIC-8 (Top View)
NorJ,DPackages

ABSOLUTE MAXIMUM RATINGS

IVDD..........................................50mA

SDFLTCH Current ..............................10mA

PL Current ....................................10mA

IMAX Input Voltage ..............................VDD

Storage Temperature ...................−65°C to +150°C

Junction Temperature...................–55°C to +150°C

Lead Temperature (Soldering, 10 sec.) .............+300°C

All voltages are with respect to VSS(the most negative voltage).
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of Databook for thermal limitations and
considerations of packages.

dropout. The fault current level is set with an external
current sense resistor, while the maximum allowable
sourcing current is programmed with a voltage divider
from VDD to generate a fixed voltage on IMAX. The cur­rent level, when the output acts as a current source, is
equal to V

IMAX/RSENSE. If desired, a controlled current

start up can be programmed with a capacitor on IMAX.
When the output current is below the fault level, the out-

put device is switched on. When the output current ex­ceeds the fault level, but is less than the maximum
sourcing level programmed by IMAX, the output remains
switched on, and the fault timer starts charging C

T. Once

C

T charges to 2.5V, the output device is turned off and

performs a retry some time later (provided that the se­lected mode of operation is Automatic Retry Mode).
When the output current reaches the maximum sourcing
current level, the output acts as a current source, limiting
the output current to the set value defined by IMAX.

Other features of the UCC3921 include undervoltage
lockout, 8-pin Small Outline (SOIC) and Dual-In-Line
(DIL) packages, and a Latched Operation Mode option,
in which the output is latched off once C

T charges to

2.5V and stays off until either SDFLTCH is toggled (for
greater than 1ms) or the IC is powered down and then
back up.

DESCRIPTION (continued)

3

UCC1921
UCC2921
UCC3921

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, TA= 0°C to 70°C for the UCC3921 and –40°C to 85°C

for the UCC2921, and –55°C to 125°C for the UCC1921; I

VDD

= 2mA, CT= 1nF (the minimum allowable value), there is no

resistor connected between the SDFLTCH and VSS pins. TA=TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Output Section

Output High Voltage I

OUT

= 0mA 8.5 10 V

I

OUT

= –1mA 6 8 V

Output Low Voltage I

OUT

= 0mA, V

SENSE–VIMAX

= 100mV 0 10 mV

I

OUT

= 2mA, V

SENSE–VIMAX

= 100mV 200 600 mV

Linear Amplifier Section

Sense Control Voltage V

IMAX

= 100mV 85 100 115 mV

V

IMAX

= 400mV 370 400 430 mV

Input Bias 50 500 nA

Power Limiting Section

V

SENSE Regulator Voltage I

PL

=64µA 4.35 4.85 5.35 V

Duty Cycle Control IPL=64µA 0.6 1.2 1.7 %

IPL= 1mA 0.045 0.1 0.17 %

Overload Section

Delay to Output Note 1 300 500 ns
Output Sink Current V

SENSE–VIMAX

= 300mV 40 100 mA

Threshold Relative to IMAX 140 200 260 mV

Shutdown/Fault/Latch Section

Shutdown Threshold 3 5 VDD+1 V
Input Current V

SDFLTCH

= 5V 50 110 250 µA
Filter Delay Time (Delay to Output) 250 500 1000 µs
Fault Output High 6 9.5 V

I

SDFLTCH

= –100µA 5 8.5 V
Fault Output Low 010mV
Output Duty Cycle Fault Condition, I

PL

= 0 1.7 2.7 3.7 %

I

SDFLTCH

= –100µA, Fault Condition, IPL=0 0 %

Note 1: Guaranteed by design. Not 100% tested in production.

PIN DESCRIPTIONS

CT: A capacitor is connected to this pin in order to set

the fault time. The fault time must be longer than the time
to charge external load capacitance. The fault time is
defined as:

T

C

I

FAULT

T

CH

=

•

2

where ICH =36µA+IPL, and IPL is the current into the
power limit pin. Once the maximum fault time is reached
the output will shutdown for a time given by:

TC

SD T

=• •

210

6

IMAX: This pin programs the maximum allowable
sourcing current. Since VDD is a regulated voltage, a
voltage divider can be derived from VDD to generate the
program level for IMAX. The current level at which the
output appears as a current source is equal to the

voltage on IMAX over the current sense resistor. If
desired, a controlled current start up can be programmed
with a capacitor on IMAX, and a programmed start delay
can be achieved by driving the shutdown with an open
collector/drain device into an RC network.

OUT: This pin provides gate output drive to the MOSFET
pass element.

PL: This feature ensures that the average MOSFET
power dissipation is controlled. A resistor is connected
from this pin to the drain of the NMOS pass element.
When the voltage across the NMOS exceeds 5V, current
will flow into the PL pin which adds to the fault timer
charge current, reducing the duty cycle from the 3%
level. When I

PL

>>36µA, then the average MOSFET

power dissipation is given by:

P avg IMAX R

MOSFET PL

=•••

−

110

6

4

UCC1921
UCC2921
UCC3921

Figure 1. Fault Timing Circuitry for the UCC3921, Including Power Limit Overload

APPLICATION INFORMATION

UDG-96275-1

SENSE: Input voltage from the current sense resistor.
When there is greater than 50mV across this pin with
respect to VSS, then a fault is sensed, and C

T

starts to

charge.
SDFLTCH: This pin provides fault output indication,

shutdown control, and operating mode selection.
Interface into and out of this pin is usually performed
through level shift transistors. When open, and under a
non-fault condition, this pin pulls to a low state with
respect to VSS. When a fault is detected by the fault
timer, or undervoltage lockout, this pin will drive to a high
state with respect fo VSS, indicating the NMOS pass
element is OFF. When > 250µA is sourced into this pin
for > 1ms, it drives high causing the output to disable the
NMOS pass device.

If an 5k < R

LATCH

< 250kΩ resistor is placed from this pin
to VSS, then the latched operating mode will be invoked.
Upon the occurrence of a fault, under the latched mode
of operation, once the C

T

capacitor charges up to 2.5V
the NMOS pass element latches off. A retry will not
periodically occur. To reset the latched off device, either
SDFLTCH is toggled high for a duration greater than 1ms
or the IC is powered down and then up.

VDD: Current driven with a resistor to a voltage approxi­mately 10V more positive than VSS. Typically a resistor is
connected to ground. The 10V shunt regulator clamps
VDD approximately 10V above VSS, and is also used as
an output reference to program the maximum allowable
sourcing current.

VSS: Ground reference for the IC and the most negative
voltage available.

PIN DESCRIPTIONS (continued)

5

UCC1921
UCC2921
UCC3921

Figure 2. Retry Operation Mode

UDG-96276

t0: Safe condition. Output current is nominal, output
voltage is at the negative rail, VSS.

t1: Fault control reached. Output current rises above
the programmed fault value, CT begins to charge at
~36µA.

t2: Maximum current reached. Output current reaches
the programmed maximum level and becomes a con­stant current with value I

MAX

.

t3: Fault occurs. CT has charged to 2.5V, fault output
goes high, the FET turns off allowing no output current
to flow, V

OUT

floats up to ground.

t4: Retry. CT has discharged to 0.5V, but fault current is
still exceeded, CT begins charging again, FET is on,
V

OUT

pulled down towards VSS.

t5 = t3: Illustrates 3% duty cycle.
t6 = t4: Retry. CT has discharged to 0.5V, but fault is

still exceeded, CT begins charging again, FET is on,
V

OUT

pulled down towards VSS.

t7: Output short circuit. If VOUT is short circuited to
ground, CT charges at a higher rate depending upon
the values for VSS and R

PL

.
t8: Fault occurs. Output is still short circuited, but the

occurrence of a fault turns the FET off so no current is
conducted.

t9 = t4: Output short circuit released, still in fault mode.
t10 = t0: Fault released, safe condition. Return to nor-

mal operation of the hot swap power manager.

APPLICATION INFORMATION (continued)

Figure 1 shows the detailed circuitry for the fault timing
function of the UCC3921. For the time being, we will dis­cuss a typical fault mode, therefore, the overload com­parator, and current source I3 does not work into the
operation. Once the voltage across the current sense re­sistor, R

S, exceeds 50mV, a fault has occurred. This

causes the timing capacitor to charge with a combination
of 36µA plus the current from the power limiting amplifier.
The PL amplifier is designed to only source current into
the CT pin and to begin sourcing current once the volt­age across the output FET exceeds 5V. The current I

PL

is related to the voltage across the FET with the following
expression:

I

VV

R

PL

FET

PL

=

−

5

where V

FET

is the voltage across the NMOS pass device.
Later it will be shown how this feature will limit average
power dissipation in the pass device. Note that under a
condition where the output current is more than the fault
level, but less than the max level, V

OUT

≈ VSS (input

voltage), I

PL

= 0, the CT charging current is 36µA.

6

UCC1921
UCC2921
UCC3921

Figure 3. Latched Operation Mode: R

LATCH

= 82k

APPLICATION INFORMATION (cont.)

UDG-96277

t0: Safe condition. Output current is nominal, output
voltage is at the negative rail, VSS.

t1: Fault control reached. Output current rises above
the programmed fault value, CT begins to charge at
~36µA.

t2: Maximum current reached. Output current reaches
the programmed maximum level and becomes a con­stant current with value I

MAX

.

t3: Fault occurs. CT has charged to 2.5V, fault output
goes high as indicated by the SDFLTCH voltage. The
FET turns off allowing no output current to flow, V

OUT

floats up to ground, and since there is an 82kΩ resistor
from the SDFLTCH pin to VSS, the internal latchset sig­nal goes high.

t4: Since the user does not want the chip to LATCH off
during this cycle, he toggles SDFLTCH high for greater
than 1ms {t6 - t4 > 1ms}.

t5: The latchset signal is reset.
t6: Forcing of SDFLTCH is released after having been

applied for > 1ms.
t7: Retry (since the latchset signal has been reset to its’

low state) - CT has discharged to 0.5V, but fault current

is still exceeded, CT begins charging again, FET is on,
V

OUT

pulled down towards VSS.

t8 = t3: Fault occurs. CT has charged to 2.5V, fault out­put goes high as indicated by the SDFLTCH voltage,
the FET turns off allowing no output current to flow,
V

OUT

floats up to ground, and since there is an 82kΩ
resistor from SDFLTCH to VSS, the internal latchset
signal goes high.

t9: Output is latched off. Even though CT has dis­charged to 0.5V, there will not be a retry since the
latchset signal was allowed to remain high.

t10: Output remains latched off. CT has discharged all
thewayto0V.

t11: The output has been latched off for quite some
time. The user now wishes to reset the latched off out­put, thus toggling SDFLTCH high for greater than 1ms
{t13 - t11}.

t12 = t5: The latchset signal is reset.
t13: Forcing of SDFLTCH is released after having been

applied for > 1ms. The fault had also been released
during the time the output was latched off, safe condi­tion, return to normal operation of the hot swap power
manager.

7

UCC1921
UCC2921
UCC3921

During a fault, CT will charge at a rate determined by the
internal charging current and the external timing capaci­tor. Once CT charges to 2.5V, the fault comparator
switches and sets the fault latch. Setting of the fault latch
causes both the output to switch off and the charging
switch to open. CT must now discharge with the 1µA cur­rent source, I2, until 0.5V is reached. Once the voltage at
CT reaches 0.5V, the fault latch resets, which re-enables
the output and allows the fault circuitry to regain control
of the charging switch. If a fault is still present, the fault
comparator will close the charging switch causing the cy­cle to repeat. Under a constant fault, the duty cycle is
given by:

Duty Cycle

A

IA

PL

=

+

1

36

µ

µ

Average power dissipation in the pass element is given
by:

PVI

A

IA

FET FET MAX

PL

AVG

=••

+

1

36

µ

µ

Where V

FET

>>5V IPLcan be approximated as:

V

R

FET

PL

and where IPL>>36µA, the duty cycle can be approxi­mated as :

1

µAR

V

PL

FET

•

Therefore, the maximum average power dissipation in
the MOSFET can be approximated by:

PVI

AR

V

IMAX A R

FET FET MAX

PL

FET

PL

AVG

=••

•

=••

1

1

µ

µ

Notice that in the approximation, V

FET

cancels, thereby
limiting the average power dissipation in the NMOS pass
element.

Overload Comparator

The linear amplifier in the UCC3921 ensures that the
output NMOS does not pass more than I

MAX

(which is

V

IMAX/RSENSE

). In the event the output current exceeds

the programmed I

MAX

by 0.2V/R

SENSE,

which can only
occur if the output FET is not responding to a command
from the IC, CT will begin charging with I3, 1mA, and
continue to charge to approximately 8V. This allows a
constant fault to show up on the SDFLTCH pin, and also
since the voltage on CT will continue charging past 2.5V
in an overload fault mode, it can be used for detection of

output FET failure or to build redundancy into the sys­tem.

Determining External Component Values

To set R

VDD

(see Fig. 4) the following must be achieved:

V

R

V

RR

mA

IN

VDD

min

>

+

+

10

12

2

In order to estimate the minimum timing capacitor, CT,
several things must be taken into account. For example,
given the schematic in Figure 4 as a possible (and at this
point, a standard) application, certain external compo­nent values must be known in order to estimate C

TMIN

.

Now, given the values of C

OUT

, Load, R

SENSE,VSS

, and
the resistors determining the voltage on the IMAX pin,
the user can calculate the approximate startup time of
the node V

OUT.

This startup time must be faster than the
time it takes for CTto charge to 2.5V (relative to VSS),
and is the basis for estimating the minimum value of C

T

.
In order to determine the value of the sense resistor,
R

SENSE

, assuming the user has determined the fault cur-

rent, R

SENSE

can be calculated by:

R

mV

I

SENSE

FAULT

=

50

Next, the variable I

MAX

must be calculated. I

MAX

is the
maximum current that the UCC3921 will allow through
the transistor, M1, and it can be shown that during
startup with an output capacitor the power MOSFET, M1,
can be modeled as a constant current source of value
I

MAX

where

I

V

R

MAX

IMAX

SENSE

=

where V

IMAX

= voltage on pin IMAX.

Given this information, calculation of the startup time is
now possible via the following:

APPLICATION INFORMATION (continued)

Figure 4.

UDG-96278

8

UCC1921
UCC2921
UCC3921

Current Source Load:

T

CV

II

START

OUT SS

MAX LOAD

=

•

−

Resistive Load:

T

CR n

IR

IR V

START

OUT OUT

MAX OUT

MAX OUT SS

=

••

•

•−













l

Once T

START

is calculated, the power limit feature of the
UCC3921 must be addressed and component values de­rived. Assuming the user chooses to limit the maximum

allowable average power that will be associated with the
hot swap power manager, the power limiting resistor,
R

PL, can be easily determined by the following:

R

Pavg

AI

PL

FET

MAX

=

•1µ

where a minimum RPLexists

defined by

R

V

mA

PL

SS

min

=

5

(Refer to Figure 5).

Finally, after computing the aforementioned variables, the
minimum timing capacitor can be derived as such:

Current Source Load:

()

C

TARVV

R

T

START PL SS

PL

min

=

•••+−

•

372 10

10

µ

Resistive Load:

()

C

TARVVIR

R

R

T

START PL SS MAX OUT

PL

O

min

=

•••+−−•

•

+

•

336 5

5

3

µ

UT SS OUT

PL

VC

R

••

•

5

Level Shift Circuitry to Interface with SDFLTCH

Some type of circuit is needed to interface with the
UCC3921 via SDFLTCH, such as opto-couplers or level
shift circuitry. Figure 6 depicts one implementation of
level shift circuitry that could be used, showing compo­nent values selected for a typical –48V telecommunica­tions application. There are three communication
conditions which could occur; two of which are Hot Swap
Power Manager (HSPM) state output indications, and the
third being an External Shutdown.

1) When open, and under a non-fault condition,
SDFLTCH is pulled to a low state. In Figure 6, the N­channel level shift transistor is off, and the
FAULT OUT

signal is pulled to LOCAL VDD through

R3. This indicates that the HSPM is not faulted.

2) When a fault is detected by the fault timer or under­voltage lockout, this pin will drive to a high state, indi­cating that the external power FET is off. In Figure 6,
the N-channel level shift transistor will conduct, and
the FAULT OUT

signal will be pulled to a Schottky Di­ode voltage drop below LOCAL GND. This indicates
that the HSPM is faulted. The Schottky Diode is nec­essary to ensure that the FAULT OUT

signal does
not traverse too far below LOCAL GND, making fault
detection difficult.

APPLICATION INFORMATION (continued)

25

22.5

20

17.5

15

12.5

10

7.5

5

2.5

0

0 25 50 75 100 125 150 175 200

V

FET

R
R

PL
PL

=500k
=200k

R

PL =1M

R

PL =2M

R

PL =5M

R

PL =10M

R

PL= ∞

I=4AMAX

= ∞

Figure 5. Plot Average Power vs FET Voltage for
Increasing Values of R

PL

Figure 6. Possible Level Shift Circuitry to
Interface to the UCC3921, showing component
values selected for a typical telecom application.

UDG-96279

= ∞

9

UCC1921
UCC2921
UCC3921

If a5k<R

LATCH

< 250kΩ resistor is tied between
SDFLTCH & VSS, as optionally shown in Figure 6,
then the latched operating mode (described earlier)
will be invoked upon the occurrence of a fault.

3) To externally shutdown the HSPM, the SHUTDOWN
signal (typically held at LOCAL VDD) must be pulled
to LOCAL GND. Assuming SHUTDOWN is tied to
LOCAL GND, the P-channel level shift transistor will
conduct, driving SDFLTCH high (to roughly VDD plus
a diode). By sourcing > 250µA into SDFLTCH for >
1ms the output to the external power FET will be dis­abled. The current sourced into SDFLTCH must be

limited to 10mA or less: I

SDFLTCHMAX < 10mA.

SAFETY RECOMMENDATIONS

Although the UCC3921 is designed to provide system
protection for all fault conditions, all integrated circuits
can ultimately fail short. For this reason, if the UCC3921
is intended for use in safety critical applications where
UL



or some other safety rating is required, a redundant
safety device such as a fuse should be placed in series
with the external power FET. The UCC3921 will prevent
the fuse from blowing for virtually all fault conditions, in­creasing system reliability and reducing maintenance
cost, in addition to providing the hot swap benefits of the
device.

APPLICATION INFORMATION (continued)

Ω

Figure 7. Typical Telecommuications Application

(The “Negative Magnitude-Side” of the Supply is Switched in)

UDG-98053

10

UCC1921
UCC2921
UCC3921

UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. [phone] • FAX [phone]

Ω

Figure 8. Floating Positive Application

The “Ground-side” of the Supply is Switched In

APPLICATION INFORMATION (continued)

UDG-98054

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