Texas Instruments UCC28070PW, UCC28070 Datasheet

PRODUCTPREVIEW

+–

OUT

12V to 21V

OUT

CPCC

CZCC

RZCR

RDM

CDR

DMX

SYN

REF

PK1

PK2

CAOA

CAOBPKLMT

GND

VAO

VINAC

VSENSE

CSA

CSB

CDR

GDB

GDA

IMO VCC

RSYNTH

VREF

DMAX

RDM

IMO

To CSB

To CSA

From Ixfrms

UCC28070

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Two-Phase Interleaved CCM PFC Controller

FEATURES APPLICATIONS

• Interleaved Average Current-Mode PWM

Control with Inherent Current Matching

• Advanced Current Synthesizer Current

Sensing for Superior Efficiency and PF

• Highly-Linear Multiplier Output with Internal

Quantized Voltage Feed-Forward Correction for Near-Unity PF

• Programmable Frequency (up to 300 kHz)

• Programmable Maximum Duty-Cycle Clamp

• Programmable Frequency Dithering Rate and

Magnitude for Enhanced EMI Reduction – Magnitude: Up to 30 kHz – Rate: Up to 30 kHz

• External Clock Synchronization Capability

• Enhanced Load and Line Transient Response

through Voltage Amplifier Output Slew-Rate Correction

• Programmable Peak Current Limiting

• Bias-Supply UVLO, Over-Voltage Protection,

Open-Loop Detection, and PFC-Enable Monitoring

• External PFC-Disable Interface

• Open-Circuit Protection on VSENSE and

VINAC pins

• Programmable Soft Start

• 20-Lead TSSOP Package

SLUS794 – NOVEMBER 2007

• High-Efficiency Server and Desktop Power

Supplies

• Telecom Rectifiers

DESCRIPTION

The UCC28070 is an advanced power factor correction device that integrates two pulse-width modulators (PWMs) operating 180 ° out of phase. This Natural Interleaved PWM operation generates substantial reduction in the input and output ripple currents, and the conducted-EMI filtering becomes easier and less expensive. A significantly improved multiplier design provides a shared current reference to two independent current amplifiers that ensures matched average current mode control in both PWM outputs while maintaining a stable, low-distortion sinusoidal input line current.

The UCC28070 contains multiple innovations including current synthesis and quantized voltage feed-forward to promote performance enhancements in PF, efficiency, THD, and transient response. Features including frequency dithering, clock synchronization, and slew rate enhancement further expand the potential performance enhancements.

The UCC28070 also contains a variety of protection features including output over-voltage detection, programmable peak-current limit, in-rush current detection, under-voltage lockout, and open-loop protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

Typical Application Diagram

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UCC28070

SLUS794 – NOVEMBER 2007

ORDERING INFORMATION

PART NUMBER PACKAGE PACKING

UCC28070PW Plastic, 20-Pin TSSOP (PW) 70-Pc. Tube

UCC28070PWR Plastic, 20-Pin TSSOP (PW) 2000-Pc. Tape and Reel

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage: VCC 22 V Supply current: I Voltage: GDA, GDB − 0.5 to VCC+0.3 V Gate drive current – continuous: GDA, GDB +/ − 0.25 Gate drive current – pulsed: GDA, GDB +/ − 0.75 Voltage: DMAX, RDM, RT, CDR, VINAC, VSENSE, SS, VAO, IMO, CSA, CSB,

CAOA, CAOB, PKLMT, VREF Current: RT, DMAX, RDM, RSYNTH − 0.5 Current: VREF, VAO, CAOA, CAOB, IMO 10 Operating junction temperature, T Storage temperature, T Lead temperature (10 seconds) 260

(1) These are stress limits. Stress beyond these limits may cause permanent damage to the device. Functional operation of the device at

these or any conditions beyond those indicated under RECOMMENDED OPERATING CONDITIONS is not implied. Exposure to

absolute maximum rated conditions for extended periods of time may affect device reliability. (2) All voltages are with respect to GND. (3) All currents are positive into the terminal, negative out of the terminal. (4) In normal use, terminals GDA and GDB are connected to an external gate driver and are internally limited in output current.

VCC

STG

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Human Body Model (HBM) 2,000

Charged Device Model (CDM) 500

(1) (2) (3) (4)

PARAMETER LIMIT UNIT

20 mA

− 0.5 to +7 V

RATING UNIT

− 40 to +125

− 65 to +150 ° C

DISSIPATION RATINGS

PACKAGE TA= 85 ° C POWER RATING

20-Pin TSSOP 125 ° C/Watt

(1) Thermal resistance is a strong function of board construction and layout. Air flow reduces thermal resistance. This number is only a

general guide. (2) Thermal resistance calculated with a low-K methodology.

THERMAL IMPEDANCE TA= 25 ° C POWER

JUNCTION-TO-AMBIENT RATING

(1)

(2)

and

800 mW

(1)

320 mW

(1)

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN MAX UNIT

VCC Input Voltage (from a low-impedance source) V VREF Load Current 2 mA VINAC Input Voltage Range 0 3 IMO Voltage Range 0 3.3 V PKLMT, CSA, & CSB Voltage Range 0 3.7 RSYNTH Resistance (R RDM Resistance (R

) 15 750

SYN

) 30 330

RDM

Product Folder Link(s): UCC28070

+ 1 V 21 V

UVLO

k Ω

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PRODUCTPREVIEW

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range − 40 ° C < TA< 125 ° C, TJ= TA, VCC = 12 V, GND = 0 V, R k Ω , R

Bias Supply

VCC

UVLO

Linear Regulator

PFC Enable

External PFC Disable

Oscillator

DMAX

and V

PWM

MAX

CDR

(1) Excessive VCC input voltage and/or current damages the device. This clamp will not protect the device from an unregulated supply. If

= R

RDM

SYN

= 100 k Ω , R

IMO

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SHUNT

VCC shunt voltage VCC current, disabled VSENSE = 0 V 7 VCC current, enabled VSENSE = 3 V (no switching) 8 TBD

VCC current, UVLO

UVLO turn-on threshold Measured at VCC (rising) 9.8 10.2 10.6 UVLO hysteresis Measured at VCC (falling) 1 V VREF enable threshold Measured at VCC (rising) TBD 8 TBD

VREF voltage, no load I VREF voltage, full load I VREF voltage, over line 11 V < VCC < 20 V, I

Enable threshold Measured at VSENSE (rising) 0.65 0.75 0.85 Enable hysteresis 0.15

Disable threshold Measured at SS (falling) TBD 0.6 Hysteresis VSENSE > 0.85 V 0.15

Output phase shift Measured between GDA and GDB TBD 180 TBD Degree

RDM

Timing regulation voltages Measured at DMAX, RT, & RDM 3 V

PWM switching frequency kHz

Duty-cycle clamp TBD% 95% TBD%

Minimum programmable off-time TBD 133 TBD ns Frequency dithering magnitude R

Change in f

PWM

Frequency dithering rate C Rate of change in f Dither rate current Measure at CDR (sink and source) 10 µ A Dither disable threshold Measured at C

an unregulated supply is used, a series-connected fixed positive voltage regulator such as a UA78L15A is recommended. See the

Absolute Maximum Ratings section for the limits on VCC voltage and current.

= 16 k Ω , C

(1)

PWM

SLUS794 – NOVEMBER 2007

= 75 k Ω , R

CDR

= 625 pF, C

VCC

= C

VREF

= 0.1 µ F, C

= 1 µ F, (unless otherwise noted)

VCC

= 10 mA 21 23 25 V

VCC = 7 V 100 µ A VCC = 9 V 4 TBD mA

= 0 mA 5.9 6 6.1

VREF

= − 2 mA 5.8 6 6.1 V

VREF

= 0 mA 5.9 6 6.1

REF

RDM

RDM RDM

RDM CDR

CDR

= 250 k Ω , R

= 0 V, V

= 25 k Ω , R

= 0 V, V

= 75 k Ω , R

= 0 V, V

= 25 k Ω , R

= 0 V, V = 313 k Ω , R

= 31 k Ω , R = 2.2 nF, R = 0.22 nF, R

= 225 k Ω ,

DMX

= 6 V

CDR

= 22.5 k Ω ,

DMX

= 6 V

CDR

= 67.5 k Ω ,

DMX

= 6 V

CDR

= 22.5 k Ω ,

DMX

= 6 V

CDR

= 75 k Ω 2.5 3 3.5

= 25 k Ω 27 30 33

= 100 k Ω 3

RDM

= 100 k Ω 30

RDM

(rising) 5 TBD V

CDR

27 30 33

270 300 330

UCC28070

= 67.5

DMX

kHz

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UCC28070

SLUS794 – NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range − 40 ° C < TA< 125 ° C, TJ= TA, VCC = 12 V, GND = 0 V, R k Ω , R

Clock Synchronization

CDR

Voltage Amplifier

SRC

Soft Start

(2) Due to the programmability of the maximum PWM switching duty cycle (D

= R

RDM

SYN

= 100 k Ω , R

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

SYNC enable threshold Measured at CDR (rising) 5 TBD V SYNC propagation delay 50 TBD ns SYNC threshold (Rising) V

SYNC threshold (Falling) V

SYNC pulses

VSENSE voltage In regulation, TA= 25 ° C 2.97 3 3.03 VSENSE voltage In regulation 2.94 3 3.06 VSENSE input bias current In regulation 250 TBD nA VAO high voltage VSENSE = 2.9 V 4.8 5 5.2 VAO low voltage VSENSE = 3.1 V 0.05 TBD VAO transconductance 2.8 V < VSENSE < 3.2 V, VAO = 3 V 70 µ S VAO sink current, overdriven limit VSENSE = 3.5 V, VAO = 3 V 30 VAO source current, overdriven VSENSE = 2.5 V, VAO = 3 V, SS = 3 V − 30 VAO source current,

overdriven limit + I Slew-rate correction threshold 92 93 95 % Slew-rate correction hysteresis Measured at VSENSE (rising) 6 TBD mV Slew-rate correction current − 100 µ A Slew-rate correction enable threshold Measured at SS (rising) 4 V

VAO discharge current VSENSE = 0.5 V, VAO = 1 V 10 µ A

SS source current VSENSE = 0.9 V, SS = 1 V − 10 µ A Adaptive source current VSENSE = 1.1 V, SS = 1 V − 1 mA Adaptive SS disable Measured as VSENSE – SS 0 mV SS sink current VSENSE = 0.5 V, SS = 0.2 V 0.5 0.9 mA

be reasonably (~5-10%) less than 2 x D

IMO

SRC

= 16 k Ω , C

CDR

= 625 pF, C

CDR

GDx (rising)

CDR CDR

= 75 k Ω , R

= C

VREF

= 0.1 µ F, C

= 1 µ F, (unless otherwise noted)

VCC

= 6 V, Measured from RDM (rising) to

= 6 V, Measured at RDM (rising) 1.2 1.5 = 6 V, Measured at RDM (falling) 0.4 0.7

= 67.5

DMX

Positive pulse width 0.2 µ s Maximum duty cycle

(2)

75 %

µ A

VSENSE = 2.5 V, VAO = 3 V − 130 Measured as VSENSE (falling) / VSENSE

(regulation)

Measured at VAO, in addition to VAO source current.

), the maximum duty cycle of a synchronization pulse must

-1.

MAX

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range − 40 ° C < TA< 125 ° C, TJ= TA, VCC = 12 V, GND = 0 V, R k Ω , R

Over Voltage

OVP

Zero-Power

ZPWR

Multiplier

MULT

IMO

Quantized Voltage Feed Forward

LVL1

LVL2

LVL3

LVL4

LVL5

LVL6

LVL7

LVL8

Current Amplifiers

(3) The Level 1 threshold represents the “ zero-crossing detection ” threshold above which VINAC must rise to initiate a new input half-cycle,

= R

RDM

SYN

= 100 k Ω , R

IMO

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

OVP threshold 104 106 108 % OVP hysteresis Measured at VSENSE (falling) 100 mV OVP propagation delay TBD 0.5 µ s

Zero-power detect threshold Measured at VAO (falling) TBD 0.75 Zero-power hysteresis 0.15

Gain constant µ A

Output current: zero µ A

Level 1 threshold

(3)

Level 2 threshold 1 Level 3 threshold 1.2 Level 4 threshold 1.4 Level 5 threshold 1.65 Level 6 threshold 1.95 Level 7 threshold 2.25 Level 8 threshold 2.6

CAOx high voltage TBD 6 CAOx low voltage TBD 0.1 CAOx transconductance 100 µ S CAOx sink current, overdriven 50 CAOx source current, overdriven − 50 Input common mode range 0 3.6 V Input offset voltage IMO = 0 V − 1 − 3 − 5

Phase mismatch TBD 0 TBD CAOx pull-down current VSENSE = 0.5 V, CAOx = 0.2 V 0.5 0.9 mA

and below which VINAC must fall to terminate that half-cycle.

= 16 k Ω , C

SLUS794 – NOVEMBER 2007

= 75 k Ω , R

CDR

= 625 pF, C

= C

VREF

= 0.1 µ F, C

= 1 µ F, (unless otherwise noted)

VCC

Measured as VSENSE (rising) / VSENSE (regulation)

Measured between VSENSE (rising) and GDx (falling)

VAO > 1.5 V 16 17 18 VAO = 1.2 V 15 17 19 VINAC = 0.9 VPK, VAO = 0.8 V -0.2 0 0.2 VINAC = 0 V, VAO = 5 V -0.2 0 0.2

0.6 0.7 0.8

Measured at VINAC (rising) V

Measured as Phase A ’ s input offset minus Phase B ’ s input offset

UCC28070

= 67.5

DMX

µ A

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PRODUCTPREVIEW

GDB

CAOB

GND

VCC

GDA

DMAX

VAO

RDM

PKLMT

RSYNTH

CSA

VSENSE

VINAC

IMO

CDR

CSB VREF

CAOA

UCC28070

SLUS794 – NOVEMBER 2007

ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range − 40 ° C < TA< 125 ° C, TJ= TA, VCC = 12 V, GND = 0 V, R k Ω , R

Current Synthesizer

RSYNTH

Peak Current Limit

PWM Ramp

RMP

In-Rush Current Detection

Gate Drive

Thermal Shutdown

= R

RDM

SYN

= 100 k Ω , R

SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Regulation voltage

Synthesizer disable threshold Measured at RSYNTH (rising) 5 TBD VINAC input bias current 250 TBD nA

Peak current limit threshold PKLMT = 3.30 V, measured at CSx (rising) 3.27 3.3 3.33 V Peak current limit propagation delay TBD 100 ns

PWM ramp amplitude 4 PWM ramp offset voltage TA= 25 ° C, R PWM ramp offset temperature

coefficient

In-rush detection threshold Measured as VSENSE - VINAC 0 In-rush detection hyst. 20

GDA, GDB output voltage, high, clamped

GDA, GDB output voltage, High C GDA, GDB output voltage, Low C Rise time GDx 1 V to 9 V, C Fall time GDx 9 V to 1 V, C GDA, GDB output voltage, UVLO VCC = 0 V, I

Thermal shutdown threshold 160 Thermal shutdown recovery 140

IMO

= 16 k Ω , C

= 75 k Ω , R

CDR

= 625 pF, C

= C

VREF

= 0.1 µ F, C

= 1 µ F, (unless otherwise noted)

VCC

VSENSE = 3 V, VINAC = 0 V 3 VSENSE = 3 V, VINAC = 2.85 V 0.15 V

Measured between CSx (rising) and GDx (falling) edges

= 75 k Ω TBD 0.7 TBD

VCC = 20 V, C

= 1 nF 10 10.5 11.5

LOAD

= 1 nF 0.2 0.3

LOAD

= 1 nF 11.5 13 15

LOAD

= 1 nF 18 30

LOAD

= 1 nF 12 25

LOAD

, I

GDA

= 2.5 mA 1.6 2 V

GDB

= 67.5

DMX

− 2 mV/ ° C

° C

DEVICE INFORMATION

TSSOP-20 Top View, PW Package

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PRODUCTPREVIEW

NAME PIN # I/O DESCRIPTION

CDR 1 I

RDM

(SYNC)

VAO 3 O connected to Multiplier input and Zero-Power comparator. Connect the voltage regulation loop

VSENSE 4 I

VINAC 5 I Current Synthesis difference amplifier. Connect a resistor-divider network between VIN, VINAC,

IMO 6 O

RSYNTH 7 I

CSB 8 I

CSA 9 I

PKLMT 10 I pin to set the voltage threshold of the cycle-by-cycle peak current limiting comparators. Allows

CAOB 11 O

CAOA 12 O

VREF 13 O

GDA 14 O device suitable for driving the Phase A switching component(s). The output voltage is typically

VCC 15 I

2 I dithering is disabled (CDR > 5 V), the internal master clock will synchronize to positive edges

GND 16 I/O networks to this pin. Connect this pin to the system through a separate trace for high-current

GDB 17 O gate-drivedevice suitable for driving the Phase B switching component(s). The output voltage is

SS 18 I

RT 19 I

DMAX 20 I

UCC28070

SLUS794 – NOVEMBER 2007

TERMINAL FUNCTIONS

Dither Rate Capacitor. Frequency-dithering timing pin. An external capacitor to GND programs

the rate of oscillator dither. Connect the CDR pin to the VREF pin to disable dithering. Dither Magnitude Resistor. Frequency-dithering magnitude and external synchronization pin. An

external resistor to GND programs the magnitude of oscillator frequency dither. When frequency presented on the RDM pin. Connect RDM to GND when dithering is disabled and synchronization

is not desired. Voltage Amplifier Output. Output of transconductance voltage error amplifier. Internally

compensation components between this pin and GND. Output Voltage Sense. Internally connected to the inverting input of the transconductance

voltage error amplifier in addition to the positive terminal of the Current Synthesis difference amplifier. Also connected to the OVP, PFC Enable, and slew-rate comparators. Connect to PFC output with a resistor-divider network.

Scaled AC Line Input Voltage. Internally connected to the Multiplier and negative terminal of the and GND identical to the PFC output divider network connected at VSENSE.

Multiplier Current Output. Connect a resistor between this pin and GND to set the multiplier gain.

Current Synthesis Down-Slope Programming. Connect a resistor between this pin and GND to set the magnitude of the current synthesizer down-slope.

Phase B Current Sense Input. During the on-time of GDB, CSB is internally connected to the inverting input of Phase B ’ s current amplifier.

Phase A Current Sense Input. During the on-time of GDA, CSA is internally connected to the inverting input of Phase A ’ s current amplifier.

Peak Current Limit Programming. Connect a resistor-divider network between VREF and this adjustment for desired Δ ILB.

Phase B Current Amplifier Output. Output of phase B ’ s transconductance current amplifier. Internally connected to the inverting input of phase B ’ s PWM comparator for trailing-edge modulation. Connect the current regulation loop compensation components between this pin and GND.

Phase A Current Amplifier Output. Output of phase A ’ s transconductance current amplifier. Internally connected to the inverting input of phase A ’ s PWM comparator for trailing-edge modulation. Connect the current regulation loop compensation components between this pin and GND.

6-V Reference Voltage and Internal Bias Voltage. Connect a 0.1- µ F ceramic bypass capacitor as close as possible to this pin and GND.

Phase A ’ s Gate Drive. This limited-current output is intended to connect to a separate gate-drive clamped to 13.5 V.

Bias Voltage Input. Connect a 0.1- µ F ceramic bypass capacitor as close as possible to this pin and GND.

Device Ground Reference. Connect all compensation and programming resistor and capacitor noise isolation.

Phase B ’ s Gate Drive. This limited-current output is intended to connect to a separate typically clamped to 13.5 V.

Soft-Start and External Fault Interface. Connect a capacitor to GND on this pin to set the soft-start slew rate based on an internally-fixed 10- µ A current source. The regulation reference voltage for VSENSE is clamped to V conditions a 1-mA current source is present at the SS pin until the SS voltage equals the VSENSE voltage. Pulling the SS pin below 0.6 V immediately disables both GDA and GDB outputs.

Timing Resistor. Oscillator frequency programming pin. A resistor to GND sets the running frequency of the internal oscillator.

Maximum Duty-Cycle Resistor. Maximum PWM duty-cycle programming pin. A resistor to GND sets the PWM maximum duty-cycle based on the ratio of R

until V

exceeds 3 V. Upon recovery from certain fault

DMX

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PRODUCTPREVIEW

GDA

VCC

GDB

S Q

PWM1

S Q

PWM2

CLKB

OffB

IpeakB

CAOA

CAOB

Driver

8CSB

CSA

CA2

CA1

CLKA

OffA

IpeakA

Gm Amp

IpeakA

IpeakB

GND

PKLMT

RSYNTH

Current

Synthesizer

VINAC

VSENSE

OutA

OutB

GND

Fault

(Clamped at 13.5V)

VCC

(Clamped at 13.5V)

Fault

VSENSE

3 VAO

18 SS

250nA

ISS

Mult.

Gm Amp

+ +

2.8V

VINAC5

6 IMO

Slew Rate Correction

10uA

100uA

250nA

ReStart

IMO

VINAC

* (V

VAO

– 1)

VFF

* 17uA

Voltage

Feed-

Forward

VFF

ReStart

10uA

Disable

ReStart

Ext. Disable

1mA

Adaptive SS

Control

Logic

DMAX

RDM/

SYNC

CLKA

CLKB

OffA

OffB

SYNC

Logic

CDR

Oscillator w/ Freq. Dither

SYNC

Enable

Dither

Disable

15VCC

10.2V

16GND

13VREF

Linear

Regulator

23V

9.2V

S Q

0.75V

ReStart

ThermSD

160 On 140 Off

0.60V

VSENSE

3.18V

ZeroPwr 0.75V

VSENSE

0.75V

VAO

OVP

Ext. Disable

0.60V

3.08V

0.90V

VINAC

In-Rush

20mV Hys.

20mV

Fault

UVLO

UCC28070

SLUS794 – NOVEMBER 2007

Functional Block Diagram

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PRODUCTPREVIEW

( )

7500

PWM

R k

f kHz

W =

( )

2 1

DMX RT MAX

R R D= ´ ´ -

UCC28070

SLUS794 – NOVEMBER 2007

APPLICATION INFORMATION

THEORY OF OPERATION

Natural Interleaving

One of the main benefits from the natural interleaving of phases is significant reductions in the high-frequency ripple components of both the input current and the current into the output capacitor of the PFC pre-regulator. Compared to that of a single-phase PFC stage of equal power, the reduced ripple on the input current eases the burden of filtering conducted-EMI noise and helps reduce the EMI filter and C high-frequency ripple current into the PFC output capacitor, C

, helps to reduce its size and cost. Furthermore,

OUT

with reduced ripple and average current in each phase, the boost inductor size can be smaller than in a single-phase design [1].

Ripple current reduction due to interleaving is often referred to as “ ripple cancellation ” , but strictly speaking, the peak-to-peak ripple is completely cancelled only at 50% duty-cycle in a 2-phase system. At duty-cycles other than 50%, ripple reduction occurs in the form of partial cancellation due to the superposition of the individual phase currents. Nevertheless, compared to the ripple currents of an equivalent single-phase PFC pre-regulator, those of a 2-phase naturally-interleaved design are extraordinarily smaller [1]. Independent of ripple cancellation, the frequency of the naturally-interleaved ripple, at both the input and output, is 2 x f

On the input, natural interleaving reduces the peak-to-peak ripple amplitude to 1/2 or less of the ripple amplitude of the equivalent single-phase current.

On the output, Natural Interleaving reduces the rms value of the PFC-generated ripple current in the output capacitor by a factor of slightly more than √ 2, for PWM duty-cycles > 50% as derived from following Erickson ’ s method [2].

sizes. Additionally, reduced

PWM

Programming the PWM Frequency and Maximum Duty-Cycle Clamp

The PWM frequency and maximum duty-cycle clamps for both GDx outputs of the UCC28070 are set through the selection of the resistors connected to the RT and DMAX pins, respectively. The selection of the RT resistor (R

) directly sets the PWM frequency (f

Once R

where D

has been determined, the D

is the desired maximum PWM duty-cycle.

MAX

PWM

resistor (R

) may be derived.

DMX

Product Folder Link(s): UCC28070

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