TEXAS INSTRUMENTS UCC27223 Technical data
T
T
查询UCC27223供应商
SLUS558 − DECEMBER 2003
FEATURES
Maximizes Efficiency by Minimizing
D
Body-Diode Conduction and Reverse
Recovery Losses
D Transparent Synchronous Buck Gate Drive
Operation From the Single Ended PWM Input
Signal
D 12-V or 5-V Input Operation
D 3.3-V Input Operation With Availability of
12-V Bus Bias
D High-Side and Low-Side ±3-A Dual Drivers
D On-Board 6.5-V Gate Drive Regulator
D ±3-A TrueDrive Gate Drives for High
Current Delivery at MOSFET Miller
Thresholds
D Automatically Adjusts for Changing
Operating Conditions
D Thermally Enhanced 14-Pin PowerPAD
HTSSOP Package Minimizes Board Area and
Junction Temperature Rise
FUNCTIONAL APPLICATION DIAGRAM
V
IN
UCC27223
IN
GND
VDD
VLO
VHI
SW
G2
G1
14
13
11,12
9,10
GND
PWM
IN
GND
IN
Note: 12-V input system shown. For 5-V input only systems, see Figure 6.
7
6,8
3
2 ENBL
4,5
APPLICATIONS
Multiphase Converters in Combination With
D
the TPS40090
D Non-Isolated 3.3-V, 5-V and 12-V Input
dc-to-dc Converters for Processor Power,
General Computer, Telecom and Datacom
Applications
DESCRIPTION
The UCC27223 is a high-speed synchronous
buck drivers for today’s high-efficiency,
lower-output voltage designs. Using Predictive
Gate Drivet (PGD) control technology, these
drivers reduce diode conduction and reverse
recovery losses in the synchronous rectifier
MOSFET(s).
The UCC27223 includes an enable pin that
controls the operation of both outputs. A logic
latch is also included to keep both outputs low until
the first PWM input pulse comes in. The RDS(on)
of the SR pull-down sourcing device is also
minimized for higher frequency operations.
This closed loop feedback system detects
body-diode conduction, and adjusts deadtime
delays to minimize the conduction time interval.
This virtually eliminates body-diode conduction
while adjusting for temperature, load- dependent
delays, and for different MOSFETs. Precise gate
timing at the nanosecond level reduces the
reverse recovery time of the synchronous rectifier
V
OU
OU
MOSFET body-diode, reducing reverse recovery
losses seen in the main (high-side) MOSFET. The
lower junction temperature in the low-side
MOSFET increases product reliability. Since the
power dissipation is minimized, a higher switching
frequency can also be used, allowing for smaller
component sizes.
The UCC27223 is offered in the thermally
enhanced 14-pin PowerPADt package with
2°C/W θ
.
jc
Predictive Gate Drivet and PowerPADt are trademarks of Texas Instruments Incorporated.
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Copyright 2003, Texas Instruments Incorporated
1
PWM INPUT
SLUS558 − DECEMBER 2003
PWP PACKAGE
(TOP VIEW)
N/C
ENBL
VDD
VLO
PVLO
AGND
IN
T
A
−40_C to 105_C NON-INVERTING UCC27223PWP
{The PWP package is available taped and reeled. Add R suffix to device type
(e.g. UCC27223PWPR) to order quantities of 2,000 devices per reel and 90
units per tube.
1
2
3
4
5
6
7
N/C − No internal connection
AVAILABLE OPTIONS
(IN)
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
14
13
12
11
10
9
8
VHI
G1
SW
SWS
G2S
G2
PGND
PACKAGED DEVICES
PowerPADt
HTSSOP−14 (PWP)
†}
Supply voltage range, VDD −0.3 to 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VHI 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SW, SWS 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply current, I
including gate drive current .100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DD,
Sink current (peak) pulsed, G1/G2 4.0 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source current (peak) pulsed, G1/G2 −4.0 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog inputs, IN, ENBL −3.0 V to V
Power Dissipation at T
Operating junction temperature range, T
Storage temperature range, T
= 25°C (PWP package) 3 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
J
stg
DD
+ 0.3 V, not to exceed 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−55°C to 115°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , a nd
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
All voltages are with respect to AGND and PGND. Currents are positive into, negative out of the specified terminal.
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Regulator output voltage
V
V
mA
Low-level input threshold voltage
Low-level input threshold voltage
SLUS558 − DECEMBER 2003
ELECTRICAL CHARACTERISTICS
V
= 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from
DD
PVLO to PGND, PVLO tied to VLO, T
VLO regulator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Regulator output voltage
Line Regulation VDD = 12 V to 20 V 2 10
Load Regulation I
Short-circuit current
Dropout voltage, (VDD at 5% VLO drop) VLO = 6.175 V, I
(1)
undervoltage lockout
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Start threshold voltage Measured at VLO 3.30 3.82 4.40
Minimum operating voltage after start 3.15 3.70 4.15
Hysteresis 0.07 0.12 0.20
= −40_C to 105_C for the UCC27223, TA = TJ (unless otherwise noted)
A
VDD = 12 V, I
VDD = 20 V, I
VDD = 10 V, I
= 0 mA to 100 mA 15 40
VLO
VDD = 8.5 V 220 mA
= 0 mA 6.2 6.5 6.8
VLO
= 0 mA 6.2 6.5 6.8
VLO
= 100 mA 6.1 6.5 6.9
VLO
= 100 mA 7.1 7.8 8.5 V
VLO
V
mV
V
bias currents
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VLO bias current at VLO (ON), 5 V applications only VLO = 4.5 V, VDD = no connect 3.6 4.7 5.8
VDD bias current
VDD = 8.5 V 5.5 7.1 8.5
fIN = 500 kHz, No load on G1/G2 8 16 25
input command (IN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage 10 V < VDD < 20 V 3.3 3.6 3.9
Low-level input voltage 10 V < VDD < 20 V 2.2 2.5 2.8
Input bias current VDD = 15 V 1 µA
input (SWS)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input threshold voltage
Input bias current SWS = 0.0 V −0.9 −1.2 −1.5 mA
fIN = 500 kHz, t
G2S = 0.0 V
fIN = 500 kHz, t
G2S = 0.0 V
fIN = 500 kHz, t
maximum,
ON, G2
minimum,
ON, G2
minimum −100 −300 −500 mV
ON, G1
1.4 2.0 2.6
0.7 1.0 1.3
input (G2S)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
High-level input voltage
Low-level input voltage
Input bias current G2S = 0 V −370 −470 −570 µA
NOTE 1: Ensured by design. Not production tested.
fIN = 500 kHz, t
SWS = 0.0 V
fIN = 500 kHz, t
SWS = 0.0 V
ON, G2
ON, G2
maximum,
minimum,
1.4 2.0 2.6
0.7 1.0 1.3
mA
V
V
V
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3
V
ns
SLUS558 − DECEMBER 2003
ELECTRICAL CHARACTERISTICS
V
= 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from
DD
PVLO to PGND, PVLO tied to VLO, T
enable (ENBL)
PARAMETER TEST CONDITION MIN TYP MAX UNITS
V
, high-level input voltage LO to HI transition 2.25 2.45 2.85
IN_H
V
, low-level input voltage HI to LO transition 1.55 1.70 1.90
IN_L
Hysteresis 1.1
R
, enable impedance VDD = 14 V, ENBL = GND 75 112 150 kΩ
ENBL
tD3, propagation delay time
tD4, propagation delay time
tr, Rise time VLO = PVLO = 8.5 V 2.5
tf, Fall time VLO = PVLO = 8.5 V 2.5
G1 main output
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Sink resistance SW = 0 V, VHI = 6 V , IN = 0 V, G1 = 0.5 V 0.5 0.9 1.5
Source resistance
Source current
Sink current
Rise time C = 2.2 nF from G1 to SW, VDD = 20 V 17 25
Fall time C = 2.2 nF from G1 to SW, VDD = 20 V 17 25
(2)
(1)(2)
(1)(2)
(5)
(5)
= −40_C to 105_C for the UCC27223, TA = TJ (unless otherwise noted)
A
TBD
TBD
SW = 0 V, VHI = 6 V, IN = 6.5 V, G1 = 5.5 V 10 25 45
SW = 0 V, VHI = 6 V, IN = 6.5 V, G1 = 3.0 V −3 −3.3
SW = 0 V, VHI = 6 V, IN = 0 V, G1 = 3.0 V 3 3.3
V
ns
ms
Ω
A
ns
G2 SR output
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(2)
(2)
(1)(2)
(1)(2)
(2)
PVLO = 6.5 V, IN = 6.5 V, G1 = 0.25 V 0.5 1.6 4.0
PVLO = 6.5 V, IN = 0 V, G2 = 6.0 V 10 20 35
PVLO = 6.5 V, IN = 0 V G2 = 3.25 V 3 3.3
PVLO = 6.5 V, IN = 6.5 V G2 = 3.25 V −3 3.3
C = 2.2 nF from G2 to PGND VDD = 20 V 17 25
Ω
A
ns
Sink resistance
Source resistance
Source current
Sink current
Rise time
Fall time C = 2.2 nF from G2 to PGND VDD = 20 V 20 35
deadtime delay
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
OFF, G2
t
OFF, G1
Delay Step Resolution 4.0 4.5 5.2
t
ON, G1
t
ON, G1
t
ON, G2
tON, G2 maximum 54
NOTE 1: Ensured by design. Not production tested.
2: The pullup / pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
, IN to G2 falling 40 80 125
, IN to G1 falling 55 80 110
minimum −17
maximum 49
minimum −15
combined current from the bipolar and MOSFET transistors. The output resistance is the R
voltage on the driver output is less than the saturation voltage of the bipolar transistor.
DS(ON) of the MOSFET transistor when the
ns
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2
t
I/O
DESCRIPTION
SLUS558 − DECEMBER 2003
OFF,G1
3.25 V
G1
G2
IN
t
OFF,G2
t
On,G1
PGD
90%
10%
t
On,G2
90%
PGD
10%
UCC27223
Figure 1. Predictive Gate Drive Timing Diagram
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
AGND 6 −
G1 13 O High-side gate driver output that swings between SW and VHI.
G2 9 O Low-side gate driver output that swings between PGND and PVLO.
G2S 10 I
IN 7 I
PGND 8 − Ground return for the G2 driver. Connect PGND to PCB ground plane with several vias.
PVLO 5 I PVLO supplies the G2 driver. Connect PVLO to VLO and bypass on the PCB.
SW 12 − G1 driver return connection.
SWS 11 I
VDD 3 I
VHI 14 I
VLO 4 O
ENBL 2 I
Analog ground for all internal logic circuitry. AGND and PGND should be tied to the PCB ground plane
with vias.
Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the
appropriate deadtime.
Digital input command pin. A logic high forces on the main switch and forces off the synchronous
rectifier.
Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain
close to the MOSFET package.
Input to the internal VLO regulator. Nominal VDD range is from 8.5 V to 20 V. Bypass with at least
0.1 µF of capacitance.
Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on-time.
Bypass VHI to SW with an external capacitor.
Output of the VLO regulator and supply input for the logic and control circuitry. Connect VLO to PVLO and
bypass on the PCB with a maximum capacitor value of 4.7 µF.
Enable input that controls the operation of both outputs (G1 and G2). It is internally pulled up to VLO with
a 110-kΩ resistor for active-high operation.
DESCRIPTION
UDG−0318
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SLUS558 − DECEMBER 2003
SIMPLIFIED BLOCK DIAGRAM
NC
ENBL
VDD
VLO
PVLO
AGND
1
2
3
4
3.82 V/3.7 V
5
6
IN
7
VLO
110 kΩ
R
ENBL
VLO
REGULATOR
PVLO
+
UVLO
VLO
PREDICTIVE
DELAY
CONTROLLER
PVLO
14
VHI
13
G1
12
SW
11
SWS
10
G2S
9
G2
8 PGND
APPLICATION INFORMATION
predictive gate drive technique
The Predictive Gate Drivet technology utilizes a digital feedback system to detect body-diode conduction, and
then adjusts the deadtime delays to minimize it. This system virtually eliminates the body-diode conduction time
intervals for the synchronous MOSFET, while adjusting for different MOSFETs characteristics, propagation and
load dependent delays. Maximum power stage efficiency is the end result.
Two internal feedback loops in the predictive delay controller continuously adjusts the turn on delays for the two
MOSFET gate drives G1 and G2. As shown in Figure 2, t
body-diode conduction in the synchronous rectifier MOSFET Q
and t
OFF,G2
are fixed by propagation delays internal to the device.
The predictive delay controller is implemented using a digital control technique, and the time delays are
therefore discrete. The turn-on delays, t
ON, G1
and t
ON, G2
switching cycle. The minimum and maximum turn-on delays for G1 and G2 are specified in the electrical
characteristics table.
and t
ON,G1
. The turn-off delay for both G1 and G2, t
2
are varied to provide minimum
ON,G2
, are changed by a single step (typically 3 ns) every
OFF,G1
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2
t
SLUS558 − DECEMBER 2003
APPLICATION INFORMATION
OFF,G1
3.25 V
G1
G2
IN
t
OFF,G2
t
On,G1
PGD
90%
10%
UCC27223
Figure 2. Predictive Gate Drive Timing Diagram
A typical application circuit for systems with 8.5-V to 20-V input is shown in Figure 3.
VIN
D1
R1
Disable
Outputs
PWM
Input
ENBL
VDD
VLO
PVLO
AGND
IN
UCC27223
VHI
G1
SW
SWS
G2S
G2
PGND
N/C
C
IN
C2
t
C1
On,G2
90%
PGD
Q1
10%
Q2
L1
Cout
UDG−0318
V
OUT
GND
Figure 3. System Application: 8.5-V to 20-V Input
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GND
UDG−03183
7
SLUS558 − DECEMBER 2003
APPLICATION INFORMATION
selection of VHI series resistor R1 (dV/dt Considerations):
The series resistor R1 may be needed to slowdown the turn-on of the main forward switch to limit the dV/dt which
can inadvertently turn on the synchronous rectifier switch. In nominal 12-V input designs, a R1 value of 4-Ω to
10-Ω can be used depending on the type of MOSFET used and the high-side/low-side MOSFET ratio. In 5-V
or lower input applications however, R1 is not needed.
When the drain-source voltage of a MOSFET quickly rises, inadvertent dV/dt induced turn-on of the device is
possible. This can especially be a problem for input voltages of 12 V or greater. As Q1 rapidly turns on, the
drain-to-source voltage of Q2 rises sharply, resulting in a dV/dt voltage spike appearing on the gate signal of
Q2. If the dV/dt induced voltage spike were to exceed the given threshold voltage, the MOSFET may briefly
turn on when it should otherwise be commanded off. Obviously this undesired event would have a negative
impact on overall efficiency.
Minimizing the dV/dt effect on Q2 can be accomplished by proper MOSFET selection and careful layout
techniques. The details of how to select a MOSFET to minimize dV/dt susceptibility are outlined in SEM−1400,
Topic 2, Appendix A, Section A5. Secondly, the switch node connecting Q1, Q2 and L1 should be laid out as
tight as possible, minimizing any parasitic inductance, which might worsen the dV/dt problem.
If the dV/dt induced voltage spike is still present on the gate Q2, a 4W to 10W value of R1 is recommended to
minimize the possibility of inadvertently turning on Q2. The addition of R1 slows the turn-on of Q1, limiting the
dV/dt rate appearing on the drain-to-source of Q2. Slowing down the turn-on of Q1 will result in slightly higher
switching loss for that device only , but the efficiency gained by preventing dV/dt turn-on of Q2 will far outweigh
the negligible effect of adding R1.
When Q2 is optimally selected for dV/dt robustness and careful attention is paid to the PCB layout of the switch
node, R1 may not be needed at all, and can therefore be replaced with a 0-Ω jumper to maintain high efficiency.
The goal of the designer should not be to completely eliminate the dV/dt turn-on spike but to assure that the
maximum amplitude is less than the MOSFET gate-to-source turn-on threshold voltage under all operating
conditions.
selection of bypass capacitor C1
Bypass capacitors should be selected based upon allowable ripple voltage, usually expressed as a percent of
the regulated power supply rail to be bypassed. In all of the UCC27223 application circuits shown herein, C1
provides the bypass for the main (high-side) gate driver. Every time Q1 is switched on, a packet of charge is
removed from C1 to charge Q1’s gate to approximately 6.0 V. The charge delivered to the gate of Q1 can be
found in the manufacturer’s datasheet curves. An example of a gate charge curve is shown in Figure 4.
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(1)
SLUS558 − DECEMBER 2003
GATE-TO-SOURCE VOLTAGE
vs
31 nC
8
6
4
2
− Gate-to-Source Voltage − V
GS
V
0
020304010
TOTAL GATE CHARGE
Q6 − Total Gate Charge − nC
Figure 4.
As shown in Figure 4, 31 nC of gate charge is required in order for Q1’s gate to be charged to 6.0 V, relative
to its source. The minimum bypass capacitor value can be found using the following calculation:
Q
C1
MIN
+
k ǒVHI * V
G
Ǔ
SW
where k is the percent ripple on C1, QG is the total gate charge required to drive the gate of Q1 from zero to
the final value of (VHI−VSW). In this example gate charge curve, the value of the quantity (VHI−VSW) is taken
to be 6.0 V. This value represents the nominal VLO regulator output voltage minus the forward voltage drop of
the external Schottky diode, D1. For the MOSFET with the gate charge described in Figure 4, the minimum
capacitance required to maintain a 3% peak-to-peak ripple voltage can be calculated to be 172 nF, so a 180-nF
or a 220-nF capacitor could be used. The maximum peak-to-peak C1 ripple must be kept below 0.4 V for proper
operation.
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