Datasheet UCC3626DW, UCC3626PWTR, UCC3626PW, UCC3626N, UCC3626DWTR Datasheet (Texas Instruments)

UCC2626
UCC3626

PRELIMINARY

04/99

FEATURES

•

Two Quadrant and Four Quadrant
Operation

•

Integrated Absolute Value Current
Amplifier

•

Pulse-by-Pulse and Average Current
Sensing

•

Accurate, Variable Duty Cycle
Tachometer Output

•

Trimmed Precision Reference

•

Precision Oscillator

•

Direction Output

Brushless DC Motor Controller

17HALLC

8DIR_OUT

14PWM_NI

13PWM_I

16HALLB

SYNCH

11

OC_REF

9

SNS_I

3

4

1

5

22 CLOW

C_TACH

R_TACH

TACH_OUT

GND

2VREF

27 AHI

25 BHI

23 CHI

26

ALOW

10

SNS_NI

IOUT

7

6

12

CT

18COAST

21DIR_IN

15HALLA

19BRAKE

20QUAD

SENSE AMPLIFIER

OVER-CURRENT
COMPARATOR

OSCILLATOR

DIRECTION
DETECTOR

EDGE

DETECTOR

28 VDD

ONE SHOT

R•C

5VOLT

REFERENCE

QQSR

PWM LOGIC

24 BLOW

1.75V

DIRECTION

SELECT

HALL

DECODER

PWM COMPARATOR

X5

Q

Q

S

R

BLOCK DIAGRAM

UDG-97173

DESCRIPTION

The UCC3626 motor controller IC combines many of the functions re

­quired to design a high performance, two or four quadrant, 3-phase,
brushless DC motor controller into one package. Rotor position inputs
are decoded to provide six outputs that control an external power stage.
A precision triangle oscillator and latched comparator provide PWM mo

­tor control in either voltage or current mode configurations. The oscilla

­tor is easily synchronized to an external master clock source via the
SYNCH input. Additionally, a QUAD select input configures the chip to
modulate either the low side switches only, or both upper and lower
switches, allowing the user to minimize switching losses in less de

­manding two quadrant applications.

The chip includes a differential current sense amplifier and absolute
value circuit which provide an accurate reconstruction of motor current,
useful for pulse by pulse over current protection as well as closing a
current control loop. A precision tachometer is also provided for imple

­menting closed loop speed control. The TACH_OUT signal is a variable
duty cycle, frequency output which can be used directly for digital con­trol or filtered to provide an analog feedback signal. Other features in­clude COAST, BRAKE, and DIR_IN commands along with a direction
output, DIR_OUT.

application

INFO

available

2

UCC2626
UCC3626

ELECTRICAL CHARACTERISTICS:

Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF,

R

TACH

= 250K, C

TACH

= 100pF, TA=TJ, TA= –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Overall

Supply Current 310mA

Under-Voltage Lockout

Start Threshold 10.5 V

UVLO Hysteresis 0.5 V

5.0 V Reference

Output Voltage I

VREF

= –2mA 4.9 5 5.1 V

Line Regulation 11V < VCC < 14.5V 10 mV

Load Regulation –1 > I

VREF

> –5mA 30 mV

Short Circuit Current 40 120 mA

Coast Input Comparator

Threshold 1.75 V

Hysteresis 0.1 V

Input Bias Current 0.1 µA

IOUT

BHI

ALO

AHI

BRAKE

BLOW

CHI

CLOW

VDD

TACH_OUT

VREF

SNS_I

SYNCH

SNS_NI

R_TACH

C_TACH

CT

GND

DIR_OUT

OC_REF HALLC

DIR_IN

QUAD

COAST

PWM_NI

PWM_I

HALLA

HALLB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

15

16

17

18

19

20

21

22

23

24

25

26

27

28

CONNECTION DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

Supply Voltage VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V

Inputs

Pins 20, 19, 18, 21, 15, 16, 17, 7, 12, 9, 10 . . . . –0.3V to V

DD

Pins 13, 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 8.0V

Output Current

Pins 22, 23, 24, 25, 26, 27 . . . . . . . . . . . . . . . . . . . . . ±200mA

Pins 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20mA

Pins 3. 8, 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C

Lead Temperature (Soldering 10 Seconds). . . . . . . . . . +300°C

Note: Unless otherwise indicated, voltages are referenced to
ground. Currents are positive into, negative out of specified ter

-

minal. Consult packaging section of Databook for thermal limi

-

tations and considerations of package.

DIL-28, SOIC-28, TSSOP-28 (Top View)
N Package, DW Package, PW Package

UCC

PACKAGE

626

TEMPERATURE RANGE

ORDERING INFORMATION

TEMPERATURE RANGE PACKAGE

UCC2626N DIL
UCC2626DW –40° C to +85° C SOIC
UCC2626PW TSSOP
UCC3626N DIL
UCC3626DW 0° C to +70° C SOIC
UCC3626PW TSSOP

3

UCC2626
UCC3626

ELECTRICAL CHARACTERISTICS:

Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF,

R

TACH

= 250K, C

TACH

= 100pF, TA=TJ, TA= –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Current Sense Amplifier

Input Offset Voltage VCM = 0V 5 mV

Input Bias Current VCM = 0V 10 µA

Gain VCM = 0V 4.9 5 5.1 V/V

CMRR –0.3V < VCM < 0.5 60 dB

PSRR 11V < VCC <14.5V 60 dB

Output High Voltage I

IOUT

= –100µA5V

Output Low Voltage I

IOUT

= 100µA50mV

Output Source Current V

IOUT

= 2V 500 µA

PWM Comparator

Input Common Mode Range 2.0 8.0 V

Propogation Delay 75 nS

Over-Current Comparator

Input Common Mode Range 0.0 5.0 V

Propogation Delay 175 nS

Logic Inputs

Logic High QUAD, BRAKE, DIR 3.5 V

Logic Low QUAD, BRAKE, DIR 1.5 V

Input Current QUAD, BRAKE, DIR 0.1 µA

Hall Buffer Inputs

VIL HALLA, HALLB, HALLC 1 V

VIH HALLA, HALLB, HALLC 1.9 V

Input Current 0V < V

IN

< 5V –25 µA

Oscillator

Frequency R

TACH

= 250k, CT = 1nF 10 KHz

Frequency Change With Voltage 12V < VCC < 14.5V 5 %

CT Peak Voltage 7.5 V

CT Valley Voltage 2.5 V

CT Peak-to-Valley Voltage 5.0 V

SYNCH Pin Minimum Pulse Width –500 ns

Tachometer

V

OH/VREF

I

OUT

= –10µA 99 100 %

Vol I

OUT

= 10µA 0 20 mV

R

ON

High I

OUT

= –100µA1kΩ

R

ON

Low I

OUT

= 100µA1kΩ

Ramp Threshold, Lo 20 mV

Ramp Threshold, Hi 2.52 V

C

TACH

Charge Current R

TACH

= 49.9kΩ 50 µA

T-on Accuracy Note 1 –3 3 %

Direction Output

DIR OUT High Level I

OUT

= –100µA 3.5 5.1 V

DIR OUT Low Level I

OUT

= 100µA01V

4

UCC2626
UCC3626

PIN DESCRIPTIONS

AHI, BHI, CHI: Digital outputs used to control the high

side switches in a three phase inverter. For specific de

-

coding information reference Table I.

ALOW, BLOW, CLOW: Digital outputs used to control
the low side switches in a three phase inverter. For spe­cific decoding information reference Table I.

BRAKE: BRAKE is a digital input which causes the de­vice to enter brake mode. In brake mode all three high
side outputs are turned off, AHI, BHI & CHI, while all
three lowside outputs are turned on, ALOW, BLOW,
CLOW. During brake mode the tachometer output re­mains operational. The only conditions which can inhibit
the low side commands during brake are UVLO, ex

-

ceeding peak current, the output of the PWM compara

-

tor, or the COAST command.

COAST: The COAST input consists of a hysteretic com

­parator which disables the outputs. The input is useful in
implementing an overvoltage bus clamp in four quadrant
applications. The outputs will be disabled when the input
is above 1.75V.

CT: This pin is used in conjunction with the R_TACH pin
to set the frequency of the oscillator. A timing capacitor
is normally connected between this point and ground
and is alternately charged and discharged between 2.5V
and 7.5V.

C_TACH: A timing capacitor is connected between this
pin and ground to set the width of the TACH_OUT pulse.
The capacitor is charged with a current set by the resis

­tor on pin RT.

DIR_IN: DIR_IN is a digital input which determines the
order in which the HALLA,B & C inputs are decoded. For
specific decode information reference Table I.

DIR_OUT: DIR_OUT represents the actual direction of
the rotor as decoded from the HALLA,B&Cinputs. For
any valid combination of HALLA, B &C inputs there are
two valid transitions, one which translates to a clockwise
rotation and another which translates to a counterclock­wise rotation. The polarity of DIR_OUT is the same as
DIR_IN while motoring, i.e. sequencing from top to bot­tom in Table 1.

GND: GND is the reference ground for all functions of the
part. Bypass and timing capacitors should be terminated
as close to this point as possible.

HALLA, HALLB, HALLC: These three inputs are de

­signed to accept rotor position information positioned
120° apart. For specific decode information reference Ta

­ble I. These inputs should be externally pulled-up to
VREF or another appropriate external supply.

IOUT: IOUT represents the output of the current sense
and absolute value amplifiers. The output signal appear

­ing is a representation of the following expression:

I ABS ISENS I ISENS NI

OUT

=−•(_ _)5

This output can be used to close a current control loop as
well as provide additional filtering of the current sense
signal.

OC_REF: OC_REF is an analog input which sets the trip
voltage of the overcurrent comparator. The sense input of
the comparator is internally connected to the output of the
current sense amplifier and absolute value circuit.

PWM_NI: PWM_NI is the noninverting input to the PWM
comparator.

PWM_I: PWM_I is the inverting input to the PWM com

­parator.

ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF,

R

TACH

= 250K, C

TACH

= 100pF, TA=TJ, TA= –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Output Section

Maximum Duty Cycle 100 %

Output Low Voltage I

OUT

= 10mA 0.4 V

Output High Voltage I

OUT

= –10mA 4.0 5.1 V

Output Low Voltage I

OUT

= 1mA 1 V

Output High Voltage I

OUT

= –1mA 4.0 5.1 V

Rise/Fall Time CI = 100pF 100 nS

Note 1: T(on) is calculated using the formula: T(on) = C

TAC H



(VHI–VLO)/I

CHARGE

. This number is compared to the formula T(on) =

R

TAC H



C

TAC H

.

5

UCC2626
UCC3626

Table 1 provides the decode logic for the six outputs,
AHI, BHI, CHI, ALOW, BLOW, and CLOW as a function
of the BRAKE, COAST, DIR_IN, HALLA, HALLB, and
HALLC inputs.

The UCC3626 is designed to operate with 120° position
sensor encoding. In this format, the three position sensor

signals are never simultaneously high or low. Motor's
whose sensors provide 60° encoding can be converted
to 120° using the circuit shown in Fig. 1.

In order to prevent noise from commanding improper
commutation states, some form of low pass filtering on
HALLA, HALLB, and HALLC is recommended. Passive

APPLICATION INFORMATION

QUAD: The QUAD input selects between “two” QUAD =

0 and “four” QUAD = 1 quadrant operation. When in
“two-quadrant” mode only the low side devices are ef

­fected by the output of the PWM comparator. In
“four-quadrant” mode both high and low side devices are
controlled by the PWM comparator.

SYNCH: The SYNCH input is used to synchronize the
PWM oscillator with an external digital clock. When using
the SYNCH feature, a resistor equal to R

TA CH

must be
placed in parallel with CT. When not used, ground
SYNCH.

SNS_NI, SNS_I: These inputs are the noninverting and
inverting inputs to the current sense amplifier, respec

­tively. The integrated amplifier is configured for a gain of
five. An absolute value function is also incorporated into
the output in order to provide a representation of actual
motor current when operating in four quadrant mode.

TACH_OUT: TACH_OUT is the output of a monostable
triggered by a change in the commutation state, thus pro

­viding a variable duty cycle, frequency output. The
on-time of the monostable is set by the timing capacitor
connected to C_TACH. The monostable is capable of be

­ing retriggered if a commutation occurs during it's
on-time.

R_TACH: A resistor connected between R_TACH and
ground programs the current for both the oscillator and
tachometer.

VDD: VDD is the input supply connection for this device.
Undervoltage lockout keeps the outputs off for inputs be

­low 10.5V. The input should be bypassed with a 0.1µFce

­ramic capacitor, minimum.

VREF: VREF is a 5V, 2% trimmed reference output with
5mA of maximum available output current. This pin
should be bypassed to ground with a 0.1µF ceramic ca

­pacitor, minimum.

PIN DESCRIPTIONS (cont.)

B
R
A
K
E

C
O
A
S

T

D

I

R

_

IN

HALL

INPUTS

HIGH SIDE

OUTPUTS

LOW SIDE
OUTPUTS

ABCABCABC

001101100010
001100100001
001110010001
001010010100
001011001100
001001001010
000101010100
000001010001
000011100001
000010100010
000110001010
000100001100

X1XXXX000000

10XXXX000111
00X111000000
00X000000000

Table 1. Commutation truth table.

1kΩ

2N2222A

1kΩ

1kΩ

1kΩ

VREF

VREF

VREF

HALLB

HALLA

HALLC

HALLA

HALLB

HALLC

2.2nF

2.2nF

2.2nF

499Ω

499Ω

Figure 1. Circuit to convert 60° hall code to 120°
code.

6

UCC2626
UCC3626

RC networks generally work well and should be located
as close to the IC as possible. Fig. 2 illustrates these
techniques.

Configuring the Oscillator

The UCC3626 oscillator is designed to operate at fre­quencies up to 250kHz and provide a triangle waveform
on CT with a peak to peak amplitude of 5V for improved
noise immunity. The current used to program CT is de

-

rived off of the R_TACH resistor according to the follow

-

ing equation:

I

RTACH

Amps

OSC

=

25

_

Oscillator frequency is set by R_TACH and CT according
to the following relationship:

Frequency

RTACH CT

Hz

=

•

25.

(_ )

Timing resistor values should be between 25kΩ and
500kΩ while capacitor values should fall between 100pF
and 1µF. Fig. 4 provides a graph of oscillator frequency
for various combinations of timing components. As with
any high frequency oscillator, timing components should
be located as close to the IC pins as possible when lay

-

ing out the printed circuit board. It is also important to ref

­erence the timing capacitor directly to the ground pin on
the UCC3626 rather than daisy chaining it to another
trace or the ground plane. This technique prevents

switching current spikes in the local ground from causing
jitter in the oscillator.

Synchronizing the Oscillator

A common system specification is for all oscillators in a
design to be synchronized to a master clock. The
UCC3626 provides a SYNCH input for exactly this pur

­pose. The SYNCH input is designed to interface with a
digital clock pulse generated by the master oscillator. A
positive going edge on this input causes the UCC3626
oscillator to begin discharging. In order for the slave os

­cillator to function properly it must be programmed for a
frequency slightly lower than that of the master. Also, a
resistor equal to R

TA CH

must be placed in parallel with
CT. Fig. 3 illustrates the waveforms for a slave oscillator
programmed to 20kHz with a master frequency of 30kHz.
The SYNCH pin should be grounded when not used.

APPLICATION INFORMATION (cont.)

1.E+03

1.E+04

1.E+05

1.E+06

1.E-10 1.E-09 1.E-08 1.E-07
CT (F)

PWM FREQUENCY (Hz)

R_TACH = 25k

R_TACH = 500k

R_TACH = 100k

R_TACH = 250k

Figure 4. PWM oscillator frequency vs. CTand
R_TACH.

SYNCH

CT

WITHOUT SYNCH

WITH SYNCH

Figure 3. Synchronized and unsynchronized
oscillator waveforms.

1kΩ

1kΩ

1kΩ

VREF

VREF

VREF

HALLA

HALLB

HALLC

HALLA

HALLB

HALLC

2.2nF

2.2nF

2.2nF

499Ω

499Ω

499Ω

Figure 2. Passive hall filtering technique.

7

UCC2626
UCC3626

Programming the Tachometer

The UCC3626 tachometer consists of a precision, 5V
monostable, triggered by either a rising or falling edge on
any of the three Hall inputs, HALLA, HALLB, HALLC. The
resulting TACH_OUT waveform is a variable dutycycle
square wave whose frequency is proportional to motor
speed, as given by:

TACH OUT

VP

Hz

_

()

=

•

20

where

P

is the number of motor pole pairs andVis motor

velocity in RPM.

The on-time of the monostable is programmed via timing
resistor R_TACH and capacitor C_TACH according to the
following equation:

On Time R TACH C TACH

−= •_ _ sec

Fig. 5 provides a graph of On-Time for various combina

­tions of R_TACH and C_TACH. On-Time is typically set to
a value less than the minimum TACH-OUT period as
given by:

TPeriod

VP

MIN

MAX

_sec=

•

20

where

P

is the number of motor pole pairs andVis motor

velocity in RPM.

The TACH_OUT signal can be used to close a digital
velocity loop using a microcontroller, as shown in Fig. 6,
or directly low pass filtered in an analog implementation,
Fig. 7.

APPLICATION INFORMATION (cont.)

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E-10 1.E-09 1.E-08 1.E-07 1.E-06
Ctach (F)

Ton (sec)

R_TACH = 25k

R_TACH = 500k

R_TACH = 100k

R_TACH = 250k

Figure 5. Tachometer on-time vs. C_TACH and
R_TACH.

5

4

14

R_TACH

C_TACH

PWM_NI

PWM_I

13

TACH_OUT

3

6CT

UCC3626

DB0 – DB7

VOUT

AD558

V

OUT

SENSE

V

OUT

SELECT

VCE

VCS

IC1

PB0 – PB7

PC0

MC68HC11

Figure 6. Digital velocity loop implementation using MC68HC11.

UDG-97188

8

UCC2626
UCC3626

Two Quadrant vs Four Quadrant Control

Fig. 8 illustrates the four possible quadrants of operation
for a motor. Two quadrant control refers to a system
whose operation is limited to quadrants I and III where
torque and velocity are in the same direction. With a two
quadrant brushless DC amplifier, there are no provisions
other than friction to decelerate the load, limiting the ap

­proach to less demanding applications. Four quadrant
controllers, on the other hand, provide controlled opera

­tion in all quadrants, including II and IV, where torque and
rotation are of opposite direction.

When configured for two quadrant operation, (QUAD=0),
the UCC3626 will only modulate the low side devices of
the output power stage. The current paths within the out

-

put stage during the PWM on and off times are illus

­trated in Fig. 9. During the 'on' interval, both switches
are on and current flows through the load down to
ground. During the 'off' time, the lower switch is shut off
and the motor current circulates through the upper half
bridge via the flyback diode. The motor is assumed to be
operating in either quadrant I or III.

APPLICATION INFORMATION (cont.)

2

5

4

14

VREF

R_TACH

C_TACH

PWM_NI

PWM_I

13

TACH_OUT

3

6CT

+

–

UCC3626

Figure 7. Simple analog velocity loop.

UDG-97189

III

III IV

VELOCITY

CW

TORQUE
CW

CCW

CCW

Figure 8. Four quadrants of operation.

IPHASE

+ BEMF -

VMOT

IOFF

ION

S1

S3 S5

S2

S4

S6

Figure 10. Two quadrant reversal.

IPHASE

+ BEMF -

VMOT

IOFF

ION

S1

S3 S5

S2

S4

S6

Figure 9. Two quadrant chopping.

9

UCC2626
UCC3626

If one attempts to operate in quadrants II or IV by chang­ing the DIR bit and reversing the torque, switches 1 and 4
are turned off and switches 2 and 3 turned on. Under this
condition motor current will very quickly decay, reverse
direction and increase until the control threshold is
reached. At this point switch 2 will turn off and current will
once again circulate in the upper half bridge, however, in
this case the motor's BEMF is in phase with the current,
i.e. the motor's direction of rotation has not yet changed.
Fig. 10 illustrates the current paths when operating in this
mode. Under these conditions there is nothing to limit the
current other than motor and drive impedance. These
high circulating currents can result in damage to the
power devices in addition to high, uncontrolled torque.

By pulse width modulating both the upper and lower
power devices (QUAD=1), motor current will always de

-

cay during the PWM “off” time, eliminating any uncon

­trolled circulating currents. In addition, current will always
flow through the current sense resistor, thus providing a
suitable feedback signal. Fig. 11 illustrates the current
paths during a four quadrant torque reversal. Motor drive

waveforms for both two and four quadrant operation are
illustrated in Fig. 12.

Power Stage Design Considerations

The flexible architecture of the UCC3626 requires the
user to pay close attention to the design of the power
output stage. Two and Four Quadrant applications that do
not require the brake function are able to utilize the
power stage approach illustrated in Fig. 13A. In many
cases the body diode of the MOSFET can be utilized to
reduce parts count and cost. If efficiency is a key require

­ment, Schottky diodes can be used in parallel with the
switches.

If the system requires a braking function, diodes must be
added in series with the lower power devices and the
lower flyback diodes returned to ground, as pictured in
Fig. 13B,C. This requirement prevents brake currents
from circulating in the lower half bridge and bypassing
the sense resistor. In addition, the combination of braking
and four quadrant control necessitates an additional re­sistor in the diode path to sense current during the PWM
'off' time as illustrated in Fig. 13C.

Current Sensing

The UCC3626 includes a differential current sense am­plifier with a fixed gain of five, along with an absolute
value circuit. The current sense signal should be low
pass filtered to eliminate leading edge spikes. In order to
maximize performance, the input impedance of the am­plifier should be balanced. If the sense voltage must be
trimmed for accuracy reasons, a low value input divider
or a differential divider should be used to maintain im

­pedance matching, as shown in Fig. 14.

With four quadrant chopping motor current always flows
through the sense resistor. However, during the flyback
period the polarity across the sense resistor is reversed.
The absolute value amplifier cancels the polarity reversal
by inverting the negative sense signal during the flyback
time, see Fig. 15. Therefore, the output of the absolute
value amplifier is a reconstructed analog of the motor
current, suitable for protection as well as feedback loop
closure.

APPLICATION INFORMATION (cont.)

IPHASE

+ BEMF -

VMOT

IOFF

ION

S1

S3 S5

S2

S4

S6

Figure 11. Four quadrant reversal.

10

UCC2626
UCC3626

0 60 120 180 240 300 360 420 480 540 600 660 720

ROTOR POSITION IN ELECTRICAL DEGREES

Code

101 100 110 010 011 001 101 100

110

010 011 001

H1

H2

H3

AHI

BHI

CHI

ALO

BLO

CLO

+

0-A

+

0-B

+

0-C

MOTOR

PHASE

CURRENTS

QUAD=0

LOW SIDE
OUTPUTS

QUAD=0

HIGH SIDE

OUTPUTS

QUAD=0

SENSOR

INPUTS

AHI

BHI

CHI

ALO

BLO

CLO

+

0-A

+

0-B

+

0-C

MOTOR

PHASE

CURRENTS

QUAD=1

LOW SIDE
OUTPUTS

QUAD=1

HIGH SIDE

OUTPUTS

QUAD=1

100% Duty Cycle PWM 50% Duty Cycle PWM

Figure 12. Motor drive and current waveforms for 2 quadrant (QUAD=0) and 4 quadrant (QUAD=1) operation.

APPLICATION INFORMATION (cont.)

UDG-97190

11

UCC2626
UCC3626

TWO

QUADRANT

FOUR

QUADRANT

SAFE

BRAKING

POWER

REVERSAL

CURRENT SENSE

PULSE BY

PULSE

AVERAGE

(a)

Yes Yes No In 4-Quad Only Yes Yes

(b)

Yes No Yes No Yes No

(c)

Yes Yes Yes In 4-Quad Only Yes Yes

(b)

(c)

TO

MOTOR

VMOT

CURRENT

SENSE

TO

MOTOR

VMOT

CURRENT

SENSE

TO

MOTOR

VMOT

CURRENT

SENSE

(a)

Figure 13. Power stage topologies.

TYPICAL APPLICATIONS

Fig. 16 illustrates a simple 175V, 2A two quadrant velocity
controller using the UCC3626. The power stage is de­signed to operate with a rectified off-line supply using
IR2210s to provide the interface between the low voltage
control signals and the power MOSFETs. The power to­pology illustrated in Fig. 13C is implemented in order to
provide braking capability.

The controller's speed command is set by potentiometer
R30 while the speed feedback signal is obtained by low
pass filtering and buffering the TACH-OUT signal using
R11 and C9. Small signal compensation of the velocity
control loop is provided by amplifier U5A, whose output is
used to control the PWM duty cycle. The integrating ca

-

pacitor, C8, places a pole at 0Hz and a zero in conjunc

­tion with R10. This zero can be used to cancel the low
frequency motor pole and cross the loop over with a
–20dB gain response.

Four quadrant applications require the control of motor
current. Fig. 17 illustrates a sign/magnitude current con­trol loop within an outer bipolar velocity loop using the
UCC3626. U1 serves as the velocity loop error amplifier
and accepts a +/-5V command signal. Velocity feedback
is provided by low pass filtering and scaling the
TACH_OUT signal using U2. The direction output,
DIR_OUT, switch and U3 set the polarity of the tachom­eter gain according to the direction of rotation. The out

­put of the velocity error amplifier, U1, is then converted
to sign/magnitude form using U5 and U6. The sign por

­tion is used to drive the DIR input while the magnitude
commands the current error amplifier, U8. Current feed

­back is provided by the internal current sense amplifier
via the IOUT pin.

12

UCC2626
UCC3626

IPHASE

+ BEMF -

VMOT

IOFF

ION

S1

S3 S5

S2

S4

S6

X5

Is

If

Im

Is

If

Im

Ip

Ip

5*Ip

Figure 15. Current sense amplifier waveform.

RF

RF

Rs

RADJ

CF

SNS_NI

SNS_I

(a)

RF

Rs

RADJ

CF

(b)

RF

SNS_I

SNS_NI

RF

RADJ << RF

Figure 14. (a) Differential divider and (b) low value divider.

TYPICAL APPLICATION (cont.)

TYPICAL APPLICATIONS (cont.)

13

UCC2626
UCC3626

Q1

IRF730

Q2

IRF730

R3

1k

C2

0.1µF

+12V

VREF

C3

2200pF

R4

499

R2

1k

C4

2200pF

R5

499

R1

1k

C5

2200pF

R6

499

C6

100pF

C11

0.1µF

VREF

C12

0.1µF

D16

11DF4

C13

0.1µF

+12V

R18

47

R17

10

R16

47

R15

10

D1

1N4148

D8

1N5418

MOTOR

PHASE A

C22

10µF

VMOT

Q3

IRF730

Q4

IRF730

C14

0.1µF

VREF

C15

0.1µF

D17

11DF4

C16

0.1µF

+12V

R22

47

R21

10

R20

47

R19

10

D11

1N5418

MOTOR

PHASE A

C21

10µF

VMOT

Q5

IRF730

Q6

IRF730

C17

0.1µF

VREF

C18

0.1µF

D18

11DF4

C19

0.1µF

+12V

R26

47

R25

10

R24

47

R23

10

D15

1N5418

MOTOR

PHASE A

C20

10µF

VMOT

R27

0.1

R28

0.1

C1

0.1µF

R13

35k

R14

15k

VREF

C10

3900pF

R12

250k

R7

10k

VREF

R8

10k

R9

10k

U5A

1/2 LM358

R11

160k

C9

0.1µF

R10

C8

C7

VREF

FROM HALL

SENSORS

R29

R30

2k

R31

2k

C23

0.01µF

R30

10K

VREF

Speed Set

D2

1N4148

D3

1N5818

D4

1N5818

D5

1N5818

D6

1N5818

IR2110

VB

6HO7VS5NC4

VCC

3LO1

COM

2

VDD

9NC8

HIN

10

LIN

12SD11NC14

VSS

13

IR2110

VB

6HO7VS5NC4

VCC

3LO1

COM

2

VDD

9NC8

HIN

10

LIN12SD11NC14VSS

13

IR2110

VB

6HO7VS5NC4

VCC

3LO1

COM

2

VDD

9NC8

HIN

10

LIN12SD

11NC14

VSS

13

UCC3626

AHI

27

BHI

25

CHI

ALOW

26

BLOW

CLOW

22

SNS_NI

9

SNS_I

10

IOUT

11

DIR_OUT

8

OC_REF

12

CTACH

5

RTACH

4

TACH_OUT

3

VDD

28

VREF

2

GND1HALLA

15

HALLB16HALLC17QUAD

20

DIR_IN

21

BRAKE19COAST18SYNCH

7CT6

PWM_NI

14

PWM_I

13

24

23

U5B

1/2 LM358

U1

U2

U3

U4

D7

1N5821

D10

1N5821

D13

1N5821

UDG-97184

Figure 16. Two quadrant velocity controller.

14

UCC2626
UCC3626

UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. [phone] • FAX [phone]

11 IOUT

+

–

13 PWM_I

CURRENT
ERROR
AMPLIFIER

+

–

U6

10k10k

+

–

10k

10k

SIGN/MAGNITUDE CONVERTER

21 DIRU7

CURRENT SIGN

3 TACH_OUT

+

–

U2

TACHOMETER

FILTER

4.99k

10k

2N7002

8DIR_OUT

4.99k

+

–

U3

10k

BIPOLAR

TACH GAIN

10k

+

–

U1

VELOCITY

COMMAND

+/– 5V

CURRENT
MAGNITUDE

U5

U8

Figure 17. Four quadrant control loop.

TYPICAL APPLICATIONS (cont.)

UDG-99061

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