TEXAS INSTRUMENTS UCC2540 Technical data

查询UCC2540供应商

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

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FEATURES

On-Chip Predictive Gate Drivet for

High-Efficiency Synchronous Buck Operation

D Dual ±3-A TrueDrivet Outputs D 1-MHz High Frequency Operation with 70-ns

Delay from SYNCIN to G1 Output

D Leading Edge Modulation D Overcurrent Protection using a Parallel

Average Current Mode Control Loop

D 3 Modes to Support 2.7-V to 35-V Bias

Operation

D Reverse Current Protection for Output Stage D User Programmable Shutdown D ±1.0% Initial Tolerance Bandgap Reference D High Bandwidth Error Amplifiers D Thermally Enhanced HTSSOP 20-Pin

PowerPADt Package

SIMPLIFIED APPLICATION DIAGRAM

APPLICATIONS

Secondary-Side Post Regulation (SSPR) for

Multiple Output Power Supplies

D Cascaded Buck Converters D Post Processing Converters for Bus

Converter and DC Transformer Architectures

DESCRIPTION

The UCC2540 is a secondary-side synchronous buck PWM controller for high current and low output voltage applications. It can be used either as the local secondary-side controller for isolated dc-to-dc converters using two-stage cascaded topologies or as a secondary-side post regulator (SSPR) for multiple output power supplies.

The UCC2540 runs with the synchronization signal from either the primary side or the high duty cycle quasi-dc output of bus converters or dc transformers. For higher efficiency, it also incorporates the Predictive Gate Drivet technology that virtually eliminates body diode conduction losses in synchronous rectifiers.

Input

Predictive Gate Drive, TrueDrive, and PowerPAD, are a trademarks of Texas Instruments Incorporated.

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UCC25701

OUT

UCC2540

SYNCIN

VEA−

7 2

REF

Main

10TR

COMP

G2C

CEA−

RSET

RAMP

Output

8 1 5

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VDRV

13 14

G2 G2S

12 16

VDD BST

19 18

G1 SWS

20 17

SW PGND

15 11

RSNS

Main

Output

AUX

Output

UDG−04057

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DESCRIPTION (CONT.)

The UCC2540 is available in the extended temperature range of –40°C to 105°C and is offered in thermally enhanced PowerPADt 20-pin HTSSOP (PWP) package. This space saving package with standard 20-pin TSSOP footprint has a drastically lower thermal resistance of 1.4°C/W θ high-current drivers on board.

to accommodate the dual

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VDD 36 V Supply current, I

Analog input voltages

Sink current (peak), I Source current (peak), I Operating junction temperature range, T Storage temperature, T Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal.

VDD

OUT_SINK

OUT_SOURCE

stg

VDD 50 mA CEA−, COMP, G2C, RAMP, SS, TR, VEA− −0.3 to 3.6 VDRV −0.3 to 9 G1, BST SW−0.3 to SW+9 SW, SWS −1 to 36 G2, G2S −1 to 9 SYNCIN −0.3 to 8.0 G1, G2 3.5 G1, G2 −3.5

(1)(2)

UCC2540 UNIT

−55 to 150

−65 to 150

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

Supply voltage, VDD Mode 1 8.5 35 Supply voltage, VDRV Mode 2 4.75 8.00 Supply voltage, REF Mode 3 3.0 3.3 3.6 Supply voltage bypass, C Reference bypass capacitor, C VDRV bypass capacitor, C BST−SW bypass capacitor, C Timer current resistor range, R PWM ramp capacitor range, C Turn-off capacitor range, C COMP pin load range, R Junction operating temperature, T

VDD

REF

VDRV

BST−SW

RSET

RAMP

G2C

LOAD

1.0 2.2

0.1 1.0 2.2

0.2

0.1 10 50 kΩ

100 680 120 1000

6.5 kΩ

−40 105 °C

°C

µF

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TA = T

ORDERING INFORMATION

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

−40°C to +105°C UCC2540PWP

(1)

The PWP package is also available at 70 devices per tube and taped and reeled at

2,000 devices per reel. Add an R suffix to the device type (i.e., UCC2540PWPR). See the application section of the data sheet for PowerPAD drawing and layout information.

HTSSOP−20 (PWP)

Bulk

(1)

CONNECTION DIAGRAM

PWP PACKAGE

(TOP VIEW)

RSET

REF G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

NOTE: The PowerPADt is not directly connected to any lead of the package. It is electrically and thermally connected to the substrate of the

device which acts as ground and should be connected to PGND on the PCB. The exposed dimension is 1.3 mm x 1.7 mm. However, the tolerances can be +1.05 mm / −0.05 mm (+41 mils / −2 mils) due to position and mold flow variation.

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12

SWS BST G1 SW VDD PGND G2 VDRV G2S

THERMAL INFORMATION

PACKAGE

FAMILY

PowerPAD

HTSSOP−20

PACKAGE

DESIGNATOR

PWP

(°C/W)

(with PowerPAD)

22.3 to 32.6

(500 to 0 LFM)

(°C/W)

(without PowerPAD)

19.9 1.4 125°C

(°C/W)

(with PowerPAD)

MAXIMUM DIE

TEMPERATURE

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, f

SYNCIN

= 200 kHz, TA = TJ = −40°C to 105°C, (unless otherwise noted).

PARAMETER

OVERALL

VDD

UNDERVOLTAGE LOCKOUT

VDD

VDRV

REF

VOLTAGE REFERENCE (REF)

REF

PWM (RAMP)

MIN

RAMP

DEAD

RAMP

CURRENT ERROR AMPLIFIER

CEA+

GBW Gain bandwidth

VOL

BIAS

SINK

CMR Common mode input range

(3)

Ensured by design. Not production tested.

Operating current

Start threshold voltage MODE 1 8.0 8.5 9.0 Stop threshold voltage MODE 1 7.5 8.0 8.5 Hysteresis MODE 1 0.3 0.5 0.8 Start threshold voltage MODE 2, V Stop threshold voltage MODE 2 4.0 4.3 4.6 Hysteresis MODE 2 0.15 0.35 0.55 Start threshold voltage MODE 3 V Stop threshold voltage MODE 3 2.25 2.50 2.70 Hysteresis MODE 3 0.3 0.5 0.8

Reference output voltage Short circuit current V

Line regulation 5.25 V ≤ V Load regulation 0 mA ≤ I

Minimum duty cycle 0% Offset voltage 0.10 0.25 0.45 Timeout threshold voltage 2.3 2.5 2.8 G1 deadtime at maximum duty cycle ratio f Ramp charge current R

Offset voltage Total variation 45 50 55 mV

(3)

Low-level output voltage

High-level output voltage Open loop 60 100 140 dB

Bias current −200 −80 −10 nA Sink current

(3)

TEST CONDITIONS MIN TYP MAX UNIT

DC 8 11 13 fS = 200 kHz, C

TA = 25°C 3.28 3.30 3.32 Total variation

= 0 V, TA = 25°C 10 13 20 mA

REF

≤ 7.2 V 0 1.5 15

REF

≤ 5 mA 0 30 70

REF

= 200 kHz 150 175 200 ns

SYNC

= 10 kΩ −325 −300 −275 µA

RSET

= 0 A, V

COMP

= 2.0 V

VEA−

= 200 µA, V

COMP

= 1 V

VEA−

= 0 A, V

COMP

= 1 V

VEA−

= 1.0 V, V

COMP

= 0 V

VEA−

= 2.2 nF

LOAD

= 4 V 4.30 4.65 4.85

VDD

CEA−

= V

= 3.3 V,

= 1.5 V

= 0 V,

= 1.5 V,

= 2.7 V 2.75 3.00 3.20

VDRV

9 12 30

3.2 3.3 3.4

3 4 MHz

0 0.60 0.83

2.2 2.5 3.0 V

0.35 0.80 1.70 mA 0 2 V

0.1

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, f

SYNCIN

= 200 kHz, TA = TJ = −40°C to 105°C, (unless otherwise noted)

PARAMETER

VOLTAGE ERROR AMPLIFIER

SS_OFF

TR_OFF

VEA+

GBW Gain bandwidth

VOL

BIAS

SINK

CURRENT SET

OUT

RSET

SYNCHRONIZATION AND SHUTDOWN TIMER (SYNCIN, G2C)

CHG(G2C)

SOFT-START (SS)

CH(SS)

DSCH(SS)

DRIVE REGULATOR (VDRV)

VDRV

G2S GATE DRIVE SENSE

G2S

SWS GATE DRIVE SENSE

SWS

(3)

Ensured by design. Not production tested.

Offset voltage from soft-start input I Offset voltage from tracking input VTR = 1.0 V, V

Threshold voltage (from VEA− to COMP)

(3)

Low-level output voltage

High-level output voltage Open loop 60 100 140 dB

Bias current −300 −150 −50 µA Sink current

Output current R R

SET

Timer threshold 2.3 2.5 2.7 SYNCIN threshold 1.50 1.65 1.80 Shutdown timer charge current R

Charge current R Discharge current R Discharge/shutdown threshold 0.35 0.45 0.55 V

Output voltage V Line regulation 9 V ≤ V Load regulation −5 mA ≤ I Short-circuit current 15 30 50 mA

G2S rising threshold voltage V G2S falling threshold voltage V Current V

SWS rising threshold voltage V SWS falling threshold voltage V Current V Negative threshold voltage −0.5 −0.3 −0.1 V

(4)

voltage R

TEST CONDITIONS MIN TYP MAX UNIT

= V

COMP

0°C ≤ TA ≤ 105°C 1.485 1.500 1.515 Total variation

= 0 A, V

COMP

= 2.0 V,

VEA−

= 200 µA, V

COMP

= 1 V, VTR = 0 V

VEA−

= 0 A, V

COMP

= 1 V

VEA−

= 1.0 V, V

COMP

= 1.5 V

VEA−

= 10 kΩ −158 −150 −142 µA

RSET

= 10 kΩ 1.42 1.50 1.58 V

RSET

= 10 kΩ −325 −300 −275 µA

RSET

= 10 kΩ −230 −200 −170

RSET

= 10 kΩ 50 70 100

RSET

= 8.5 V 6.87 7.20 7.53 V

VDD

= 0 V 1.90 2.25 3.10

SWS

= 0 V 1.00 1.25 1.03

SWS

= 0 V −0.70 −0.50 −0.37 mA

G2S

= 0 V 1.90 2.25 2.90

G2S

= 0 V 1.0 1.2 1.3

G2S

= 0 V −1.8 −1.3 −0.9 mA

SWS

VEA−,

≤ 35 V 0 50 100

≤ 0 mA 0 50 100

VDRV

= 1.5 V 0.40 0.75 1.00 V

SS− COMP

CEA−

= V

VEA−

= 1.75 V,

= 0 V,

= 0 V

= 0 V,

25 48 70 mV

1.47 1.50 1.53 3 4 MHz

0 0.60 0.83

2.2 2.5 3.0

0.35 0.80 1.70 mA

0.1

µA

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, f

SYNCIN

= 200 kHz, TA = TJ = −40°C to 105°C, (unless otherwise noted)

PARAMETER

G1 MAIN OUTPUT

SINK

SRC

SINK

SRCE

RISE

FALL

G2 SYNCHRONOUS RECTIFIER OUTPUT

SINK

SRC

RISE

FALL

DEADTIME DELAY (see Figure 1)

ON(G1)

OFF(G1)

ON(G2)

OFF(G2)

ON(G2)

OFF(G2)

(3)

Ensured by design. Not production tested.

Sink resistance VSW = 0 V, V Source resistance VSW = 0 V, V Sink current Source current Rise time C Fall time C

Sink resistance VG2 = 0.3 V 5 15 30 Ω Sink current Source current Rise time C Fall time C High-level output voltage, G2 VSW = GND 6.2 6.7 7.5 V

RAMP rising to G1 rising 90 115 130 SYNCIN falling to G1 falling 50 70 90

Delay control resolution 3.5 5.0 6.5 G2 on-time minimum wrt G1 falling −24

G2 on-time maximum wrt G1 falling 62 G2 off-time minimum wrt G1 rising −68 G2 off-time maximum wrt G1 rising 10

(3)

TEST CONDITIONS MIN TYP MAX UNIT

= 6 V, VG1 = 0.5 V 0.3 0.7 1.3

BST

= 6 V, VG1 = 5.7 V 10 25 45

BST

VSW = 0 V, V VSW = 0 V, V

= 2.2 nF, from G1 to SW 12 25

LOAD

= 2.2 nF, from G1 to SW 12 25

LOAD

VG2 = 3.25 V 3 VG2 = 3.25 V −3

= 2.2 nF, from G2 to PGND 12 25

LOAD

= 2.2 nF, from G2 to PGND 12 25

LOAD

OFF(G1)

= 6 V, VG1 = 3.0 V 3

BST

= 6 V, VG1 = 3.0 V −3

BST

Ω

SYNCIN

ERR

G2C

RAMP

ON(G1)

OFF(G2)

ON(G2)

Figure 1. Predictive Gate Drive Timing Diagram

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FUNCTIONAL BLOCK DIAGRAM

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

RSET

REF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

VREF

−

2 × I

SET

1.5V

VREF

SET

UVLO

2 × I

SET

ERROR

AMPLIFIERS

FAULT LOGIC

G1D

GLO

SYNC

AND

VDD

REFERENCE

G2 TIMER

RAMP

VERR

HUP

VREF

G2TO

CLK

100 ns

RAMP

PWM LOGIC

UVLO

VREF

VDDVDRV

1.33 × I

UVLO

PWM

SET

GLO

PREDICTIVE

LOGIC

PWR

G1D

DRIVE

REGULATOR

BIAS

PWR

PGND

HIGH SIDE

DRIVER

PGND

LOW SIDE

DRIVER

SWS

BST

VDD

PGND

VDRV

G2S

1.73 × I

SET

UDG−04056

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I/O

DESCRIPTION

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

PIN ASSIGNMENTS

TERMINAL

NAME NO.

BST 19 I CEA− 8 I Inverting input of the current error amplifier used for output current regulation.

COMP 9 I Output of the voltage and current error amplifiers for compensation. G1 18 O High-side gate driver output that swings between SW and BST. G2 14 O Low-side gate driver output that swings between PGND and VDRV.

G2C 3 I

G2S 12 I GND 6 − Ground for internal circuitry. GND and PGND should be tied to the pc-board ground plane with vias.

PGND 15 − Ground return for the G2 driver. Connect PGND to the pc-board ground plane with several vias. RAMP 5 I Input pin to connect capacitor to GND to generate the PWM ramp and serve as a maximum duty ratio timer.

(1)

REF

RSET 1 I

SS 11 I SYNCIN 4 I Input pin for timing signal.

SW 17 − G1 driver return connection. SWS 20 I TR 10 I Tracking input to the voltage error amplifier. Connect to REF when not used. VDD 16 I

VDRV 13 I VEA− 7 I Inverting input of the voltage error amplifier used for output voltage regulation.

(1)

REF is an input in Mode 3 only.

2 I/O

Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on time. Bypass BST to SW with an external capacitor.

Timer pin to turn off synchronous rectifier. The capacitor connected to this pin programs the maximum duration that G2 is allowed to stay HIGH.

Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate deadtime.

3.3-V reference pin. All internal circuits are powered from this 3.3-V rail. Bypass this pin with at least 0.1 µF of capacitance for REF loads that are 0 mA to −1 mA. Bypass this pin with at least 1 µF of capacitance if it is used as an input (Mode 3) or if it has large or pulsating loads.

Pin to program timer currents for G2C, RAMP, SS charge and SS discharge. This pin generates a current proportional to the value of the external resistor connected from RSET pin to GND. RSET range is 10 kΩ to 50 kΩ (giving a programmable nominal ISET range of 30 µA to 150 µA, respectively).

Soft start and shutdown pin. Connect a capacitor to GND to set the soft-start time. Add switch to GND for immediate shutdown functionality.

Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain close to the MOSFET package.

Power supply pin to the device and input to the internal VDRV drive regulator. Normal VDD range is from 4.5 V to 36 V. Bypass the pin with at least 1 µF of capacitance.

Output of the drive regulator and power supply pin for the G2 driver. VDRV is also the supply voltage for the internal logic and control circuitry.

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APPLICATION INFORMATION

The UCC2540 is a high-efficiency synchronous buck controller that can be used in many point-of-load applications. It can be used as a local controller for cascaded techniques such as post processing converters for isolated integrated bus converters (IBC) and dc transformer architectures. It can also be used as a general purpose secondary-side post regulator for high-accuracy multiple-output power supplies.

Using UCC2540 as the Secondary-Side PWM Controller in the Cascaded Push-Pull Buck Two Stage Converter

The two-stage cascaded push-pull buck topology converts higher-input bus voltage such as 48-V telecom voltage to sub 2-V output voltages.

Q2’

NS2

13 14 13 16 19 18 20 17 15 11

VDRV G2 G2S VDD BST G1 SWS SW PGND SS

UCC2540

SYNCIN

VEA−

REF

COMP

G2C

CEA− RSET

RAMP

7 2

10TR

8 1 5

VIN

48−V

NP1

OUT1 OUT2

SYNC

UCC28089

NP2

NS1

Q2Q1

Q1’

CLOCK RESET

Figure 2. Secondary-Side Controlled Cascaded Push-Pull/Buck Converter

The primary-side power stage is an open loop push-pull converter that provides voltage step-down, and galvanic isolation. This takes the high bus voltage and converts it into an intermediate voltage such as 7 V. The primary-side push-pull gate drive signals can come from either off-the-shelf oscillators or a fully integrated 50% duty dual-output oscillator such as the UCC28089.

OUT1

UDG−02140

The secondary-side power stage is a buck converter that is optimized for low-output voltage regulation. The clock reset pulse signal from the primary side is transmitted using a signal transformer.

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APPLICATION INFORMATION

There are many advantages to this secondary-side control circuit. The simple isolated power stage does not require any feedback across the isolation boundary. Since the primary-side oscillator is free running, there is no need for an isolated start-up power supply. This high-frequency circuit provides soft-switching operation (for all six MOSFET switches), optimum transformer core utilization, and minimizes filter requirements because there are no additional high-current inductors.

The push-pull primary side permits simple direct drive control of the input stage MOSFETs. In exchange, it requires that the input MOSFETs are rated to at least twice the peak input line voltage. This configuration works well for 36-V to 72-V input line applications, because there are many suitable power MOSFETs available in the range of 150 V. For applications with larger input voltages, a half bridge or full bridge with alternating modulation might be more suitable for an input stage. Thus, the cascaded topology has a large degree of flexibility with input power stages. The cascaded topology also has flexibility in the output stages, as well.

For additional information on this topology refer to Power Supply Seminar SEM−1300 Topic 1: Unique Cascaded Power Converter Topology for High Current Low Output Voltage Applications [1]. The topic discusses the operating principles, design trade-offs, and critical design procedure steps.

UCC2540 in Multiple Output Power Supplies

One such flexibility is an ability to easily add independently regulated auxiliary outputs. A multiple output implementation of the cascaded push-pull/buck power converter is shown in Figure 3.

Q2’

1418G2

UCC2540

SYNCIN

UCC2540

SYNCIN

OUT1

OUT2

UDG−02142

INPUT

NP1 NP2

Q1 Q2

OUT1 OUT2

SYNC

UCC28089

Q1’

PWM

CLOCK RESET

PWM2

SYNCIN

Figure 3. Multiple Output Implementation of Push-Pull/Buck Cascaded Converter

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APPLICATION INFORMATION

Using UCC2540 as the Secondary-Side Post Regulator

UCC2540 can also be used as a secondary-side post regulator (SSPR) for precision regulation of the auxiliary voltages of multiple output power supplies, as shown in Figure 4. The UCC2540 uses leading-edge modulation so that it is compatible with either voltage-mode or current-mode primary-side control converters using any topology such as forward, half-bridge or push-pull.

Q2’

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INPUT

NP1 NP2

Q1 Q2

OUT1 OUT2

UCC3808x

1FB

Q1’

PWM2

UCC2540

18G2G1

Figure 4. Multiple Output Converter with Primary Side Push−Pull Converter

SYNCIN

MAIN

OUTPUT

AUX

OUT1

UDG−02145

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APPLICATION INFORMATION

CEA− and VEA− pins: Current Limit and Hiccup Mode

Typical power supply load voltage versus load current is shown in Figure 5. This figure shows steady state operation for no-load to overcurrent shutdown (soft-start retry is not depicted in the diagram). During the voltage regulation conditions, the voltage error amplifier output is lower than the current error amplifier, allowing the voltage error amplifier to control operation. During the current limit conditions, the current error amplifier output is lower than the voltage error amplifier, allowing the current error amplifier to control operation. The boundary between voltage and current control occurs when the difference between CEA− and VEA− tries to exceed 50 mV.

Current limiting begins to occur when the difference between CEA− and VEA− exceeds 50 mV. For currents that exceed this operating condition, the UCC2540 controls the converter to operate as a pure current source until the output voltage falls to half of its rated steady state level. Then the UCC2540 sets both G1 and G2 outputs to LOW and it latches a fault that discharges the soft-start voltage at 30% of its charging rate. The UCC2540 inhibits a retry until the soft-start voltage falls below 0.5 V. A functional diagram of the voltage and current error amplifiers is shown in Figure 6.

REG

Limited Current

− Load Voltage − V

LOAD

Shutdown

− Load Current − A

LOAD

Figure 5. Typical Power Supply Load Voltage vs Current

UDG−04053

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