TEXAS INSTRUMENTS UCC2540 Technical data

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

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FEATURES

On-Chip Predictive Gate Drivet for

High-Efficiency Synchronous Buck Operation

D Dual ±3-A TrueDrivet Outputs D 1-MHz High Frequency Operation with 70-ns

Delay from SYNCIN to G1 Output

D Leading Edge Modulation D Overcurrent Protection using a Parallel

Average Current Mode Control Loop

D 3 Modes to Support 2.7-V to 35-V Bias

Operation

D Reverse Current Protection for Output Stage D User Programmable Shutdown D ±1.0% Initial Tolerance Bandgap Reference D High Bandwidth Error Amplifiers D Thermally Enhanced HTSSOP 20-Pin

PowerPADt Package

SIMPLIFIED APPLICATION DIAGRAM

APPLICATIONS

Secondary-Side Post Regulation (SSPR) for

Multiple Output Power Supplies

D Cascaded Buck Converters D Post Processing Converters for Bus

Converter and DC Transformer Architectures

DESCRIPTION

The UCC2540 is a secondary-side synchronous buck PWM controller for high current and low output voltage applications. It can be used either as the local secondary-side controller for isolated dc-to-dc converters using two-stage cascaded topologies or as a secondary-side post regulator (SSPR) for multiple output power supplies.

The UCC2540 runs with the synchronization signal from either the primary side or the high duty cycle quasi-dc output of bus converters or dc transformers. For higher efficiency, it also incorporates the Predictive Gate Drivet technology that virtually eliminates body diode conduction losses in synchronous rectifiers.

Input

Predictive Gate Drive, TrueDrive, and PowerPAD, are a trademarks of Texas Instruments Incorporated.

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UCC25701

OUT

UCC2540

SYNCIN

VEA−

7 2

REF

Main

10TR

COMP

G2C

CEA−

RSET

RAMP

Output

8 1 5

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VDRV

13 14

G2 G2S

12 16

VDD BST

19 18

G1 SWS

20 17

SW PGND

15 11

RSNS

Main

Output

AUX

Output

UDG−04057

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DESCRIPTION (CONT.)

The UCC2540 is available in the extended temperature range of –40°C to 105°C and is offered in thermally enhanced PowerPADt 20-pin HTSSOP (PWP) package. This space saving package with standard 20-pin TSSOP footprint has a drastically lower thermal resistance of 1.4°C/W θ high-current drivers on board.

to accommodate the dual

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VDD 36 V Supply current, I

Analog input voltages

Sink current (peak), I Source current (peak), I Operating junction temperature range, T Storage temperature, T Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages are with respect to GND. Currents are positive into, and negative out of the specified terminal.

VDD

OUT_SINK

OUT_SOURCE

stg

VDD 50 mA CEA−, COMP, G2C, RAMP, SS, TR, VEA− −0.3 to 3.6 VDRV −0.3 to 9 G1, BST SW−0.3 to SW+9 SW, SWS −1 to 36 G2, G2S −1 to 9 SYNCIN −0.3 to 8.0 G1, G2 3.5 G1, G2 −3.5

(1)(2)

UCC2540 UNIT

−55 to 150

−65 to 150

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

Supply voltage, VDD Mode 1 8.5 35 Supply voltage, VDRV Mode 2 4.75 8.00 Supply voltage, REF Mode 3 3.0 3.3 3.6 Supply voltage bypass, C Reference bypass capacitor, C VDRV bypass capacitor, C BST−SW bypass capacitor, C Timer current resistor range, R PWM ramp capacitor range, C Turn-off capacitor range, C COMP pin load range, R Junction operating temperature, T

VDD

REF

VDRV

BST−SW

RSET

RAMP

G2C

LOAD

1.0 2.2

0.1 1.0 2.2

0.2

0.1 10 50 kΩ

100 680 120 1000

6.5 kΩ

−40 105 °C

°C

µF

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TA = T

ORDERING INFORMATION

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

−40°C to +105°C UCC2540PWP

(1)

The PWP package is also available at 70 devices per tube and taped and reeled at

2,000 devices per reel. Add an R suffix to the device type (i.e., UCC2540PWPR). See the application section of the data sheet for PowerPAD drawing and layout information.

HTSSOP−20 (PWP)

Bulk

(1)

CONNECTION DIAGRAM

PWP PACKAGE

(TOP VIEW)

RSET

REF G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

NOTE: The PowerPADt is not directly connected to any lead of the package. It is electrically and thermally connected to the substrate of the

device which acts as ground and should be connected to PGND on the PCB. The exposed dimension is 1.3 mm x 1.7 mm. However, the tolerances can be +1.05 mm / −0.05 mm (+41 mils / −2 mils) due to position and mold flow variation.

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12

SWS BST G1 SW VDD PGND G2 VDRV G2S

THERMAL INFORMATION

PACKAGE

FAMILY

PowerPAD

HTSSOP−20

PACKAGE

DESIGNATOR

PWP

(°C/W)

(with PowerPAD)

22.3 to 32.6

(500 to 0 LFM)

(°C/W)

(without PowerPAD)

19.9 1.4 125°C

(°C/W)

(with PowerPAD)

MAXIMUM DIE

TEMPERATURE

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, f

SYNCIN

= 200 kHz, TA = TJ = −40°C to 105°C, (unless otherwise noted).

PARAMETER

OVERALL

VDD

UNDERVOLTAGE LOCKOUT

VDD

VDRV

REF

VOLTAGE REFERENCE (REF)

REF

PWM (RAMP)

MIN

RAMP

DEAD

RAMP

CURRENT ERROR AMPLIFIER

CEA+

GBW Gain bandwidth

VOL

BIAS

SINK

CMR Common mode input range

(3)

Ensured by design. Not production tested.

Operating current

Start threshold voltage MODE 1 8.0 8.5 9.0 Stop threshold voltage MODE 1 7.5 8.0 8.5 Hysteresis MODE 1 0.3 0.5 0.8 Start threshold voltage MODE 2, V Stop threshold voltage MODE 2 4.0 4.3 4.6 Hysteresis MODE 2 0.15 0.35 0.55 Start threshold voltage MODE 3 V Stop threshold voltage MODE 3 2.25 2.50 2.70 Hysteresis MODE 3 0.3 0.5 0.8

Reference output voltage Short circuit current V

Line regulation 5.25 V ≤ V Load regulation 0 mA ≤ I

Minimum duty cycle 0% Offset voltage 0.10 0.25 0.45 Timeout threshold voltage 2.3 2.5 2.8 G1 deadtime at maximum duty cycle ratio f Ramp charge current R

Offset voltage Total variation 45 50 55 mV

(3)

Low-level output voltage

High-level output voltage Open loop 60 100 140 dB

Bias current −200 −80 −10 nA Sink current

(3)

TEST CONDITIONS MIN TYP MAX UNIT

DC 8 11 13 fS = 200 kHz, C

TA = 25°C 3.28 3.30 3.32 Total variation

= 0 V, TA = 25°C 10 13 20 mA

REF

≤ 7.2 V 0 1.5 15

REF

≤ 5 mA 0 30 70

REF

= 200 kHz 150 175 200 ns

SYNC

= 10 kΩ −325 −300 −275 µA

RSET

= 0 A, V

COMP

= 2.0 V

VEA−

= 200 µA, V

COMP

= 1 V

VEA−

= 0 A, V

COMP

= 1 V

VEA−

= 1.0 V, V

COMP

= 0 V

VEA−

= 2.2 nF

LOAD

= 4 V 4.30 4.65 4.85

VDD

CEA−

= V

= 3.3 V,

= 1.5 V

= 0 V,

= 1.5 V,

= 2.7 V 2.75 3.00 3.20

VDRV

9 12 30

3.2 3.3 3.4

3 4 MHz

0 0.60 0.83

2.2 2.5 3.0 V

0.35 0.80 1.70 mA 0 2 V

0.1

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, f

SYNCIN

= 200 kHz, TA = TJ = −40°C to 105°C, (unless otherwise noted)

PARAMETER

VOLTAGE ERROR AMPLIFIER

SS_OFF

TR_OFF

VEA+

GBW Gain bandwidth

VOL

BIAS

SINK

CURRENT SET

OUT

RSET

SYNCHRONIZATION AND SHUTDOWN TIMER (SYNCIN, G2C)

CHG(G2C)

SOFT-START (SS)

CH(SS)

DSCH(SS)

DRIVE REGULATOR (VDRV)

VDRV

G2S GATE DRIVE SENSE

G2S

SWS GATE DRIVE SENSE

SWS

(3)

Ensured by design. Not production tested.

Offset voltage from soft-start input I Offset voltage from tracking input VTR = 1.0 V, V

Threshold voltage (from VEA− to COMP)

(3)

Low-level output voltage

High-level output voltage Open loop 60 100 140 dB

Bias current −300 −150 −50 µA Sink current

Output current R R

SET

Timer threshold 2.3 2.5 2.7 SYNCIN threshold 1.50 1.65 1.80 Shutdown timer charge current R

Charge current R Discharge current R Discharge/shutdown threshold 0.35 0.45 0.55 V

Output voltage V Line regulation 9 V ≤ V Load regulation −5 mA ≤ I Short-circuit current 15 30 50 mA

G2S rising threshold voltage V G2S falling threshold voltage V Current V

SWS rising threshold voltage V SWS falling threshold voltage V Current V Negative threshold voltage −0.5 −0.3 −0.1 V

(4)

voltage R

TEST CONDITIONS MIN TYP MAX UNIT

= V

COMP

0°C ≤ TA ≤ 105°C 1.485 1.500 1.515 Total variation

= 0 A, V

COMP

= 2.0 V,

VEA−

= 200 µA, V

COMP

= 1 V, VTR = 0 V

VEA−

= 0 A, V

COMP

= 1 V

VEA−

= 1.0 V, V

COMP

= 1.5 V

VEA−

= 10 kΩ −158 −150 −142 µA

RSET

= 10 kΩ 1.42 1.50 1.58 V

RSET

= 10 kΩ −325 −300 −275 µA

RSET

= 10 kΩ −230 −200 −170

RSET

= 10 kΩ 50 70 100

RSET

= 8.5 V 6.87 7.20 7.53 V

VDD

= 0 V 1.90 2.25 3.10

SWS

= 0 V 1.00 1.25 1.03

SWS

= 0 V −0.70 −0.50 −0.37 mA

G2S

= 0 V 1.90 2.25 2.90

G2S

= 0 V 1.0 1.2 1.3

G2S

= 0 V −1.8 −1.3 −0.9 mA

SWS

VEA−,

≤ 35 V 0 50 100

≤ 0 mA 0 50 100

VDRV

= 1.5 V 0.40 0.75 1.00 V

SS− COMP

CEA−

= V

VEA−

= 1.75 V,

= 0 V,

= 0 V

= 0 V,

25 48 70 mV

1.47 1.50 1.53 3 4 MHz

0 0.60 0.83

2.2 2.5 3.0

0.35 0.80 1.70 mA

0.1

µA

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ELECTRICAL CHARACTERISTICS

VDD = 12 V, 1-µF capacitor from VDD to GND, 1-µF capacitor from BST to SW, 1-µF capacitor from REF to GND, 0.1-µF and 2.2-µF capacitors from VDRV to PGND, f

SYNCIN

= 200 kHz, TA = TJ = −40°C to 105°C, (unless otherwise noted)

PARAMETER

G1 MAIN OUTPUT

SINK

SRC

SINK

SRCE

RISE

FALL

G2 SYNCHRONOUS RECTIFIER OUTPUT

SINK

SRC

RISE

FALL

DEADTIME DELAY (see Figure 1)

ON(G1)

OFF(G1)

ON(G2)

OFF(G2)

ON(G2)

OFF(G2)

(3)

Ensured by design. Not production tested.

Sink resistance VSW = 0 V, V Source resistance VSW = 0 V, V Sink current Source current Rise time C Fall time C

Sink resistance VG2 = 0.3 V 5 15 30 Ω Sink current Source current Rise time C Fall time C High-level output voltage, G2 VSW = GND 6.2 6.7 7.5 V

RAMP rising to G1 rising 90 115 130 SYNCIN falling to G1 falling 50 70 90

Delay control resolution 3.5 5.0 6.5 G2 on-time minimum wrt G1 falling −24

G2 on-time maximum wrt G1 falling 62 G2 off-time minimum wrt G1 rising −68 G2 off-time maximum wrt G1 rising 10

(3)

TEST CONDITIONS MIN TYP MAX UNIT

= 6 V, VG1 = 0.5 V 0.3 0.7 1.3

BST

= 6 V, VG1 = 5.7 V 10 25 45

BST

VSW = 0 V, V VSW = 0 V, V

= 2.2 nF, from G1 to SW 12 25

LOAD

= 2.2 nF, from G1 to SW 12 25

LOAD

VG2 = 3.25 V 3 VG2 = 3.25 V −3

= 2.2 nF, from G2 to PGND 12 25

LOAD

= 2.2 nF, from G2 to PGND 12 25

LOAD

OFF(G1)

= 6 V, VG1 = 3.0 V 3

BST

= 6 V, VG1 = 3.0 V −3

BST

Ω

SYNCIN

ERR

G2C

RAMP

ON(G1)

OFF(G2)

ON(G2)

Figure 1. Predictive Gate Drive Timing Diagram

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FUNCTIONAL BLOCK DIAGRAM

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

RSET

REF

G2C

SYNCIN

RAMP

GND

VEA−

CEA−

COMP

VREF

−

2 × I

SET

1.5V

VREF

SET

UVLO

2 × I

SET

ERROR

AMPLIFIERS

FAULT LOGIC

G1D

GLO

SYNC

AND

VDD

REFERENCE

G2 TIMER

RAMP

VERR

HUP

VREF

G2TO

CLK

100 ns

RAMP

PWM LOGIC

UVLO

VREF

VDDVDRV

1.33 × I

UVLO

PWM

SET

GLO

PREDICTIVE

LOGIC

PWR

G1D

DRIVE

REGULATOR

BIAS

PWR

PGND

HIGH SIDE

DRIVER

PGND

LOW SIDE

DRIVER

SWS

BST

VDD

PGND

VDRV

G2S

1.73 × I

SET

UDG−04056

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I/O

DESCRIPTION

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

PIN ASSIGNMENTS

TERMINAL

NAME NO.

BST 19 I CEA− 8 I Inverting input of the current error amplifier used for output current regulation.

COMP 9 I Output of the voltage and current error amplifiers for compensation. G1 18 O High-side gate driver output that swings between SW and BST. G2 14 O Low-side gate driver output that swings between PGND and VDRV.

G2C 3 I

G2S 12 I GND 6 − Ground for internal circuitry. GND and PGND should be tied to the pc-board ground plane with vias.

PGND 15 − Ground return for the G2 driver. Connect PGND to the pc-board ground plane with several vias. RAMP 5 I Input pin to connect capacitor to GND to generate the PWM ramp and serve as a maximum duty ratio timer.

(1)

REF

RSET 1 I

SS 11 I SYNCIN 4 I Input pin for timing signal.

SW 17 − G1 driver return connection. SWS 20 I TR 10 I Tracking input to the voltage error amplifier. Connect to REF when not used. VDD 16 I

VDRV 13 I VEA− 7 I Inverting input of the voltage error amplifier used for output voltage regulation.

(1)

REF is an input in Mode 3 only.

2 I/O

Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on time. Bypass BST to SW with an external capacitor.

Timer pin to turn off synchronous rectifier. The capacitor connected to this pin programs the maximum duration that G2 is allowed to stay HIGH.

Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the appropriate deadtime.

3.3-V reference pin. All internal circuits are powered from this 3.3-V rail. Bypass this pin with at least 0.1 µF of capacitance for REF loads that are 0 mA to −1 mA. Bypass this pin with at least 1 µF of capacitance if it is used as an input (Mode 3) or if it has large or pulsating loads.

Pin to program timer currents for G2C, RAMP, SS charge and SS discharge. This pin generates a current proportional to the value of the external resistor connected from RSET pin to GND. RSET range is 10 kΩ to 50 kΩ (giving a programmable nominal ISET range of 30 µA to 150 µA, respectively).

Soft start and shutdown pin. Connect a capacitor to GND to set the soft-start time. Add switch to GND for immediate shutdown functionality.

Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain close to the MOSFET package.

Power supply pin to the device and input to the internal VDRV drive regulator. Normal VDD range is from 4.5 V to 36 V. Bypass the pin with at least 1 µF of capacitance.

Output of the drive regulator and power supply pin for the G2 driver. VDRV is also the supply voltage for the internal logic and control circuitry.

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APPLICATION INFORMATION

The UCC2540 is a high-efficiency synchronous buck controller that can be used in many point-of-load applications. It can be used as a local controller for cascaded techniques such as post processing converters for isolated integrated bus converters (IBC) and dc transformer architectures. It can also be used as a general purpose secondary-side post regulator for high-accuracy multiple-output power supplies.

Using UCC2540 as the Secondary-Side PWM Controller in the Cascaded Push-Pull Buck Two Stage Converter

The two-stage cascaded push-pull buck topology converts higher-input bus voltage such as 48-V telecom voltage to sub 2-V output voltages.

Q2’

NS2

13 14 13 16 19 18 20 17 15 11

VDRV G2 G2S VDD BST G1 SWS SW PGND SS

UCC2540

SYNCIN

VEA−

REF

COMP

G2C

CEA− RSET

RAMP

7 2

10TR

8 1 5

VIN

48−V

NP1

OUT1 OUT2

SYNC

UCC28089

NP2

NS1

Q2Q1

Q1’

CLOCK RESET

Figure 2. Secondary-Side Controlled Cascaded Push-Pull/Buck Converter

The primary-side power stage is an open loop push-pull converter that provides voltage step-down, and galvanic isolation. This takes the high bus voltage and converts it into an intermediate voltage such as 7 V. The primary-side push-pull gate drive signals can come from either off-the-shelf oscillators or a fully integrated 50% duty dual-output oscillator such as the UCC28089.

OUT1

UDG−02140

The secondary-side power stage is a buck converter that is optimized for low-output voltage regulation. The clock reset pulse signal from the primary side is transmitted using a signal transformer.

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APPLICATION INFORMATION

There are many advantages to this secondary-side control circuit. The simple isolated power stage does not require any feedback across the isolation boundary. Since the primary-side oscillator is free running, there is no need for an isolated start-up power supply. This high-frequency circuit provides soft-switching operation (for all six MOSFET switches), optimum transformer core utilization, and minimizes filter requirements because there are no additional high-current inductors.

The push-pull primary side permits simple direct drive control of the input stage MOSFETs. In exchange, it requires that the input MOSFETs are rated to at least twice the peak input line voltage. This configuration works well for 36-V to 72-V input line applications, because there are many suitable power MOSFETs available in the range of 150 V. For applications with larger input voltages, a half bridge or full bridge with alternating modulation might be more suitable for an input stage. Thus, the cascaded topology has a large degree of flexibility with input power stages. The cascaded topology also has flexibility in the output stages, as well.

For additional information on this topology refer to Power Supply Seminar SEM−1300 Topic 1: Unique Cascaded Power Converter Topology for High Current Low Output Voltage Applications [1]. The topic discusses the operating principles, design trade-offs, and critical design procedure steps.

UCC2540 in Multiple Output Power Supplies

One such flexibility is an ability to easily add independently regulated auxiliary outputs. A multiple output implementation of the cascaded push-pull/buck power converter is shown in Figure 3.

Q2’

1418G2

UCC2540

SYNCIN

UCC2540

SYNCIN

OUT1

OUT2

UDG−02142

INPUT

NP1 NP2

Q1 Q2

OUT1 OUT2

SYNC

UCC28089

Q1’

PWM

CLOCK RESET

PWM2

SYNCIN

Figure 3. Multiple Output Implementation of Push-Pull/Buck Cascaded Converter

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APPLICATION INFORMATION

Using UCC2540 as the Secondary-Side Post Regulator

UCC2540 can also be used as a secondary-side post regulator (SSPR) for precision regulation of the auxiliary voltages of multiple output power supplies, as shown in Figure 4. The UCC2540 uses leading-edge modulation so that it is compatible with either voltage-mode or current-mode primary-side control converters using any topology such as forward, half-bridge or push-pull.

Q2’

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INPUT

NP1 NP2

Q1 Q2

OUT1 OUT2

UCC3808x

1FB

Q1’

PWM2

UCC2540

18G2G1

Figure 4. Multiple Output Converter with Primary Side Push−Pull Converter

SYNCIN

MAIN

OUTPUT

AUX

OUT1

UDG−02145

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APPLICATION INFORMATION

CEA− and VEA− pins: Current Limit and Hiccup Mode

Typical power supply load voltage versus load current is shown in Figure 5. This figure shows steady state operation for no-load to overcurrent shutdown (soft-start retry is not depicted in the diagram). During the voltage regulation conditions, the voltage error amplifier output is lower than the current error amplifier, allowing the voltage error amplifier to control operation. During the current limit conditions, the current error amplifier output is lower than the voltage error amplifier, allowing the current error amplifier to control operation. The boundary between voltage and current control occurs when the difference between CEA− and VEA− tries to exceed 50 mV.

Current limiting begins to occur when the difference between CEA− and VEA− exceeds 50 mV. For currents that exceed this operating condition, the UCC2540 controls the converter to operate as a pure current source until the output voltage falls to half of its rated steady state level. Then the UCC2540 sets both G1 and G2 outputs to LOW and it latches a fault that discharges the soft-start voltage at 30% of its charging rate. The UCC2540 inhibits a retry until the soft-start voltage falls below 0.5 V. A functional diagram of the voltage and current error amplifiers is shown in Figure 6.

REG

Limited Current

− Load Voltage − V

LOAD

Shutdown

− Load Current − A

LOAD

Figure 5. Typical Power Supply Load Voltage vs Current

UDG−04053

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From Power MOSFET Switch Node

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

APPLICATION INFORMATION

LOAD

1.25 R

Inverting Amplifier

ERR

Modulator

COMP

UCC2540

+ + +

50 mV

Voltage Error Amplifier

Current Error Amplifier

1.5 V

0.7 V +

1.5 V

VEA−

CEA−

ZFV

FIR

ZIV

UDG−04052

Figure 6. Error Amplifier Configuration

Component selection includes setting the voltage regulation threshold, then the current limit threshold, as described below.

Voltage vs. Current Programming (refer to Figure 6):

1. Determine the ratio

2. Sense resistor V

offset = 50 mV (typ).

CEA+

3. Arbitrarily select either R

VEA*

1 )

or RV2 so that the smallest of the two resistors is between 6.5 kΩ and 20 kΩ.

LOAD(reg)

) Threshold Voltage

offset voltage

CEA)

S(max)

* 1V+

, where I

LOAD(reg)

1.5 V (typ)

S(max)

* 1V

is the current limit level,

Then calculate the value of the other resistor using the equation in the first step.

If the converter is in a current-limit condition and the output voltage falls below half of the regulated output voltage, the UCC2540 enters into a hiccup (restart-retry) mode. Figure 7 shows typical signals during hiccup mode.

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

SYNCIN

3.3 V SS

0.5 V

LOAD

RAMP

G2C

APPLICATION INFORMATION

G1 G2

Figure 7. Typical Hiccup Mode waveforms

COMP, VEA− and CEA− pins: Voltage and Current Error Amplifiers

From no-load to full rated load operating conditions, the UCC2540 operates as a voltage mode controller . Above the programmed rated current, there are two levels of over current protection; constant current limit and overcurrent reset/retry. This section gives suggestions on how to design the voltage controller and current controller so that they interact with one another in a stable fashion. Refer to the functional diagram of the voltage and current error amplifiers in Figure 6. The voltage error amplifier in the figure shows three non-inverting inputs. The lowest of the three non-inverting inputs (1.5 V, SS and TR) is summed with the non-inverting input to achieve the voltage error signal. The lowest of the two outputs drives the inverting stage which in turn, drives the modulator.

During steady state voltage control operation, the feedback elements in the current loop have no effect on the loop stability. When current limit occurs, the voltage error amplifier effectively shuts OFF and the current error amplifier takes control. During steady state current limit operation, the negative feedback elements in the voltage error amplifier loop become positive feedback elements in the current error amplifier loop. In order for the current error amplifier to be stable, the impedances in the feedback path of the current error amplifier must be lower than the impedances in the feedback path of the voltage error amplifier. This means that resistors in the current error amplifier negative feedback path must be less than the resistors in the voltage error amplifier negative feedback path. Also capacitors in the current error amplifier negative feedback path must be larger than capacitors in the negative feedback path of the voltage error amplifier negative feedback path. (Capacitance is really an admittance value rather than an impedance value). This concept is illustrated in Figure 6.

UDG−04046

In order for the current loop to be stable in Figure 6, ||Z can be achieved if R

< RFV and C

> CFV.

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|| must be less than ||ZFV|| over all frequencies. This

SLUS539A − JUNE 2004 − REVISED AUGUST 2004



APPLICATION INFORMATION

Another issue that can occur during current limit operation is modulator stability. In order for the modulator to be stable, the rising slope of the current ripple measured at the COMP pin must be smaller than the rising slope that is measured at the RAMP pin. This can be met either in the selection of the ratio of ||Z the addition of a capacitor in parallel to R

Stable Dynamic Current Loop Design (refer to Figure 6):

1. Using any favorite approach, design the voltage error amplifier for stable voltage mode design. Use at least 15 kΩ for any resistors in the negative feedback path of the voltage error amplifier (between pins 9 and 7). This does not apply to resistance values between the power supply output voltage and pin 7; it also does not apply to resistance values between ground and pin 7.

2. The goal is to design the current limit control loop so that it drives the converter to maintain 50 mV between the VEA− pin and the CEA− pin during current-limit conditions. Select the current sense element and the voltage divider ratios for the VEA− pin to ground and the CEA− pin to ground to provide the desired current limit level.

3. Place the same configuration of components in the negative feedback path of the current error amplifier (between pins 9 and 8), that are in the negative feedback path of the voltage error amplifier (between pins 9 and 7). However, use resistors with values that are 67% of the corresponding resistors that are between pins 9 and 7 and use capacitors that are 150% of the corresponding capacitors that are between pin 9 and pin 7.

and CFI, such as C

, in Figure 6.

FIR

|| to ||ZFV||, or by



4. Check the COMP signal. If it is unstable, place a capacitor (or increase the capacitance) between pins 9 and 8 in order to attenuate the current ripple. Raise the value of the capacitor until the COMP pin voltage becomes stable. Compare the COMP voltage with the RAMP voltage. With stable operation, the rising slope of the COMP voltage ripple is less than the rising slope of the RAMP pin.

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APPLICATION INFORMATION

RSET, RAMP, G2C, SS pins: Programming the Timer Currents

Set the base current to the timers with a resistor between RSET and GND. The block diagram of the UCC2540 shows the interaction of the RSET pin and the dependent current sources for the RAMP, G2C and SS features. The RSET pin is a voltage source; the current of the RSET pin is reflected and multiplied by a gain and distributed to the RAMP (gain = 2), G2C (gain = 2) and SS (charge gain = 1.33, net discharge gain = 0.4). The resistance applied to the RSET pin and GND should be in the range of 10 kΩ < R are programmed by the selection of capacitors tied between each of their respective pins and GND.

G2C pin: G2 Timer

G2 Timeout

2 y I

RSET

G2C

2.5 V

Comparator

*G1D

< 50 kΩ. RAMP, G2C and SS timers

RSET

G2C

Latch

G2TO

G2C

GLO

UVLO

*G1 with delay, but not blanked

UDG−04047

Figure 8. Functional diagram of the G2 Timer

The G2C pin programs the maximum duration of the synchronous rectifier to facilitate low or zero duty ratio operation. FIgure 8 shows the functional diagram. This function is programmed by connecting a capacitor between the G2C pin and GND. The capacitor on G2C should be slightly larger than the capacitor on the RAMP pin. For best results, program the typical G2 time limit to be between 1.5 and 3 times the switching period (T). Notice that when the G2 timer reaches its limit, both G1 and G2 are forced to a LOW output. This feature prevents the current in the output inductor from excessive negative excursions during zero-duty ratio conditions. Program the G2 time-out (G2TO) duration using equation (1):

G2C

2 V

RSET

G2 Timeout Duration

G2C Timer Threshold

, Farads

where

D V D 1.5 T < G2 Timeout Duration < 3T

RSET

= 1.5 V(typ)

D G2C Timer Threshold = 2.5 V (typ)

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APPLICATION INFORMATION

RAMP pin: PWM Modulator and G1 Timer

The RAMP pin serves two purposes: (1) programming the gain of the PWM modulator and (2) programming the time-out duration of G1 in case the main power stage has not caused a SYNC pulse to occur. A diagram of the PWM modulator and G1 timer is shown in Figure 9. The UCC2540 has a leading edge modulator that compares the error output with the RAMP voltage. The modulator frequency is externally driven through the SYNCIN pin. The RAMP pin provides both a sawtooth wave for the PWM comparator and it functions as G1 time-out protection that is programmed by R

A switching cycle begins with the falling edge of the SYNCIN signal, which must be LOW for at least 50 nanoseconds. The falling edge of SYNCIN generates a 100 ns discharge strobe (CLK), to the RAMP function and then, allows the RAMP capacitor to charge from the 2 × I

and the value of the RAMP capacitor.

SET

current source.

RSET





RAMP

ENA

CLK

2 y I

RSET

ERR

250 mV

2.5 V G1 Timeout

Comparator

PWM Comparator

PWM

Latch

PWM

UDG−04048

Figure 9. PWM Modulator and G1 Time-Out Comparator

Low-line or brownout conditions can cause the primary side duty ratio to approach 100% where parasitic converter impedances may temporarily impair the quality of the SYNCIN pulse. The RAMP timing function terminates the G1 pulse when the RAMP voltage exceeds 2.5 V. The duration of the RAMP timing function should be set as follows:

RSET

timeout threshold voltage

RAMP

PWM

RAMP

where

D T

= switching period

D V D PWM

SET

RSET

RAMP

(RAMP)

= 1.5 (typ)

= 2.5 V (typ)

1.2

å Gain (PWM modulator) w 0.4

In order to use the G1 Timer feature, the peak RAMP voltage at the end of a switch cycle should be as close to 2.5 V as the C

RAMP

and R

tolerances allow. In other words, the PWM modulator gain should be

RSET

programmed to be equal to, or slightly greater than 0.4 inverse-V.

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APPLICATION INFORMATION

SYNCIN pin

A falling edge applied to the SYNCIN pin generates a narrow pulse that is the base timer for internal UCC2540 functions. The SYNCIN pulse must be HI for at least 100 ns preceding the falling edge and LOW for at least 50 ns in order to be registered as a valid pulse. Due to the critical nature of the timing, avoid filtering the falling edge of the SYNCIN signal in order to avoid signal delay. The peak SYNCIN voltage can easily range from between 2.5 V and 6.6 V, which allows a simple resistive divider to scale the secondary transformer voltage in post regulator applications.

Situations where the line voltage varies more extensively or there is extensive ringing may call for clamping and/or additional gain.

Ground Clamping

In applications where a ring or a spike causes SYNCIN to fall below GND, protect the pin with a Schottky diode (cathode = SYNCIN, anode = GND).

Overvoltage Clamping

The SYNCIN signal may require overvoltage clamping in applications where the peak SYNCIN voltage is perilously close to the absolute maximum level of 8 V, due to either ringing or voltage levels. The REF or VDRV can be used as clamp voltages, as in Figure 10. Make sure that REF or VDRV always sources current. The reason is that both REF and VDRV are used to detect the mode of operation when they are back-driven and they could latch into the wrong operating mode at start-up.

Main Output

UCC2540

2 REF

1 µF

4 SYNCIN

18G1

Auxiliary Output

14G2

UDG−04049

Figure 10. REF Clamp for SYNCIN. Note the REF Load Resistor.

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APPLICATION INFORMATION

Another overvoltage clamping option is to directly clamp the SYNCIN pin. Unfortunately, Zener diodes have excessive junction capacitance which causes too much delay in the signal. However, a base-emitter clamp that achieves the desired clamping action can be employed with minimal delay to the SYNCIN signal. See Figure 11. Simply select R the ratio of R

and (RCB + RBE) to give the appropriate 0 V to 3.3 V signal at low-line conditions. Then, select

to RBE to cause the transistor to turn-on when SYNCIN exceeds 4 V.

Main Output



UCC2540

4 SYNCIN

18G1

Auxiliary Output

14G2

UDG−04050

Figure 11. VBE Clamp for SYNCIN

SYNCIN Clamping for the Isolated Cascaded Buck Topology

The UCC2540 is ideally suited as a secondary side controller for the cascaded buck topology, when it is partnered with the UCC28089 primary side start-up controller. The primary side controller transmits a pulse edge during its dead time. The UCC2540 uses the primary-side pulse in order to provide zero voltage conditions for primary- and secondary-side switches. The predictive delay feature tunes the secondary-side transition to minimize reverse recovery losses in the synchronous rectifier. The pulse-edge information can vary with the primary side bias voltage and therefore, it must be clamped. The circuit shown in Figure 12 includes the appropriate pulse-edge shaping circuit, clamping and 1500-V isolation. The recommended transformer, COEV part # MGBBT−00011−01, is smaller than many opto-isolators.

Secondary GroundPrimary Ground

UCC28089

SYNC

GND

634 Ω

680 pF

15 µH

1:1

QCL 2N3904

UCC2540

REF

SYNCIN

Figure 12. Isolation and Clamping the SYNCIN Signal for Cascaded Buck Converters

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UDG−04051

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

APPLICATION INFORMATION

VDD, VDRV, VREF and BST pins: Modes of Operation

Depending on the available bias voltage for the UCC2540, the startup, shutdown, and restart conditions are different. There are three distinct configurations or modes of biasing the UCC2540. The mode is detected and latched into an internal register during power-up when VREF crosses 2 V. The register is cleared when VDD, VDRV and VREF are simultaneously less than 1 V. All modes are compatible with either cascaded buck or with secondary-side post regulator (SSPR) topologies. The main bias voltage of Modes 1 and 2 can be implemented with a diode and a capacitor from an ac-voltage such as the secondary winding of the transformer. A summary of the modes and their programming requirements are listed in Table 1.

Table 1. Modes and Programming Requirements

Mode

1 8.5 to 36 VDD [16] V

2 4.75 to 8.5 VDRV [13] V

3 3.0 to 3.6 VREF [2] V

BIAS

Range (V)

Bias Pin

UVLO ON

(V)

= 8.5 V

VDD

= 4.65 V

VDRV

= 3.0 V

REF

UVLO OFF

(V)

= 8.0

VDD

= 4.3

VDRV

= 2.5

REF

Mode Requirement

at Power-Up and

VREF

VDD

VDRV

REF

VDRV

VDD

V V

= 2 V

and V and V

and V

REF

VDRV

Remarks

Widest line operation

Needs regulated bias and low

VTH power MOSFETs

D Mode 1, or normal operation requires the availability of a bias of 8.5 V or higher for the device. Here, the

bias drives the VDD pin. The low-side drive bias, V and it directly draws current from the VDD pin. The high-side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin, when G2 is HI, via a diode between G2 and BST. The UCC2540 operates in Mode 1 if V

VDD

> (V

VDRV

and V

VREF

range of bias voltages, operational from 8.5 V < V have a 12 V

bias supply already available. Alternatively, Mode 1 is particularly useful for applications

where the input line voltage varies over a wide range and the bias is to be derived directly from the reflected line voltage, such as in Fig. 13.

= 7 V, is generated from an internal linear regulator

VDRV

) when V

< 35 V. This mode is compatible with systems that

VDD

rises above 2 V. Mode 1 permits the widest

VREF

D Mode 2 is suitable for applications where the bias is typically 5 V (between 4.5 V and 8.0 V). The bias

voltage is applied to the VDRV terminal of the UCC2540. The high-side driver bias is a flying capacitor that is charged from the VDRV pin through the G2 pin, when G2 is HI. Bias voltage to the VDD pin is obtained through an external voltage-doubler charge pump. If the system uses low threshold voltage power MOSFETs, VDD can be directly tied to the VDR V pin. The bias voltage could be either a bus converter output or an auxiliary supply, or the reflected converter input voltage that originates from a regulated source.

D Mode 3 is for synchronous buck converter applications where the bias voltage is a regulated 3.3-V source.

This is a common main output voltage in multiple output power converters. The bias voltage is applied to the VREF pin of the UCC2540. The UCC2540 operates in Mode 3 if it detects (V when V

rises above 2 V.

VREF

Assorted combinations of modes and biasing schemes are shown in Figure 13 through Figure 18. In Mode 1 and Mode 2, the bias voltage can either be an independent auxiliary supply or it can be generated by rectifying and filtering the reflected line voltage, as shown in Figure 13 through Figure 16. A regulated auxiliary supply must be used with Mode 3 because the tolerance of the VREF voltage is the control tolerance of the UCC2540. In Mode 3, the regulated auxiliary supply can be independent of the power supply input voltage (as shown in Figure 18) or, the regulated auxiliary supply can be the same source as the power supply input voltage.

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VREF

> V

VDRV

and VDD)

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

APPLICATION INFORMATION

UCC2540

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

Rectified Bias

8.5 V ≤ V

VDD

Vin 0 V

8.5 V ≤ VIN ≤ 35 V

Figure 13. Mode 1 With Rectified Biasing for Input Voltages Between 8.5 V and 35 V

UCC2540

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

AUX Bias

8.5 V ≤ V

≤ 35 V

VDD

0 V ≤ VIN ≤ 35 V

Vin 0 V

≤ 35 V

UDG−04038

UDG−04039

Figure 14. Mode 1 With Auxiliary Biasing for Bias Voltages Between 8.5 V and 35 V

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APPLICATION INFORMATION

UCC2540

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

4.75 V ≤ V

Rectified Bias

VDRV

Vin

0 V

Figure 15. Mode 2 With Rectified Biasing for Input Voltages Between 4.75 V and 8.0 V

AUX BiasUCC2540

4.75 V ≤ V

0 V ≤ VIN ≤ 35 V

Vin

0 V

VDRV

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

≤ 8.0 V

UDG−04040

≤ 8.0 V

UDG−04041

Figure 16. Mode 2 With Auxiliary Biasing for Bias Voltages Between 4.75 V and 8.0 V

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APPLICATION INFORMATION

UCC2540

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C3 C4

AUX Bias

4.75 V ≤ V

≤ 8.0 V

VDRV

0 V ≤ VIN ≤ 35 V

(Low VTH)

Vin 0 V

UDG−04042

Figure 17. Mode 2 With Auxiliary Biasing for Bias Voltages Between 4.75 V and 8.0 V and Low Threshold

Power MOSFET Transistors

UCC2540

Predictive

Logic

Drive (7.2 V)

Regulator

VREF (3.3 V)

Regulator

High−Side

Driver

Low−Side

Driver

VDD

VDRV

VREF

BST

SWS

G2S

PGND

C2 C4

Regulated 3.3-VDC Bias

4.75 V 3 V

D3D2

DC or Pulse Train

1.8 V 3 VIN 3 5 V

Q1 (Low VTH)

(Low VTH)

VDRV

3 8.0 V

UDG−04043

Figure 18. Mode 3 With Regulated 3.3-VDC Bias

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APPLICATION INFORMATION

Charge Pump Capacitor Selection

Capacitors C1 through C5 are all part of a charge distribution network that allows the UCC2540 to pass charge to the MOSFET gates of Q1 and Q2 (all reference designators in this section refer to the schematics in Figure 13 through Figure 18). This section gives guidelines on selecting the values of C1 through C5 so that the converter functions properly. Specific capacitor values may need to be larger than the recommended value due to MOSFET characteristics, diode D1 – D4 characteristics and closed-loop converter performance. All three modes of operation require a charge pump capacitor and diode, C1 and D1, in order to drive the high-side power MOSFET. Modes 2 and 3 require additional charge pump capacitors and diodes in order to supply voltage to VDD. In general, all charge pump diodes should be Schottky diodes in order to have low forward voltage and high speed. The charge pump capacitors should be ceramic capacitors with low effective series resistance (ESR), such as X5R or X7R capacitors.

The value of the charge pump capacitor C1 depends on the power MOSFET gate charge and capacitance, the voltage level of the Miller plateau threshold, the forward drop of D1 and the closed-loop response time. The unloaded high-side gate driver typically draws 2 nC of charge per rising edge plus 30 µA of direct current from C1. Usually, the unloaded high−side gate driver load is miniscule compared to the gate charge requirements of the high-side power MOSFET, Q1. Typical values for C1 are approximately 50 to 100 times the input capacitance (C where C1 does not have sufficient time to fully recharge. If C1 is excessively large, its ESR and ESL prevents it from recharging during transients, including the start-up transient.

) of MOSFET Q1. This usually allows for transient operation at extremely large duty ratio,

ISS

Capacitors C2 through C5 are then selected based on the direction of charge transfer and the requirements of the UCC2540. Selection guidelines are shown in Table 2. Keep in mind that each converter design may require adjustments for larger capacitor ratios than those that are suggested in Table 2. The selection process begins at the left side of Table 2 and progresses towards the right side of the table, which is the reverse order of the charge flow during the first few cycles of start-up. If iteration is required in the design process, review the progression of the capacitors in the order from left to right that is shown in the table.

Table 2. Charge Pump and Bias Capacitor Selection Guidelines

Mode

1 C1 > 50 C 2 C1 > 50 C

3 C1 > 50 C

High-Side Drive

Capacitor (≥ 0.1 µF)

ISS ISS

ISS

For Modes 2 and 3, the VDD filter capacitor, C4, in Table 2 must supply the I

VDRV Filter

Capacitor

C3 > 2 × C1 C2 > 0.1 µF C4 > 1 µF n/a C3 > 2 × C1 C2 > 0.1 µF C4 > 1 µF, 2 × C3 C5 > 2 × C4

C4 > 1 µF

2 × C1

VREF Filter

Capacitor

C2 > 1.0 µF C4 > 1 µF, 2 × C1 C5 > 2 × C4

VDD Filter

Capacitor

idle current to the UCC2540

VDD

VDD Charging

Capacitor

(approximately 11 mA) plus the charge to drive the gates G1 and G2. Capacitor C4 must be large enough to sustain adequate operating voltages during start-ups and other transients under the full operational I current. Knowing the operating frequency and the MOSFET gate charges (QG), the average I

current can

VDD

be estimated as:

VDD

D where f

+ I

VDD(idle)

is switching frequency

)

QG1) Q

In order to prevent noise problems, C4 must be at least 1 µF. Furthermore, it needs to be large enough to pass charge along to the power MOSFET gates. Thus C4 often needs to have at least twice the capacitance of the VDRV filter capacitor, as shown in Table 2.

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APPLICATION INFORMATION

Output Stage

The UCC2540 includes dual gate drive outputs and each is capable of ±3-A peak current. The pull-up/ pull-down circuits of the driver are bipolar and MOSFET transistors in parallel. High-side and low-side dual drivers provide a true 3-A high-current capability at the MOSFET’s Miller Plateau switching region where it is most needed. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the R saturation voltage of the bipolar transistor.

The output drivers can switch from VDD to GND. Each output stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external-schottky-clamp diodes are not required. The outputs are also designed to withstand 500-mA reverse current without either damage to the device or logic upset.

of the MOSFET transistor when the voltage on the driver output is less than the

DS(on)





For additional information on drive current requirements at MOSFET’s Miller plateau region, refer to the Power Supply Seminar SEM−1400

[2]

and the UCC37323/4/5 datasheet

[3]

Predictive Gate DriveTM Technology

The Predictive Gate Drive technology maximizes efficiency by minimizing body diode conduction. It utilizes a digital feedback system to detect body diode conduction, and adjusts the deadtime delays to minimize the conduction time interval. This closed loop system virtually eliminates body diode conduction while adjusting for different MOSFETs, temperature, and load dependent delays. Since the power dissipation is minimized, a higher switching frequency can be utilized, allowing for a smaller component size. Precise gate timing at the nanosecond level reduces the reverse recovery time of the synchronous rectifier MOSFET body diode, which reduces reverse recovery losses seen in the main (high-side) MOSFET. Finally, the lower power dissipation results in increased reliability.

19 BST

Predictive

Logic

VDRV

SWS

G2S

PGND

UDG−02149

Figure 19.

For additional information on Predictive Gate Drive control and efficiency comparisons to earlier adaptive delay and adaptive control techniques, refer to the UCC27223 datasheet

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APPLICATION INFORMATION

VDD and IDD

Although quiescent VDD current is low, total supply current is higher, depending on output gate drive requirements and the programmed oscillator frequency. Total VDD current (I current and the average output currents of G1 and G2, as described in equation (3). Knowing the operating frequency and the MOSFET gate charge (Q

+ QG f

), average driver output current, per gate, can be calculated from:

where

D f

is switching frequency

To prevent noise problems, connect a 1-µF ceramic capacitor between the VDD and GND pins. Place the 1-µF ceramic capacitor as close to the UCC2540 as possible. This capacitor is in addition to any electrolytic energy storage capacitors that may be used in the bias supply design.

Soft-Start and Tracking Features

Separate pins are provided for the soft-start feature and the tracking feature. Soft-start or tracking (sequencing) can be easily implemented with this configuration using a minimum number of external components. During a power-up transient, the converter output tracks the lower of the SS voltage, the TR voltage or a 1.5-V internal reference, provided the system is not in current limit. In other words, the voltage control loop is closed during power-up, provided the system is not current limited. Figure 20 shows the UCC2540 configured for soft-start operation. For applications that do not use the tracking feature, connect the TR pin to either SS or REF, as shown in the figure. Remote shutdown and sequential power-up can be easily implemented as a transistor switch across C

) is the sum of quiescent VDD

VDD

VEA−

HUP

REF (3.3 V)

1.33 y I

RSET

0.7 V

1.73 y I

1.5 V

RSET

UVLO

+ + +

50 mV

Figure 20. Using the Soft-Start Feature

UCC2540

Voltage

Error

Amplifier

COMP

To Positive Input of Current Error Amplifier

UDG−04045

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APPLICATION INFORMATION

The soft-start interval begins when the UCC2540 recognizes that the appropriate voltage (see Mode 1, 2 or 3) is above the UVLO level. The voltage of C

3.3V. Regulation should be reached when the soft-start voltage reaches about 2.2 V (1.5 V plus a diode drop). Select a C

capacitor value using equation (5) to program a desired soft-start duration, ∆tSS.

+ 1.33

RSET

SET

+ 1.33

If a UVLO fault is encountered, both outputs of the UCC2540 are disabled and the soft-start pin (SS) is discharged to GND. The UCC2540 does not retry until the UVLO fault is cleared.

Using the TR pin, the UCC2540 can be programmed to track another converter output voltage. If the voltage to be tracked is between 0 V and 3.3 V, simply connect the TR pin to the voltage to be tracked with a resistor that is approximately equal to the DC impedance that is connected to the VEA− terminal (R If the voltage is above that range, use a voltage divider, again with an equivalent resistance that approximately equals the DC impedance that is connected to the VEA− terminal. Other strategies can be used to achieve sequential, ratiometric or simultaneous power supply tracking

An implementation of sequential sequencing of a multiple output power supply Applications where the loads include a processor with a core voltage of 1.5 V and I/O ports that require 3.3 V can require sequential sequencing in order to resolve system level bus contention problems during start-up. In this circumstance the core must power-up first, then after an initialization period of 130 ms, the ports are allowed to power-up.

From Transformer Secondary

TPS3103K33

VDD

RESET

GND

PFO

PFI

then linearly increases until it is clamped at the REF voltage of

1.5 V R

1 kΩ

SET

2.2 V

UCC2540

1.6 kΩ

G1TR

Farads

[14

5 V

0 V

|| RV2, in Figure 6).

[5]

is shown in Figure 21.

I/O

3.3 V



10 kΩ

UCC2540

REF

Figure 21. Sequencing a Multiple Output Post Regulated Power Supply

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Core

1.5 V

UDG−04061

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

APPLICATION INFORMATION

Regulation loss due to loss of primary line voltage

3.3

V − Voltage − V

1.5

1.43

CORE

130 ms

I/O

t − Time

UDG−04061

Figure 22.

Using the TR pin, the UCC2540 can be programmed to ratio-metrically track another converter output voltage

[5]

Ratio-metric tracking is when the ratio of the output voltages is constant from zero volts to the point where one or more of the outputs lock into regulation. The TR pin is easier to use for tracking than the SS pin because the external currents that would be applied to the SS pin may interfere with SS discharge currents and fault recovery. It should be understood that the voltage that is being tracked must lag the bias voltages (VDD, VDRV and REF) on start-up and lead the bias voltages during shutdown. Furthermore, the output that is being tracked must not reach its steady state DC level before the output that is tracking reaches its steady state DC level. Figure 23 illustrates the concept of programming an output voltage V

Main Power Supply

(Leader)

, to ratio-metrically track another output, VM.

(Leader)

(Tracker)

(a)

ratio−metric sequencing

Core Power Supply

(Trader)

UCC2540

7TR

Tracking Ratio

(Leader)

(Tracker)

(Leader)

(Tracker)

(b)

simultaneous

sequencing

(c)

ratio−metric sequencing

UDG−04061

Figure 23. Ratio−Metric Tracking

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(7)

(8)

(9)

(10)

(11)

SLUS539A − JUNE 2004 − REVISED AUGUST 2004

APPLICATION INFORMATION

The general circuit to program the UCC2540 to track the leader supply voltage by the tracking ratio AT is shown in Figure 24. To program the tracking profile gains G that is listed below. The special case of simultaneous sequencing for V R

= RV1 and RT2= RV2, GT2 is not needed. In many other cases, the circuit can be simplified with the removal

of the operational amplifier for G

and the Zener clamping diode. If an operational amplifier is necessary, it

should be capable of rail to rail operation and usually low voltage bias; the TLV271 is an inexpensive solution for both of those requirements. Notice that the tracking circuit in Figure 24 also has a soft-start capacitor, C The soft-start capacitor is useful for limiting the time between short-circuit retry attempts and it can prevent overshoot when recovering from a fault that is experienced in only the tracking supply but not the main supply.

Ratio-Metric Tracking Design Procedure (see Figures 21 and 22)

1. Determine the tracking ratio, AT. M

where MC and MM are the soft-start slopes of VC and VM, respectively.

and GT2, follow the ratio-metric tracking design procedure

> 1.5V is the simplest to design; set





2. Determine G

RV1) R

where RV2 and RV1are selected when designing the voltage control loop.

3. Test G

a. If G

if necessary when VM ≤ 1.5 V or ATGV > 1.

is needed, set GT2 so that both equations (8) and (9) apply.

+ 1 )

so that both of the following apply:

b. If G

4. Set G

5. Select R

1.5 V

is not needed, set GT2 = 1.

AT G

and R

so that R

and G

RT1) R

|| R

AT G

≈ R

|| R

to minimize offset differences.

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

TLV271

RT1) R

needed only if VMGT1GT2 > 3 V

GT2+ 1 )

Use GT2 stage if ATGV > 1 OR if VMGT1 ≤ 1.5 V at steady-state

3.3 V

CSS

Rectified Secondary Voltage

UCC2540

G1TR

VEA−

Determined by voltage loop design

RV1) R

Main

Power

Supply

(Leader)

0 V

UDG−0405

Figure 24. Programming the UCC2540 to Track Another Output

More elaborate power supply sequencing and tracking can easily be implemented by extending the above techniques. Consult reference [5] for further information

THERMAL INFORMATION

The useful temperature range of a controller that contains high-current output drivers is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. The UCC2540 is available in the 20-pin HTSSOP PowerPADt package.

The PowerPAD semiconductor junction and therefore long term reliability improvement. As illustrated in [5], the PowerPAD packages offer a leadframe die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC board directly underneath the device package, reducing the θjc down to 2°C/W. Data is presented in [5] to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the heat removal subsystem, as summarized in [6] to realize a significant improvement in heat−sinking over standard non-PowerPAD surface mount packages.

HTSSOP-20 (PWP) offers the most effective means of removing the heat from the

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RAMP CURRENT

REGULATOR OUTPUT VOLTAGE

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

TYPICAL CHARACTERISTICS

3.40

3.35

3.30

− Reference Voltage − V

3.25

VREF

3.20

−50

OUTPUT REFERENCE VOLTAGE

TEMPERATURE

TJ − Junction Temperature − °C

50 100 150

Figure 25

TEMPERATURE

−275

−285

−295

−305

− Ramp Current − µA

RAMP

−315

−325

−50 0 50 100 15 TJ − Junction Temperature − °C

RSET

Figure 26

= 10 kΩ

G2C/IRAMP

1.1 I

G2C/IRAMP

1.0

G2C/IRAMP

0.9

0.8

µA/µA

0.7

0.6

0.5

ISS/I

−50 0 50 100 150

, R

RAMP

, R

RAMP

TJ − Junction Temperature − °C

AND ISS/I

TEMPERATURE

= 10 kΩ

RSET

= 50 kΩ

RSET

= 10 kΩ

RSET

= 50 kΩ

RSET

RAMP

Figure 27

7.6 MODE 1

7.4

7.2

− Regulator Output Voltage − V

7.0

VDRV

6.8

−50 0 50 100 15

TEMPERATURE

TJ − Junction Temperature − °C

Figure 28

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TRACKING TO VOLTAGE ERROR AMPLIFIER OFFSET

CURRENT ERROR AMPLIFIER OFFSET

INVERTING AMPLIFIER GAIN AND PHASE



SLUS539A − JUNE 2004 − REVISED AUGUST 2004

TYPICAL CHARACTERISTICS

− Offset Voltage − mV

TR(OS)

−50 0 50 100 15

TEMPERATURE

TJ − Junction Temperature − °C

Figure 29

− Current Error Amplifier Offset Voltage − m V

CEA−

−50 0 50 100 15

TEMPERATURE

TJ − Junction Temperature − °C

Figure 30

SYNCIN THRESHOLD VOLTAGE

1.80

1.75

1.70

TEMPERATURE

1.65

− Timing Signal Voltage − V

1.60

SYNCHIN

1.55

1.50

−50 0 50 100 150 TJ − Junction Temperature − °C

Figure 31

Gain − dB

−5

−10

−15

−20

−25

FREQUENCY

Phase

Gain

10 k 100 M1 k 1 M

100 k 10 M

f − Frequency − Hz

−45

−90

−135

−180

−225

−270

Phase − °

Figure 32

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CURRRENT ERROR AMPLIFIER GAIN AND PHASE

VOLTAGE ERROR AMPLIFIER GAIN AND PHASE

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

TYPICAL CHARACTERISTICS

Gain − dB

120

100

−20

−40

FREQUENCY

Gain

Phase

100 1 k 10 M 100 M10

f − Frequency − Hz

100 k 1 M10 k1

−45

−90

−135

−180

Phase − °

120

100

Gain − dB

−20

−40

Phase

100 1 k 10 M 100 M10 100 k 1 M10 k1

f − Frequency − Hz

Figure 33

FREQUENCY

Gain

−45

−90 Phase − °

−135

−180

Figure 34

OPERATING CURRENT (DC)

BIAS VOLTAGE

− Bias Current − mA 4

VDD

5 1525304003510 20

− Bias Voltage − V

VDD

Figure 35

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

TYPICAL CHARACTERISTICS

G2 Lower Gate

Drive (5V/div)

SW Node

(5V/div)

t − Time − 20 ns/div

Predictive

Delay

Adjustment

Figure 36. Predictive Gate Drive − G2 Falling

G2 Lower Gate

Drive (5V/div)

SW Node

(500 mV/div)

Synchronous

FET Body Diode

Conduction

t − Time − 20 ns/div

Figure 37. Predictive Gate Drive − G2 Falling

G2 Lower Gate Drive

Predictive

Delay

Adjustment

SW Node

t − Time − 20 ns/div

Figure 38. Predictive Gate Drive − G2 Falling

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SLUS539A − JUNE 2004 − REVISED AUGUST 2004

TEXAS INSTRUMENTS UCC2540 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual