TEXAS INSTRUMENTS UCC1809-1, UCC1809-2, UCC2809-1, UCC2809-2, UCC3809-1 Technical data

...

Economy Primary Side Controller

application

INFO

available

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

FEATURES

User Programmable Soft Start With

•

Active Low Shutdown User Programmable Maximum Duty

•

Cycle Accessible 5V Reference

•

Undervoltage Lockout

•

Operation to 1MHz

•

0.4A Source/0.8A Sink FET Driver

•

Low 100µA Startup Current

•

PART

NUMBER

UCCX809-1 10V 8V UCCX809-2 15V 8V

TURN ON

THRESHOLD

TURN OFF

THRESHOLD

DESCRIPTION

The UCC3809 family of BCDMOS economy low power integrated circuits contains all the control and drive circuitry required for off-line and isolated DC-to-DC fixed frequency current mode switching power supplies with minimal external parts count. Internally implemented circuits include

undervoltage lockout featuring startup current less than 100µA, a user ac cessible voltage reference, logic to ensure latched operation, a PWM com parator, and a totem pole output stage to sink or source peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off state.

Oscillator frequency and maximum duty cycle are programmed with two resistors and a capacitor. The UCC3809 family also features full cycle soft start.

The family has UVLO thresholds and hysteresis levels for off-line and DC-to-DC systems as shown in the table to the left.

The UCC3809 and the UCC2809 are offered in the 8 pin SOIC (D), PDIP (N), TSSOP (PW), and MSOP (P) packages. The small TSSOP and MSOP packages make the device ideal for applications where board space and height are at a premium.

TYPICAL APPLICATION DIAGRAM

FEEDBACK

CURRENT

SENSE

START

SLOPE

COMP

DISABLE

NOISE

FILTER

RT1

RT2

+5V

6µA

0.5V

OSC

– +

17.5V

REF

– +

REF

UDG-99036

OUT

VDD

OUT

GND

+ –

– +

CLK

PWM LATC H

REF

–

15/8V

10/8V

UVLO

SLUS166B - NOVEMBER 1999 - REVISED NOVEMBER 2004

ABSOLUTE MAXIMUM RATINGS*

VDD...........................................19V

..........................................25mA

VDD

(tpw < 1µs and Duty Cycle < 10%)........–0.4A to 0.8A

OUT

RT1, RT2, SS ......................–0.3V to REF + 0.3V

.........................................–15mA

REF

Storage Temperature ...................–65°C to +150°C

Junction Temperature...................–55°C to +150°C

Lead Temperature (Soldering, 10 sec.) .............+300°C

* Values beyond which damage may occur.

All voltages are with respect to ground unless otherwise stated. Currents are positive into, negative out of the specified termi nal. Consult Packaging Section of Databook for thermal limita tions and considerations of packages.

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

CONNECTION DIAGRAM

SOIC-8, DIL-8 (Top View) D, N and J Packages

TSSOP-8 (Top View) PW Package

RT1

RT2

REF

VDD

OUT

GND

MSOP-8 (Top View) P Package

RT1

RT2

REF

VDD

OUT

GND

ORDERING INFORMATION

Temperature Range Available Packages

UCC1809-X –55°C to +125°C J UCC2809-X –40°C to +85°C N, D, P, PW UCC3809-X 0°C to +70°C N, D, P, PW

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Supply Section

VDD Clamp I I

VDD

Starting (Note 1) 110 µA

VDD

Standby UCCx809-1, VDD = Start Threshold - 300mV 110 125 µA

VDD

Undervoltage Lockout Section

Start Threshold (UCCx809-1) 9.4 10.4 V UVLO Hysteresis (UCCx809-1) 1.65 V Start Threshold (UCCx809-2) 14.0 15.6 V UVLO Hysteresis (UCCx809-2) 6.2 V

Voltage Reference Section

Output Voltage I Line Regulation VDD = 10V to 15V 2 mV Load Regulation I

Comparator Section

Comparator Threshold 0.9 0.95 1 V OUT Propagation Delay (No Load) V

= 10mA 16 17.5 19 V

VDD

No Load 600 900 µA

UCCx809-2, VDD = Start Threshold - 300mV 130 170 µA

= 0mA 4.75 5 5.25 V

REF

= 0mA to 5mA 2 mV

REF

Output Off –100 nA

= 0.8V to 1.2V at TR= 10ns 50 100 ns

UCC 809 –

= 0.47 mF, VDD = 12V. TA=TJ.

VREF

UVLO OPTION

PACKAGE

TEMPERATURE RANGE

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

ELECTRICAL CHARACTERISTICS: Unless otherwise specified, C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Soft Start Section

Low VDD = 7.5V, ISS = 200mA 0.2 V

Shutdown Threshold 0.44 0.48 0.52 V

Oscillator Section

Frequency RT1 = 10k, RT2 = 4.32k, CT = 820pF 90 100 110 kHz Frequency Change with Voltage VDD = 10V to 15V 0.1 %/V

Peak Voltage 3.33 V

Valley Voltage 1.67 V

Peak to Peak Voltage 1.54 1.67 1.80 V

Output Section

Output V Output V Output Low Voltage During UVLO I Minimum Duty Cycle V Maximum Duty Cycle 70 % Rise Time C Fall Time C

Note 1. Ensured by design. Not 100% production tested.

Low I

SAT

High I

SAT

VDD = 16V, VSS = 0V; –40°Cto+85°C –4.9 –7.0 –9.1 mA VDD = 16V, V

= 80mA (dc) 0.8 1.5 V

OUT

= –40mA (dc), VDD – OUT 0.8 1.5 V

OUT

= 20mA (dc) 1.5 V

OUT

=2V 0 %

= 1nF 35 ns

OUT

= 1nF 18 ns

OUT

SS = 0V; < –40°C; >+85°C –4.0 –7.0 –10.0 mA

= 0.47 mF, VDD = 12V. TA=TJ.

VREF

PIN DESCRIPTIONS

FB: This pin is the summing node for current sense

feedback, voltage sense feedback (by optocoupler) and slope compensation. Slope compensation is derived from the rising voltage at the timing capacitor and can be buffered with an external small signal NPN transistor. External high frequency filter capacitance applied from this node to GND is discharged by an internal 250W on resistance NMOS FET during PWM off time and offers effective leading edge blanking set by the RC time constant of the feedback resistance from current sense resistor to FB input and the high frequency filter capacitor capacitance at this node to GND.

GND: Reference ground and power ground for all functions.

OUT: This pin is the high current power driver output. A minimum series gate resistor of 3.9W is recommended to limit the gate drive current when operating with high bias voltages.

REF: The internal 5V reference output. This reference is buffered and is available on the REF pin. REF should be bypassed with a 0.47mF ceramic capacitor.

RT2: This pin connects to timing resistor RT2 and controls the negative ramp time of the internal oscillator (Tf = 0.74 · (C

+ 27pF) · RT2). The negative threshold

of the internal oscillator is sensed through inactive timing resistor RT1 which connects to pin RT1 and timing capacitor C

SS: This pin serves two functions. The soft start timing capacitor connects to SS and is charged by an internal

6µA current source. Under normal soft start SS is discharged to at least 0.4V and then ramps positive to 1V during which time the output driver is held low. As SS charges from 1V to 2V soft start is implemented by an increasing output duty cycle. If SS is taken below 0.5V, the output driver is inhibited and held low. The user accessible 5V voltage reference also goes low and I

VDD

< 100mA. VDD: The power input connection for this device. This

pin is shunt regulated at 17.5V which is sufficiently below the voltage rating of the DMOS output driver stage. VDD should be bypassed with a 1mF ceramic capacitor.

RT1: This pin connects to timing resistor RT1 and controls the positive ramp time of the internal oscillator (Tr = 0.74 · (C

+ 27pF) · RT1). The positive threshold of

the internal oscillator is sensed through inactive timing resistor RT2 which connects to pin RT2 and timing capacitor C

APPLICATION INFORMATION

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

OUT

C19

C18

R17

12.1K

C14

470pF

C13

0.1µ F

R15

750

R14

H11AV1

10K

TL431

R16

12.1K

C17

C16

MBR2535CTL

R19

5.1K

C10

0.22 µF

R13

1.1K

OUT

–V

6.3V

330 µF

6.3V

330 µF

6.3V

330 µF

6.3V

330 µF

µF

C15

0.015

SF24

80µH

2N2907A

5:1

IRF640

R10

680

R11

0.15

15K

1N5245

+VIN

1µF

1N5240

470

PGND1

150 µF

27K

R12

UCC3809

150 µF

0.47 µF

0.1µ F

1µF

REF

VDD

TP1

OUT

RT1

GND

RT2

12.1K

ON/OFF

R20

5.62K

6.19K

5.1k

5231B

330pF

C22

0.1µ F

R18

3.01K

2N2222A

1nF

0.01 µF

2N2222A

1.1K

PGND1

–VIN

UDG-99179

Figure 1. Isolated 50W flyback converter utilizing the UCC3809. The switching frequency is 70kHz, Vin = -32V to

-72V, Vout = +5V, Iout = 0A to 10A

APPLICATION INFORMATION (cont.)

The Typical Application Diagram shows an isolated flyback converter utilizing the UCC3809. Note that the capacitors C

REF

and C tors for the reference and IC input voltage, respectively. Both capacitors should be low ESR and ESL ceramic, placed as close to the IC pins as possible, and returned directly to the ground pin of the chip for best stability. REF provides the internal bias to many of the IC func

tions and C

should be at least 0.47µF to prevent REF

REF

from drooping.

FB Pin

The basic premise of the UCC3809 is that the voltage sense feedback signal originates from an optocoupler that is modulated by an external error amplifier located on the secondary side. This signal is summed with the current sense signal and any slope compensation at the FB pin and compared to a 1V threshold, as shown in the Typical Application Diagram. Crossing this 1V threshold resets the PWM latch and modulates the output driver on-time much like the current sense comparator used in the UC3842. In the absence of a FB signal, the output will follow the programmed maximum on-time of the oscillator.

When adding slope compensation, it is important to use a small capacitor to AC couple the oscillator waveform before summing this signal into the FB pin. By correctly selecting the emitter resistor of the optocoupler, the voltage sense signal can force the FB node to exceed the 1V threshold when the output that is being compared ex ceeds a desired level. Doing so drives the UCC3809 to zero percent duty cycle.

Oscillator

are local decoupling capaci

VDD

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

reference) sensed through RT1. The R input to the oscil lator latch, R(OSC), is also level sensitive and resets the CLK signal low when CT crosses the 1.67V threshold,

turning off Q2 and turning on Q1, initiating another charg ing cycle.

Figure 3 shows the waveforms associated with the oscil lator latch and the PWM latch (shown in the Typical Ap

plication Diagram). A high CLK signal not only initiates a discharge cycle for CT, it also turns on the internal NMOS FET on the FB pin causing any external capacitance used for leading edge blanking connected to this pin to be discharged to ground. By discharging any external capacitor completely to ground during the external switch’s off-time, the noise immunity of the converter is enhanced allowing the user to design in smaller RC com ponents for leading edge blanking. A high CLK signal also sets the level sensitive S input of the PWM latch, S(PWM), high, resulting in a high output, Q(PWM), as shown in Figure 3. This Q(PWM) signal will remain high until a reset signal, R(PWM) is received. A high R(PWM) signal results from the FB signal crossing the 1V threshold, or during soft start or if the SS pin is disabled.

Assuming the UVLO threshold is satisfied, the OUT signal of the IC will be high as long as Q(PWM) is high and S(PWM), also referred to as CLK, is low. The OUT signal will be dominated by the FB signal as long as the FB signal trips the 1V threshold while CLK is low. If the FB signal does not cross the 1V threshold while CLK is low, the OUT signal will be dominated by the maximum duty

cycle programmed by the user. Figure 3 illustrates the

various waveforms for a design set up for a maximum duty cycle of 70%.

The following equation sets the oscillator frequency:

−

[]FCTpFRTRT

=•+ •+

OS C

DRTCTpFF

=•• + •074 1 27.

MAX OS C

()

074 27 1 2

()

Referring to Figure 2 and the waveforms in Figure 3, when Q1is on, CT charges via the R

DS(on)

of Q1 and RT1. During this charging process, the voltage of CT is sensed through RT2. The S input of the oscillator latch, S(OSC), is level sensitive, so crossing the upper thresh old (set at 2/3 VREF or 3.33V for a typical 5.0V refer ence) sets the Q output (CLK signal) of the oscillator latch high. A high CLK signal results in turning off Q1 and turning on Q2. CT now discharges through RT2 and the R

DS(on)

of Q2. CT discharges from 3.33V to the lower

threshold (set at 1/3 VREF or 1.67V for a typical 5.0V

REF

RT1

RT2

Figure 2. UCC3809 oscillator.

3.33V

1.67V

+ –

OSC

OS CILLAT OR

LATC H

UDG-97195

APPLICATION INFORMATION (cont.)

CHARGINGCTDISCHARG ING

3.33V

1.67V

S(OSC)

R(OSC)

Q(OSC)=CLK

=S(P WM)

R(PWM)

UCC1809-1/-2 UCC2809-1/-2 UCC3809-1/-2

Q(PWM)

OUT

FB S IG NAL DO MINAN T MAX. D UT Y CYCLE D O MINANT

Figure 3. Waveforms associated with the oscillator latch and the PWM latch.

The recommended value for CT is 1nF for frequencies in the 100 kHz or less range and smaller CT for higher fre

1000

quencies. The minimum recommended values of RT1 and RT2 are 10kΩ and 4.32kΩ, respectively. Using these

values maintains a ratio of at least 20:1 between the R

of the internal FETs and the external timing resis

DS(on)

tors, resulting in minimal change in frequency over tem perature. Because of the oscillator's susceptibility to

100

capacitive coupling, examine the oscillator frequency by looking at the common RT1-RT2-CT node on the circuit

FREQUENCY [kHz]

board as opposed to looking at pins 3 and 4 directly. For good noise immunity, RT1 and RT2 should be placed as close to pins 3 and 4 of the IC as possible. CT should be returned directly to the ground pin of the IC with minimal stray inductance and capacitance.

100 1000 10000

Figure 4. Oscillator frequency vs. CT(RT1 = 10k, RT2 = 4.32k)

70%

30% OFF

UDG-99037

CT [pF]

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