Texas Instruments UC3854DW, UC3854QTR, UC3854Q, UC3854N, UC3854DWTR Datasheet

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BLOCK DIAGRAM

• Control Boost PWM to 0.99 Power Factor

• Limit Line Current Distortion To <5%

• World-Wide Operation Without Switches

• Feed-Forward Line Regulation

• Average Current-Mode Control

• Low Noise Sensitivity

• Low Start-Up Supply Current

• Fixed-Frequency PWM Drive

• Low-Offset Analog Multiplier/Divider

• 1A Totem-Pole Gate Driver

• Precision Voltage Reference

The UC1854 provides active power factor correction for power sys­tems t hat otherwise would draw non-sinusoidal current from sinusoi­dal power lines. This device implements all the control functions
necessary to build a power supply capable of optimally using available
power- line current w hile mini mizing line-cur rent distort ion. To do t his,
the UC1854 contains a vo ltage amplifier, an analog m ultiplier/divider,
a current amplifier, and a fixed-frequency PWM. In addition, the
UC1854 c ontains a power MOSFET compatible gat e driver, 7.5V ref­ere nce, line anticipator, load-enable comparator, low-su pply detector,
and over-current comparator.

The UC1854 us es average current-mode control to accompli sh fixed­freque ncy current control with stability and low distortion. Unlike peak
current-mode, average current control accurately maintains sinusoidal
line curr ent without slope compensation and with minimal response to
noise transients.

The UC1854’s high reference voltage and high oscillator amplitude
minimi ze noise s ensitivity while fas t PWM elements permit choppi ng
freque ncies above 2 00kHz. The UC1854 can b e used in single and
three pha se systems with line voltages that vary from 75 to 275 volts
and l ine frequencies acr oss the 50Hz to 400H z range. To reduce the
bur den on t he cir cui try t hat s uppl ies pow er to this device, the UC1854
features low starting supply current.

These devi ces are available pack aged in 16-pin plastic and ceramic
dual in-line packages, and a variety of surface-mount packages.

UC1854
UC2854
UC3854

High Power Factor Preregulator

FEATURES

DESCRIPTION

UDG-92055

Supply Voltage VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V

GT Drv Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

GT Drv Current, 50% Duty Cycle. . . . . . . . . . . . . . . . . . . . . . . . . 1.5A

Input Voltage, V

SENSE

, V

RMS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V

Input Voltage, I

SENSE

, Mult Out . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V

Input Voltage, PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V

Input Current, R

SET

, IAC, PKLMT, ENA . . . . . . . . . . . . . . . . . . . 10mA

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Storage Temperature . . . . . . . . . . . . . . . . . . . . –65

o

C to +150oC

Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . . . . +300

o

C

ABSOLUTE MAXIMUM RATINGS

PACK AGE PIN FUN CTION

FUNCTION PIN

N/C 1
Gnd 2
PKLMT 3
CA Out 4
I

SENSE

5
N/C 6
Mult Out 7
I

AC

8
VA Out 9
V

RMS

10
N/C 11
V

REF

12
ENA 13
V

SENSE

14
R

SET

15
N/C 16
SS 17
C

T

18
V

CC

19
GT Drv 20

PLCC-20 & LCC-20
(Top V ie w )
Q & L Packages

CONNECTION DIAGRAMS

DIL–16 & SOIC-16
(Top V ie w )
J, N & DW Packages

Unless otherwise stated, VCC=18V, R

SET

=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,

V

RMS

=1.5V, IAC=100µA, I

SENSE

=0V, CA Out=3.5V, VA Out=5V, V

SENSE

=7.5V, no load on SS, CA Out,

VA Out, REF, GT Drv, –55

o

C<TA<125oC for the UC1854, –40oC<TA<85oC for the UC2854, and

0

o

C<TA<70oC for the UC3854, and TA=TJ.

ELECTRICAL
CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

OVERALL

Supply Current, Off ENA=0V 1.5 2.0 mA
Supply Current, On 10 16 mA
V

CC

Turn-On Threshold 14.5 16 17.5 V
VCC Turn-Off Threshold 9 10 11 V
ENA Threshold, Rising 2.4 2.55 2.7 V
ENA Threshold Hysteresis 0.2 0.25 0.3 V
ENA Input Current ENA=0V –5.0 –0.2 5.0 µA
V

RMS

Input Current V

RMS

=5V –1.0 –.01 1.0 µA

VOLTAGE AMPLIFIER

Voltage Amp Offset Voltage VA Out=5V –8 8 mV
V

SENSE

Bias Current –500 –25 500 nA
Voltage Amp Gain 70 100 dB
Voltage Amp Output Swing 0.5 to 5.8 V
Voltage Amp Short Circuit Current VA Out=0V –36 –20 –5 mA
SS Current SS=2.5V –20 –14 –6 µA

UC1854
UC2854
UC3854

Note 1: All voltages with respect to Gnd (Pin 1).
Note 2: All currents are positive into the specified termi­nal.
Note 3: ENA input is internally clamped to approximately
14V.
Note 4: Consult Unitrode Integrated Circuits databook for
information regarding thermal specifications and limita-

2

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CURRENT AMPLIFIER

Current Amp Offset Voltage –4 4 mV
I

SENSE

Bias Current –500 –120 500 nA

Input Range, I

SENSE

, Mult Out –0.3 to 2.5 V
Current Amp Gain 80 110 dB
Current Amp Output Swing 0.5 to 16 V
Current Amp Short Circuit Current CA Out=0V –36 –20 –5 mA
Current Amp Gain-BW Product T

A

=25oC (Note 6) 400 800 kHz

REFERENCE

Reference Output Voltage I

REF

=0mA, TA=25oC 7.4 7.5 7.6 V

I

REF

=0mA, Over Temp. 7.35 7.5 7.65 V

V

REF

Load Regulation –10mA<I

REF

<0mA –15 5 15 mV

V

REF

Line Regulation 15V<VCC<35V –10 2 10 mV

V

REF

Short Circuit Current REF=0V –50 –28 –12 mA

MULTIPLIER

Mult Out Current I

AC

Limited IAC=100µA, R

SET

=10k, V

RMS

=1.25V –220 –200 –180 µA

Mult Out Current Zero IAC=0µA, R

SET

=15k –2.0 –0.2 2.0 µA

Mult Out Current R

SET

Limited IAC=450µA, R

SET

=15k, V

RMS

=1V, VA Out = 6V –280 –255 –220 µA

Mult Out Current IAC=50µA, V

RMS

=2V, VA=4V –50 –42 –33 µA

IAC=100µA, V

RMS

=2V, VA=2V –38 –27 –12 µA

I

AC

=200µA, V

RMS

=2V, VA=4V –165 –150 –105 µA

IAC=300µA, V

RMS

=1V, VA=2V –250 –225 –150 µA

IAC=100µA, V

RMS

=1V, VA=2V –95 –80 –60 µA

Multiplier Gain Constant (Note 5) –1.0 V

OSCILLATOR

Oscillator Frequency R

SET

=15k 46 55 62 kHz

R

SET

=8.2k 86 102 118 kHz
CT Ramp Peak-to-Valley Amplitude 4.9 5.4 5.9 V
CT Ramp Valley Voltage 0.8 1.1 1.3 V

GATE DRIVER

Maximum GT Drv Output Voltage 0mA load on GT Drv, 18V<V

CC

<35V 13 14.5 18 V
GT Drv Output Voltage High –200mA load on GT Drv, VCC=15V 12 12.8 V
GT Drv Output Voltage Low, Off VCC=0V, 50mA load on GT Drv 0.9 1.5 V
GT Drv Output Voltage Low 200mA load on GT Drv 1.0 2.2 V

10mA load on GT Drv 0.1 0.4 V
Peak GT Drv Current 10nF from GT Drv to Gnd 1.0 A
GT Drv Rise/Fall Time 1nF from GT Drv to Gnd 35 ns
GT Drv Maximum Duty Cycle V

CA Out

=7V 95 %

CURRENT LIMIT

PKLMT Offset Voltage –10 10 mV
PKLMT Input Current PKLMT=–0.1V –200 –100 µA
PKLMT to GT Drv Delay PKLMT falling from 50mV to –50mV 175 ns

Unless otherwise stated, V

CC

=18V, R

SET

=15k to ground, CT=1.5nF to ground, PKLMT=1V, ENA=7.5V,

V

RMS

=1.5V, IAC=100µA, I

SENSE

=0V, CA Out=3.5V, VA Out=5V, V

SENSE

=7.5V, no load on SS, CA Out,

VA Out, REF, GT Drv, –55

o

C<TA<125oC for the UC1854, –40oC<TA<85oC for the UC2854, and

0

o

C<TA<70oC for the UC3854, and TA=TJ.

UC1854
UC2854
UC3854

Note 5: Multiplier Gain Constant (k) is defined by:

I

Mult Out

=

k

×

I

AC

× (

VA Out

−1)

V

RMS

2

Note 6: Guaranteed by design. Not 100% tested in production.

ELECTRICAL
CHARACTERISTICS

3