•Equally Usable For Either Positive
or Negative Regulator Design
•Adjustable Low Threshold Current
Sense Amplifier
•Under And Over-Voltage Fault Alert
With Programmable Delay
•Over-Voltage Fau lt Latch With
100mA Crowbar Drive Output
BLOCK DIAGRA M
DESCRIPTI ON
The UC1834 family of integrated circuits is optimized for the design of low
input-output differen tial linear regulators. A high gain amplifier and 200mA
sink or source drive outputs facilitate high output current designs which use
an external pass devi ce. With both positive and negative precision references, either polarity of regulator can be implemented. A current sense amplifier with a low, adjustable, threshold can be used to sense and limit
currents in either the positive or negative supply lines.
In addition, this series of parts has a fault monitoring circuit which senses
both under and ove r-voltage fault conditions. After a user defined delay for
transient reje ction, this circuitry provides a fault alert output for either fault
condition. In the over-voltage case, a 100mA crowbar output is activated.
An over-voltage latch will maintain the crowb ar output and can be used to
shutdown the driver outputs. System control to the device can be accommodated at a single input which will act as both a supply reset and remote
shutdown terminal. These die are protected against excessive power dissipation by an internal thermal shutdown function.
Lead Temperat ur e (sold ering , 10 secon ds). . . . . . . . . . . 300°C
Note 1: Volta ges are re fe ren ce t o V
Currents are positiv e into , negat ive out of th e specifi ed
terminals.
Consult Packag in g sect ion of Dat abo ok f or therm a l
limitations and cons id era tion s of packa ge.
Input Offs et Vo lta geV
Input Bias Cur rentV
Input Offs et Cu rr entV
Small Signal Open Loop Gain Output @ Pin 14, Pin 12 = V
CMRRV
PSRRV
Driver Sectio n
Maximum Output Current200350200350mA
Saturation Volta geI
Output Leakage Cu rrentPin 12 = 35V, Pin 13 = V
Shutdown Input Volta ge
at Pin 14
Shutdown In put Current
at Pin 14
Thermal Shutdown (Note 3)165165°C
Fault Amplifier Sect i on
Under- and Over-Voltage
Fault Threshold
Common Mode Sen sitivit yV
Supply SensitivityV
Fault Delay304560304560ms/µF
Fault Alert Out put Current2525mA
Fault Alert Satur ation Voltage I
O.V. Latc h Out put Curr ent2424mA
O.V. Latch Satura tion Voltag e I
O.V. Latch Out put Reset
Voltage
Crowbar Gate Current−100−175−100−175mA
Crowbar Gate Leakage
Current
Note 2: When using both th e 1.5V and −2.0V references t he cur rent out of pin 3 should be bala nced by an equivalent cur ren t into
−
Pin 2. The
2.0V outp ut will change −2.3mV per µA of imbalance.
Note 3: Thermal shut down turns off the drive r . If Pin 15 (O.V. Lat ch Out put ) is tied to P in 14 (Compe nsat ion/ Shu td own) the
O.V. Latch will be reset.
J = 25°C1.4851.51.5151.471.51.53V
T
J(MIN
IN+ = 5 to 35V110115mV
OUT = 0 to 2mA110115mV
J
= 25°C−2.04−2−1.96 −2.06−2−1.94V
T
T
J(MIN)≤ TJ ≤ TJ(MAX)−2.06−1.94 −2.08−1.92
IN+ = 5 to 35V1.5151.520mV
CM = 1.5V16110mV
CM = 1.5V−1−4−1−8µA
CM = 1.5V0.110.12µA
Pin 13, 20Ω to VIN−
CM = 0.5 to 33V, V
IN+ = 5 to 35V, VCM = 1.5V7010070100dB
OUT = 100mA0.51.20.51.5V
I
OUT≤ 100µA, Pin 13 = VIN−, Pin 12 =
V
IN+
Pin 14 = V
IOUT≤ 100µA, Pin 13 = VIN−
CM = 1.5V, @ E/A I n puts120150180110150190mV
V
IN+ = 35V, VCM = 1.5 to 33V−0.4−0.8−0.4−1.0%/v
CM = 1.5V, VIN+ = 5 to 35V−0.5−1.0−0.5−1.2%/V
OUT = 1mA0 .20.50.20.5V
OUT = 1mA1 .01.31.01.3V
V
IN+ = 35V, Pin 16 = VIN−−0.5−50−0.5−50µA
Unless otherwise stated, these specifications apply for TA=−55°C to +125°C
for the UC1834, −40°C to +85°C for the UC2834, and 0°C to +70°C for the
UC3834. V
≤ TJ ≤ TJ(MAX)1.471.531.4551.545
)
IN−, Pin 12 = VIN+
IN+ = 15V , V IN− = 0V, TA = TJ.
UC1834
UC3834UNITS
UC2834
MINTYPMAXMINTYPMAX
IN+
+
= 35V60806080dB
IN
IN−, Pin 14 = VIN−0.1500.150µA
50655065dB
0.410.41V
−100−150−100−150µA
0.30.40.60.30.40.6V
3
UC1834
UC2834
UC3834
ELECTRICAL CHARACTERISTICS:
Unless otherwise stated, these specifications apply for TA=−55°C to +125°C
for the UC1834, −40°C to +85°C for the UC2834, and 0°C to +70°C for the
UC3834. V
PARAMETERTEST CONDITIONS
Current Sense Amplifier Section
Threshold Volt agePin 4 Open, V
Pin 4 = 0.5V, V
Threshold Sup ply Sensit ivity Pin 4 Open, V
Adj. Input Cur ren tPin 4 = 0.5V−2−10−2−10µA
Sense Inpu t Bias CurrentV
CM = VIN+100200100200µA
V
CM = VIN−−100−200−100−200
CM = VIN+ or VIN−130150170120150180mV
CM
CM = VIN−, VIN+ = 5 to 35V−0.1−0.3−0.1−0.5%/V
Current Sense Th reshold Adj ust ment
IN+ = 15V , V IN− = 0V. TA = TJ
UC1834
UC2834
MINTYPMAXMINTYPMAX
= VIN+ or VIN−405060305070
UC3834UNITS
Current Limiting Knee Characteristics
Error Amplifier Gain and Phase
Frequency Response
Differential Voltage at Curren t Sense
Inputs - mV (reference to sense − input)
Current Sense Amplifier Gai n an d Ph as e
Frequency Respo n s e
4
APPLICATION INF ORMATI ON
UC1834
UC2834
UC3834
Foldback Current Limiti n g
Both the curren t sense and error ampl ifie rs on the UC1834
are tran scondu ctan ce type a mpli fier s. A s a resu lt, their v olt age gain is a direct func tion of the load impedance at their
shared output pin, Pin 14. Their small signal voltage gain as
a function of load and frequency is nominally given by;
Z
L
A
V E
for: f
⁄
A
≤
(f)
=
700
and A
Ω
500kHz and |ZL(f)| ≤ 1 M
V C. S
Z
L
=
(f)
70Ω
. ⁄
A
Ω
Where:
A
V=Small Sign al Volta ge G ain t o pi n 1 4.
Z
L(f) = Load Impedance at Pin 14.
The UC1834 fault delay circuitry prevents the fault outputs
from responding to transient fault conditions. The delay reset
latch insures that the f ull, use r def ined, delay pass es befo re an
over-voltage fault respon se occurs. This p reven ts un necessa ry
crowbar, or latched-off conditions, from occurring following
sharp under-voltage to over-voltage transients.
Setting the Thresho l d Adju st Vo lt age ( V
The crowbar output on the UC1834 is activated following a
sustained over-voltage condition. The crowbar output remains
high as long as the fault condition persists, or, as long as the
over-voltage latch is set. The latch is set with an over-voltage
fault if the voltage at Pin 15 is above the latch reset threshold,
typically 0.4V. When the latch is set, its Q− output will pull Pin
15 low through a series diode. As long as a nominal pull-up
load exists, the series diode prevents Q− from pulling Pin 15
below the reset threshold. However, Pin 15 is pulled low
enough to disable the driver outputs if Pins 15 and 14 are
tied together. With Pin 15 and 14 common, the regulator
will latch off in response to an over-voltage fault. If the
fault condition is cleared and Pins 14 and 15 are momentarily pulled below the latch reset threshold, the driver outputs are re-enabled.
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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