Texas Instruments UC2878N, UC2875QPTR, UC2876N, UC2875QP, UC2875N Datasheet

UC1875/6/7/8
UC2875/6/7/8
UC3875/6/7/8

DESCRIPTION

The UC1875 family of integrated circuits implements control of a bridge
power stage by phase-shifting the switching of one half-bridge with respect
to the other, allowing constant frequency pulse-width modulation in combi

­nation with resonant, zero-voltage switching for high efficiency performance
at high frequencies. This family of circuits may be configured to provide
control in either voltage or current mode operation, with a separate
over-current shutdown for fast fault protection.

A programmable time delay is provided to insert a dead-time at the turn-on
of each output stage. This delay, providing time to allow the resonant
switching action, is independently controllable for each output pair (A-B,
C-D).

With the oscillator capable of operation at frequencies in excess of 2MHz,
overall switching frequencies to 1MHz are practical. In addition to the stan

­dard free running mode, with the CLOCKSYNC pin, the user may configure
these devices to accept an external clock synchronization signal, or may
lock together up to 5 units with the operational frequency determined by the
fastest device.

Protective features include an undervoltage lockout which maintains all out­puts in an active-low state until the supply reaches a 10.75V threshold.

1.5V hysteresis is built in for reliable, boot-strapped chip supply.
Over-current protection is provided, and will latch the outputs in the OFF
state within 70nsec of a fault. The current-fault circuitry implements
full-cycle restart operation.

Phase Shift Resonant Controller

FEATURES

•

Zero to 100% Duty Cycle Control

•

Programmable Output Turn-On Delay

•

Compatible with Voltage or Current
Mode Topologies

•

Practical Operation at Switching
Frequencies to 1MHz

•

Four 2A Totem Pole Outputs

•

10MHz Error Amplifier

•

Undervoltage Lockout

•

Low Startup Current –150µA

•

Outputs Active Low During UVLO

•

Soft-Start Control

• Latched Over-Current Comparator
With Full Cycle Restart

• Trimmed Reference

07/99

BLOCK DIAGRAM

UDG-95073

application

INFO

available

2

UC1875/6/7/8
UC2875/6/7/8
UC3875/6/7/8

Dil-20 (Top View)
J or N Package

ABSOLUTE MAXIMUM RATINGS

Supply Voltage (VC, VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . 20V

Output Current, Source or Sink

DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5A

Pulse (0.5µs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3A

Analog I/0s

(Pins 1, 2, 3, 4, 5, 6, 7, 15, 16, 17, 18, 19) . . . . –0.3 to 5.3V

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C

Note: Pin references are to 20 pin packages.All voltages are

with respect to ground.Currents are positive into, neg­ative out of, device terminals. Consult Unitrode
databook for information regarding thermal specifica­tions and limitations of packages.

SOIC-28, (Top View)
DWP Package

CONNECTION DIAGRAMS

Additional features include an error amplifier with band

­width in excess of 7MHz, a 5V reference, provisions for
soft-starting, and flexible ramp generation and slope com

­pensation circuitry.

These devices are available in 20-pin DIP, 28-pin
“bat-wing” SOIC and 28 lead power PLCC plastic pack

­ages for operation over both 0°C to 70°C and –25°C to
+85°C temperature ranges; and in hermetically sealed
cerdip, and surface mount packages for –55°C to +125°C
operation.

Device UVLO

Turn-On

UVLO

Turn-Off

Delay

Set

UC1875 10.75 9.25V Yes
UC1876 15.25V 9.25V Yes
UC1877 10.75V 9.25V No
UC1878 15.25V 9.25V No

DESCRIPTION (cont.)

PLCC-28 (Top View)
QP Package

3

UC1875/6/7/8
UC2875/6/7/8
UC3875/6/7/8

ELECTRICAL CHARACTERISTICS:

Unless otherwise stated, –55°C < TA< 125°C for the UC1875/6/7/8, –25°C < TA<

85°C for the UC2875/6/7/8 and 0°C < T

A

< 70°C for the UC3875/6/7/8, VC = VIN = 12V, R

FREQSET

= 12kΩ,C

FREQSET

= 330pF,

R

SLOPE

= 12kΩ, C

RAMP

= 200pF, C

DELAYSET A-B=CDELAYSET C-D

= 0.01µF, I

DELAYSET A-B=IDELAYSET C-D

= –500µA, TA=TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Undervoltage Lockout

Start Threshold UC1875/UC1877 10.75 11.75 V

UC1876/UC1878 15.25 V

UVLO Hysteresis UC1875/UC1877 0.5 1.25 2.0 V

UC1876/UC1878 6.0 V

Supply Current

I

IN

Startup VIN = 8V, VC = 20V, R

SLOPE

open, I

DELAY

= 0 150 600 µA

I

C

Startup VIN = 8V, VC = 20V, R

SLOPE

open, I

DELAY

= 0 10 100 µA

I

IN

30 40 mA

I

C

15 30 mA

Voltage Reference

Output Voltage T

J

= +25°C 4.92 5 5.08 V
Line Regulation 11 < VIN < 20V 1 10 mV
Load Regulation I

VREF

= –10mA 5 20 mV
Total Variation Line, Load, Temperature 4.9 5.1 V
Noise Voltage 10Hz to 10kHz 50 µVrms
Long Term Stability T

J

= 125°C, 1000 hours 2.5 mV

Short Circuit Current VREF = 0V, T

J

= 25°C 60 mA

Error Amplifier

Offset Voltage 515mV
Input Bias Current 0.6 3 µA
AVOL 1V < V

E/AOUT

< 4V 60 90 dB

CMRR 1.5V < V

CM

< 5.5V 75 95 dB
PSRR 11V < VIN < 20V 85 100 dB
Output Sink Current V

E/AOUT

= 1V 1 2.5 mA

Output Source Current V

E/AOUT

= 4V –1.3 –0.5 mA

Output Voltage High I

E/AOUT

= –0.5mA 4 4.7 5 V

Output Voltage Low I

E/AOUT

= 1mA 0 0.5 1 V
Unity Gain BW 7 11 MHz
Slew Rate 611 V/µsec

4

UC1875/6/7/8
UC2875/6/7/8
UC3875/6/7/8

ELECTRICAL CHARACTERISTICS:

Unless otherwise stated, –55°C < TA< 125°C for the UC1875/6/7/8, –25°C < TA<

85°C for the UC2875/6/7/8 and 0°C < T

A

< 70°C for the UC3875/6/7/8, VC = VIN = 12V, R

FREQSET

= 12kΩ,C

FREQSET

= 330pF,

R

SLOPE

= 12kΩ, C

RAMP

= 200pF, C

DELAYSET A-B=CDELAYSET C-D

= 0.01µF, I

DELAYSET A-B=IDELAYSET C-D

= –500µA, TA=TJ.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

PWM Comparator

Ramp Offset Voltage T

J

= 25°C (Note 3) 1.3 V
Zero Phase Shift Voltage (Note 4) 0.55 0.9 V
PWM Phase Shift (Note1) V

E/AOUT

> (Ramp Peak + Ramp Offset) 98 99.5 102 %

V

E/AOUT

< Zero Phase Shift Voltage 0 0.5 2 %

Output Skew (Note 1) V

E/AOUT

< 1V 5 ±20 nsec

Ramp to Output Delay UC3875/6/7/8 (Note 6) 65 100 nsec

UC1875/6/7/8, UC2875/6/7/8 (Note 6) 65 125 nsec

Oscillator

Initial Accuracy T

J

= 25°C 0.85 1 1.15 MHz
Voltage Stability 11V < VIN < 20V 0.2 2 %
Total Variation Line, Temperature 0.80 1.20 MHz
Sync Pin Threshold T

J

= 25°C 3.8 V
Clock Out Peak T

J

= 25°C 4.3 V
Clock Out Low T

J

= 25°C 3.3 V

Oscillator (cont.)

Clock Out Pulse Width R

CLOCKSYNC

= 3.9kΩ 30 100 nsec

Maximum Frequency R

FREQSET

= 5kΩ 2 MHz

Ramp Generator/Slope Compensation

Ramp Current, Minimum I

SLOPE

= 10µA, V

FREQSET

= VREF –11 –14 µA

Ramp Current, Maximum I

SLOPE

= 1mA, V

FREQSET

= VREF –0.8 –0.95 mA
Ramp Valley 0V
Ramp Peak - Clamping Level R

FREQSET

= 100kΩ 3.8 4.1 V

Current Limit

Input Bias V

CS

+ = 3V 2 5 µA
Threshold Voltage 2.4 2.5 2.6 V
Delay to Output UC3875/6/7/8 85 125 nsec

UC1875/6/7/8, UC2875/6/7/8 85 150 nsec

Soft-Start/Reset Delay

Charge Current V

SOFTSTART

= 0.5V –20 –9 –3 µA

Discharge Current V

SOFTSTART

= 1V 120 230 µA
Restart Threshold 4.3 4.7 V
Discharge Level 300 mV