TEXAS INSTRUMENTS UC1842, UC1843, UC1844, UC1845 Technical data

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Current Mode PWM Controller

UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5

FEATURES

Optimized For Off-line And DC

•

To DC Converters Low Start Up Current (<1mA)

•

Automatic Feed Forward

•

Compensation Pulse-by-pulse Current Limiting

•

Enhanced Load Response

•

Characteristics Under-voltage Lockout With

•

Hysteresis Double Pulse Suppression

•

High Current Totem Pole

•

Output

• Internally Trimmed Bandgap Reference

• 500khz Operation

• Low R

O Error Amp

DESCRIPTION

The UC1842/3/4/5 family of control ICs provides the necessary features to implement off-line or DC to DC fixed frequency current mode control schemes with a minimal external parts count. Internally implemented circuits include under-voltage lockout featuring start up current less than 1mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N Channel MOSFETs, is low in the off state.

Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line applications. The corresponding thresholds for the UC1843 and UC1845 are

8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles approaching 100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.

BLOCK DIAGRAM

Note 1: A = DIL-8 Pin Number. B = SO-14 and CFP-14 Pin Number. Note 2: Toggle flip flop used only in 1844 and 1845.

A/B

SLUS223A - APRIL1997 - REVISED MAY 2002

ABSOLUTE MAXIMUM RATINGS(Note 1)

Supply Voltage (Low Impedance Source)..............30V

Supply Voltage (I

Output Current...................................±1A

Output Energy (Capacitive Load) ....................5µJ

Analog Inputs (Pins 2, 3)...................-0.3V to +6.3V

Error Amp Output Sink Current ....................10mA

Power Dissipation at T Power Dissipation at T

Storage Temperature Range..............-65°C to +150°C

Junction Temperature Range .............-55°C to +150°C

Lead Temperature (soldering, 10 seconds)...........300°C

Note 1: All voltages are with respect to Pin 5.

CC < 30mA) .................Self Limiting

A ≤ 25°C (DIL−8).................1W

A ≤ 25°C (SOIC-14) .........725mW

All currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.

CONNECTION DIAGRAMS

UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5

DIL-8, SOIC-8 (TOP VIEW) N or J Package, D8 Package

SOIC-14, CFP-14. (TOP VIEW) D or W Package

PLCC-20 (TOP VIEW) Q Package

PACKAGE PIN FUNCTION

FUNCTION PIN

N/C COMP N/C 3 N/C 4 VFB 5 N/C 6 ISENSE 7 N/C 8 N/C 9 RT/CT 10 N/C 11 PWR GND 12 GROUND 13 N/C 14 OUTPUT 15 N/C 16 VC 17 VCC 18 N/C 19 VREF 20

1 2

DISSIPATION RATING TABLE

Package TA ≤ 25°C

Power Rating

W 700 mW 5.5 mW/°C 452 mW 370 mW 150 mW

Derating Factor

Above TA ≤ 25°C

TA ≤ 70°C

Power Rating

TA ≤ 85°C

Power Rating

TA ≤ 125°C

Power Rating

UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5

ELECTRICAL CHARACTERISTICS:

PARAMETER TEST CONDITIONS

Unless otherwise stated, these specifications apply for -55°C≤TA≤125°C for the UC184X; -40°C≤T (Note 5); R

T = 10k; CT = 3.3nF, TA=TJ.

85°C for the UC284X; 0°C≤T

≤

UC1842/3/4/5

70°C for the 384X; V

≤

UC3842/3/4/5 UNITS

UC2842/3/4/5

MIN TYP MAX MIN TYP MAX

Reference Section

Output Voltage T Line Regulation 12≤V Load Regulation 1≤I

J = 25°C, IO = 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V

25V 6 20 6 20 mV

≤

20mA 6 25 6 25 mV

≤

Temp. Stability (Note 2) (Note 7) 0.2 0.4 0.2 0.4 mV/°C Total Output Variation Line, Load, Temp. (Note 2) 4.9 5.1 4.82 5.18 V Output Noise Voltage 10Hz≤f≤10kHz, T Long Term Stability T

A = 125°C, 1000Hrs. (Note 2) 5 25 5 25 mV

J = 25°C (Note2) 50 50

Output Short Circuit -30 -100 -180 -30 -100 -180 mA

Oscillator Section

Initial Accuracy T Voltage Stability 12≤V Temp. Stability T Amplitude V

J = 25°C (Note 6) 47 52 57 47 52 57 kHz

25V 0.2 1 0.2 1 %

≤

MIN PIN 4 peak to peak (Note 2) 1.7 1.7 V

≤

MAX (Note 2) 5 5 %

≤

Error Amp Section

Input Voltage V

PIN 1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V

Input Bias Current -0.3 -1 -0.3 -2 A

VOL 2

Unity Gain Bandwidth (Note 2) T PSRR 12≤V Output Sink Current V Output Source Current V V

OUT High VPIN 2 = 2.3V, RL = 15k to ground 5 6 5 6 V

OUT Low VPIN 2 = 2.7V, RL = 15k to Pin 8 0.7 1.1 0.7 1.1 V

4V 65 90 65 90 dB

≤

J = 25°C 0.7 1 0.7 1 MHz

25V 60 70 60 70 dB

≤

PIN 2 = 2.7V, VPIN 1 = 1.1V 2 6 2 6 mA PIN 2 = 2.3V, VPIN 1 = 5V -0.5 -0.8 -0.5 -0.8 mA

Current Sense Section

Gain (Notes 3 and 4) 2.85 3 3.15 2.85 3 3.15 V/V Maximum Input Signal V PSRR 12≤V

PIN 1 = 5V (Note 3) 0.9 1 1.1 0.9 1 1.1 V

25V (Note 3) (Note 2) 70 70 dB

≤

Input Bias Current -2 -10 -2 -10 Delay to Output V

PIN 3 = 0 to 2V (Note 2) 150 300 150 300 ns

CC = 15V

Note 2: These parameters, although guaranteed, are not 100% tested in production. Note 3: Parameter measured at trip point of latch with V

PIN 2 =0.

Note 4: Gain defined as

VPIN

∆

Note 5: Adjust V

VPIN V=≤≤

VPIN

CC above the start threshold before setting at 15V.

0308,.

Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.

Output frequency is one half oscillator frequency for the UC1844 and UC1845.

Note 7: Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:

V max VREF min

Temp Stability

REF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate

REF

TJ max TJ min

−

() ()

−

() ()

temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.

UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5

ELECTRICAL CHARACTERISTICS:

PARAMETER TEST CONDITION

Unless otherwise stated, these specifications apply for −55°C≤TA

UC184X; −40°C≤T 15V (Note 5); R

T = 10k; CT = 3.3nF, TA=TJ.

85°C for the UC284X; 0°C≤TA≤70°C for the 384X; VCC =

≤

UC1842/3/4/5

UC3842/3/4/5 UNITS

UC2842/3/4/5

125°C for the

≤

MIN TYP MAX MIN TYP MAX

Output Section

Output Low Level I

Output High Level I

Rise Time T Fall Time T

SINK = 20mA 0.1 0.4 0.1 0.4 V

SINK = 200mA 1.5 2.2 1.5 2.2 V SOURCE = 20mA 13 13.5 13 13.5 V

SOURCE = 200mA 12 13.5 12 13.5 V

J = 25°C, CL = 1nF (Note 2) 50 150 50 150 ns J = 25°C, CL = 1nF (Note 2) 50 150 50 150 ns

Under-voltage Lockout Section

Start Threshold X842/4 15 16 17 14.5 16 17.5 V

X843/5 7.8 8.4 9.0 7.8 8.4 9.0 V

Min. Operating Voltage After Turn On

X842/4 9 10 11 8.5 10 11.5 V X843/5 7.0 7.6 8.2 7.0 7.6 8.2 V

PWM Section

Maximum Duty Cycle X842/3 95 97 100 95 97 100 %

X844/5 46 48 50 47 48 50 %

Minimum Duty Cycle 0 0 %

Total Standby Current

Start-Up Current 0.5 1 0.5 1 mA Operating Supply Current V V

CC Zener Voltage ICC = 25mA 30 34 30 34 V

PIN 2 =VPIN 3 =0V 1117 1117mA

Note 2: These parameters, although guaranteed, are not 100% tested in production. Note 3: Parameter measured at trip point of latch with V

PIN 2 =0

Note 4: Gain defined as:

Note 5: Adjust V

CC above the start threshold before setting at 15V.

∆

VPIN

VPIN V=≤≤

0308;.

VPIN

Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.

Output frequency is one half oscillator frequency for the UC1844 and UC1845.

ERROR AMP CONFIGURATION

Error Amp can Source or Sink up to 0.5mA

UNDER-VOLTAGE LOCKOUT

UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5

During under-voltage lock-out, the output driver is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent

CURRENT SENSE CIRCUIT

Peak Current (IS) is Determined By The Formula

SMAX ′

A small RC filter may be required to suppress switch transients

OSCILLATOR SECTION

activating the power switch with extraneous leakage currents.

1.0V

OUTPUT SATURATION CHARACTERISTICS

OPEN-LOOP LABORATORY FIXTURE

UC1842/3/4/5 UC2842/3/4/5

ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE

High peak currents associated with capacitive loads ne cessitate careful grounding techniques. Timing and by pass capacitors should be connected close to pin 5 in a

SHUT DOWN TECHNIQUES

Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset domi nant so that the output will remain low until the next

single point ground. The transistor and 5k potentiometer

are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.

clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling V

UVLO threshold. At this point the reference turns off, al lowing the SCR to reset.

CC below the lower

OFFLINE FLYBACK REGULATOR

UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5

Power Supply Specifications

1. Input Voltages 5VAC to 130VA

2. Line Isolation 3750V

3. Switching Frequency 40kHz

4. Efficiency at Full Load 70%

SLOPE COMPENSATION

(50 Hz/60Hz)

5. Output Voltage: A. +5V,±5%; 1A to 4A load Ripple voltage: 50mV P-P Max

B. +12V,±3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max

C. -12V ,±3%; 0.1A to 0.3A load Ripple voltage: 100mV P-P Max

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%.

PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status

5962-8670401PA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC 5962-8670401VPA ACTIVE CDIP JG 8 1 None CallTI Level-NC-NC-NC 5962-8670401VXA ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC

5962-8670401XA ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

5962-8670402PA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC 5962-8670402VPA ACTIVE CDIP JG 8 1 None Call TI Level-NC-NC-NC 5962-8670402VXA ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC

5962-8670402XA ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

5962-8670403PA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC 5962-8670403VPA ACTIVE CDIP JG 8 1 None Call TI Level-NC-NC-NC 5962-8670403VXA ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC

5962-8670403XA ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

5962-8670404PA ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC 5962-8670404VPA ACTIVE CDIP JG 8 1 None Call TI Level-NC-NC-NC 5962-8670404VXA ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC

5962-8670404XA ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

UC1842J ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC1842J883B ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC1842JQMLV ACTIVE CDIP JG 8 None Call TI Call TI

UC1842L883B ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

UC1842W ACTIVE CFP W 14 1 None A42 SNPB Level-NC-NC-NC

UC1843J ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC1843J883B ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC1843JQMLV ACTIVE CDIP JG 8 None Call TI Call TI

UC1843L ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

UC1843L883B ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

UC1843LQMLV ACTIVE LCCC FK 20 None Call TI Call TI

UC1843W ACTIVE CFP W 14 1 None A42 SNPB Level-NC-NC-NC

UC1844J ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC1844J883B ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC1844JQMLV ACTIVE CDIP JG 8 None Call TI Call TI

UC1844L ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

UC1844L883B ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

UC1844LQMLV ACTIVE LCCC FK 20 None Call TI Call TI

UC1844W ACTIVE CFP W 14 1 None A42 SNPB Level-NC-NC-NC

UC1845J ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC1845J883B ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC1845JQMLV ACTIVE CDIP JG 8 None Call TI Call TI

UC1845L ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

UC1845L883B ACTIVE LCCC FK 20 1 None POST-PLATE Level-NC-NC-NC

UC1845LQMLV ACTIVE LCCC FK 20 None Call TI Call TI

UC1845W ACTIVE CFP W 14 1 None A42 SNPB Level-NC-NC-NC

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

4-Mar-2005

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

4-Mar-2005

UC2842D ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM

UC2842D8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM

UC2842D8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM

UC2842DR ACTIVE SOIC D 14 None Call TI Call TI

UC2842DTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM

UC2842DW ACTIVE SOIC DW 16 40 None CU NIPDAU Level-2-220C-1 YEAR

UC2842DWTR ACTIVE SOIC DW 16 2000 None CU NIPDAU Level-2-220C-1 YEAR

UC2842J OBSOLETE CDIP JG 8 None Call TI Call TI

UC2842N ACTIVE PDIP P 8 50 Pb-Free

CU SNPB Level-NC-NC-NC

(RoHS) UC2842P OBSOLETE PDIP P 8 None Call TI Call TI UC2843D ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM

UC2843D8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM

UC2843D8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM

UC2843DR OBSOLETE SOIC D 14 None Call TI Call TI

UC2843DTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM

UC2843J OBSOLETE CDIP JG 8 None Call TI Call TI

UC2843N ACTIVE PDIP P 8 50 Pb-Free

CU SNPB Level-NC-NC-NC

(RoHS) UC2844D ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM

UC2844D8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM

UC2844D8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM

UC2844DTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM

UC2844N ACTIVE PDIP P 8 50 Pb-Free

CU SNPB Level-NC-NC-NC

(RoHS) UC2845D ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM

UC2845D8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM

UC2845D8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM

UC2845DTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM

UC2845J OBSOLETE CDIP JG 8 None Call TI Call TI

UC2845N ACTIVE PDIP P 8 50 Pb-Free

CU SNPB Level-NC-NC-NC

(RoHS) UC3842D ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM

UC3842D8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM

UC3842D8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM

UC3842DTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM

UC3842J ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC3842N ACTIVE PDIP P 8 50 Pb-Free

CU SNPB Level-NC-NC-NC

(RoHS) UC3842P OBSOLETE PDIP P 8 None Call TI Call TI UC3843D ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM

UC3843D8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM

UC3843D8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM

UC3843DTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM

UC3843J ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

(3)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

UC3843N ACTIVE PDIP P 8 50 Pb-Free

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

CU SNPB Level-NC-NC-NC

4-Mar-2005

(3)

(RoHS) UC3843P OBSOLETE PDIP P 8 None Call TI Call TI

UC3843QTR OBSOLETE PLCC FN 20 None Call TI Call TI

UC3844D ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM

UC3844D8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM

UC3844D8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM

UC3844DTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM

UC3844J ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC3844N ACTIVE PDIP P 8 50 Pb-Free

CU SNPB Level-NC-NC-NC

(RoHS) UC3844P OBSOLETE PDIP P 8 None Call TI Call TI UC3845D ACTIVE SOIC D 14 50 None CU NIPDAU Level-1-220C-UNLIM

UC3845D8 ACTIVE SOIC D 8 75 None CU NIPDAU Level-1-220C-UNLIM

UC3845D8TR ACTIVE SOIC D 8 2500 None CU NIPDAU Level-1-220C-UNLIM

UC3845DTR ACTIVE SOIC D 14 2500 None CU NIPDAU Level-1-220C-UNLIM

UC3845J ACTIVE CDIP JG 8 1 None A42 SNPB Level-NC-NC-NC

UC3845N ACTIVE PDIP P 8 50 Pb-Free

CU SNPB Level-NC-NC-NC

(RoHS) UC3845P OBSOLETE PDIP P 8 None Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.063 (1,60)

0.015 (0,38)

0.100 (2,54)

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.023 (0,58)

0.015 (0,38)

0.280 (7,11)

0.245 (6,22)

0.310 (7,87)

0.290 (7,37)

0.200 (5,08) MAX Seating Plane

0.130 (3,30) MIN

0°–15°

0.014 (0,36)

0.008 (0,20)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 1835 GDIP1-T8

4040107/C 08/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A SQ

B SQ

12826 27

1314151618 17

0.020 (0,51)

0.010 (0,25)

MIN

0.342 (8,69)

0.442

0.640

0.739

0.938

1.141

0.358 (9,09)

0.458

(11,63)

0.660

(16,76)

0.761

(19,32)(18,78)

0.962

(24,43)

1.165

(29,59)

NO. OF

TERMINALS

432

0.020 (0,51)

0.010 (0,25)

(11,23)

(16,26)

(23,83)

(28,99)

MINMAX

0.307 (7,80)

0.406

(10,31)

0.495

(12,58)

0.495

(12,58)

0.850 (21,6)

1.047 (26,6)

0.080 (2,03)

0.064 (1,63)

MAX

0.358 (9,09)

0.458

(11,63)

0.560

(14,22)

0.560

(14,22)

0.858 (21,8)

1.063 (27,0)

0.055 (1,40)

0.045 (1,14)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

4040140/D 10/96

MECHANICAL DATA

MPDI001A – JANUARY 1995 – REVISED JUNE 1999

P (R-PDIP-T8) PLASTIC DUAL-IN-LINE

0.400 (10,60)

0.355 (9,02)

0.260 (6,60)

0.240 (6,10)

0.021 (0,53)

0.015 (0,38)

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001

0.070 (1,78) MAX

0.020 (0,51) MIN

0.200 (5,08) MAX

0.125 (3,18) MIN

0.100 (2,54)

0.010 (0,25)

Seating Plane

0.325 (8,26)

0.300 (7,62)

0.015 (0,38) Gage Plane

0.010 (0,25) NOM

0.430 (10,92) MAX

4040082/D 05/98

For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MPLC004A – OCT OBER 1994

FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

E1E

NO. OF

PINS

D/E

0.032 (0,81)

0.026 (0,66)

0.050 (1,27)

0.008 (0,20) NOM

D1/E1

MINMAXMIN

MAX

D2/E2

MIN

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

D2/E2

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

MAX

20 28 44 52 68 84

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Falls within JEDEC MS-018

0.385 (9,78)

0.485 (12,32)

0.685 (17,40)

0.785 (19,94)

0.985 (25,02)

1.185 (30,10)

0.395 (10,03)

0.495 (12,57)

0.695 (17,65)

0.795 (20,19)

0.995 (25,27)

1.195 (30,35)

0.350 (8,89)

0.450 (11,43)

0.650 (16,51)

0.750 (19,05)

0.950 (24,13)

1.150 (29,21)

0.356 (9,04)

0.456 (11,58)

0.656 (16,66)

0.756 (19,20)

0.958 (24,33)

1.158 (29,41)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.441 (11,20)

0.541 (13,74)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.469 (11,91)

0.569 (14,45)

4040005/B 03/95

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