TEXAS INSTRUMENTS UC1842, UC1843, UC1844, UC1845 Technical data
Current Mode PWM Controller
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
FEATURES
Optimized For Off-line And DC
•
To DC Converters
Low Start Up Current (<1mA)
•
Automatic Feed Forward
•
Compensation
Pulse-by-pulse Current Limiting
•
Enhanced Load Response
•
Characteristics
Under-voltage Lockout With
•
Hysteresis
Double Pulse Suppression
•
High Current Totem Pole
•
Output
• Internally Trimmed Bandgap
Reference
• 500khz Operation
• Low R
O Error Amp
DESCRIPTION
The UC1842/3/4/5 family of control ICs provides the necessary features to
implement off-line or DC to DC fixed frequency current mode control schemes
with a minimal external parts count. Internally implemented circuits include
under-voltage lockout featuring start up current less than 1mA, a precision
reference trimmed for accuracy at the error amp input, logic to insure latched
operation, a PWM comparator which also provides current limit control, and a
totem pole output stage designed to source or sink high peak current. The
output stage, suitable for driving N Channel MOSFETs, is low in the off state.
Differences between members of this family are the under-voltage lockout
thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have
UVLO thresholds of 16V (on) and 10V (off), ideally suited to off-line
applications. The corresponding thresholds for the UC1843 and UC1845 are
8.4V and 7.6V. The UC1842 and UC1843 can operate to duty cycles
approaching 100%. A range of zero to 50% is obtained by the UC1844 and
UC1845 by the addition of an internal toggle flip flop which blanks the output
off every other clock cycle.
BLOCK DIAGRAM
Note 1: A = DIL-8 Pin Number. B = SO-14 and CFP-14 Pin Number.
Note 2: Toggle flip flop used only in 1844 and 1845.
A/B
SLUS223A - APRIL1997 - REVISED MAY 2002
ABSOLUTE MAXIMUM RATINGS(Note 1)
Supply Voltage (Low Impedance Source)..............30V
Supply Voltage (I
Output Current...................................±1A
Output Energy (Capacitive Load) ....................5µJ
Analog Inputs (Pins 2, 3)...................-0.3V to +6.3V
Error Amp Output Sink Current ....................10mA
Power Dissipation at T
Power Dissipation at T
Storage Temperature Range..............-65°C to +150°C
Junction Temperature Range .............-55°C to +150°C
Lead Temperature (soldering, 10 seconds)...........300°C
Note 1: All voltages are with respect to Pin 5.
CC < 30mA) .................Self Limiting
A ≤ 25°C (DIL−8).................1W
A ≤ 25°C (SOIC-14) .........725mW
All currents are positive into the specified terminal.
Consult Packaging Section of Databook for thermal
limitations and considerations of packages.
CONNECTION DIAGRAMS
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
DIL-8, SOIC-8 (TOP VIEW)
N or J Package, D8 Package
SOIC-14, CFP-14. (TOP VIEW)
D or W Package
PLCC-20 (TOP VIEW)
Q Package
PACKAGE PIN FUNCTION
FUNCTION PIN
N/C
COMP
N/C 3
N/C 4
VFB 5
N/C 6
ISENSE 7
N/C 8
N/C 9
RT/CT 10
N/C 11
PWR GND 12
GROUND 13
N/C 14
OUTPUT 15
N/C 16
VC 17
VCC 18
N/C 19
VREF 20
1
2
DISSIPATION RATING TABLE
Package TA ≤ 25°C
Power Rating
W 700 mW 5.5 mW/°C 452 mW 370 mW 150 mW
Derating Factor
Above TA ≤ 25°C
TA ≤ 70°C
Power Rating
2
TA ≤ 85°C
Power Rating
TA ≤ 125°C
Power Rating
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS:
PARAMETER TEST CONDITIONS
Unless otherwise stated, these specifications apply for -55°C≤TA≤125°C for the
UC184X; -40°C≤T
(Note 5); R
T = 10k; CT = 3.3nF, TA=TJ.
85°C for the UC284X; 0°C≤T
A
≤
UC1842/3/4/5
70°C for the 384X; V
A
≤
UC3842/3/4/5 UNITS
UC2842/3/4/5
MIN TYP MAX MIN TYP MAX
Reference Section
Output Voltage T
Line Regulation 12≤V
Load Regulation 1≤I
J = 25°C, IO = 1mA 4.95 5.00 5.05 4.90 5.00 5.10 V
IN
25V 6 20 6 20 mV
≤
0
20mA 6 25 6 25 mV
≤
Temp. Stability (Note 2) (Note 7) 0.2 0.4 0.2 0.4 mV/°C
Total Output Variation Line, Load, Temp. (Note 2) 4.9 5.1 4.82 5.18 V
Output Noise Voltage 10Hz≤f≤10kHz, T
Long Term Stability T
A = 125°C, 1000Hrs. (Note 2) 5 25 5 25 mV
J = 25°C (Note2) 50 50
Output Short Circuit -30 -100 -180 -30 -100 -180 mA
Oscillator Section
Initial Accuracy T
Voltage Stability 12≤V
Temp. Stability T
Amplitude V
J = 25°C (Note 6) 47 52 57 47 52 57 kHz
CC
25V 0.2 1 0.2 1 %
≤
T
MIN
PIN 4 peak to peak (Note 2) 1.7 1.7 V
T
A
≤
MAX (Note 2) 5 5 %
≤
Error Amp Section
Input Voltage V
PIN 1 = 2.5V 2.45 2.50 2.55 2.42 2.50 2.58 V
Input Bias Current -0.3 -1 -0.3 -2
A
VOL 2
Unity Gain Bandwidth (Note 2) T
PSRR 12≤V
Output Sink Current V
Output Source Current V
V
OUT High VPIN 2 = 2.3V, RL = 15k to ground 5 6 5 6 V
V
OUT Low VPIN 2 = 2.7V, RL = 15k to Pin 8 0.7 1.1 0.7 1.1 V
VO
4V 65 90 65 90 dB
≤
≤
J = 25°C 0.7 1 0.7 1 MHz
CC
25V 60 70 60 70 dB
≤
PIN 2 = 2.7V, VPIN 1 = 1.1V 2 6 2 6 mA
PIN 2 = 2.3V, VPIN 1 = 5V -0.5 -0.8 -0.5 -0.8 mA
Current Sense Section
Gain (Notes 3 and 4) 2.85 3 3.15 2.85 3 3.15 V/V
Maximum Input Signal V
PSRR 12≤V
PIN 1 = 5V (Note 3) 0.9 1 1.1 0.9 1 1.1 V
25V (Note 3) (Note 2) 70 70 dB
≤
CC
Input Bias Current -2 -10 -2 -10
Delay to Output V
PIN 3 = 0 to 2V (Note 2) 150 300 150 300 ns
CC = 15V
V
µ
A
µ
A
µ
Note 2: These parameters, although guaranteed, are not 100% tested in production.
Note 3: Parameter measured at trip point of latch with V
PIN 2 =0.
Note 4: Gain defined as
VPIN
∆
A
∆
Note 5: Adjust V
1
VPIN V=≤≤
VPIN
CC above the start threshold before setting at 15V.
0308,.
3
Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
Note 7: Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
V max VREF min
Temp Stability
V
REF (max) and VREF (min) are the maximum and minimum reference voltages measured over the appropriate
REF
=
TJ max TJ min
−
() ()
−
() ()
temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
3
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
ELECTRICAL CHARACTERISTICS:
PARAMETER TEST CONDITION
Unless otherwise stated, these specifications apply for −55°C≤TA
A
UC184X; −40°C≤T
15V (Note 5); R
T = 10k; CT = 3.3nF, TA=TJ.
85°C for the UC284X; 0°C≤TA≤70°C for the 384X; VCC =
≤
UC1842/3/4/5
UC3842/3/4/5 UNITS
UC2842/3/4/5
125°C for the
≤
MIN TYP MAX MIN TYP MAX
Output Section
Output Low Level I
Output High Level I
Rise Time T
Fall Time T
SINK = 20mA 0.1 0.4 0.1 0.4 V
I
SINK = 200mA 1.5 2.2 1.5 2.2 V
SOURCE = 20mA 13 13.5 13 13.5 V
I
SOURCE = 200mA 12 13.5 12 13.5 V
J = 25°C, CL = 1nF (Note 2) 50 150 50 150 ns
J = 25°C, CL = 1nF (Note 2) 50 150 50 150 ns
Under-voltage Lockout Section
Start Threshold X842/4 15 16 17 14.5 16 17.5 V
X843/5 7.8 8.4 9.0 7.8 8.4 9.0 V
Min. Operating Voltage
After Turn On
X842/4 9 10 11 8.5 10 11.5 V
X843/5 7.0 7.6 8.2 7.0 7.6 8.2 V
PWM Section
Maximum Duty Cycle X842/3 95 97 100 95 97 100 %
X844/5 46 48 50 47 48 50 %
Minimum Duty Cycle 0 0 %
Total Standby Current
Start-Up Current 0.5 1 0.5 1 mA
Operating Supply Current V
V
CC Zener Voltage ICC = 25mA 30 34 30 34 V
PIN 2 =VPIN 3 =0V 1117 1117mA
Note 2: These parameters, although guaranteed, are not 100% tested in production.
Note 3: Parameter measured at trip point of latch with V
PIN 2 =0
.
Note 4: Gain defined as:
Note 5: Adjust V
CC above the start threshold before setting at 15V.
∆
A
∆
VPIN
1
VPIN V=≤≤
0308;.
3
.
VPIN
Note 6: Output frequency equals oscillator frequency for the UC1842 and UC1843.
Output frequency is one half oscillator frequency for the UC1844 and UC1845.
ERROR AMP CONFIGURATION
Error Amp can Source or Sink up to 0.5mA
4
UNDER-VOLTAGE LOCKOUT
UC1842/3/4/5
UC2842/3/4/5
UC3842/3/4/5
During under-voltage lock-out, the output driver is
biased to sink minor amounts of current. Pin 6 should
be shunted to ground with a bleeder resistor to prevent
CURRENT SENSE CIRCUIT
Peak Current (IS) is Determined By The Formula
SMAX ′
I
A small RC filter may be required to suppress switch transients
OSCILLATOR SECTION
activating the power switch with extraneous leakage
currents.
1.0V
RS
.
5
OUTPUT SATURATION CHARACTERISTICS
OPEN-LOOP LABORATORY FIXTURE
UC1842/3/4/5
UC2842/3/4/5
ERROR AMPLIFIER OPEN-LOOP
FREQUENCY RESPONSE
High peak currents associated with capacitive loads ne
cessitate careful grounding techniques. Timing and by
pass capacitors should be connected close to pin 5 in a
SHUT DOWN TECHNIQUES
Shutdown of the UC1842 can be accomplished by two
methods; either raise pin 3 above 1V or pull pin 1 below
a voltage two diode drops above ground. Either method
causes the output of the PWM comparator to be high
(refer to block diagram). The PWM latch is reset domi
nant so that the output will remain low until the next
-
single point ground. The transistor and 5k potentiometer
-
are used to sample the oscillator waveform and apply
an adjustable ramp to pin 3.
clock cycle after the shutdown condition at pin 1 and/or
3 is removed. In one example, an externally latched
shutdown may be accomplished by adding an SCR
which will be reset by cycling V
-
UVLO threshold. At this point the reference turns off, al
lowing the SCR to reset.
CC below the lower
-
6
Loading...