The UC1823 family of PWM control ICs is optimized for high fre
quency switched mode power supply applications. Particular care
was given to minimizing propagation delays through the compara
tors and logic circuitry while maximizing bandwidth and slew rate
of the error amplifier. This controller is designed for use in either
current-mode or voltage-mode systems with the capability for in
put voltage feed-forward.
Protection circuitry includes a current limit comparator, a TTL
compatible shutdown port, and a soft start pin which will double as
a maximum duty cycle clamp. The logic is fully latched to provide
jitter free operation and prohibit multiple pulses at the output. An
under-voltage lockout section with 800mV of hysteresis assures
low start up current. During under-voltage lockout, the output is high
impedance. The current limit reference (pin 11) is a DC input voltage
to the current limit comparator. Consult specifications for det ails.
These devices feature a totem pole output designed to source
•Low Start Up Current (1.1mA)
•Trimmed Bandgap Reference (5.1V±1%)
and sink high peak currents from capacitive loads, such as the
gate of a power MOSFET. The on state is defined as a high level.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pins 15, 13)........................30V
Analog Inputs (Pins 1, 2, 7, 8, 9, 11)...........–0.3V to +6V
Clock Output Current (Pin 4) ......................–5mA
Error Amplifier Output Current (Pin 3) ................5mA
Soft Start Sink Current (Pin 8) .....................20mA
Oscillator Charging Current (Pin 5) .................–5mA
Power Dissipation at T
Storage Temperature Range .............–65°C to +150°C
Lead Temperature (Soldering, 10 seconds) ..........300°C
Note: All voltages are with respect to ground, Pin 10.
Currents are positive into the specified terminal.
Consult Packaging Section of Databook for thermal
limitations
=60°C......................1W
A
-
-
-
BLOCK DIAGRAM
SLUS219A - MARCH 1997 - REVISED FEBRUARY 2006
CONNECTION DIAGRAMS
UC1823
UC2823
UC3823
DIL-16, SOIC-16 (TOP VIEW)
J or N, DW Package
PLCC-20, LCC-20 (TOP VIEW)
Q, L Package
PACKAGE PIN FUNCTION
FUNCTIONPIN
N/C1
Inv.2
N.I.3
E/A Out4
Clock5
N/C6
R
T7
C
T8
Ramp9
Soft start10
N/C11
I
LIM/S.D.12
Ground13
I
LIM REF14
PWR Gnd15
N/C16
V
C17
OUT18
V
CC19
V
REF 5.1V20
THERMAL PACKAGING INFORMATION
PACKAGEq
JA
J-1680 - 12028 (Note2)
N-1690 (Note1)45
DW-1645 - 90 (Note1)25
PLCC-20 Q Package43 - 75 (Note1)34
LCC-20 LPackage70 - 8020 (Note2)
Note 1. Specified qJA(junction to ambient) is for devices mounted to 5-in-2 FR4 PC board with one ounce copper where noted.
When resistance range is given, lower values are for 5-in-2 aluminum PC board. Test PWB was 0.062 in thick and typically used
0.635 mm trace widths for power pkgs and 1.3 mm trace widths for non-power pkgs with a 100 x 100 mil probe land area at the
end of each trace.
Note 2. q
data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states that “The baseline values shown are
JC
worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square
mils. For device die sizes greater than14400 square mils use the following values; dual-in-line, 11°C/W; flat pack, 10°C/W; pin grid
array,10°C/W”
q
JC
2
UC1823
UC2823
UC3823
ELECTRICAL CHARACTERISTICS:
PARAMETERTEST CONDITIONS
Unless otherwise noted, these specifications apply for RT = 3.65k, CT = 1nF,
V
CC = 15V, 0°C < TA < +70°C for the UC3823, -25°C < TA < +85°C for the
UC2823, and -55°C < T
A < +125°C for the UC1823, TA =TJ.
UC1823
UC3823UNITS
UC2823
MINTYPMAXMINTYPMAX
Reference Section
Output VoltageT
Line Regulation10 < V
Load Regulation1 < I
Temperature Stability*T
J = 25°C, lO = 1mA5.055.105.155.005.105.20V
CC < 30V220220mV
O < 10mA520520mV
MIN <TA <TMAX0.20.40.20.4mV/°C
Total Output Variation*Line, Load, Temp.5.005.204.955.25
Output Noise Voltage*10Hz<f<10kHz5050
Long Term Stability*T
Short Circuit CurrentV
Initial Accuracy*T
Voltage Stability*10 < V
Temperature Stability*T
J=25°C360400440360400440kHz
CC < 30V0.220.22%
MIN <TA <TMAX55%
Total Variation*Line, Temp.340460340460kHz
Clock Out High3.94.53.94.5V
Clock Out Low2.32.92.32.9V
Ramp Peak*2.62.83.02.62.83.0V
Ramp Valley*0.71.01.250.71.01.25V
Error Amplifier Section
Input Offset Voltage1015mV
Input Bias Current0.630.63
Input Offset Current0.110.11
Open Loop Gain1 < V
CMRR1.5 < V
PSRR10 < V
Output Sink CurrentV
Output Source CurrentV
Output High VoltageI
Output Low VoltageI
O <4V60956095dB
CM < 5.5V75957595dB
CC < 30V8511085110dB
PIN 3 =1V12.512.5mA
PIN 3 = 4V-0.5-1.3-0.5-1.3mA
High speed circuits demand careful attention to layout
and component placement. To assure proper perfor
mance of the UC1823, follow these rules. 1) Use a
ground plane. 2) Damp or clamp parasitic inductive kick
energy from the gate of driven MOSFET. Don’t allow the
output pins to ring below ground. A series gate resistor or
a shunt 1 Amp Schottky diode at the output pin will serve
ERROR AMPLIFIER CIRCUIT
Simplified Schematic
UC1823
UC2823
UC3823
this purpose. 3) Bypass VCC,VC, and VREF. Use 0.1µF
monolithic ceramic capacitors with low equivalent series
inductance. Allow less than 1 cm of total lead length for
each capacitor between the bypassed pin and the ground
plane. 4) Treat the timing capacitor, C
pacitor.
T, like a bypass ca
-
Open Loop Frequency Response
PWM APPLICATIONS
Conventional (Voltage Mode)
Unity Gain Slew Rate
Current-Mode
* A small filter may be required to suppress switch noise
5
OSCILLATOR CIRCUIT
UC1823
UC2823
UC3823
SYNCHRONIZED OPERATION
Two Units in Close Proximity
Generalized Synchronization
6
CONSTANT VOLT-SECOND CLAMP CIRCUIT
The circuit shown here will achieve a constant
volt-second product clamp over varying input voltages.
The ramp generator components, R
chosen so that the ramp at Pin 9 crosses the 1V
threshold at the same time the desired maximum
volt-second product is reached. The delay through the
inverter must be such that the ramp capacitor can be
completely discharged during the minimum deadtime.
T and CR are
OUTPUT SECTION
UC1823
UC2823
UC3823
FEED FORWARD TECHNIQUE FOR OFF-LINE VOLTAGE MODE APPLICATION
7
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable DeviceStatus
5962-89905012AACTIVELCCCFK201TBDPOST-PLATE N / A for Pkg Type
5962-8990501EAACTIVECDIPJ161TBDA42 SNPBN / A for Pkg Type
UC1823JACTIVECDIPJ161TBDA42 SNPBN / A for Pkg Type
UC1823J883BACTIVECDIPJ161TBDA42 SNPBN / A for Pkg Type
UC1823LACTIVELCCCFK201TBDPOST-PLATE N / A for Pkg Type
UC1823L883BACTIVELCCCFK201TBDPOST-PLATE N / A for Pkg Type
UC2823DWACTIVESOICDW1640Green (RoHS &
UC2823DWG4ACTIVESOICDW1640Green (RoHS &
UC2823DWTRACTIVESOICDW162000 Green (RoHS &
UC2823DWTRG4ACTIVESOICDW162000 Green (RoHS &
UC2823NACTIVEPDIPN1625Green (RoHS &
UC2823NG4ACTIVEPDIPN1625Green (RoHS &
UC2823QACTIVEPLCCFN2046Green (RoHS &
UC2823QG3ACTIVEPLCCFN2046Green (RoHS &
UC2823QTRACTIVEPLCCFN201000 Green (RoHS &
UC2823QTRG3ACTIVEPLCCFN201000 Green (RoHS &
UC3823DWACTIVESOICDW1640Green (RoHS &
UC3823DWG4ACTIVESOICDW1640Green (RoHS &
UC3823DWTRACTIVESOICDW162000 Green (RoHS &
UC3823DWTRG4ACTIVESOICDW162000 Green (RoHS &
UC3823NACTIVEPDIPN1625Green (RoHS &
UC3823NG4ACTIVEPDIPN1625Green (RoHS &
UC3823QACTIVEPLCCFN2046Green (RoHS &
UC3823QG3ACTIVEPLCCFN2046Green (RoHS &
UC3823QTRACTIVEPLCCFN201000 Green (RoHS &
UC3823QTRG3ACTIVEPLCCFN201000 Green (RoHS &
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU SNLevel-2-260C-1 YEAR
CU SNLevel-2-260C-1 YEAR
CU SNLevel-2-260C-1 YEAR
CU SNLevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAULevel-2-260C-1 YEAR
CU NIPDAUN / A for Pkg Type
CU NIPDAUN / A for Pkg Type
CU SNLevel-2-260C-1 YEAR
CU SNLevel-2-260C-1 YEAR
CU SNLevel-2-260C-1 YEAR
CU SNLevel-2-260C-1 YEAR
20-Dec-2007
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
20-Dec-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.