High Speed PWM Controller
application
INFO
available
UC1823
UC2823
UC3823
FEATURES
Compatible with Voltage or Current-Mode
•
Topologies
Practical Operation @ Switching Frequencies
•
to 1.0MHz
50ns Propagation Delay to Output
•
High Current Totem Pole Output (1.5A peak)
•
Wide Bandwidth Error Amplifier
•
Fully Latched Logic with Double Pulse
•
Suppression
Pulse-by-Pulse Current Limiting
•
Soft Start/Max. Duty Cycle Control
•
Under-Voltage Lockout with Hysteresis
•
DESCRIPTION
The UC1823 family of PWM control ICs is optimized for high fre
quency switched mode power supply applications. Particular care
was given to minimizing propagation delays through the compara
tors and logic circuitry while maximizing bandwidth and slew rate
of the error amplifier. This controller is designed for use in either
current-mode or voltage-mode systems with the capability for in
put voltage feed-forward.
Protection circuitry includes a current limit comparator, a TTL
compatible shutdown port, and a soft start pin which will double as
a maximum duty cycle clamp. The logic is fully latched to provide
jitter free operation and prohibit multiple pulses at the output. An
under-voltage lockout section with 800mV of hysteresis assures
low start up current. During under-voltage lockout, the output is high
impedance. The current limit reference (pin 11) is a DC input voltage
to the current limit comparator. Consult specifications for det ails.
These devices feature a totem pole output designed to source
• Low Start Up Current (1.1mA)
• Trimmed Bandgap Reference (5.1V±1%)
and sink high peak currents from capacitive loads, such as the
gate of a power MOSFET. The on state is defined as a high level.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Pins 15, 13)........................30V
Output Current, Source or Sink (Pin14)
DC..........................................0.5A
Pulse (0.5µs)..................................2.0A
Analog Inputs (Pins 1, 2, 7, 8, 9, 11)...........–0.3V to +6V
Clock Output Current (Pin 4) ......................–5mA
Error Amplifier Output Current (Pin 3) ................5mA
Soft Start Sink Current (Pin 8) .....................20mA
Oscillator Charging Current (Pin 5) .................–5mA
Power Dissipation at T
Storage Temperature Range .............–65°C to +150°C
Lead Temperature (Soldering, 10 seconds) ..........300°C
Note: All voltages are with respect to ground, Pin 10.
Currents are positive into the specified terminal.
Consult Packaging Section of Databook for thermal
limitations
=60°C......................1W
A
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-
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BLOCK DIAGRAM
SLUS219A - MARCH 1997 - REVISED FEBRUARY 2006
CONNECTION DIAGRAMS
UC1823
UC2823
UC3823
DIL-16, SOIC-16 (TOP VIEW)
J or N, DW Package
PLCC-20, LCC-20 (TOP VIEW)
Q, L Package
PACKAGE PIN FUNCTION
FUNCTION PIN
N/C 1
Inv. 2
N.I. 3
E/A Out 4
Clock 5
N/C 6
R
T 7
C
T 8
Ramp 9
Soft start 10
N/C 11
I
LIM/S.D. 12
Ground 13
I
LIM REF 14
PWR Gnd 15
N/C 16
V
C 17
OUT 18
V
CC 19
V
REF 5.1V 20
THERMAL PACKAGING INFORMATION
PACKAGE q
JA
J-16 80 - 120 28 (Note2)
N-16 90 (Note1) 45
DW-16 45 - 90 (Note1) 25
PLCC-20 Q Package 43 - 75 (Note1) 34
LCC-20 LPackage 70 - 80 20 (Note2)
Note 1. Specified qJA(junction to ambient) is for devices mounted to 5-in-2 FR4 PC board with one ounce copper where noted.
When resistance range is given, lower values are for 5-in-2 aluminum PC board. Test PWB was 0.062 in thick and typically used
0.635 mm trace widths for power pkgs and 1.3 mm trace widths for non-power pkgs with a 100 x 100 mil probe land area at the
end of each trace.
Note 2. q
data values stated were derived from MIL-STD-1835B. MIL-STD-1835B states that “The baseline values shown are
JC
worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square
mils. For device die sizes greater than14400 square mils use the following values; dual-in-line, 11°C/W; flat pack, 10°C/W; pin grid
array,10°C/W”
q
JC
2
UC1823
UC2823
UC3823
ELECTRICAL CHARACTERISTICS:
PARAMETER TEST CONDITIONS
Unless otherwise noted, these specifications apply for RT = 3.65k, CT = 1nF,
V
CC = 15V, 0°C < TA < +70°C for the UC3823, -25°C < TA < +85°C for the
UC2823, and -55°C < T
A < +125°C for the UC1823, TA =TJ.
UC1823
UC3823 UNITS
UC2823
MIN TYP MAX MIN TYP MAX
Reference Section
Output Voltage T
Line Regulation 10 < V
Load Regulation 1 < I
Temperature Stability* T
J = 25°C, lO = 1mA 5.05 5.10 5.15 5.00 5.10 5.20 V
CC < 30V 2 20 2 20 mV
O < 10mA 5 20 5 20 mV
MIN <TA <TMAX 0.2 0.4 0.2 0.4 mV/°C
Total Output Variation* Line, Load, Temp. 5.00 5.20 4.95 5.25
Output Noise Voltage* 10Hz<f<10kHz 50 50
Long Term Stability* T
Short Circuit Current V
J = 125°C, 1000 hrs. 5 25 5 25 mV
REF=0V -15 -50 -100 -15 -50 -100 mA
Oscillator Section
Initial Accuracy* T
Voltage Stability* 10 < V
Temperature Stability* T
J=25°C 360 400 440 360 400 440 kHz
CC < 30V 0.2 2 0.2 2 %
MIN <TA <TMAX 55%
Total Variation* Line, Temp. 340 460 340 460 kHz
Clock Out High 3.9 4.5 3.9 4.5 V
Clock Out Low 2.3 2.9 2.3 2.9 V
Ramp Peak* 2.6 2.8 3.0 2.6 2.8 3.0 V
Ramp Valley* 0.7 1.0 1.25 0.7 1.0 1.25 V
Error Amplifier Section
Input Offset Voltage 10 15 mV
Input Bias Current 0.6 3 0.6 3
Input Offset Current 0.1 1 0.1 1
Open Loop Gain 1 < V
CMRR 1.5 < V
PSRR 10 < V
Output Sink Current V
Output Source Current V
Output High Voltage I
Output Low Voltage I
O <4V 6095 6095 dB
CM < 5.5V 75 95 75 95 dB
CC < 30V 85 110 85 110 dB
PIN 3 =1V 1 2.5 1 2.5 mA
PIN 3 = 4V -0.5 -1.3 -0.5 -1.3 mA
PIN 3 = −0.5mA 4.0 4.7 5.0 4.0 4.7 5.0 V
PIN 3 = 1mA 0 0.5 1.0 0 0.5 1.0 V
Unity Gain Bandwidth* 3 5.5 3 5.5 MHz
Slew Rate* 6 12 6 12 V/µS
Ramp Valley to Peak* 1.6 1.8 2.0 1.6 1.8 2.0 V
* These parameters are guaranteed by design but not 100% tested in production.
V
µ
A
µ
A
µ
3
UC1823
UC2823
UC3823
ELECTRICAL CHARACTERISTICS: Unless otherwise noted, these specifications apply for RT = 3.65k, CT = 1nF, VCC
= 15V, 0°C < TA < +70°C for the UC3823, -25°C < TA < +85°C for the
UC2823, and -55°C < T
A < +125°C for the UC1823, TA =TJ.
PARAMETER TEST CONDITIONS
UC1823
UC2823
UC3823 UNITS
MIN TYP MAX MIN TYP MAX
PWM Comparator Section
Pin 7 Bias Current V
PIN 7 =0V -1-5 -1-5
Duty Cycle Range 0 80 0 85 %
Pin 3 Zero D.C. Threshold V
PIN 7 = 0V 1.1 1.25 1.1 1.25 V
Delay to Output* 50 80 50 80 ns
Soft-Start Section
Charge Current V
Discharge Current V
= 0.5V 3 9 20 3 9 20
PIN 8
PIN 8 =1V 1 1 mA
Current Limit/Shutdown Section
Pin 9 Bias Current 0 < V
Current Limit Offset V
Current Limit Common Mode
Range (V
PIN 11)
PIN 9 <4V
PIN 11 = 1.1V 15 15 mV
10
±
10
±
1.0 1.25 1.0 1.25 V
Shutdown Threshold 1.25 1.40 1.55 1.25 1.40 1.55 V
Delay to Output* 50 80 50 80 ns
Output Section
Output Low Level I
Output High Level I
Collector Leakage V
Rise/Fall Time* C
OUT = 20mA 0.25 0.40 0.25 0.40 V
I
OUT = 200mA 1.2 2.2 1.2 2.2 V
OUT = −20mA 13.0 13.5 13.0 13.5 V
I
OUT = −200mA 12.0 13.0 12.0 13.0 V
C = 30V 100 500 100 500
L = 1nF 30 60 30 60 ns
Under-Voltage Lockout Section
Start Threshold 8.8 9.2 9.6 8.8 9.2 9.6 V
UVLO Hysteresis 0.4 0.8 1.2 0.4 0.8 1.2 V
Supply Current
Start Up Current V
CC VPIN 1,VPIN 7, VPIN 9 =0V, VPIN 2 =1V 2233 2233mA
I
CC = 8V 1.1 2.5 1.1 2.5 mA
* These parameters are ensured by design but not 100% tested in production.
A
µ
A
µ
A
µ
A
µ
4
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