TEXAS INSTRUMENTS TVP70025I Technical data

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TVP70025I

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...................................................................................................................................................................................................... SLES232 – JUNE 2008

TRIPLE 10-BIT, 90-MSPS,

VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL

1

FEATURES

23

• Analog Channels • Horizontal Phase-Locked Loop (PLL)

– – 6-dB to 6-dB Analog Gain – Fully Integrated Horizontal PLL for Pixel – Analog Input Multiplexers (MUXs) – Automatic Video Clamp – Three Digitizing Channels, Each With

Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC) – 5-Bit Programmable Subpixel Accurate

– Clamping: Selectable Clamping Between

Bottom Level and Mid Level • Output Formatter

– Offset: 1024-Step Programmable RGB or – Supports 20-bit 4:2:2 Outputs With

YPbPr Offset Control Embedded Syncs – Gain: 8-Bit Programmable Gain Control – Support for RGB/YCbCr 4:4:4 and YCbCr – ADC: 10-Bit 90-MSPS A/D Converter – Automatic Level Control (ALC) Circuit – Composite Sync: Integrated Sync-on-Green

Extraction From Green/Luminance Channel – Support for DC- and AC-Coupled Input

Signals – Programmable Video Bandwidth Control – Supports Component Video Standards 480i,

576i, 480p, 576p, 720p, and 1080i – Supports PC Graphics Inputs up to 90

MSPS – Programmable RGB-to-YCbCr Color Space

Conversion

Clock Generation

– 9-MHz to 90-MHz Pixel Clock Generation

From HSYNC Input

– Adjustable Horizontal PLL Loop Bandwidth

for Minimum Jitter

Positioning of Sampling Phase

4:2:2 Output Modes to Reduce Board Traces

– Dedicated DATACLK Output With

Programmable Output Polarity for Easy Latching of Output Data

• System

– Industry-Standard Normal/Fast I2C Interface

With Register Readback Capability – Space-Saving 100-Pin TQFP Package – Thermally-Enhanced PowerPAD™ Package

for Better Heat Dissipation – Industrial Temperature Range – 40 ° C to

85 ° C

APPLICATIONS

• LCD TV/Monitors/Projectors

• DLP TV/Projectors

• PDP TV/Monitors

• LCOS TV/Monitors

• PCTV Set-Top Boxes

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments. 3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

• Digital Image Processing

• Video Capture/Video Editing

• Scan Rate/Image Resolution Converters

• Video Conferencing

• Video/Graphics Digitizing Equipment

TVP70025I

SLES232 – JUNE 2008 ......................................................................................................................................................................................................

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DESCRIPTION/ORDERING INFORMATION

The TVP70025I is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 90 MHz. Therefore, it can be used for PC graphics digitizing up to WXGA (1440 × 900) resolution at a 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080i.

The TVP70025I is powered from 3.3-V and 1.8-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP70025I includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP70025I can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.

The TVP70025I also contains a complete horizontal phase-locked loop (PLL) block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 9 MHz to 90 MHz.

All programming of the device is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP70025I is available in a space-saving 100-pin TQFP PowerPAD package.

ORDERING INFORMATION

T

A

– 40 ° C to 85 ° C

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com .

(2) Package drawings, thermal data, and symbolization are available atwww.ti.com/packaging .

100-PIN PLASTIC FLATPACK PowerPAD

PACKAGED DEVICES

TVP70025IPZP Tray

TVP70025IPZPR Reel

(1)

(2)

PACKAGE OPTION

Product Folder Link(s): TVP70025I

Output

Formatter

R[9:0]

G[9:0]

Host

Interface

Timing Processor

and

Clock Generation

RIN_1

SCL

SDA

I2CA

GIN_1

BIN_1

Clamp

Gain and

Offset

10-bit

ADC

HSYNC_A

VSYN C_A

COAST

CLAMP

FILT1

SOGIN_1

RESETB

PWDN

B[9:0]

SOGOUT

HSOUT

VSOUT

DATACLK

RIN_2

GIN_2

BIN_2

EXT_CLK

SOGIN_2

HSYNC_B

VSYN C_B

FILT2

RIN_3

GIN_3 GIN_4

SOGIN_3

BIN_3

FIDOUT

Color Space

Conversion

and

4:4:4 to 4:2:2

Conversion

Gain and

Offset

Gain and

Offset

10-bit

ADC

10-bit

ADC

TVP70025I

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...................................................................................................................................................................................................... SLES232 – JUNE 2008

FUNCTIONAL BLOCK DIAGRAM

Product Folder Link(s): TVP70025I

100-Pin TQFP Package

(TopView)

1 00

GIN_299SOGIN_2

98

GIN_397SOGIN_3

96

GIN_495A33GND

9

4

A33VDD

93

A33VDD

92

A33GND

91

NSUB90PLL_AGND89PLL_F88FIL

T2

87

FIL

T1

86

PLL_AGND85PLL_AVDD84PLL_AVDD83PLL_AGND82HSYNC_B

81

HSYNC_A

80

EXT_CLK

79

VSYNC_B

78

VSYNC_A

77

COAST76CLAMP

26

IOVDD

27

IOGND

28

ATACLK

29

B_9

30

B_8

31

B_7

32

B_6

33

B_5

34

B_4

35

B_3

36

B_2

37

B_1

38

B_0

39

DVDD

40

GND

41

IOVDD

42

IOGND

43

G_9

44

G_8

45

G_7

46

G_6

47

G_5

48

G_4

49

G_3

50

G_2

75

SDA

74

SCL

73

I2CA

72

TMS

71

RESETB

70

PWDN

69

DVDD

68

GND

67

IOGND

66

IOVDD

65

R_0

64

R_1

63

R_2

62

R_3

61

R_4

60

IOGND

59

R_5

58

R_6

57

R_7

56

R_8

55

R_9

54

IOGND

53

IOVDD

52

G_0

51

G_1

1

SOGIN_1

2

GIN_1

3

AGND

4

AVDD

5

A DGN

6

AVDD

7

AVDD

8

AGND

9

RI _N 3

10

RIN_2

11

RIN_1

12

A33GND

13

A33VDD

14

A33VDD

15

A33GND

16

BIN_3

17

BIN_2

18

BIN_1

19

AV DD

20

AGND

21

NSUB

22

FIDOUT

23

VSOUT

24

HSOUT

25

SOGOUT

TVP70025I

SLES232 – JUNE 2008 ......................................................................................................................................................................................................

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TERMINAL ASSIGNMENTS

Product Folder Link(s): TVP70025I

TVP70025I

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...................................................................................................................................................................................................... SLES232 – JUNE 2008

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

Analog Video

RIN_1 11 I Analog video input for R/Pr 1 RIN_2 10 I Analog video input for R/Pr 2 RIN_3 9 I Analog video input for R/Pr 3 GIN_1 2 I Analog video input for G/Y 1 GIN_2 100 I Analog video input for G/Y 2 GIN_3 98 I Analog video input for G/Y 3 GIN_4 96 I Analog video input for G/Y 4 BIN_1 18 I Analog video input for B/Pb 1 BIN_2 17 I Analog video input for B/Pb 2 BIN_3 16 I Analog video input for B/Pb 3

Clock Signals

DATACLK 28 O Data clock output EXT_CLK 80 I External clock input. May be used as a timing reference for the mode detection block instead of

Digital Video

R[9:0] 55 – 59, 61 – 65 O Digital video output of R/Cr, R[9] is the most significant bit (MSB). G[9:0] 43-52 O Digital video output of G/Y, G[9] is the MSB. B[9:0] 29-38 O Digital video output of B/Cb, B[9] is the MSB.

Miscellaneous Signals

PWDN 70 I Power down input

RESETB 71 I Reset input, active low. Outputs are placed in a high-impedance mode during reset (see

TMS 72 I Test mode select input, active high. Used to enable scan test mode. For normal operation,

FILT1 87 O External filter connection for the horizontal PLL. A 0.1- µ F capacitor in series with a 1.5-k Ω

FILT2 88 O External filter connection for the horizontal PLL. A 4.7-nF capacitor should be connected from

PLL_F 89 I Horizontal PLL filter internal supply connection

Host Interface

I2CA 73 I I2C slave address input. Has internal pulldown resistor (see Table 6 ).

SCL 74 I I2C clock input SDA 75 I/O I2C data bus

I/O DESCRIPTION

The inputs must be ac coupled. The recommended coupling capacitor is 0.1 µ F. Unused analog inputs should be connected to ground using a 10-nF capacitor.

the internal clock reference. Also may be used as the ADC sample clock instead of the H-PLL generated clock.

For 4:2:2 mode, multiplexed CbCr data is output on B[9:0]. Unused outputs can be left unconnected.

0 = Normal mode 1 = Power down

Table 7 ).

connect to ground.

resistor should be connected from this pin to pin 89 (see Figure 4 ).

this pin to pin 89 (see Figure 4 ).

0 = Slave address = B8h 1 = Slave address = BAh

Product Folder Link(s): TVP70025I

TVP70025I

SLES232 – JUNE 2008 ......................................................................................................................................................................................................

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME NO.

Power Supplies

NSUB 21, 91 I Substrate ground. Connect to analog ground. A33VDD 13, 14, 93, 94 I Analog power. Connect to 3.3 V. A33GND 12, 15, 92, 95 I Analog 3.3-V return. Connect to ground. AGND 3, 5, 8, 20 I Analog 1.8-V return. Connect to ground. AVDD 4, 6, 7, 19 I Analog power. Connect to 1.8 V. PLL_AVDD 84, 85 I PLL analog power. Connect to 1.8 V. PLL_AGND 83, 86, 90 I PLL analog power return. Connect to ground. DGND 40, 68 I Digital return. Connect to ground. DVDD 39, 69 I Digital power. Connect to 1.8 V. IOGND 27, 42, 54, 60, I Digital power return. Connect to ground.

67

IOVDD 26, 41, 53, 66 I Digital power. Connect to 3.3 V or less for reduced noise.

Sync Signals

CLAMP 76 I External clamp input. Unused inputs can be connected to ground. COAST 77 I External PLL COAST signal input. Unused inputs can be connected to ground. VSYNC_A 78 I Vertical sync input A

VSYNC_B 79 I Vertical sync input B

HSYNC_A 81 I Horizontal sync input A HSYNC_B 82 I Horizontal sync input B

SOGIN_1 1 I Sync-on-green input 1 SOGIN_2 99 I Sync-on-green input 2 SOGIN_3 97 I Sync-on-green input 3

FIDOUT 22 O Field ID output. Using register 17h, this pin also may be programmed to be the internal sync

VSOUT 23 O Vertical sync output HSOUT 24 O Horizontal sync output SOGOUT 25 O Sync-on-green slicer output

I/O DESCRIPTION

Unused inputs can be connected to ground.

Unused inputs should be connected to ground using a 1-nF capacitor.

processing REFCLK output, coast output, clamp pulse output, or data enable.

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TVP70025I

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ABSOLUTE MAXIMUM RATINGS

...................................................................................................................................................................................................... SLES232 – JUNE 2008

(1)

over operating free-air temperature range (unless otherwise noted)

IOVDD to IOGND – 0.5 V to 4.5 V

Supply voltage range

DVDD to DGND – 0.5 V to 2.3 V PLL_AVDD to PLL_AGND and AVDD to AGND – 0.5 V to 2.3 V

A33VDD to A33GND – 0.5 V to 4.5 V Digital input voltage range VIto DGND – 0.5 V to 4.5 V Analog input voltage range AIto A33GND – 0.2 V to 2.3 V Digital output voltage range VOto DGND – 0.5 V to 4.5 V

T

A

T

stg

Operating free-air temperature range -40C to 85 ° C Storage temperature range – 65 ° C to 150 ° C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

IOVDD Digital I/O supply voltage 3 3.3 3.6 V DVDD Digital supply voltage 1.7 1.8 1.95 V PLL_AVDD Analog supply voltage for horizontal PLL 1.7 1.8 1.95 V AVDD Analog supply voltage 1.7 1.8 1.95 V A33VDD Analog supply voltage 3 3.3 3.6 V V

I(PP)

V

IH

V

IL

I

OH

I

OL

I

OH_DATACLK

I

OL_DATACLK

T

A

Analog input voltage (ac coupling necessary) 0.5 2 V Digital input voltage high 0.7 IOVDD V Digital input voltage low 0.3 IOVDD V High-level output current 2 mA Low-level output current – 2 mA DATACLK high-level output current 4 mA DATACLK low-level output current – 4 mA ADC conversion rate 9 90 MHz Operating free-air temperature – 40 85 ° C

Product Folder Link(s): TVP70025I

TVP70025I

SLES232 – JUNE 2008 ......................................................................................................................................................................................................

ELECTRICAL CHARACTERISTICS

IOVDD = 3.3 V, DVDD = 1.8 V, PLL_AVDD = 1.8 V, AVDD = 1.8 V, A33VDD = 3.3 V, TA= 25 ° C

PARAMETER TEST CONDITIONS TYP

Power Supply

I

A33VDD

I

IOVDD

I

AVDD

I

PLL_VDD

I

DVDD

P

TOT

I

A33VDD

I

IOVDD

I

AVDD

I

PLL_VDD

I

DVDD

P

TOT

P

DOWN

(1) SMPTE color bar RGB input pattern used. (2) Multi-burst input pattern used.

3.3-V supply current 480p (27 MSPS) 43 43 mA

3.3-V supply current 480p (27 MSPS) 11 14 mA

1.8-V supply current 480p (27 MSPS) 168 170 mA

1.8-V supply current 480p (27 MSPS) 11 11 mA

1.8-V supply current 480p (27 MSPS) 10 12 mA Total power dissipation, normal mode 480p (27 MSPS) 518 535 mW

3.3-V supply current WXGA (85.5MSPS) 70 70 mA

3.3-V supply current WXGA (85.5 MSPS) 35 60 mA

1.8-V supply current WXGA (85.5 MSPS) 195 200 mA

1.8-V supply current WXGA (85.5 MSPS) 20 20 mA

1.8-V supply current WXGA (85.5 MSPS) 30 40 mA Total power dissipation, normal mode WXGA (85.5 MSPS) 787 897 mW Total power dissipation, power-down mode 15 15 mW

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(1)

(2)

TYP

UNIT

Product Folder Link(s): TVP70025I

TVP70025I

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...................................................................................................................................................................................................... SLES232 – JUNE 2008

ELECTRICAL CHARACTERISTICS

IOVDD = 3.3 V, DVDD = 1.8 V, PLL_AVDD = 1.8 V, AVDD = 1.8 V, A33VDD = 3.3 V, TA= – 40 ° C to 85 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Analog Interface

Input voltage range By design 0.5 1 2 V

Z

I

Digital Logic Interface

C

I

Z

I

V

OH

V

OL

V

OH_SCLK

V

OL_SCLK

V

IH

V

IL

A/D CONVERTERS

DNL DC differential nonlinearity 10 bit, 90 MHz – 1 ± 0.5 +1 LSB INL DC integral nonlinearity 10 bit, 90 MHz – 4 ± 1 +4 LSB

SNR Signal-to-noise ratio 10 MHz, 1 V

Horizontal PLL

Analog ADC Channel

Sync Processing

Input impedance, analog video inputs By design 500 k Ω

Input capacitance By design 10 pF Input impedance By design 500 k Ω Output voltage high IOH= 2 mA 0.8 IOVDD V Output voltage low IOL= – 2 mA 0.2 IOVDD V DATACLK output voltage high IOH= 4 mA 0.8 IOVDD V DATACLK output voltage low IOH= – 2 mA 0.2 IOVDD V High-level input voltage By design 0.7 IOVDD V Low-level input voltage By design 0.3 IOVDD V

ADC full-scale input range Clamp disabled 0.95 1 1.05 V ADC resolution 10-bit range 10 bits

Missing code 10 bit, 90 MHz none

at 90 MSPS 55 dB

PP

Analog 3-dB bandwidth 350 500 MHz

By design (W/O LPF) BW select [3:0] = 0h

Phase adjustment 11.6 degree VCO frequency range 9 90 MHz

Coarse gain full-scale control range Gain control value NG= 15 ± 6 dB Coarse offset full-scale control range Referred to 10-bit ADC output ± 124 counts Coarse offset step size Referred to 10-bit ADC output 4 counts

Internal clock reference frequency 5 6.5 7 MHz

pp

Product Folder Link(s): TVP70025I

DATACLK

t1

t2

t3

Valid Data

R, G, B, HSOUT

Valid Data

V

OH

V

OL

CLK POL = 0

CLK POL = 1

TVP70025I

SLES232 – JUNE 2008 ......................................................................................................................................................................................................

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TIMING REQUIREMENTS

PARAMETER TEST CONDITIONS

Clocks, Video Data, Sync Timing

Positive Duty cycle DATACLK (CLK POL = 0) 48 50 52 %

Positive Duty cycle DATACLK (CLK POL = 1) 41 44 45 % t1 DATACLK rise time 10% to 90% 1.2 ns t2 DATACLK fall time 90% to 10% 1.2 ns t3 R,G,B, HSOUT Output delay time 0 2 ns

(1) Measured at 90 MHz with 22- Ω series termination resistor and 10-pF load. Specified by characterization only. Data is clocked out on the

rising edge of DATACLK with Reg 18h CLK POL=0 and is clocked out on the falling edge of DATACLK with CLK POL=1.

(1)

MIN TYP MAX UNIT

Figure 1. Clock, Video Data, and HSOUT Timing

Product Folder Link(s): TVP70025I

SDA

t1

t6

t7

t2

t8

t3

t4

t6

SCL

Data

Stop Start Stop

t5

TVP70025I

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...................................................................................................................................................................................................... SLES232 – JUNE 2008

TIMING REQUIREMENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I2C Host Port

t1 Bus free time between Stop and Start Specified by design 1.3 µ s t2 Setup time for a (repeated) Start condition Specified by design 0.6 µ s t3 Hold time (repeated) Start condition Specified by design 0.6 µ s t4 Setup time for a Stop condition Specified by design 0.6 ns t5 Data setup time Specified by design 100 ns t6 Data hold time Specified by design 0 0.9 µ s t7 Rise time, SDA and SCL signal Specified by design 250 ns t8 Fall time, SDA and SCL signal Specified by design 250 ns C

b

f

I2C

Capacitive load for each bus line Specified by design 400 pF I2C clock frequency Specified by design 400 kHz

Figure 2. I2C Host Port Timing

Product Folder Link(s): TVP70025I

TVP70025I

SLES232 – JUNE 2008 ......................................................................................................................................................................................................

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FUNCTIONAL DESCRIPTION

Analog Channel

The TVP70025I contains three identical analog channels that are independently programmable. Each channel consists of a clamping circuit, programmable gain control, programmable offset control, and an A/D converter.

Analog Input Switch Control

TVP70025I has three analog channels that accept up to ten video inputs. The user can configure the internal analog video switches via the I2C interface. The ten analog video inputs can be used for different input configurations, some of which are:

• Up to three SDTV, EDTV, or HDTV component video inputs (limited by number of SOG inputs)

• Up to two 5-wire PC graphics inputs (limited by number of HSYNC and VSYNC inputs)

The input selection is performed by the input select register at I2C subaddress 19h a 1Ah (see Input Mux Select 1 and Input Mux Select 2).

Supported Video Formats

The TVP70025I supports A/D conversion of SDTV (480i, 576i), EDTV (480p, 576p), and HDTV (720p, 1080i) YPbPr component video inputs. The TVP70025I also supports A/D conversion and color space conversion of all standard PC graphics formats (RGB) from VGA up to WXGA 60Hz.

A summary of the analog video standards supported by the TVP70025I module is shown in the Table below.

Analog Video Standards

VIDEO FORMAT VIDEO STANDARDS

SDTV (YPbPr Component) 480i, 576i EDTV (YPbPr Component) 480p, 576p HDTV (YPbPr Component) 720p, 1080i

PC graphics (RGB Component) VGA - XGA 75Hz, WXGA

SCART (RGB Component) 576i

Analog Input Clamping

The TVP70025I provides dc restoration for all analog video inputs including the SOG slicer inputs. The dc restoration circuit (a.k.a. clamp circuit) restores the ac-coupled video signal to a fixed dc level. One dc restoration circuit is implemented prior to each of the three A/D converters, and a fourth one is located prior to the SOG slicer. The dc restoration circuit can be programmed to operate as either a sync-tip clamp (a.k.a. coarse clamp) or a back-porch clamp (a.k.a. fine clamp). The sync-tip clamp always clamps the video sync-tip level near the bottom of the A/D converter range. The back-porch type clamp supports two clamping levels (bottom level and mid level) that are selectable using bits 0, 1, and 2 of register 10h. When using the fine bottom-level clamp, an optional 300-mV common-mode offset may be selected using bit 7 of register 2Ah.

In general, the analog video input being used for horizontal synchronization purposes should always use the sync-tip clamp; all other analog video inputs should use the back-porch clamp. The advantage of the back-porch clamp is that it has negligible video droop or tilt across a video line.

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TVP70025I

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...................................................................................................................................................................................................... SLES232 – JUNE 2008

The selection between bottom- and mid-level clamping is performed by I2C subaddress 10h (see Section Sync-On-Green Threshold). The fine clamps also must be enabled via I2C register 2Ah for proper operation. The internal clamping time can be adjusted using the I2C clamp start and width registers at subaddress 05h and 06h, respectively (see Clamp Start and Clamp Width).

Table 1. Recommended Clamp Setting by Video Mode

VIDEO MODE

YPbPr Component Coarse Fine Bottom Level Fine Mid Level Fine Mid Level

PC Graphics Coarse Fine Bottom Level Fine Bottom Level Fine Bottom Level

SCART-RGB Coarse Fine Bottom Level Fine Bottom Level Fine Bottom Level

SOG INPUT GREEN ADC CHANNEL RED ADC CHANNEL BLUE ADC CHANNEL

(Y/G) (Y/G) (Pr/R) (Pb/B)

A single-pole low-pass filter with three selectable cutoff frequencies (0.5, 1.7, and 4.8 MHz) is implemented in the feedback loop of the sync-tip clamp circuit.

Programmable Gain Control

The TVP70025I provides a 4-bit coarse analog gain control (before A/D conversion) and an 8-bit fine digital gain control (after A/D conversion). The coarse analog gain and the fine digital gain are both independently programmable for each ADC channel.

Coarse Gain Control

The 4-bit coarse analog gain control has a 4:1 linear gain control range defined by the following equation.

Coarse Gain = 0.5 + N

/10, where 0 ≤ N

CG

≤ 15

CG

0.5 ≤ Coarse Gain ≤ 2.0 Default: N

The 4-bit coarse gain control can scale a signal with a voltage-input compliance of 0.5 V 10-bit A/D output code range. The minimum gain corresponds to a code 0h (2-V while the maximum gain corresponds to code Fh (0.5-V

= 7 (Coarse Gain = 1.2)

CG

to 2 V

PP

full-scale input, – 6-dB gain)

full scale, +6-dB gain). The 4-bit coarse gain control is

PP

to a full-scale

PP

independently controllable for each ADC channel (Red Coarse Gain, Green Coarse Gain, and Blue Coarse Gain).

Fine Gain Control

The 8-bit fine digital gain control has a 2:1 linear gain control range defined by the following equation.

Fine Gain = 1.0 + N

/256 where 0 ≤ N

FG

≤ 255

FG

1.0 ≤ Fine Gain < 2.0 Default: N

= 0 (Fine Gain = 1.0)

FG

The 8-bit fine gain control is independently controllable for each ADC channel (Red Fine Gain, Green Fine Gain, and Blue Fine Gain). For a normal PC graphics input, the fine gain is used mostly.

Programmable Offset Control

The TVP70025I provides a 6-bit coarse analog offset control (before A/D conversion) and a 10-bit fine digital offset control (after A/D conversion). The coarse analog offset and the fine digital offset are both independently programmable for each ADC channel.

Coarse Offset Control

A 6-bit code sets the coarse offset (Red Coarse Offset, Green Coarse Offset, Blue Coarse Offset) with individual adjustment per channel. The coarse offset ranges from – 32 counts to +31 counts. The coarse offset registers apply before the ADC.

Fine Offset Control

A 10-bit fine offset registers (Red Fine Offset, Green Fine Offset, Blue Fine Offset) apply after the ADC. The fine offset ranges from – 512 counts to +511 counts.

Product Folder Link(s): TVP70025I

COAST

HSYNC

Phase

Detector

PLL Control

Register 03h

Bit [5:3]

PLL Control

Register 03h

Bit [7:6]

Phase Select

Register 04h

Bit [7:3]

Charge

Pump

VCO

Phase Select

Divider

ADC

Sampling

CLK

External

Clock

PLL Divide

Register 01h and 02h

1:0]Bit [1

Loop Filter

N = 1 or 2

Post

Divider

÷N

Post Divider

Register 04h

Bit [0]

TVP70025I

SLES232 – JUNE 2008 ......................................................................................................................................................................................................

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Automatic Level Control (ALC)

The ALC circuit maintains the level of the signal to be set at a value that is programmed at the fine offset I2C register. It consists of a pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by the I2C register at subaddress 26h.

The ALC circuit needs a timing pulse generated internally but the user should program the position properly. The ALC pulse must be positioned after the clamp pulse. The position of ALC pulse is controlled by ALC placement I2C register at address 31h. This is available only for internal ALC pulse timing. When using an external clamp pulse, the fine clamp and the ALC both start on the leading edge of the external clamp pulse. Therefore, it is recommended to keep the external clamp pulse as long as possible.

Analog-to-Digital Converters (ADCs)

All ADCs have a resolution of 10 bits and can operate up to 90 MSPS. All A/D channels receive an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 12 MHz and 90 MHz. All ADC reference voltages are generated internally. The external sampling clock also can be used.

Horizontal PLL

The horizontal PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal sync signal supplied on the HSYNC input or from extracted horizontal sync of the sync slicer block for embedded sync signals. The horizontal PLL consists of a phase detector, charge pump, loop filter, voltage controlled oscillator (VCO), phase select, feedback divider, and post divider. The horizontal PLL block diagram is shown in

Figure 3 .

Figure 3. Horizontal PLL Block Diagram

The COAST signal is used to allow the H-PLL to keep running at the same frequency, in the absence of the incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other time that the HSYNC is not available. The fine clamp is disabled during the H-PLL coast interval.

There are several PLL controls to produce the correct sampling clock. The 12-bit feedback divider register is programmable to select exact multiplication number to generate the pixel clock in the range of 12 MHz to 90 MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the low-pass loop filter. The applicable current values are listed in Table 2 .

Product Folder Link(s): TVP70025I

0.1 µF

4.7 nF

1.5 kW

TVP70025I

PLL_F

FILT2

FILT1

89

88

87

TVP70025I

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...................................................................................................................................................................................................... SLES232 – JUNE 2008

The purpose of the 2-bit VCO range control is to improve the noise performance of the TVP70025I. The frequency ranges for the VCO are shown in Table 2 . The phase of the ADC sample clock generated by the horizontal PLL can be accurately controlled in 32 uniform steps over a single clock period (360/32 = 11.25 degrees phase resolution) using the phase select register located at subaddress 04h.

The horizontal PLL characteristics are determined by the loop filter design, the PLL charge pump current, and the VCO range setting. The loop filter design is shown in Figure 4 . Supported settings of VCO range and charge pump current for VESA standard display modes are listed in Table 2 .

Figure 4. Horizontal PLL Loop Filter

In addition to sourcing the ADC sample clock from the horizontal PLL, an external pixel clock can be used (from pin 80).

Table 2. Recommended VCO Range and Charge Pump Current Settings

for Supporting Standard Display Formats

STANDARD RESOLUTION RATE RATE [11:4] REG [3:0] REG REG 03h DIVIDER

640 × 480 59.94 31.469 25.175 800 32h 00h 20h 0 ULow (00b) 100b

VGA

SVGA 800 × 600 72.188 48.077 50 1040 41h 00h 58h 0 Low (01b) 011b

XGA 1024 × 768 70.069 56.476 75 1328 53h 00h A8h 0 Med (10b) 101b

WXGA 1280 × 768 59.87 47.776 79.5 1664 68h 00h A0h 0 Med (10b) 100b

Video

640 × 480 72.809 37.861 31.5 832 34h 00h 20h 0 ULow (00b) 100b 640 × 480 75 37.5 31.5 840 34h 80h 20h 0 ULow (00b) 100b 640 × 480 85.008 43.269 36 832 34h 00h 60h 0 Low (01b) 100b 800 × 600 56.25 35.156 36 1024 40h 00h 58h 0 Low (01b) 011b 800 × 600 60.317 37.879 40 1056 42h 00h 58h 0 Low (01b) 011b

800 × 600 75 46.875 49.5 1056 42h 00h 58h 0 Low (01b) 011b 800 × 600 85.061 53.674 56.25 1048 41h 80h 58h 0 Low (01b) 011b

1024 × 768 60.004 48.363 65 1344 54h 00h 58h 0 Low (01b) 011b

1024 × 768 75.029 60.023 78.75 1312 52h 00h A8h 0 Med (10b) 101b 1280 × 768 59.995 47.396 68.25 1440 5Ah 00h 50h 0 Low (01b) 010b

1440 x 900 59.01 55.469 88.75 1600 64h 00h A0h 0 Med (10b) 100b

720 × 480i 29.97 15.374 13.5 858 35h A0h 18h 0 ULow (00b) 011b

720 × 576i 25 15.625 13.5 864 36h 00h 18h 0 ULow (00b) 011b 720 × 480p 59.94 31.469 27 858 35h A0h 18h 0 ULow (00b) 011b 720 × 576p 50 31.25 27 864 36h 00h 18h 0 ULow (00b) 011b

1280 × 720p 60 45 74.25 1650 67h 20h A0h 0 Med (10b) 100b 1280 × 720p 50 37.5 74.25 1980 7Bh C0h 98h 0 Med (10b) 011b 1920 × 1080i 60 33.75 74.25 2200 89h 80h 98h 0 Med (10b) 011b 1920 × 1080i 50 28.125 74.25 2640 A5h 00h 90h 0 Med (10b) 010b

FRAME PIXEL PLLDIV PLLDIV OUTPUT

(Hz) (MHz) 01h [7:0] 02h [7:4] REG 04h [0]

LINE RATE DIVIDER RANGE CURRENT

(kHz) TOTAL REG 03h REG 03h

PLL VCO CP

PIX/LINE [7:6] [5:3]

Product Folder Link(s): TVP70025I

TVP70025I

SLES232 – JUNE 2008 ......................................................................................................................................................................................................

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RGB-to-YCbCr Color Space Conversion

The TVP70025I supports RGB-to-YCbCr color space conversion (CSC) with I2C programmable coefficients. The TVP70025I should default to the CSC coefficients required for HDTV component video inputs. The TVP70025I supports the ability to bypass the CSC block and defaults to the bypass mode (bit 3of subaddress 23h).

RGB-to-YCbCr CSC coefficients for HDTV component video (see CEA-770.3-C, ITU-R BT.709) (default coefficients):

G ' B ' R '

Y 00000016E3 000000024F 00000006CE

Pb FFFFFFF3AB 0000001000 FFFFFFFC55

Pr FFFFFFF178 FFFFFFFE88 0000001000

RGB-to-YCbCr CSC coefficients for SDTV component video (see CEA-770.2-C, ITU-R BT.601) (informative only):

G ' B ' R '

Y 00000012C9 00000003A6 0000000991

Pb FFFFFFF566 0000001000 FFFFFFFA9A

Pr FFFFFFF29A FFFFFFFD66 0000001000

4:4:4 to 4:2:2 Conversion

For 4:4:4 YPbPr component video inputs, the TVP70025I can downsample the chroma samples (CbCr) from 1 × to 0.5 × using a 27-tap half-band filter.

NOTE:

• Selection between the 30-bit 4:4:4 output format and the 20-bit 4:2:2 output format is made

using bit 1 of register 15h.

• Multiplexed CbCr data is output on BOUT [9:0] in the 20-bit 4:2:2 output format.

• 4:4:4 to 4:2:2 conversion is implemented after RGB-to-YCbCr color space conversion.

Product Folder Link(s): TVP70025I

TVP70025I

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Sync Processing

Horizontal Sync Selection

The TVP70025I provides two HSYNC inputs and three analog SOG inputs for HDTV and PC graphics inputs. The sync input used by the horizontal PLL is automatically selected based on activity detection.

Sync Slicer

TVP70025I includes a circuit that compares the input signal on Green channel to a level 150 mV (typical value) above the clamped level (sync tip). The slicing level is programmable by I2C register subaddress at 10h. The digital output of the composite sync slicer is available on the SOGOUT pin.

Noise Immunity

In general, noise on a slowly varying input signal (i.e., sync falling edge) may cause a voltage comparator to false trigger as the input passes through the linear range of the comparator. To improve the overall performance of the TVP70025I sync slicer in the presence of noise on the SOG input, the voltage comparator includes hysteresis. Maintaining a 50% slice level using the I2C programmable slice level control can further improve the noise immunity of the Sync slicer. The slice level is programmable in 11.2-mV increments over a 350-mV range as follows.

slice_level = (350 mV) × (N where 0 ≤ N

≤ 31, default: 11

TH

0 ≤ slice_level ≤ 350 mV

Glitch Immunity

During white-to-black transitions, the input video waveform may undershoot below the sync slicer threshold. To help attenuate the amplitude of such glitches, a single-pole low-pass filter with three selectable cutoff frequencies (2.5, 10, and 33 MHz) is provided at the input of the SOG voltage comparator circuit. This filter is bypassed in the default mode.

/31)

TH

NOTE:

Although the low-pass filter may attenuate the amplitude of glitches present on the SOG input, it also makes the sync falling edge less sharp.

Sync Separator

The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at the SOG input. The G or Y input containing the composite sync must be ac coupled to the SOG input pin using a 1-nF capacitor. Support for PC graphics, SDTV, EDTV, and HDTV up to 1080i is provided.

Sync Activity Detection

The TVP70025I provides activity detection on the sync inputs (VSYNC, HSYNC) to enable the host processor to determine whether the PC graphics source is configured as a 3-wire, 4-wire, or 5-wire interface as defined here:

• 5 wire (G, B, R, HSYNC, VSYNC)

• 4 wire (G, B, R, CSYNC)

• 3 wire (G, B, R with SOG)

If activity is detected on the VSYNC input, the host processor should assume that the PC graphics input is a standard 5-wire interface. In this case, the HSYNC input of the TVP70025I should be configured as an HSYNC input. If AHSO and AVSO are set for automatic selection in I2C Reg 0Eh, the TVP70025I automatically uses the HSYNC and VSYNC inputs, provided signals are present at both inputs.

Product Folder Link(s): TVP70025I