Texas Instruments TVP5147M1PFP User Manual

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 y    !"  #$%E %& '( )%*+$& % % ,( 

Data M anua

March 2007 Digital Audio Video

SLES140A

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty . Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony

Video & Imaging www.ti.com/video Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Contents

Section Page

1 Introduction 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Detailed Functionality 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 TVP5147M1 Applications 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Related Products 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Functional Block Diagram 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Terminal Assignments 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Terminal Functions 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Description 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Analog Processing and A/D Converters 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Video Input Switch Control 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Analog Input Clamping 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Automatic Gain Control 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 Analog Video Output 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 A/D Converters 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Digital Video Processing 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 2y Decimation Filter 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Composite Processor 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Luminance Processing 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Color Transient Improvement 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Clock Circuits 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Real-Time Control (RTC) 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Output Formatter 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 Separate Syncs 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Embedded Syncs 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 I2C Host Interface 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 Reset and I2C Bus Address Selection 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 I2C Operation 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.3 VBUS Access 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 VBI Data Processor 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 VBI FIFO and Ancillary Data in Video Stream 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.2 VBI Raw Data Output 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Reset and Initialization 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Adjusting External Syncs 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Internal Control Registers 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Register Definitions 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.1 Input Select Register 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.2 AFE Gain Control Register 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.3 Video Standard Register 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.4 Operation Mode Register 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.5 Autoswitch Mask Register 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.6 Color Killer Register 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.7 Luminance Processing Control 1 Register 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.8 Luminance Processing Control 2 Register 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.9 Luminance Processing Control 3 Register 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.10 Luminance Brightness Register 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2005 SLES140

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Contents

Section Page

2.11.11 Luminance Contrast Register 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.12 Chrominance Saturation Register 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.13 Chroma Hue Register 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.14 Chrominance Processing Control 1 Register 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.15 Chrominance Processing Control 2 Register 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.16 AVID Start Pixel Register 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.17 AVID Stop Pixel Register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.18 HSYNC Start Pixel Register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.19 HSYNC Stop Pixel Register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.20 VSYNC Start Line Register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.21 VSYNC Stop Line Register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.22 VBLK Start Line Register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.23 VBLK Stop Line Register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.24 CTI Delay Register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.25 CTI Control Register 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.26 Sync Control Register 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.27 Output Formatter 1 Register 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.28 Output Formatter 2 Register 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.29 Output Formatter 3 Register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.30 Output Formatter 4 Register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.31 Output Formatter 5 Register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.32 Output Formatter 6 Register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.33 Clear Lost Lock Detect Register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.34 Status 1 Register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.35 Status 2 Register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.36 AGC Gain Status Register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.37 Video Standard Status Register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.38 GPIO Input 1 Register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.39 GPIO Input 2 Register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.40 AFE Coarse Gain for CH 1 Register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.41 AFE Coarse Gain for CH 2 Register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.42 AFE Coarse Gain for CH 3 Register 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.43 AFE Coarse Gain for CH 4 Register 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.44 AFE Fine Gain for Pb Register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.45 AFE Fine Gain for Y_Chroma Register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.46 AFE Fine Gain for Pr Register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.47 AFE Fine Gain for CVBS_Luma Register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.48 Field ID Control Register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.49 F-bit and V-bit Control 1 Register 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.50 Back-End AGC Control Register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.51 AGC Decrement Speed Control Register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.52 ROM Version Register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.53 AGC White Peak Processing Register 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.54 F and V Bit Control Register 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.55 VCR Trick Mode Control Register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.56 Horizontal Shake Increment Register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.57 AGC Increment Speed Register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.58 AGC Increment Delay Register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2005SLES140

Contents

Section Page

2.11.59 Analog Output Control 1 Register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.60 Chip ID MSB Register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.61 Chip ID LSB Register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.62 CPLL Speed Control Register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.63 Status Request Register 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.64 Vertical Line Count Register 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.65 AGC Decrement Delay Register 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.66 VDP TTX Filter And Mask Registers 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.67 VDP TTX Filter Control Register 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.68 VDP FIFO Word Count Register 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.69 VDP FIFO Interrupt Threshold Register 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.70 VDP FIFO Reset Register 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.71 VDP FIFO Output Control Register 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.72 VDP Line Number Interrupt Register 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.73 VDP Pixel Alignment Register 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.74 VDP Line Start Register 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.75 VDP Line Stop Register 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.76 VDP Global Line Mode Register 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.77 VDP Full Field Enable Register 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.78 VDP Full Field Mode Register 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.79 VBUS Data Access With No VBUS Address Increment Register 66 . . . . . . . . . . . . . . .

2.11.80 VBUS Data Access With VBUS Address Increment Register 66 . . . . . . . . . . . . . . . . . .

2.11.81 FIFO Read Data Register 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.82 VBUS Address Access Register 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.83 Interrupt Raw Status 0 Register 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.84 Interrupt Raw Status 1 Register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.85 Interrupt Status 0 Register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.86 Interrupt Status 1 Register 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.87 Interrupt Mask 0 Register 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.88 Interrupt Mask 1 Register 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.89 Interrupt Clear 0 Register 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.90 Interrupt Clear 1 Register 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 VBUS Register Definitions 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.1 VDP Closed Caption Data Register 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.2 VDP WSS Data Register 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.3 VDP VITC Data Register 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.4 VDP V-Chip TV Rating Block 1 Register 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.5 VDP V-Chip TV Rating Block 2 Register 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.6 VDP V-Chip TV Rating Block 3 Register 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.7 VDP V-CHIP MPAA Rating Data Register 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.8 VDP General Line Mode and Line Address Register 76 . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.9 VDP VPS/Gemstar Data Register 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.10 Analog Output Control 2 Register 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12.11 Interrupt Configuration Register 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Electrical Specifications 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings† 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Recommended Operating Conditions 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Crystal Specifications 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2005 SLES140

Contents

Section Page

3.3 Electrical Characteristics 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 DC Electrical Characteristics 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 Analog Processing and A/D Converters 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3 Timing 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Example Register Settings 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Example 1 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Assumptions 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 Recommended Settings 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Example 2 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Assumptions 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 Recommended Settings 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Example 3 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 Assumptions 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.2 Recommended Settings 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Information 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Application Example 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Designing With PowerPAD Devices 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2005SLES140

List of Illustrations

Figure Title Page

1−1 Functional Block Diagram 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1−2 Terminal Assignments Diagram 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 Analog Processors and A/D Converters 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Digital Video Processing Block Diagram 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Composite and S-Video Processing Block Diagram 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 Color Low-Pass Filter Frequency Response 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Color Low-Pass Filter With Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling 13 . . . . . . . . .

2−6 Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling 13 . . . . . . . . . . . . . . . . . . . .

2−7 Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling 13 . . . . . . . . . . . . . . . . . . . . . .

2−8 Luminance Edge-Enhancer Peaking Block Diagram 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 Reference Clock Configurations 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 RTC Timing 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 Vertical Synchronization Signals for 525-Line System 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−13 Vertical Synchronization Signals for 625-Line System 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−14 Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−15 Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−16 VSYNC Position With Respect to HSYNC 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−17 VBUS Access 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−18 Reset Timing 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−19 Teletext Filter Function 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Clocks, Video Data, and Sync Timing 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 I

5−1 Example Application Circuit 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Host Port Timing 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

July 2005 SLES140

vii

List of Tables

Table Title Page

1−1 Terminal Functions 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 Output Format 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Summary of Line Frequencies, Data Rates, and Pixel/Line Counts 16 . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 EAV and SAV Sequence 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 I

2−5 I2C Address Selection 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 Supported VBI System 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 Ancillary Data Format and Sequence 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 VBI Raw Data Output Format 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 Reset Sequence 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 I2C Register Summary 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 VBUS Register Summary 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 Analog Channel and Video Mode Selection 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Host Interface Terminal Description 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

July 2005SLES140

1 Introduction

Macrovision is a trademark of Macrovision Corporation. O

The TVP5147M1 device is a high-quality, single-chip digital video decoder that digitizes and decodes all popular baseband analog video formats into digital component video. The TVP5147M1 decoder supports the analog-to-digital (A/D) conversion of component YPbPr signals, as well as the A/D conversion and decoding of NTSC, PAL, and SECAM composite and S-video into component YCbCr. This decoder includes two 10-bit 30-MSPS A/D converters (ADCs). Preceding each ADC in the device, the corresponding analog channel contains an analog circuit that clamps the input to a reference voltage and applies a programmable gain and offset. A total of 10 video input terminals can be configured to a combination of YPbPr, CVBS, or S-video video inputs.

Composite or S-video signals are sampled at 2× the ITU-R BT.601 clock frequency, line-locked alignment, and are then decimated to the 1× pixel rate. CVBS decoding uses five-line adaptive comb filtering for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap filter is also available. On CVBS and S-video inputs, the user can control video characteristics such as contrast, brightness, saturation, and hue via an I programmable gain is included, as well as a patented chroma transient improvement (CTI) circuit.

The following output formats can be selected: 20-bit 4:2:2 YCbCr or 10-bit 4:2:2 YCbCr. The TVP5147M1 decoder generates synchronization, blanking, field, active video window, horizontal and

vertical syncs, clock, genlock (for downstream video encoder synchronization), host CPU interrupt and programmable logic I/O signals, in addition to digital video outputs.

Introduction

C host port interface. Furthermore, luma peaking (sharpness) with

The TVP5147M1 decoder includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor (VDP) slices, parses, and performs error checking on teletext, closed caption (CC), and other VBI data. A built-in FIFO stores up to 11 lines of teletext data, and with proper host port synchronization, full-screen teletext retrieval is possible. The TVP5147M1 decoder can pass through the output formatter 2× sampled raw luma data for host-based VBI processing.

The main blocks of the TVP5147M1 decoder include:

• Robust sync detection for weak and noisy signals as well as VCR trick modes

• Y/C separation by 2-D 5-line adaptive comb or chroma trap filter

• Two 10-bit, 30-MSPS A/D converters with analog preprocessors [clamp and automatic gain control

(AGC)]

• Analog video output

• Luminance processor

• Chrominance processor

• Clock/timing processor and power-down control

• Software-controlled power-saving standby mode

• Output formatter

• I

C host port interface

• VBI data processor

• Macrovision copy protection detection circuit (Type 1, 2, 3, and separate color stripe detection)

• 3.3-V tolerant digital I/O ports

ther trademarks are the property of their respective owners.

SLES140A—March 2007 TVP5147M1PFP

Introduction

1.1 Detailed Functionality

• Two 30-MSPS, 10-bit A/D channels with programmable gain control

• Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60) and SECAM (B, D, G, K, K1, L) CVBS, and

S-video

• Supports analog component YPbPr video format with embedded sync

• 10 analog video input terminals for multisource connection

• Supports analog video output

• User-programmable video output formats

− 10-bit ITU-R BT.656 4:2:2 YCbCr with embedded syncs

− 10-bit 4:2:2 YCbCr with separate syncs

− 20-bit 4:2:2 YCbCr with separate syncs

−2× sampled raw VBI data in active video during a vertical blanking period

− Sliced VBI data during a vertical blanking period or active video period (full field mode)

• HSYNC/VSYNC outputs with programmable position, polarity, width, and field ID (FID) output

• Composite and S-video processing

− Adaptive 2-D 5-line adaptive comb filter for composite video inputs; chroma-trap available

− Automatic video standard detection (NTSC/PAL/SECAM) and switching

− Luma-peaking with programmable gain

− Patented chroma transient improvement (CTI)

− Patented architecture for locking to weak, noisy, or unstable signals

− Single 14.31818-MHz reference crystal for all standards

− Line-locked internal pixel sampling clock generation with horizontal and vertical lock signal outputs

− Genlock output RTC format for downstream video encoder synchronization

• Certified Macrovision copy protection detection

SLES140A—March 2007TVP5147M1PFP

• VBI data processor

Gemstar is a trademark of Gemstar-TV Guide Intermational. P

− Teletext (NABTS, WST)

− CC and extended data service (EDS)

− Wide screen signaling (WSS)

− Copy generation management system (CGMS)

− Video program system (VPS/PDC)

− Vertical interval time code (VITC)

− Gemstar 1×/2× mode

− V-Chip decoding

− Register readback of CC, WSS (CGMS), VPS/PDC, VITC and Gemstar 1×/2× sliced data

• I

C host port interface

• Reduced power consumption: 1.8-V digital core, 3.3-V for digital I/O, and 1.8-V/3.3 V analog core with power-save and power-down modes

• 80-terminal TQFP PowerPAD package

1.2 TVP5147M1 Applications

• DLP projectors

• Digital TV

• LCD TV/monitors

• DVD recorders

• PVR

• PC video cards

• Video capture/video editing

• Video conferencing

Introduction

1.3 Related Products

• TVP5146M2 NTSC/PAL/SECAM 2y10-Bit Digital VIdeo Decoder With MacrovisionE Detection, YPbPr/RGB Inputs, and 5-Line Comb Filter (SLES141)

• TVP5150AM1 Ultralow Power NTSC/PAL/SECAM Video Decoder With Robust Sync Detector (SLES098)

1.4 Ordering Information

0°C to 70°C TVP5147M1PFP

owerPAD is a trademark of Texas Instruments.

PACKAGED DEVICES

80-TERMINAL PLASTIC

FLAT-PACK PowerPADE PACKAGE

SLES140A—March 2007 TVP5147M1PFP

Introduction

1.5 Functional Block Diagram

CVBS/

C/Pb

CVBS/

C/Pr

CVBS/Y

VI_1_A VI_1_B

VI_1_C

VI_2_A VI_2_B

VI_2_C

VI_3_A VI_3_B

VI_3_C

VI_4_A

Analog

Front End

Clamping

AGC

2 × 11-Bit

ADC

Sampling Clock

Copy

Protection

Detector

M U X

Timing Processor

With Sync Detector

CVBS/Y

C/CbCr

VBI

Data

Processor

Composite and S-Video Processor

Y/C

Separation

5-line

Adaptive

Comb

Luma

Processing

Chroma

Processing

YCbCr

Y[9:0]

Output

Formatter

C[9:0]

GPIO

Host

Interface

FID

XTAL1

XTAL2

PWDN

RESETB

AVID

DATACLK

GLCO

HS/CS

VS/VBLK

Figure 1−1. Functional Block Diagram

SCL

SDA

SLES140A—March 2007TVP5147M1PFP

1.6 Terminal Assignments

VI_1_A

CH1_A18GND

CH1_A18VDD

PLL_A18GND

PLL_A18VDD

XTAL2

XTAL1

PFP PACKAGE

(TOP VIEW)

VS/VBLK/GPIO

HS/CS/GPIO

FID/GPIO

C_0/GPIO

C_1/GPIO

DGND

DVDD

C_2/GPIO

C_3/GPIO

C_4/GPIO

C_5/GPIO

IOGND

IOVDD

Introduction

VI_1_B VI_1_C

CH1_A33GND

CH1_A33VDD CH2_A33VDD

CH2_A33GND

VI_2_A VI_2_B VI_2_C

CH2_A18GND

CH2_A18VDD A18VDD_REF

A18GND_REF

NC VI_3_A VI_3_B VI_3_C

79 78 77 76 7580 74 72 71 7073

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

22 23

VI_4_A

25 26 27 28

AGND

A18VDD

A18GND

SCL

DGND

69 682167 66 65 64

30 31 32 33

SDA

DVDD

INTREQ

34 35 36 37 38 39 40

PWDN

GPIO

DGND

RESETB

AVID/GPIO

63 62 61

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

IOVDD

IOGND

GLCO/I2CA

DATACLK

C_6/GPIO C_7/GPIO C_8/GPIO C_9/GPIO DGND DVDD Y_0 Y_1 Y_2 Y_3 Y_4 IOGND IOVDD Y_5 Y_6 Y_7 Y_8 Y_9 DGND DVDD

Figure 1−2. Terminal Assignments Diagram

SLES140A—March 2007 TVP5147M1PFP

Introduction

I/O

DESCRIPTION

VI_2_B

VI_4_A: Analog video input for CVBS/Y

VI_2_B

VI_4_A: Analog video input for CVBS/Y

1.7 Terminal Functions

TERMINAL

NAME NUMBER

Analog Video

VI_1_A VI_1_B VI_1_C VI_2_A

I/O

VI_1_A: Analog video input for CVBS/Pb/C or analog video output (see Section 2.11.59) 1 2 7

VI_1_x: Analog video input for CVBS/Pb/C

VI_2_x: Analog video input for CVBS/Y

VI_3_x: Analog video input for CVBS/Pr/C

Table 1−1. Terminal Functions

VI_2_C VI_3_A VI_3_B VI_3_C VI_4_A

Clock Signals

DATACLK 40 O Line-locked data output clock XTAL1 74 I XTAL2 75 O External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator.

Digital Video

C_[9:0]/ GPIO[9:0]

Y[9:0]

Miscellaneous Signals

GPIO 35 I/O Programmable general-purpose I/O GLCO/I2CA 37 I/O INTREQ 30 O Interrupt request

PWDN 33 I

RESETB 34 I Reset input, active low (see Section 2.8)

Host Interface

SCL 28 I I2C clock input SDA 29 I/O I2C data bus

16 17 18 23

57, 58, 59, 60, 63, 64, 65, 66,

69, 70

43, 44, 45, 46, 47, 50, 51, 52,

53, 54

14, 15, 19, 20,

21, 22

Up to 10 composite, 4 S-video, and 2 composite or 3 component video inputs (or a combination thereof)

can be supported.

The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 µF.

The possible input configurations are listed in the input select register at I2C subaddress 00h (see

Section 2.11.1).

External clock reference input. It can be connected to an external oscillator with a 1.8-V compatible clock

signal or a 14.31818-MHz crystal oscillator.

Digital video output of CbCr, C[9] is MSB and C[0] is LSB. Also, these terminals can be programmable

general-purpose I/O.

I/O

For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.

Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB.

For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.

Genlock control output (GLCO) uses real time control (RTC) format.

During reset, this terminal is an input used to program the I2C address LSB.

Not connected. These terminals can be connected to power or ground (compatible with TVP5146

terminals), internally floating.

Power down input:

1 = Power down

0 = Normal mode

SLES140A—March 2007TVP5147M1PFP

Table 1−1. Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NUMBER

Power Supplies

AGND 26 Analog ground. Connect to analog ground. A18GND_REF 13 Analog 1.8-V return A18VDD_REF 12 Analog power for reference 1.8 V CH1_A18GND

CH2_A18GND A18GND

CH1_A18VDD CH2_A18VDD A18VDD

CH1_A33GND CH2_A33GND

CH1_A33VDD CH2_A33VDD

DGND

DVDD IOGND 39, 49, 62 Digital power return

IOVDD 38, 48, 61 Digital power. Connect to 3.3 V or less for reduced noise. PLL_A18GND 77 Analog power return PLL_A18VDD 76 Analog power. Connect to 1.8 V.

Sync Signals

HS/CS/GPIO 72 I/O

VS/VBLK/GPIO 73 I/O

FID/GPIO 71 I/O

AVID/GPIO 36 I/O

79 10 24

78 11 25

3 6

4 5

27, 32, 42,

56, 68

31, 41, 55,

Analog 1.8-V return

Analog power. Connect to 1.8 V.

Analog 3.3-V return

Analog power. Connect to 3.3 V.

Digital return

Digital power. Connect to 1.8 V.

Horizontal sync output or digital composite sync output Programmable general-purpose I/O

Vertical sync output (for modes with dedicated VSYNC) or VBLK output Programmable general-purpose I/O

Odd/even field indicator output. This terminal needs a pulldown resistor (see Figure 5−1). Programmable general-purpose I/O

Active video indicator output Programmable general-purpose I/O

Introduction

SLES140A—March 2007 TVP5147M1PFP

Introduction

SLES140A—March 2007TVP5147M1PFP

2 Functional Description

2.1 Analog Processing and A/D Converters

Figure 2−1 shows a functional diagram of the analog processors and A/D converters, which provide the analog interface to all video inputs. It accepts up to 10 inputs and performs source selection, video clamping, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal. The TVP5147M1 supports one analog video output for the selected analog input video.

I/O

VI_1_A

PGA

U X

Functional Description

Analog Front End

VBS/

Pb/C

VBS/

Pr/C

VI_1_B VI_1_C

VI_2_A VI_2_B VI_2_C

VI_3_A VI_3_B

VI_3_C

VI_4_A

M U X

Clamp

PGA

11-Bit

ADC

11-Bit

ADC

CH1 A/D

CH2 A/D

Line-Locked Sampling Clock

Figure 2−1. Analog Processors and A/D Converters

2.1.1 Video Input Switch Control

The TVP5147M1 decoder has two analog channels that accept up to 10 video inputs. The user can configure the internal analog video switches via the I

C interface. The 10 analog video inputs can be used for different

input configurations, some of which are:

SLES140A—March 2007 TVP5147M1PFP

Functional Description

• Up to 10 selectable individual composite video inputs

• Up to four selectable S-video inputs

• Up to three selectable analog YPbPr video inputs and one CVBS input

• Up to two selectable analog YPbPr video inputs, two S-video inputs, and two CVBS inputs

The input selection is performed by the input select register at I

2.1.2 Analog Input Clamping

An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection between bottom and mid clamp is performed automatically by the TVP5147M1 decoder.

2.1.3 Automatic Gain Control

The TVP5147M1 decoder uses two programmable gain amplifiers (PGAs), one per channel. The PGA can scale a signal with a voltage-input compliance of 0.5-V range. A 4-bit code sets the coarse gain with individual adjustment per channel. Minimum gain corresponds to a code 0x0 (2.0-V full scale, +6-dB gain). The TVP5147M1 decoder also has 12-bit fine gain controls for each channel and applies independently to coarse gain controls. For composite video, the input video signal amplitude can vary significantly from the nominal level of 1 V automatically: an automatic gain control (AGC) can be enabled and can adjust the signal amplitude such that the maximum range of the ADC is reached without clipping. Some nonstandard video signals contain peak white levels that saturate the ADC. In these cases, the AGC automatically cuts back gain to avoid clipping. If the AGC is on, then the TVP5147M1 decoder can read the gain currently being used.

full-scale input, −6-dB gain) while maximum gain corresponds to code 0xF (0.5 V

C subaddress 00h (see Section 2.11.1).

to 2.0-VPP to a full-scale 10-bit A/D output code

. The TVP5147M1 decoder can adjust its PGA setting

The TVP5147M1 AGC comprises the front-end AGC before Y/C separation and the back-end AGC after Y/C separation. The back-end AGC restores the optimum system gain whenever an amplitude reference such as the composite peak (which is only relevant before Y/C separation) forces the front-end AGC to set the gain too low. The front-end and back-end AGC algorithms can use up to four amplitude references: sync height, color burst amplitude, composite peak, and luma peak.

The specific amplitude references being used by the front-end and back-end AGC algorithms can be independently controlled using the AGC white peak processing register located at subaddress 74h. The TVP5147M1 gain increment speed and gain increment delay can be controlled using the AGC increment speed register located at subaddress 78h and the AGC increment delay register located at subaddress 79h.

2.1.4 Analog Video Output

One of the analog input signals is available at the analog video output terminal, which is shared with input selected by I voltage is 2 V p-p, thus the signal can be used to drive a 75-Ω line. The magnitude is maintained with an AGC in 16 steps controlled by the TVP5147M1 decoder. In order to use this function, terminal VI_1_A must be set as an output terminal. The input mode selection register also selects an active analog output signal.

C registers. The signal at this terminal must be buffered by a source follower . The nominal output

2.1.5 A/D Converters

All ADCs have a resolution of 10 bits and can operate up to 30 MSPS. All A/D channels receive an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and 30 MHz. All ADC reference voltages are generated internally.

SLES140A—March 2007TVP5147M1PFP

2.2 Digital Video Processing

Figure 2−2 is a block diagram of the TVP5147M1 digital video decoder processing. This block receives digitized video signals from the ADCs and performs composite processing for CVBS and S-video inputs and YCbCr signal enhancements for CVBS and S-video inputs. It also generates horizontal and vertical syncs and other output control signals such as genlock for CVBS and S-video inputs. Additionally, it can provide field identification, horizontal and vertical lock, vertical blanking, and active video window indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with external syncs or 10-bit 4:2:2 with embedded/separate syncs. The circuit detects pseudosync pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected material. Information present in the VBI interval can be retrieved and either inserted in the ITU-R BT.656 output as ancillary data or stored in internal FIFO and/or registers for retrieval via the host port interface.

Functional Description

CH1 A/D

CH2 A/D

2×

Decimation

2×

Decimation

Protection

Detector

XTAL1 XTAL2

RESETB

PWDN

DATACLK

Copy

CVBS/Y C/CbCr

Timing

Processor

VBI Data

Processor

Composite Processor

FID VS/VBLK HS/CS GLCO AVID

Slice VBI Data

YCbCr

Figure 2−2. Digital Video Processing Block Diagram

Output

Formatter

Host

Interface

Y[9:0]

C[9:0]

SCL SDA

2.2.1 2× Decimation Filter

All input signals are typically oversampled by a factor of 2 (27 MHz). The A/D outputs initially pass through decimation filters that reduce the data rate to 1× the pixel rate. The decimation filter is a half-band filter. Oversampling and decimation filtering can effectively increase the overall signal-to-noise ratio by 3 dB.

2.2.2 Composite Processor

Figure 2−3 is a block diagram of the TVP5147M1 digital composite video processing circuit. This processing circuit receives a digitized composite or S-video signal from the ADCs and performs Y/C separation (bypassed for S-video input), chroma demodulation for PAL/NTSC and SECAM, and YUV signal enhancements.

The 10-bit composite video is multiplied by the subcarrier signals in the quadrature demodulator to generate color difference signals U and V. The U and V signals are then sent to low-pass filters to achieve the desired bandwidth. An adaptive 5-line comb filter separates UV from Y based on the unique property of color phase shifts from line to line. The chroma is remodulated through a quadrature modulator and subtracted from line-delayed composite video to generate luma. This form of Y/C separation is completely complementary, thus there is no loss of information. However, in some applications, it is desirable to limit the U/V bandwidth to avoid crosstalk. In that case, notch filters can be turned on. To accommodate some viewing preferences, a peaking filter is also available in the luma path. Contrast, brightness, sharpness, hue, and saturation controls are programmable through the host port.

SLES140A—March 2007 TVP5147M1PFP

Functional Description

CVBS/Y

CVBS

Line

Delay

SECAM Luma

SECAM

Color

Demodulation

Peaking

–

NTSC/PAL

Remodulation

Color LPF

↓ 2

Accumulator

Burst

(U)

Burst

(V)

5-Line

Adaptive

Comb

Filter

Delay

Notch

Filter

Notch

Filter

Notch

Filter

Delay

Contrast

Brightness

Saturation

Adjust

CVBS/C

NTSC/PAL

Demodulation

Figure 2−3. Composite and S-Video Processing Block Diagram

2.2.2.1 Color Low-Pass Filter

High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for nonstandard video sources that have asymmetrical U and V side bands, it is desirable to limit the filter bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the three notch filters. Figure 2−4 and Figure 2−5 represent the frequency responses of the wideband color low-pass filters.

Color LPF

↓ 2

Notch

Filter

Delay

SLES140A—March 2007TVP5147M1PFP

Functional Description

−10

−20

−30 ITU-R BT.601 −3 dB

−40

Amplitude − dB

−50

−60

−70

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

@ 1.42 MHz

f − Frequency − MHz

Figure 2−4. Color Low-Pass Filter Frequency

Response

2.2.2.2 Y/C Separation

−10

−20

−30

−40

Amplitude − dB

−50

−60

−70

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4. f − Frequency − MHz

Filter 2

−3 dB @ 844 kHz Filter 0

−3 dB @ 1.41 MHz

Filter 3

−3 dB @ 554 kHz Filter 1

−3 dB

@ 1.03 MHz

Figure 2−5. Color Low-Pass Filter With Filter

Characteristics, NTSC/PAL ITU-R BT.601

Sampling

Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter. The comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma trap filters are used which are shown in Figure 2−6 and Figure 2−7. The TI patented adaptive comb filter algorithm reduces artifacts such as hanging dots at color boundaries. It detects and properly handles false colors in high-frequency luminance images such as a multiburst pattern or circle pattern.

−5

−10 Notch 1 Filter

−15

−20

Amplitude − dB

Notch 2 Filter

−25

No Notch Filter

−30

−35

−40

01234567

Notch 3 Filter

f − Frequency − MHz

−5

−10

−15

−20

Amplitude − dB

−25

−30

−35

−40

Notch 1 Filter

Notch 2 Filter

No Notch Filter

01234567

f − Frequency − MHz

Notch 3 Filter

Figure 2−6. Chroma Trap Filter Frequency

Response, NTSC ITU-R BT.601 Sampling

SLES140A—March 2007 TVP5147M1PFP

Figure 2−7. Chroma Trap Filter Frequency

Response, PAL ITU-R BT.601 Sampling

Functional Description

Gain

2.2.3 Luminance Processing

The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter, either of which removes chrominance information from the composite signal to generate a luminance signal. The luminance signal is then fed into the input of a peaking circuit. Figure 2−8 illustrates the basic functions of the luminance data path. In the case of S-video, the luminance signal bypasses the comb filter or chroma trap filter and is fed directly to the circuit. A peaking filter (edge enhancer) amplifies high-frequency components of the luminance signal. Figure 2−9 shows the characteristics of the peaking filter at four dif ferent gain settings that are user-programmable via the I

C interface.

Peak

Detector

Bandpass

Filter

Peaking

Filter

Delay

OUT

Figure 2−8. Luminance Edge-Enhancer Peaking Block Diagram

Amplitude − dB

−1 01234567

f − Frequency − MHz

Peak at

f = 2.64 MHz

Gain = 2

Gain = 1

Gain = 0.5

Gain = 0

Figure 2−9. Peaking Filter Response,

NTSC/PAL ITU-R BT.601 Sampling

2.2.4 Color Transient Improvement

Color transient improvement (CTI) enhances horizontal color transients. The color difference signal transition points are maintained, but the edges are enhanced for signals which have bandwidth-limited color components.

SLES140A—March 2007TVP5147M1PFP

2.3 Clock Circuits

An internal line-locked PLL generates the system and pixel clocks. A 14.318-MHz clock is required to drive the PLL. This can be input to the TVP5147M1 decoder at the 1.8-V level on terminal 74 (XTAL1), or a crystal of 14.318-MHz fundamental resonant frequency can be connected across terminals 74 and 75 (XTAL2). If a parallel resonant circuit is used as shown in Figure 2−10, then the external capacitors must have the following relationship:

= CL2 = 2C

where C configurations. The TVP5147M1 decoder generates the DATACLK signal used for clocking data.

is the terminal capacitance with respect to ground. Figure 2−10 shows the reference clock

STRAY

Functional Description

− C

STRAY

TVP5147M1

XTAL1

XTAL2

Figure 2−10. Reference Clock Configurations

2.4 Real-Time Control (RTC)

Although the TVP5147M1 decoder is a line-locked system, the color burst information is used to determine accurately the color subcarrier frequency and phase. This ensures proper operation with nonstandard video signals that do not follow exactly the required frequency multiple between color subcarrier frequency and video line frequency . The frequency control word of the internal color subcarrier PLL and the subcarrier reset bit are transmitted via terminal 37 (GLCO) for optional use in an end system (for example, by a video encoder). The frequency control word is a 23-bit binary number. The instantaneous frequency of the color subcarrier can be calculated using the following equation:

PLL

where F

PLL

two times the pixel frequency. This information can be generated on the GLCO terminal. Figure 2−11 shows the detailed timing diagram.

ctrl

sclk

is the frequency of the subcarrier PLL, F

14.318-MHz Clock

TVP5147M1

XTAL1

XTAL2

is the 23-bit PLL frequency control word, and F

ctrl

Valid

Sample

Invalid

Sample

14.318-MHz Crystal

sclk

Reserved

RTC

1 CLK

Start

Bit

NOTE: RTC reset bit (R) is active-low, Sequence bit (S) P AL: 1 = (R-Y) line normal, 0 = (R-Y) line inverted, NTSC: 1 = no change

S B

45 CLK18 CLK

23-Bit Fsc PLL Increment

L S B

Figure 2−11. RTC Timing

2.5 Output Formatter

The output formatter sets how the data is formatted for output on the TVP5147M1 output buses. Table 2−1 shows the available output modes.

SLES140A—March 2007 TVP5147M1PFP

3 CLK128 CLK

Functional Description

Table 2−1. Output Format

TERMINAL

NAME

Y_9 43 Cb9, Y9, Cr9 Y9 Y_8 44 Cb8, Y8, Cr8 Y8 Y_7 45 Cb7, Y7, Cr7 Y7 Y_6 46 Cb6, Y6, Cr6 Y6 Y_5 47 Cb5, Y5, Cr5 Y5 Y_4 50 Cb4, Y4, Cr4 Y4 Y_3 51 Cb3, Y3, Cr3 Y3 Y_2 52 Cb2, Y2, Cr2 Y2 Y_1 53 Cb1, Y1, Cr1 Y1 Y_0 54 Cb0, Y0, Cr0 Y0 C_9 57 Cb9, Cr9 C_8 58 Cb8, Cr8 C_7 59 Cb7, Cr7 C_6 60 Cb6, Cr6 C_5 63 Cb5, Cr5 C_4 64 Cb4, Cr4 C_3 65 Cb3, Cr3 C_2 66 Cb2, Cr2 C_1 69 Cb1, Cr1 C_0 70 Cb0, Cr0

TERMINAL

NUMBER

10-Bit 4:2:2

YCbCr

20-Bit 4:2:2

YCbCr

Table 2−2. Summary of Line Frequencies, Data Rates, and Pixel/Line Counts

STANDARDS

601 sampling

NTSC-J, M 858 720 525 13.5 3.579545 15.73426 NTSC-4.43 858 720 525 13.5 4.43361875 15.73426 PAL-M 858 720 525 13.5 3.57561149 15.73426 PAL-60 858 720 525 13.5 4.43361875 15.73426 PAL-B, D, G, H, I 864 720 625 13.5 4.43361875 15.625 PAL-N 864 720 625 13.5 4.43361875 15.625 PAL-Nc 864 720 625 13.5 3.58205625 15.625

SECAM 864 720 625 13.5

PIXELS PER

LINE

ACTIVE PIXELS

PER LINE

LINES PER

FRAME

PIXEL

FREQUENCY

(MHz)

COLOR

SUBCARRIER

FREQUENCY (MHz)

Dr = 4.406250

Db = 4.250000

HORIZONTAL

LINE RATE (kHz)

15.625

2.5.1 Separate Syncs

VS, HS, and VBLK are independently software programmable to a 1× pixel count. This allows any possible alignment to the internal pixel count and line count. The default settings for 525-line and 625-line video outputs are given as examples below. FID changes at the same transient time when the trailing edge of vertical sync occurs. The polarity of FID is programmable by an I

C interface.

SLES140A—March 2007TVP5147M1PFP

First Field Video

FID

VBLK

Functional Description

525-Line

525

12345678910 2021

VS Start VS Stop

VBLK Start VBLK Stop

262

263 264 265 266 267 268 269 270 271 272 273 283 284

Second Field Video

FID

VBLK

VBLK Start VBLK Stop

NOTE: Line numbering conforms to ITU-R BT.470

Figure 2−12. Vertical Synchronization Signals for 525-Line System

VS Start VS Stop

SLES140A—March 2007 TVP5147M1PFP

Functional Description

First Field Video

FID

VBLK

625-Line

6226236246251234567 232425

VS Start VS Stop

VBLK Start VBLK Stop

310

311 312 313 314 315 316 317 318 319 320 336 337

Second Field Video

FID

VBLK

VBLK Start VBLK Stop

NOTE: Line numbering conforms to ITU-R BT.470

Figure 2−13. Vertical Synchronization Signals for 625-Line System

338

VS Start VS Stop

SLES140A—March 2007TVP5147M1PFP

ATACLK

Y[9:0]

Y Cr Y

EAV

EAV3EAV

Horizontal Blanking

SAV1SAV2SAV3SAV

Functional Description

Cb0 Y0 Cr0 Y1

HS Start

A C

AVID

AVID Stop AVID Start

DATACLK = 2× Pixel Clock

Mode A BC

NTSC 601 106 PAL 601

NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference

112

HS Stop

128 1284248

276 288

Figure 2−14. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode

SLES140A—March 2007 TVP5147M1PFP

Functional Description

ATACLK

Y[9:0] Y Y Y Y Y0 Y1 Y2 Y3Horizontal Blanking

CbCr[9:0]

AVID

NOTE: AVID rising edge occurs 4 clock cycles early.

NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference

Cr Cb Cr Cb0 Cr0 Cb1 Cr1

A C

AVID Stop AVID Start

DATACLK = 1× Pixel Clock

Mode A BC

NTSC 601 53 PAL 601

Horizontal Blanking

HS Start

5664641922

HS Stop

136 142

Figure 2−15. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode

SLES140A—March 2007TVP5147M1PFP

Functional Description

First Field B/2

Second Field

10-Bit (PCLK = 2× Pixel Clock)

Mode B/2 NTSC 601 64 PAL 601

H/2 + B/2 H/2 + B/2

Figure 2−16. VSYNC Position With Respect to HSYNC

H/2 858 864

20-Bit (PCLK = 1× Pixel Clock)

B/2

32 32

H/2 429 432

B/2

2.5.2 Embedded Syncs

Standards with embedded syncs insert the SA V and EAV codes into the data stream on the rising and falling edges of AVID. These codes contain the V and F bits which also define vertical timing. Table 2−3 gives the format of the SAV and EAV codes.

H equals 1 always indicates EA V. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard.

The P bits are protection bits:

P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H

Table 2−3. EAV and SAV Sequence

D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0

Preamble 1 1 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 0 0 Status word 1 F V H P3 P2 P1 P0 0 0

2.6 I2C Host Interface

Communication with the TVP5147M1 decoder is via an I2C host interface. The I2C standard consists of two signals, the serial input/output data (SDA) line and the serial input clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CA) is used for slave address selection. Although

an I

C system can be multimastered, the TVP5147M1 decoder functions as a slave device only.

Because SDA an d S C L a r e kept open-drain at a logic-high output level or when the bus is not driven, the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on the board. The slave addresses select signal, terminal 37 (I2CA), enables the use of two TVP5147M1 devices tied to the same I because it controls the least significant bit of the I

C device address.

C bus,

SLES140A—March 2007 TVP5147M1PFP

Functional Description

T able 2−4. I2C Host Interface Terminal Description

SIGNAL TYPE DESCRIPTION

I2CA I Slave address selection SCL I Input clock line SDA I/O Input/output data line

2.6.1 Reset and I2C Bus Address Selection

The TVP5147M1 decoder can respond to two possible chip addresses. The address selection is made at reset by an externally supplied level on the I2CA terminal. The TVP5147M1 decoder samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures the I

C bus address bit A0. The I2CA terminal

has an internal pulldown resistor to pull the terminal low to set a zero.

T able 2−5. I

A6 A5 A4 A3 A2 A1 A0 (I2CA) R/W HEX

1 0 1 1 1 0 0 (default) 1/0 B9/B8 1 0 1 1 1 0 1

†

If terminal 37 is strapped to DVDD via a 2.2-kΩ resistor, I2C device address A0 is set to 1.

C Address Selection

†

1/0 BB/BA

2.6.2 I2C Operation

Data transfers occur using the following illustrated formats.

S 10111000 ACK Subaddress ACK Send data ACK P

Read from I2C control registers

S 10111000 ACK Subaddress ACK S 10111001 ACK Receive data NAK P

S = I2C bus start condition

P = I

C bus stop condition ACK = Acknowledge generated by the slave NAK = Acknowledge generated by the master, for multiple-byte read master with ACK each byte except

last byte Subaddress = Subaddress byte Data = Data byte. If more than one byte of data is transmitted (read and write), the subaddress pointer is

automatically incremented.

C bus address = Example shown that I2CA is in default mode. Write (B8h), read (B9h)

2.6.3 VBUS Access

The TVP5147M1 decoder has additional internal registers accessible through an indirect access to an internal 24-bit address wide VBUS. Figure 2−17 shows the VBUS register access.

SLES140A—March 2007TVP5147M1PFP

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