Texas instruments TUSB9260 Data Manual

TUSB9260

USB 3.0 TO SATA BRIDGE

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SLLS962C

December 2009–Revised July 2010

TUSB9260

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Contents

1 MAIN FEATURES ................................................................................................................ 5

1.1 TUSB9260 Features ........................................................................................................ 5

1.2 Target Applications ......................................................................................................... 5

2 INTRODUCTION .................................................................................................................. 6

2.1 System Overview ........................................................................................................... 6

2.2 Device Block Diagram ...................................................................................................... 6

3 OPERATION ....................................................................................................................... 8

3.1 General Functionality ....................................................................................................... 8

3.2 Firmware Support ........................................................................................................... 9

3.3 GPIO/PWM LED Designations ............................................................................................ 9

3.4 Power Up and Reset Sequence ......................................................................................... 10

4 SIGNAL DESCRIPTIONS ..................................................................................................... 11

5 CLOCK CONNECTIONS ...................................................................................................... 15

5.1 Clock Source Requirements ............................................................................................. 15

5.2 Clock Source Selection Guide ........................................................................................... 15

5.3 Oscillator .................................................................................................................... 16

5.4 Crystal ....................................................................................................................... 16

6 ELECTRICAL SPECIFICATIONS .......................................................................................... 17

6.1 Absolute Maximum Ratings .............................................................................................. 17

6.2 Recommended Operating Conditions .................................................................................. 17

6.3 DC Electrical Characteristics for 3.3-V Digital I/O ..................................................................... 17

7 POWER CONSUMPTION ..................................................................................................... 18

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List of Figures

2-1 Device Block Diagram............................................................................................................. 7

5-1 Typical Crystal Connections .................................................................................................... 15

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List of Tables

3-1 GPIO/PWM LED Designations................................................................................................... 9

4-1 I/O Definitions..................................................................................................................... 11

4-2 Clock and Reset Signals ........................................................................................................ 11

4-3 SATA Interface Signals.......................................................................................................... 11

4-4 USB Interface Signals ........................................................................................................... 12

4-5 Serial Peripheral Interface (SPI) Signals...................................................................................... 12

4-6 JTAG, GPIO, and PWM Signals ............................................................................................... 13

4-7 Power and Ground Signals ..................................................................................................... 14

5-1 Oscillator Specification .......................................................................................................... 16

5-2 Crystal Specification ............................................................................................................. 16

7-1 SuperSpeed USB Power Consumption ....................................................................................... 18

7-2 High Speed USB Power Consumption ........................................................................................ 18

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USB 3.0 TO SATA BRIDGE

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1 MAIN FEATURES

1.1 TUSB9260 Features

• Universal Serial Bus (USB) – SuperSpeed USB 3.0 Compliant - TID 340000007

• Integrated Transceiver Supports SS/HS/FS Signaling

– Best in Class Adaptive Equalizer

• Allows for Greater Jitter Tolerance in the Receiver

– USB Class Support

• USB Attached SCSI Protocol (UASP)

• USB Mass Storage Class Bulk-Only Transport (BOT)

• Support for Error Conditions Per the 13 Cases (Defined in the BOT Specification)

• USB Bootability Support

• USB Human Interface Device (HID)

– Supports Firmware Update Via USB, Using a TI Provided Application

• SATA Interface – Serial ATA Specification Revision 2.6

• gen1i, gen1m, gen2i, and gen2m

– Support for Mass-Storage Devices Compatible With the ATA/ATAPI-8 Specification

• Integrated ARM Cortex M3 Core – Customizable Application Code Loaded From EEPROM Via SPI Interface – Two Additional SPI Port Chip Selects for Peripheral Connection – Up to 12 GPIOs for End-User Configuration

• 2 GPIOs Have PWM Functionality for LED Blink Speed Control

– Serial Communications Interface for Debug (UART)

• General Features – Can Operate from Either a Single Low Cost Crystal or Clock Oscillator

• Supports 40 MHz

– A JTAG Interface is Used for IEEE1149.1 and IEEE1149.6 Boundary Scan – Available in a Fully RoHS Compliant Package

1.2 Target Applications

• External HDD/SSD

• External DVD

• External CD

• HDD-Based Portable Media Player

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SATA

Gen1/2

TUSB9260

HDD

USB 3.0

SuperSpeed

(1)

USB 2.0

High-speed

(1)

with

USB 3.0

Support

(1) USB connection is made at either SuperSpeed or High-Speed depending on the upstream connection support.

TUSB9260

SLLS962C–DECEMBER 2009–REVISED JULY 2010

2 INTRODUCTION

2.1 System Overview

The TUSB9260 is an ARM cortex M3 microcontroller based USB 3.0 to serial ATA bridge. It provides the necessary hardware and firmware to implement a USB attached SCSI protocol (UASP) compliant mass storage device suitable for bridging hard disk drives (HDD), solid state disk drives (SSD), optical drives and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus. In addition to UASP support, the firmware implements the mass storage class bulk-only transport (BOT), and USB human in-terface device (HID) interfaces.

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2.2 Device Block Diagram

The major functional blocks are as follows:

• Cortex M3 microcontroller subsystem including the following peripherals: – Time interrupt modules, including watchdog timer – Universal asynchronous receive/transmit (SCI) – Serial peripheral interface (SPI) – General purpose input/output (GPIO) – PWM for support of PWM outputs (PWM)

• USB 3.0 core (endpoint controller) and integrated SuperSpeed PHY

• AHCI compliant SATA controller and integrated SATA PHY – Supporting gen1i, gen1m, gen2i, and gen2m

• Chip level clock generation and distribution

• Support for JTAG 1149.1 and 1149.6

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ROM

RAM

ARM

Cortex M3

Power

and

Reset

Distribution

JTAG

Clock

Generation

TCK TMS TDO

TDI TRST

SCI

(UART)

Watchdog

SPI

Timer

GPIO PWM

Timer

Data Path

RAM

80 kB

TX+

TX-

ARX+

ARX-

SATA II

PHY

USB SS

PHY

USB HS/FS

PHY

SATA AHCI

USB 3.0

Device

Controller

SSTX+

SSTX-

SSRX+

SSRX-

VBUS

VDD3.3

VDD1.8

VDD1.1

DATA_OUT

DATA_IN

CS[2:0]

GPIO[11:0]

PWM[1:0]

DP/DM

USB_R1

USB_R1RTN

GRSTz

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Figure 2-1. Device Block Diagram

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3 OPERATION

3.1 General Functionality

The TUSB9260 ROM contains boot code that executes after a global reset which performs the initial con-figuration required to load a firmware image from an attached SPI flash memory to local RAM. In the ab-sence of an attached SPI flash memory or a valid image in the SPI flash memory, the firmware will idle and wait for a connection from a USB host through its HID interface which is also configured from the boot code. The latter can be accomplished using a custom application or driver to load the firmware from a file resident on the host system.

Once the firmware is loaded it configures the SATA advanced host controller interface host bus adapter (AHCI) and the USB device controller. In addition, the configuration of the AHCI includes a port reset which initiates an out of band (OOB) TX sequence from the AHCI link layer to determine if a device is connected, and if so negotiate the connection speed with the device (3.0 Gbps or 1.5 Gbps).

The configuration of the USB device controller includes creation of the descriptors and configuration of the device endpoints for support of UASP and USB mass storage class bulk-only transport (BOT). In addition, the firmware provides any other custom configuration required for application specific implementation, for example a HID interface for user initiated backup.

After USB device controller configuration is complete, if a SATA device was detected during the AHCI con-figuration the firmware connects the device to the USB bus when VBUS is detected. According to the USB 3.0 specification, the TUSB9260 will initially try to connect at SuperSpeed, if successful it will enter U0; otherwise, after the training time out it will enable the DP pull up and connect as a USB 2.0 high-speed or full-speed device depending on the speed supported by host or hub port.

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When connected, the firmware presents the BOT interface as the primary interface and the UASP inter-face as the secondary interface. If the host stack is UASP aware, it can enable the UASP interface using a SET_INTERFACE request for alternate interface 1.

Following speed negotiation, the device should transmit a device to host (D2H) FIS with the device signature. This first D2H FIS is received by the link layer and copied to the port signature register. When firmware is notified of the device connection it queries the device for capabilities using the IDENTIFY DEVICE command. Firmware then configures the device as appropriate for its interface and features supported, for example an HDD that supports native command queuing (NCQ).

The configuration of the USB device controller includes creation of the descriptors, configuration of the device endpoints for support of UASP and USB mass storage class bulk-only transport (BOT), allocation of memory for the transmit request blocks (TRBs), and creation of the TRBs necessary to transmit and receive packet data over the USB. In addition, the firmware provides any other custom configuration required for application specific implementation, for example a HID interface for user initiated backup.

After USB device controller configuration is complete, if a SATA device was detected during the AHCI configuration the firmware connects the device to the USB bus when VBUS is detected. According to the USB 3.0 specification, the TUSB9260 will initially try to connect at SuperSpeed, if successful it will enter U0; otherwise, after the training time out it will enable the DP pull up and connect as a USB 2.0 high-speed or full-speed device depending on the speed supported by host or hub port.

When connected as a SuperSpeed device, the firmware presents the UASP interface as the primary interface, and the BOT interface as a secondary interface. If the host stack is not UASP aware, it can enable the BOT interface using a SET_INTERFACE request for alternate interface 1.

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3.2 Firmware Support

Default firmware support is provided for the following:

• USB 3.0 SuperSpeed and USB 2.0 High-Speed and Full-Speed

• USB Attached SCSI Protocol (UASP)

• USB Mass Storage Class (MSC) Bulk-Only Transport (BOT) – Including the 13 Error Cases

• USB Mass Storage Specification for Bootability

• USB Device Class Definition for Human Interface Devices (HID) – Firmware Update and Custom Functionality (e.g. One-Touch Backup)

• Serial ATA Advanced Host Controller Interface (AHCI)

• General Purpose Input/Output (GPIO) – LED Control and Custom Functions (e.g. One-Touch Backup Control)

• Pulse Width Modulation (PWM) – LED Dimming Control

• Serial Peripheral Interface (SPI) – Firmware storage and storing Custom Device Descriptors

• Serial Communications Interface (SCI) – Debug Output Only

SLLS962C–DECEMBER 2009–REVISED JULY 2010

3.3 GPIO/PWM LED Designations

The default firmware provided by TI drives the GPIO and PWM outputs as listed in the table below.

Table 3-1. GPIO/PWM LED Designations

GPIO0 SW heartbeat

GPIO1/GPIO5 USB3 power state (U0-U3)

GPIO2 HS/FS suspend GPIO3 Push button input on customer board GPIO4 Not used GPIO6 FS/HS connected GPIO7 SS connected PWM0 Disk activity PWM1 U3 or HS/FS suspend state (fades high and low) GPIO10

(SPICS1) GPIO11

(SPICS2)

The LED’s on the TUSB9260 Product Development Kit (PDK) board are connected as in the table above. Please see the TUSB9260 PDK Guide (SLLA303) for more information on GPIO LED connection and usage. This EVM is available for purchase, contact TI for ordering information.

Not used

00: U3 state or default 01: U2 state 10: U1 state 11: U0 state

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3.4 Power Up and Reset Sequence

The TUSB9260 does not have specific power sequencing requirements with respect to the core power (VDD), I/O power (VDD33), or analog power (VDDA11, VDDA33, VDDA18, and VDDR18). The core power (VDD) or IO power (VDD33) may be powered up for an indefinite period of time while others are not powered up if all of these constraints are met:

• All maximum ratings and recommended operating conditions are observed.

• All warnings about exposure to maximum rated and recommended conditions are observed, par-ticularly junction temperature. These apply to power transitions as well as normal operation.

• Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the device.

• Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that range, either stable or in transition.

A minimum reset duration of 1 ms is required. This is defined as the time when the power supplies are in the recommended operating range to the de-assertion of GRSTz.

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4 SIGNAL DESCRIPTIONS

Table 4-1. I/O Definitions

I/O TYPE DESCRIPTION

I Input

O Output I/O Input - Output PU Internal pull-up resistor PD Internal pull-down resistor

PWR Power signal

Table 4-2. Clock and Reset Signals

TERMINAL

NAME

GRSTz 4

XI 52 I be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor

XO 54 O external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback

FREQSEL[1:0] 31, 30

PIN NO.

I/O DESCRIPTION

I Global power reset. This reset brings all of the TUSB9260 internal registers to their default

PU states. When GRSTz is asserted, the device is completely nonfunctional.

Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately

is required between X1 and XO.

Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an

resistor is required between X1 and XO.

Frequency select. These terminals indicate the oscillator input frequency and are used to

configure the correct PLL multiplier. The field encoding is as follows:

FREQSEL[1] FREQSEL[0] INPUT CLOCK FREQUENCY

0 0 Reserved 0 1 Reserved 1 0 Reserved 1 1 40 MHz

Table 4-3. SATA Interface Signals

TERMINAL

NAME

SATA_TXP 57 O Serial ATA transmitter differential pair (positive) SATA_TXM 56 O Serial ATA transmitter differential pair (negative) SATA_RXP 60 I Serial ATA receiver differential pair (positive) SATA_RXM 59 I Serial ATA receiver differential pair (negative)

PIN NO.

I/O DESCRIPTION

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Table 4-4. USB Interface Signals

TERMINAL

NAME

USB_SSTXP 43 O USB SuperSpeed transmitter differential pair (positive) USB_SSTXM 42 O USB SuperSpeed transmitter differential pair (negative) USB_SSRXP 46 I USB SuperSpeed receiver differential pair (positive) USB_SSRXM 45 I USB SuperSpeed receiver differential pair (negative) USB_DP 36 I/O USB High-speed differential transceiver (positive) USB_DM 35 I/O USB High-speed differential transceiver (negative) USB_VBUS 33 I USB bus power USB_R1 39 O Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN. USB_R1RTN 40 I Precision resistor reference return

PIN NO.

I/O DESCRIPTION

Table 4-5. Serial Peripheral Interface (SPI) Signals

TERMINAL

NAME

SPI_SCLK 17 SPI clock

SPI_DATA_IN 18 SPI master data in

SPI_DATA_OUT 20 SPI master data out

SPI_CS0 21 Primary SPI chip select for Flash RAM SPI_CS2/

GPIO11 SPI_CS1/ GPIO10

PIN NO.

I/O DESCRIPTION

PU I/O SPCI chip select for additional peripherals. When not used for SPI chip select this pin may be

PU used as general purpose I/O. I/O SPCI chip select for additional peripherals. When not used for SPI chip select this pin may be

PU used as general purpose I/O.

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Table 4-6. JTAG, GPIO, and PWM Signals

TERMINAL

NAME

JTAG_TCK 25 JTAG test clock

JTAG_TDI 26 JTAG test data in

JTAG_TDO 27 JTAG test data out

JTAG_TMS 28 JTAG test mode select

JTAG_TRSTz 29 JTAG test reset

GPIO9/UART_TX 6

GPIO8/UART_RX 5

GPIO7 16

GPIO6 15

GPIO5 14

GPIO4 13

GPIO3 11

GPIO2 10

GPIO1 9

GPIO0 8

PWM0 2

PWM1 3

(1) PWM pull down resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down

resistors are enabled by default.

PIN NO.

I/O DESCRIPTION

PD I/O GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a

PU UART channel. This pin defaults to a general purpose output. I/O GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART

PU channel. This pin defaults to a general purpose output. I/O

PD I/O

Configurable as general purpose input/outputs

I/O PD

(1)

Pulse Width Modulation (PWM). Can be used to drive status LED's.

(1)

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Table 4-7. Power and Ground Signals

TERMINAL

NAME

VDDR18 48, 62 PWR 1.8-V power rail VDDA18 37 PWR 1.8-V analog power rail

VDD 44, 47, PWR 1.1-V power rail

VDD33 PWR 3.3-V power rail VDDA33 34 PWR 3.3-V analog power rail

VSSOSC 53 PWR using an oscillator, this should be connected to PCB ground. See the Clock Source

VSS 65 PWR Ground - Thermal Pad

PIN NO.

1, 12, 19, 32, 38, 41,

49, 55, 58, 61,

63, 64

7, 24,

50, 51

I/O DESCRIPTION

Oscillator ground. If using a crystal, this should not be connected to PCB ground plane. If Requirements section for more details.

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5 CLOCK CONNECTIONS

5.1 Clock Source Requirements

The TUSB9260 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is used, the connection needs to follow the guidelines below.

Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as possible and away from any switching leads. It is also recommended to minimize the capacitance be-tween XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external capaci-tors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be connected to PCB ground when using a crystal.

Load capacitance (C entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2 in Figure 5-1. The trace length between the decoupling capacitors and the corresponding power pins on the TUSB9260 needs to be minimized. It is also recommended that the trace length from the capacitor pad to the power or ground plane be minimized.

) of the crystal varying with the crystal vendors is the total capacitance value of the

load

SLLS962C–DECEMBER 2009–REVISED JULY 2010

Figure 5-1. Typical Crystal Connections

5.2 Clock Source Selection Guide

Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the trans-mit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter reference clock is required to achieve compliance with supported USB3.0 standards. For example, USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of additional jitter compo-nents, the Reference Clock jitter must be considerably below the overall jitter budget.

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5.3 Oscillator

XI should be tied to the 1.8-V clock source and XO should be left floating. VSSOSC should be connected to the PCB ground plane. A 40-MHz clock can be used.

PARAMETER CONDITIONS MIN TYP MAX UNIT

tosc_i

duty

TR/T R

p-p

(1) Sigma value assuming Gaussian distribution (2) After application of JTF (3) Calculated as 14.1 x RJ+ D (4) Absolute phase jitter (p-p)

XI input capacitance 0.414 pF Low-level input voltage 0.35 x VDDR18 V

High-level input voltage 0.65 x VDDR18 V Frequency tolerance Operational temperature –50 50 ppm Duty cycle 45 50 55 % Rise/Fall time 20% - 80 % 6 ns

Reference clock R Reference clock T

Reference clock jitter (absolute p-p)

Table 5-1. Oscillator Specification

VDDIO = 1.8 V,

TJ= 25°C

JTF (1 sigma) JTF (total p-p)

(1)(2) (2)(3)

(4)

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0.8 ps 25 ps 50 ps

5.4 Crystal

A parallel, 20-pF load capacitor should be used if a crystal source is used. VSSOSC should not be connected to the PCB ground plane. A 40-MHz crystal can be used.

tosc_i

Frequency tolerance Operational temperature –50 50 ppm Frequency stability 1 year aging –50 50 ppm Load capacitance 12 20 24 pF

Table 5-2. Crystal Specification

PARAMETER CONDITIONS MIN TYP MAX UNIT

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6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

VALUE UNIT

VDDR18/ VDDA18

VDD Steady-state supply voltage –0.3 to 1.4 V VDD33/

VDDA33

6.2 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

VDDR18 Digital 1.8 supply voltage 1.71 1.8 1.89 V VDDA18 Analog 1.8 supply voltage 1.62 1.8 1.89 V VDD Digital 1.1 supply voltage 1.045 1.1 1.155 V VDD33 Digital 3.3 supply voltage 3 3.3 3.6 V VDDA33 Analog 3.3 supply voltage 3 3.3 3.6 V VBUS Voltage at VBUS PAD 0 1.155 V T

Steady-state supply voltage –0.3 to 2.45 V

Steady-state supply voltage –0.3 to 3.8 V

MIN NOM MAX UNIT

Operating free-air temperature range 0 70 °C Operating junction temperature range 0 105 °C HBM ESD 1000 V CDM ESD 500 V

6.3 DC Electrical Characteristics for 3.3-V Digital I/O

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DRIVER

RECEIVER

hys

Rise time 5 pF 1.5 ns Fall time 5 pF 1.53 ns Low-level output current VDD33 = 3.3 V, TJ= 25°C 6 mA High-level output current VDD33 = 3.3 V, TJ= 25°C –6 mA Low-level output voltage IOL= 2 mA 0.4 V High-level output voltage IOL= –2 mA 2.4 V Output voltage 0 VDD33 V

Input voltage 0 VDD33 V Low-level input voltage 0 0.8 V High-level input voltage 2 V Input hysteresis 200 mV Input transition time (TRand TF) 10 ns Input current VI= 0 V to VDD33 12 µA Input capacitance VDD33 = 3.3 V, TJ= 25°C 0.384 pF

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7 POWER CONSUMPTION

All transfers are to a SATA Gen II SSD. A SATA Gen I target yields an approximate 10-mA power savings on the 1.1-V rail.

Table 7-1. SuperSpeed USB Power Consumption

POWER RAIL TYPICAL ACTIVE CURRENT (mA)

(3)

VDD11 VDD18 VDD33

(4) (5)

319 308

58 58

6 6

(1) Transferring data via SS USB to a SSD SATA Gen II device. No SATA power management, U0 only. (2) SATA Gen II SSD attached no active transfer. No SATA power management, U0 only. (3) All 1.1-V power rails connected together. (4) All 1.8-V power rails connected together. (5) All 3.3-V power rails connected together.

Table 7-2. High Speed USB Power Consumption

POWER RAIL TYPICAL ACTIVE CURRENT (mA)

(3)

VDD11

(4)

VDD18

(5)

VDD33

(1) Transferring data via HS USB to a SSD SATA Gen II device. No SATA power management. (2) SATA Gen II SSD attached no active transfer. No SATA power management. (3) All 1.1-V power rails connected together. (4) All 1.8-V power rails connected together. (5) All 3.3-V power rails connected together.

197 193

45 36 14 14

(1)

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TYPICAL IDLE CURRENT

(mA)

(2)

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PACKAGE OPTION ADDENDUM

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26-Jul-2010

PACKAGING INFORMATION

Orderable Device

TUSB9260PAP PREVIEW HTQFP PAP 64 160 TBD Call TI Call TI Samples Not Available TUSB9260PVP PREVIEW HTQFP PVP 64 250 TBD Call TI Call TI Samples Not Available

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Status

(1)

Package Type Package

Drawing

Pins Package Qty

Eco Plan

(2)

Lead/

Ball Finish

MSL Peak Temp

(3)

Samples

(Requires Login)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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Texas instruments TUSB9260 Data Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 MAIN FEATURES

1.1 TUSB9260 Features

1.2 Target Applications

2 INTRODUCTION

2.1 System Overview

2.2 Device Block Diagram

3 OPERATION

3.1 General Functionality

3.2 Firmware Support

3.3 GPIO/PWM LED Designations

3.4 Power Up and Reset Sequence

4 SIGNAL DESCRIPTIONS

5 CLOCK CONNECTIONS

5.1 Clock Source Requirements

5.2 Clock Source Selection Guide

5.3 Oscillator

5.4 Crystal

6 ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings

6.2 Recommended Operating Conditions

6.3 DC Electrical Characteristics for 3.3-V Digital I/O

7 POWER CONSUMPTION