PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLLS962C
December 2009–Revised July 2010
TUSB9260
SLLS962C–DECEMBER 2009–REVISED JULY 2010
www.ti.com
Contents
1MAIN FEATURES ................................................................................................................ 5
1.1TUSB9260 Features ........................................................................................................ 5
•Allows for Greater Jitter Tolerance in the Receiver
– USB Class Support
•USB Attached SCSI Protocol (UASP)
•USB Mass Storage Class Bulk-Only Transport (BOT)
•Support for Error Conditions Per the 13 Cases (Defined in the BOT Specification)
•USB Bootability Support
•USB Human Interface Device (HID)
– Supports Firmware Update Via USB, Using a TI Provided Application
• SATA Interface
– Serial ATA Specification Revision 2.6
•gen1i, gen1m, gen2i, and gen2m
– Support for Mass-Storage Devices Compatible With the ATA/ATAPI-8 Specification
• Integrated ARM Cortex M3 Core
– Customizable Application Code Loaded From EEPROM Via SPI Interface
– Two Additional SPI Port Chip Selects for Peripheral Connection
– Up to 12 GPIOs for End-User Configuration
•2 GPIOs Have PWM Functionality for LED Blink Speed Control
– Serial Communications Interface for Debug (UART)
• General Features
– Can Operate from Either a Single Low Cost Crystal or Clock Oscillator
•Supports 40 MHz
– A JTAG Interface is Used for IEEE1149.1 and IEEE1149.6 Boundary Scan
– Available in a Fully RoHS Compliant Package
1.2Target Applications
• External HDD/SSD
• External DVD
• External CD
• HDD-Based Portable Media Player
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
(1) USB connection is made at either SuperSpeed or High-Speed depending on the upstream connection support.
TUSB9260
SLLS962C–DECEMBER 2009–REVISED JULY 2010
2INTRODUCTION
2.1System Overview
The TUSB9260 is an ARM cortex M3 microcontroller based USB 3.0 to serial ATA bridge. It provides the
necessary hardware and firmware to implement a USB attached SCSI protocol (UASP) compliant mass
storage device suitable for bridging hard disk drives (HDD), solid state disk drives (SSD), optical drives
and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus. In addition to UASP
support, the firmware implements the mass storage class bulk-only transport (BOT), and USB human
in-terface device (HID) interfaces.
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2.2Device Block Diagram
The major functional blocks are as follows:
•Cortex M3 microcontroller subsystem including the following peripherals:
– Time interrupt modules, including watchdog timer
– Universal asynchronous receive/transmit (SCI)
– Serial peripheral interface (SPI)
– General purpose input/output (GPIO)
– PWM for support of PWM outputs (PWM)
•USB 3.0 core (endpoint controller) and integrated SuperSpeed PHY
•AHCI compliant SATA controller and integrated SATA PHY
– Supporting gen1i, gen1m, gen2i, and gen2m
The TUSB9260 ROM contains boot code that executes after a global reset which performs the initial
con-figuration required to load a firmware image from an attached SPI flash memory to local RAM. In the
ab-sence of an attached SPI flash memory or a valid image in the SPI flash memory, the firmware will idle
and wait for a connection from a USB host through its HID interface which is also configured from the boot
code. The latter can be accomplished using a custom application or driver to load the firmware from a file
resident on the host system.
Once the firmware is loaded it configures the SATA advanced host controller interface host bus adapter
(AHCI) and the USB device controller. In addition, the configuration of the AHCI includes a port reset
which initiates an out of band (OOB) TX sequence from the AHCI link layer to determine if a device is
connected, and if so negotiate the connection speed with the device (3.0 Gbps or 1.5 Gbps).
The configuration of the USB device controller includes creation of the descriptors and configuration of the
device endpoints for support of UASP and USB mass storage class bulk-only transport (BOT). In addition,
the firmware provides any other custom configuration required for application specific implementation, for
example a HID interface for user initiated backup.
After USB device controller configuration is complete, if a SATA device was detected during the AHCI
con-figuration the firmware connects the device to the USB bus when VBUS is detected. According to the
USB 3.0 specification, the TUSB9260 will initially try to connect at SuperSpeed, if successful it will enter
U0; otherwise, after the training time out it will enable the DP pull up and connect as a USB 2.0
high-speed or full-speed device depending on the speed supported by host or hub port.
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When connected, the firmware presents the BOT interface as the primary interface and the UASP
inter-face as the secondary interface. If the host stack is UASP aware, it can enable the UASP interface
using a SET_INTERFACE request for alternate interface 1.
Following speed negotiation, the device should transmit a device to host (D2H) FIS with the device
signature. This first D2H FIS is received by the link layer and copied to the port signature register. When
firmware is notified of the device connection it queries the device for capabilities using the IDENTIFY
DEVICE command. Firmware then configures the device as appropriate for its interface and features
supported, for example an HDD that supports native command queuing (NCQ).
The configuration of the USB device controller includes creation of the descriptors, configuration of the
device endpoints for support of UASP and USB mass storage class bulk-only transport (BOT), allocation
of memory for the transmit request blocks (TRBs), and creation of the TRBs necessary to transmit and
receive packet data over the USB. In addition, the firmware provides any other custom configuration
required for application specific implementation, for example a HID interface for user initiated backup.
After USB device controller configuration is complete, if a SATA device was detected during the AHCI
configuration the firmware connects the device to the USB bus when VBUS is detected. According to the
USB 3.0 specification, the TUSB9260 will initially try to connect at SuperSpeed, if successful it will enter
U0; otherwise, after the training time out it will enable the DP pull up and connect as a USB 2.0
high-speed or full-speed device depending on the speed supported by host or hub port.
When connected as a SuperSpeed device, the firmware presents the UASP interface as the primary
interface, and the BOT interface as a secondary interface. If the host stack is not UASP aware, it can
enable the BOT interface using a SET_INTERFACE request for alternate interface 1.
•Serial Communications Interface (SCI)
– Debug Output Only
SLLS962C–DECEMBER 2009–REVISED JULY 2010
3.3GPIO/PWM LED Designations
The default firmware provided by TI drives the GPIO and PWM outputs as listed in the table below.
Table 3-1. GPIO/PWM LED Designations
GPIO0SW heartbeat
GPIO1/GPIO5USB3 power state (U0-U3)
GPIO2HS/FS suspend
GPIO3Push button input on customer board
GPIO4Not used
GPIO6FS/HS connected
GPIO7SS connected
PWM0Disk activity
PWM1U3 or HS/FS suspend state (fades high and low)
GPIO10
(SPICS1)
GPIO11
(SPICS2)
The LED’s on the TUSB9260 Product Development Kit (PDK) board are connected as in the table above.
Please see the TUSB9260 PDK Guide (SLLA303) for more information on GPIO LED connection and
usage. This EVM is available for purchase, contact TI for ordering information.
Not used
Not used
00: U3 state or default
01: U2 state
10: U1 state
11: U0 state
The TUSB9260 does not have specific power sequencing requirements with respect to the core power
(VDD), I/O power (VDD33), or analog power (VDDA11, VDDA33, VDDA18, and VDDR18). The core
power (VDD) or IO power (VDD33) may be powered up for an indefinite period of time while others are not
powered up if all of these constraints are met:
•All maximum ratings and recommended operating conditions are observed.
•All warnings about exposure to maximum rated and recommended conditions are observed,
par-ticularly junction temperature. These apply to power transitions as well as normal operation.
•Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of
the device.
•Bus contention while VDD33 is powered down may violate the absolute maximum ratings.
A supply bus is powered up when the voltage is within the recommended operating range. It is powered
down when it is below that range, either stable or in transition.
A minimum reset duration of 1 ms is required. This is defined as the time when the power supplies are in
the recommended operating range to the de-assertion of GRSTz.
(1) PWM pull down resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down
resistors are enabled by default.
PIN
NO.
I/ODESCRIPTION
I
PD
I
PU
O
PD
I
PU
I
PD
I/OGPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a
PUUART channel. This pin defaults to a general purpose output.
I/OGPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART
PUchannel. This pin defaults to a general purpose output.
I/O
PD
I/O
PD
I/O
PD
I/O
PD
Configurable as general purpose input/outputs
I/O
PD
I/O
PD
I/O
PD
I/O
PD
O
(1)
PD
Pulse Width Modulation (PWM). Can be used to drive status LED's.
The TUSB9260 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead
of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a
crystal is used, the connection needs to follow the guidelines below.
Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short
as possible and away from any switching leads. It is also recommended to minimize the capacitance
be-tween XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external
capaci-tors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be
connected to PCB ground when using a crystal.
Load capacitance (C
entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2
in Figure 5-1. The trace length between the decoupling capacitors and the corresponding power pins on
the TUSB9260 needs to be minimized. It is also recommended that the trace length from the capacitor
pad to the power or ground plane be minimized.
) of the crystal varying with the crystal vendors is the total capacitance value of the
load
SLLS962C–DECEMBER 2009–REVISED JULY 2010
Figure 5-1. Typical Crystal Connections
5.2Clock Source Selection Guide
Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the
trans-mit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing
system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock
detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter
reference clock is required to achieve compliance with supported USB3.0 standards. For example,
USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random
phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of
additional jitter compo-nents, the Reference Clock jitter must be considerably below the overall jitter
budget.
XI should be tied to the 1.8-V clock source and XO should be left floating.
VSSOSC should be connected to the PCB ground plane.
A 40-MHz clock can be used.
PARAMETERCONDITIONSMINTYPMAXUNIT
C
XI
V
IL
V
IH
T
tosc_i
T
duty
TR/T
R
J
T
J
T
p-p
(1) Sigma value assuming Gaussian distribution
(2) After application of JTF
(3) Calculated as 14.1 x RJ+ D
(4) Absolute phase jitter (p-p)
XI input capacitance0.414pF
Low-level input voltage0.35 x VDDR18V
High-level input voltage0.65 x VDDR18V
Frequency toleranceOperational temperature–5050ppm
Duty cycle455055%
Rise/Fall time20% - 80 %6ns
F
Reference clock R
Reference clock T
J
J
Reference clock jitter(absolute p-p)
J
Table 5-1. Oscillator Specification
VDDIO = 1.8 V,
TJ= 25°C
JTF (1 sigma)
JTF (total p-p)
(1)(2)
(2)(3)
(4)
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0.8ps
25ps
50ps
5.4Crystal
A parallel, 20-pF load capacitor should be used if a crystal source is used.
VSSOSC should not be connected to the PCB ground plane.
A 40-MHz crystal can be used.
T
C
tosc_i
L
Frequency toleranceOperational temperature–5050ppm
Frequency stability1 year aging–5050ppm
Load capacitance122024pF
All transfers are to a SATA Gen II SSD. A SATA Gen I target yields an approximate 10-mA power savings
on the 1.1-V rail.
Table 7-1. SuperSpeed USB Power Consumption
POWER RAILTYPICAL ACTIVE CURRENT (mA)
(3)
VDD11
VDD18
VDD33
(4)
(5)
319308
5858
66
(1) Transferring data via SS USB to a SSD SATA Gen II device. No SATA power management, U0 only.
(2) SATA Gen II SSD attached no active transfer. No SATA power management, U0 only.
(3) All 1.1-V power rails connected together.
(4) All 1.8-V power rails connected together.
(5) All 3.3-V power rails connected together.
Table 7-2. High Speed USB Power Consumption
POWER RAILTYPICAL ACTIVE CURRENT (mA)
(3)
VDD11
(4)
VDD18
(5)
VDD33
(1) Transferring data via HS USB to a SSD SATA Gen II device. No SATA power management.
(2) SATA Gen II SSD attached no active transfer. No SATA power management.
(3) All 1.1-V power rails connected together.
(4) All 1.8-V power rails connected together.
(5) All 3.3-V power rails connected together.
TUSB9260PAPPREVIEWHTQFPPAP64160TBDCall TICall TISamples Not Available
TUSB9260PVPPREVIEWHTQFPPVP64250TBDCall TICall TISamples Not Available
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Status
(1)
Package Type Package
Drawing
PinsPackage Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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